Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	88467	1			T3	1340		T4	436		T12	938
accum_cnt_1000	214516	1			T1	2033		T3	1684		T4	820
accum_cnt_100	23826	1			T1	251		T3	98		T4	217
accum_cnt_50	68489	1			T1	189		T2	32		T3	74
accum_cnt_10	191723	1			T1	44		T2	28		T3	27
accum_cnt_0	377125	1			T1	2507		T3	1141		T4	826

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	251147	1			T1	1256		T2	15		T3	1135
class_index[0x1]	251147	1			T1	1256		T2	15		T3	1135
class_index[0x2]	251147	1			T1	1256		T2	15		T3	1135
class_index[0x3]	251147	1			T1	1256		T2	15		T3	1135

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24217	1			T3	508		T4	159		T12	414
class_index[0x0]	accum_cnt_1000	55595	1			T3	472		T4	120		T12	675
class_index[0x0]	accum_cnt_100	6792	1			T3	26		T4	11		T12	78
class_index[0x0]	accum_cnt_50	15922	1			T2	13		T3	18		T4	5
class_index[0x0]	accum_cnt_10	53903	1			T1	6		T2	2		T3	13
class_index[0x0]	accum_cnt_0	82192	1			T1	1250		T3	3		T4	181
class_index[0x1]	accum_cnt_2000	18898	1			T3	316		T16	494		T25	422
class_index[0x1]	accum_cnt_1000	54861	1			T1	1098		T3	734		T4	112
class_index[0x1]	accum_cnt_100	5947	1			T1	90		T3	43		T4	54
class_index[0x1]	accum_cnt_50	17210	1			T1	55		T2	10		T3	35
class_index[0x1]	accum_cnt_10	46166	1			T1	12		T2	5		T3	6
class_index[0x1]	accum_cnt_0	102249	1			T1	1		T3	1		T4	184
class_index[0x2]	accum_cnt_2000	20503	1			T16	454		T25	408		T37	610
class_index[0x2]	accum_cnt_1000	49845	1			T4	82		T12	6		T16	565
class_index[0x2]	accum_cnt_100	5540	1			T4	56		T12	22		T5	21
class_index[0x2]	accum_cnt_50	17716	1			T4	41		T12	1183		T18	20
class_index[0x2]	accum_cnt_10	47694	1			T2	15		T3	2		T4	778
class_index[0x2]	accum_cnt_0	99321	1			T1	1256		T3	1133		T4	259
class_index[0x3]	accum_cnt_2000	24849	1			T3	516		T4	277		T12	524
class_index[0x3]	accum_cnt_1000	54215	1			T1	935		T3	478		T4	506
class_index[0x3]	accum_cnt_100	5547	1			T1	161		T3	29		T4	96
class_index[0x3]	accum_cnt_50	17641	1			T1	134		T2	9		T3	21
class_index[0x3]	accum_cnt_10	43960	1			T1	26		T2	6		T3	6
class_index[0x3]	accum_cnt_0	93363	1			T3	4		T4	202		T17	27