Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	1403	1			T5	86		T46	6		T23	5
alert[0x1]	5165	1			T5	1340		T6	1		T25	28
alert[0x2]	2164	1			T4	31		T5	34		T46	10
alert[0x3]	5752	1			T4	12		T12	3		T6	1
alert[0x4]	10723	1			T23	11		T32	133		T101	527
alert[0x5]	2812	1			T46	4		T62	46		T77	675
alert[0x6]	8582	1			T4	22		T46	2		T62	16
alert[0x7]	1724	1			T5	23		T77	58		T47	1
alert[0x8]	5881	1			T5	18		T23	7		T62	1084
alert[0x9]	4334	1			T5	9		T46	1		T47	2
alert[0xa]	7309	1			T4	709		T5	15		T62	4
alert[0xb]	4823	1			T4	683		T46	4		T25	356
alert[0xc]	5411	1			T4	1		T62	124		T25	795
alert[0xd]	4008	1			T4	22		T5	12		T32	224
alert[0xe]	5866	1			T4	428		T46	2		T25	164
alert[0xf]	2638	1			T23	11		T62	52		T25	34
alert[0x10]	7713	1			T5	50		T25	81		T51	1
alert[0x11]	6257	1			T4	973		T25	86		T32	49
alert[0x12]	2316	1			T4	73		T46	6		T23	1
alert[0x13]	7955	1			T4	17		T12	1		T46	1
alert[0x14]	6820	1			T4	275		T46	5		T25	24
alert[0x15]	3390	1			T46	1		T31	4		T32	96
alert[0x16]	10132	1			T23	4		T29	1		T31	1
alert[0x17]	5048	1			T5	254		T31	2		T32	12
alert[0x18]	8932	1			T12	1		T32	6		T7	1
alert[0x19]	3373	1			T23	14		T25	1499		T307	1
alert[0x1a]	7695	1			T46	18		T23	1		T62	933
alert[0x1b]	3208	1			T4	681		T6	1		T46	11
alert[0x1c]	8808	1			T4	88		T25	1012		T31	17
alert[0x1d]	6140	1			T5	39		T46	87		T25	169
alert[0x1e]	3733	1			T46	2		T62	1		T25	195
alert[0x1f]	2024	1			T4	21		T12	1		T46	2
alert[0x20]	2630	1			T12	4		T64	1		T25	387
alert[0x21]	5415	1			T25	373		T31	28		T32	238
alert[0x22]	5758	1			T62	179		T25	239		T32	49
alert[0x23]	1611	1			T4	108		T5	86		T77	128
alert[0x24]	5546	1			T5	7		T6	2		T46	1
alert[0x25]	2294	1			T5	14		T46	2		T25	337
alert[0x26]	3152	1			T12	2		T5	2		T25	58
alert[0x27]	6756	1			T4	20		T46	5		T62	767
alert[0x28]	3996	1			T32	33		T218	10		T308	1
alert[0x29]	3794	1			T5	1		T46	5		T23	6
alert[0x2a]	3126	1			T4	30		T12	2		T46	7
alert[0x2b]	3299	1			T4	376		T5	4		T46	2
alert[0x2c]	2627	1			T4	3		T31	6		T32	53
alert[0x2d]	6762	1			T4	60		T5	33		T25	58
alert[0x2e]	6306	1			T62	11		T77	100		T47	1
alert[0x2f]	4642	1			T4	65		T25	201		T29	1
alert[0x30]	7847	1			T23	2		T62	186		T25	17
alert[0x31]	4176	1			T4	14		T5	386		T6	1
alert[0x32]	9528	1			T12	1		T46	99		T62	871
alert[0x33]	9896	1			T46	1		T23	7		T32	8
alert[0x34]	3048	1			T4	275		T12	11		T5	48
alert[0x35]	3211	1			T5	181		T6	1		T62	59
alert[0x36]	2597	1			T46	5		T23	3		T64	3
alert[0x37]	7702	1			T4	213		T5	3		T6	2
alert[0x38]	2819	1			T4	4		T62	3		T25	22
alert[0x39]	9805	1			T23	2		T62	218		T25	273
alert[0x3a]	6992	1			T62	18		T25	199		T32	256
alert[0x3b]	5981	1			T4	129		T5	279		T46	1
alert[0x3c]	3626	1			T4	35		T5	3		T6	3
alert[0x3d]	5977	1			T4	235		T46	7		T62	166
alert[0x3e]	3835	1			T4	5		T5	148		T46	9
alert[0x3f]	2691	1			T25	67		T32	266		T309	2
alert[0x40]	8651	1			T4	120		T46	3		T62	9

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	115474	1			T4	5637		T5	1048		T6	2
class_i[0x1]	31275	1			T4	83		T6	7		T46	94
class_i[0x2]	100865	1			T4	8		T5	1634		T6	1
class_i[0x3]	90621	1			T12	26		T5	393		T6	2

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

337560

1

T4

5728

T12

26

T5

3075

alert_ping_fail

675

1

T6

12

T7

5

T8

9

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	1393	1			T5	86		T46	6		T23	5
alert_integrity_fail	alert[0x1]	5153	1			T5	1340		T25	28		T31	3
alert_integrity_fail	alert[0x2]	2154	1			T4	31		T5	34		T46	10
alert_integrity_fail	alert[0x3]	5743	1			T4	12		T12	3		T25	55
alert_integrity_fail	alert[0x4]	10713	1			T23	11		T32	133		T101	527
alert_integrity_fail	alert[0x5]	2800	1			T46	4		T62	46		T77	675
alert_integrity_fail	alert[0x6]	8572	1			T4	22		T46	2		T62	16
alert_integrity_fail	alert[0x7]	1710	1			T5	23		T77	58		T47	1
alert_integrity_fail	alert[0x8]	5865	1			T5	18		T23	7		T62	1084
alert_integrity_fail	alert[0x9]	4324	1			T5	9		T46	1		T47	2
alert_integrity_fail	alert[0xa]	7298	1			T4	709		T5	15		T62	4
alert_integrity_fail	alert[0xb]	4817	1			T4	683		T46	4		T25	356
alert_integrity_fail	alert[0xc]	5399	1			T4	1		T62	124		T25	795
alert_integrity_fail	alert[0xd]	4003	1			T4	22		T5	12		T32	224
alert_integrity_fail	alert[0xe]	5853	1			T4	428		T46	2		T25	164
alert_integrity_fail	alert[0xf]	2630	1			T23	11		T62	52		T25	34
alert_integrity_fail	alert[0x10]	7703	1			T5	50		T25	81		T51	1
alert_integrity_fail	alert[0x11]	6247	1			T4	973		T25	86		T32	49
alert_integrity_fail	alert[0x12]	2308	1			T4	73		T46	6		T23	1
alert_integrity_fail	alert[0x13]	7944	1			T4	17		T12	1		T46	1
alert_integrity_fail	alert[0x14]	6808	1			T4	275		T46	5		T25	24
alert_integrity_fail	alert[0x15]	3382	1			T46	1		T31	4		T32	96
alert_integrity_fail	alert[0x16]	10119	1			T23	4		T29	1		T31	1
alert_integrity_fail	alert[0x17]	5037	1			T5	254		T31	2		T32	12
alert_integrity_fail	alert[0x18]	8919	1			T12	1		T32	6		T83	4
alert_integrity_fail	alert[0x19]	3364	1			T23	14		T25	1499		T101	46
alert_integrity_fail	alert[0x1a]	7682	1			T46	18		T23	1		T62	933
alert_integrity_fail	alert[0x1b]	3199	1			T4	681		T46	11		T62	32
alert_integrity_fail	alert[0x1c]	8799	1			T4	88		T25	1012		T31	17
alert_integrity_fail	alert[0x1d]	6127	1			T5	39		T46	87		T25	169
alert_integrity_fail	alert[0x1e]	3728	1			T46	2		T62	1		T25	195
alert_integrity_fail	alert[0x1f]	2012	1			T4	21		T12	1		T46	2
alert_integrity_fail	alert[0x20]	2626	1			T12	4		T64	1		T25	387
alert_integrity_fail	alert[0x21]	5403	1			T25	373		T31	28		T32	238
alert_integrity_fail	alert[0x22]	5743	1			T62	179		T25	239		T32	49
alert_integrity_fail	alert[0x23]	1596	1			T4	108		T5	86		T77	128
alert_integrity_fail	alert[0x24]	5537	1			T5	7		T46	1		T32	5
alert_integrity_fail	alert[0x25]	2277	1			T5	14		T46	2		T25	337
alert_integrity_fail	alert[0x26]	3141	1			T12	2		T5	2		T25	58
alert_integrity_fail	alert[0x27]	6740	1			T4	20		T46	5		T62	767
alert_integrity_fail	alert[0x28]	3981	1			T32	33		T218	10		T310	1949
alert_integrity_fail	alert[0x29]	3781	1			T5	1		T46	5		T23	6
alert_integrity_fail	alert[0x2a]	3112	1			T4	30		T12	2		T46	7
alert_integrity_fail	alert[0x2b]	3295	1			T4	376		T5	4		T46	2
alert_integrity_fail	alert[0x2c]	2622	1			T4	3		T31	6		T32	53
alert_integrity_fail	alert[0x2d]	6755	1			T4	60		T5	33		T25	58
alert_integrity_fail	alert[0x2e]	6293	1			T62	11		T77	100		T47	1
alert_integrity_fail	alert[0x2f]	4632	1			T4	65		T25	201		T29	1
alert_integrity_fail	alert[0x30]	7835	1			T23	2		T62	186		T25	17
alert_integrity_fail	alert[0x31]	4167	1			T4	14		T5	386		T23	2
alert_integrity_fail	alert[0x32]	9526	1			T12	1		T46	99		T62	871
alert_integrity_fail	alert[0x33]	9885	1			T46	1		T23	7		T32	8
alert_integrity_fail	alert[0x34]	3032	1			T4	275		T12	11		T5	48
alert_integrity_fail	alert[0x35]	3202	1			T5	181		T62	59		T25	2
alert_integrity_fail	alert[0x36]	2593	1			T46	5		T23	3		T64	3
alert_integrity_fail	alert[0x37]	7692	1			T4	213		T5	3		T62	20
alert_integrity_fail	alert[0x38]	2810	1			T4	4		T62	3		T25	22
alert_integrity_fail	alert[0x39]	9793	1			T23	2		T62	218		T25	273
alert_integrity_fail	alert[0x3a]	6981	1			T62	18		T25	199		T32	256
alert_integrity_fail	alert[0x3b]	5971	1			T4	129		T5	279		T46	1
alert_integrity_fail	alert[0x3c]	3609	1			T4	35		T5	3		T46	15
alert_integrity_fail	alert[0x3d]	5964	1			T4	235		T46	7		T62	166
alert_integrity_fail	alert[0x3e]	3828	1			T4	5		T5	148		T46	9
alert_integrity_fail	alert[0x3f]	2686	1			T25	67		T32	266		T56	1
alert_integrity_fail	alert[0x40]	8647	1			T4	120		T46	3		T62	9
alert_ping_fail	alert[0x0]	10	1			T307	1		T311	1		T312	1
alert_ping_fail	alert[0x1]	12	1			T6	1		T313	1		T311	2
alert_ping_fail	alert[0x2]	10	1			T7	1		T86	1		T311	1
alert_ping_fail	alert[0x3]	9	1			T6	1		T268	1		T314	2
alert_ping_fail	alert[0x4]	10	1			T309	1		T315	1		T316	1
alert_ping_fail	alert[0x5]	12	1			T70	1		T313	1		T231	2
alert_ping_fail	alert[0x6]	10	1			T313	1		T317	1		T309	1
alert_ping_fail	alert[0x7]	14	1			T307	1		T313	2		T318	1
alert_ping_fail	alert[0x8]	16	1			T313	1		T319	1		T254	1
alert_ping_fail	alert[0x9]	10	1			T307	1		T268	1		T320	1
alert_ping_fail	alert[0xa]	11	1			T321	2		T307	1		T317	1
alert_ping_fail	alert[0xb]	6	1			T313	2		T311	1		T318	1
alert_ping_fail	alert[0xc]	12	1			T322	1		T307	1		T313	1
alert_ping_fail	alert[0xd]	5	1			T307	1		T323	1		T311	1
alert_ping_fail	alert[0xe]	13	1			T8	1		T308	1		T86	1
alert_ping_fail	alert[0xf]	8	1			T307	1		T309	1		T324	1
alert_ping_fail	alert[0x10]	10	1			T86	2		T324	1		T314	1
alert_ping_fail	alert[0x11]	10	1			T322	1		T324	1		T325	1
alert_ping_fail	alert[0x12]	8	1			T313	1		T309	1		T231	1
alert_ping_fail	alert[0x13]	11	1			T311	1		T254	1		T326	1
alert_ping_fail	alert[0x14]	12	1			T7	1		T312	1		T327	2
alert_ping_fail	alert[0x15]	8	1			T313	1		T309	1		T86	1
alert_ping_fail	alert[0x16]	13	1			T305	2		T326	1		T316	2
alert_ping_fail	alert[0x17]	11	1			T309	2		T325	2		T254	1
alert_ping_fail	alert[0x18]	13	1			T7	1		T8	1		T311	1
alert_ping_fail	alert[0x19]	9	1			T307	1		T313	1		T324	1
alert_ping_fail	alert[0x1a]	13	1			T313	1		T231	3		T325	1
alert_ping_fail	alert[0x1b]	9	1			T6	1		T322	1		T324	1
alert_ping_fail	alert[0x1c]	9	1			T8	1		T70	2		T318	1
alert_ping_fail	alert[0x1d]	13	1			T308	1		T70	1		T86	1
alert_ping_fail	alert[0x1e]	5	1			T8	1		T316	1		T226	1
alert_ping_fail	alert[0x1f]	12	1			T313	1		T86	1		T312	1
alert_ping_fail	alert[0x20]	4	1			T321	1		T324	1		T328	1
alert_ping_fail	alert[0x21]	12	1			T8	1		T307	1		T313	1
alert_ping_fail	alert[0x22]	15	1			T321	2		T307	1		T309	1
alert_ping_fail	alert[0x23]	15	1			T7	1		T8	1		T308	1
alert_ping_fail	alert[0x24]	9	1			T6	2		T309	2		T326	1
alert_ping_fail	alert[0x25]	17	1			T7	1		T317	1		T231	2
alert_ping_fail	alert[0x26]	11	1			T307	1		T313	1		T309	1
alert_ping_fail	alert[0x27]	16	1			T308	1		T307	1		T324	1
alert_ping_fail	alert[0x28]	15	1			T308	1		T70	1		T309	1
alert_ping_fail	alert[0x29]	13	1			T307	1		T313	1		T318	1
alert_ping_fail	alert[0x2a]	14	1			T8	1		T308	1		T309	2
alert_ping_fail	alert[0x2b]	4	1			T312	1		T329	1		T330	1
alert_ping_fail	alert[0x2c]	5	1			T86	1		T312	1		T226	1
alert_ping_fail	alert[0x2d]	7	1			T308	1		T311	1		T320	1
alert_ping_fail	alert[0x2e]	13	1			T308	1		T309	1		T268	1
alert_ping_fail	alert[0x2f]	10	1			T86	2		T312	1		T331	1
alert_ping_fail	alert[0x30]	12	1			T86	2		T324	1		T332	1
alert_ping_fail	alert[0x31]	9	1			T6	1		T231	1		T324	1
alert_ping_fail	alert[0x32]	2	1			T308	1		T333	1		-	-
alert_ping_fail	alert[0x33]	11	1			T308	1		T322	1		T86	1
alert_ping_fail	alert[0x34]	16	1			T309	1		T86	1		T318	1
alert_ping_fail	alert[0x35]	9	1			T6	1		T324	1		T320	1
alert_ping_fail	alert[0x36]	4	1			T309	1		T226	1		T334	1
alert_ping_fail	alert[0x37]	10	1			T6	2		T8	1		T311	1
alert_ping_fail	alert[0x38]	9	1			T317	2		T318	1		T325	1
alert_ping_fail	alert[0x39]	12	1			T322	1		T307	1		T313	1
alert_ping_fail	alert[0x3a]	11	1			T308	2		T313	1		T320	1
alert_ping_fail	alert[0x3b]	10	1			T311	2		T312	1		T335	1
alert_ping_fail	alert[0x3c]	17	1			T6	3		T8	1		T308	2
alert_ping_fail	alert[0x3d]	13	1			T313	1		T325	3		T312	1
alert_ping_fail	alert[0x3e]	7	1			T313	1		T231	1		T325	1
alert_ping_fail	alert[0x3f]	5	1			T309	2		T318	1		T336	1
alert_ping_fail	alert[0x40]	4	1			T337	1		T328	1		T335	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	115280	1			T4	5637		T5	1048		T46	230
alert_integrity_fail	class_i[0x1]	31060	1			T4	83		T46	94		T62	4
alert_integrity_fail	class_i[0x2]	100691	1			T4	8		T5	1634		T23	48
alert_integrity_fail	class_i[0x3]	90529	1			T12	26		T5	393		T62	6068
alert_ping_fail	class_i[0x0]	194	1			T6	2		T8	1		T70	5
alert_ping_fail	class_i[0x1]	215	1			T6	7		T7	5		T305	2
alert_ping_fail	class_i[0x2]	174	1			T6	1		T8	7		T321	5
alert_ping_fail	class_i[0x3]	92	1			T6	2		T8	1		T308	14