Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.66 100.00 100.00 100.00 99.38 99.48


Total test records in report: 826
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T772 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2830917560 Mar 28 12:39:53 PM PDT 24 Mar 28 12:40:39 PM PDT 24 696076011 ps
T147 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3977033228 Mar 28 12:39:57 PM PDT 24 Mar 28 12:48:35 PM PDT 24 14224193238 ps
T155 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3194940140 Mar 28 12:39:36 PM PDT 24 Mar 28 12:57:26 PM PDT 24 16699290656 ps
T773 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.424718320 Mar 28 12:40:11 PM PDT 24 Mar 28 12:40:13 PM PDT 24 14149007 ps
T774 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.703379547 Mar 28 12:39:46 PM PDT 24 Mar 28 12:39:48 PM PDT 24 9393550 ps
T775 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2320808137 Mar 28 12:39:38 PM PDT 24 Mar 28 12:39:39 PM PDT 24 7494323 ps
T776 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3935211852 Mar 28 12:39:35 PM PDT 24 Mar 28 12:39:45 PM PDT 24 602774524 ps
T777 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.882498420 Mar 28 12:39:33 PM PDT 24 Mar 28 12:39:55 PM PDT 24 753379403 ps
T187 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1436377178 Mar 28 12:39:51 PM PDT 24 Mar 28 12:40:34 PM PDT 24 2552365193 ps
T778 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.230452366 Mar 28 12:39:36 PM PDT 24 Mar 28 12:39:38 PM PDT 24 7136605 ps
T779 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3470602584 Mar 28 12:39:34 PM PDT 24 Mar 28 12:40:14 PM PDT 24 501327890 ps
T780 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3802857944 Mar 28 12:39:37 PM PDT 24 Mar 28 12:39:39 PM PDT 24 8300168 ps
T781 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.803214379 Mar 28 12:39:59 PM PDT 24 Mar 28 12:40:09 PM PDT 24 876785293 ps
T782 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.111922995 Mar 28 12:39:50 PM PDT 24 Mar 28 12:39:52 PM PDT 24 8438730 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2808216047 Mar 28 12:39:39 PM PDT 24 Mar 28 12:39:41 PM PDT 24 9937078 ps
T189 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.43109263 Mar 28 12:39:39 PM PDT 24 Mar 28 12:40:22 PM PDT 24 600535506 ps
T177 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2654563682 Mar 28 12:39:36 PM PDT 24 Mar 28 12:40:12 PM PDT 24 1793614209 ps
T784 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.476238258 Mar 28 12:40:06 PM PDT 24 Mar 28 12:40:13 PM PDT 24 43944259 ps
T785 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3284635731 Mar 28 12:39:40 PM PDT 24 Mar 28 12:39:41 PM PDT 24 11446416 ps
T786 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3070030317 Mar 28 12:39:33 PM PDT 24 Mar 28 12:39:46 PM PDT 24 364837585 ps
T787 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1815761500 Mar 28 12:39:34 PM PDT 24 Mar 28 12:39:41 PM PDT 24 362609197 ps
T788 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2484989967 Mar 28 12:39:50 PM PDT 24 Mar 28 12:39:52 PM PDT 24 61434021 ps
T173 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3710752807 Mar 28 12:39:36 PM PDT 24 Mar 28 12:41:03 PM PDT 24 2518738935 ps
T789 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2216270889 Mar 28 12:39:34 PM PDT 24 Mar 28 12:39:40 PM PDT 24 39059071 ps
T790 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3516368026 Mar 28 12:39:38 PM PDT 24 Mar 28 12:39:46 PM PDT 24 1914286376 ps
T791 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1246656821 Mar 28 12:39:39 PM PDT 24 Mar 28 12:39:48 PM PDT 24 529271123 ps
T792 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.283919648 Mar 28 12:39:38 PM PDT 24 Mar 28 12:40:15 PM PDT 24 979243525 ps
T793 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3646723726 Mar 28 12:39:33 PM PDT 24 Mar 28 12:46:03 PM PDT 24 22886221132 ps
T794 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2589799548 Mar 28 12:39:34 PM PDT 24 Mar 28 12:41:23 PM PDT 24 3157250881 ps
T277 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.390464130 Mar 28 12:39:39 PM PDT 24 Mar 28 12:39:44 PM PDT 24 59928080 ps
T795 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.255281743 Mar 28 12:39:40 PM PDT 24 Mar 28 12:39:48 PM PDT 24 76081162 ps
T163 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.73375737 Mar 28 12:39:54 PM PDT 24 Mar 28 12:44:38 PM PDT 24 2188542619 ps
T796 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2138954695 Mar 28 12:39:36 PM PDT 24 Mar 28 12:39:38 PM PDT 24 10430833 ps
T797 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3674412764 Mar 28 12:39:39 PM PDT 24 Mar 28 12:39:45 PM PDT 24 60795238 ps
T798 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.329949625 Mar 28 12:39:39 PM PDT 24 Mar 28 12:40:02 PM PDT 24 168617250 ps
T799 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2190855433 Mar 28 12:39:39 PM PDT 24 Mar 28 12:39:48 PM PDT 24 120168248 ps
T800 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1321163028 Mar 28 12:40:02 PM PDT 24 Mar 28 12:40:04 PM PDT 24 10174452 ps
T801 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.706262056 Mar 28 12:39:38 PM PDT 24 Mar 28 12:39:39 PM PDT 24 14986915 ps
T802 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1994076258 Mar 28 12:39:37 PM PDT 24 Mar 28 12:39:55 PM PDT 24 256751418 ps
T803 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1725713623 Mar 28 12:39:40 PM PDT 24 Mar 28 12:39:52 PM PDT 24 336356896 ps
T152 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2956895445 Mar 28 12:39:54 PM PDT 24 Mar 28 12:45:56 PM PDT 24 5457181954 ps
T804 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2632455575 Mar 28 12:39:32 PM PDT 24 Mar 28 12:40:34 PM PDT 24 623094085 ps
T188 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.612315857 Mar 28 12:39:30 PM PDT 24 Mar 28 12:40:39 PM PDT 24 14778623642 ps
T179 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.44238121 Mar 28 12:39:18 PM PDT 24 Mar 28 12:40:00 PM PDT 24 1873287892 ps
T805 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2346058795 Mar 28 12:39:40 PM PDT 24 Mar 28 12:40:02 PM PDT 24 1029179270 ps
T806 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.680747482 Mar 28 12:40:09 PM PDT 24 Mar 28 12:40:11 PM PDT 24 20925155 ps
T807 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3265975613 Mar 28 12:39:39 PM PDT 24 Mar 28 12:39:49 PM PDT 24 52993416 ps
T153 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2431306538 Mar 28 12:39:37 PM PDT 24 Mar 28 12:58:00 PM PDT 24 18062352772 ps
T161 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.769918936 Mar 28 12:39:54 PM PDT 24 Mar 28 12:49:36 PM PDT 24 102315320482 ps
T808 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3621443451 Mar 28 12:39:39 PM PDT 24 Mar 28 12:39:51 PM PDT 24 371560004 ps
T156 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.446482540 Mar 28 12:39:51 PM PDT 24 Mar 28 12:46:37 PM PDT 24 11918406295 ps
T162 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4007051878 Mar 28 12:39:35 PM PDT 24 Mar 28 12:58:21 PM PDT 24 18757395903 ps
T809 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2112272675 Mar 28 12:39:38 PM PDT 24 Mar 28 12:39:51 PM PDT 24 728781756 ps
T166 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3730795973 Mar 28 12:39:39 PM PDT 24 Mar 28 12:42:44 PM PDT 24 2929535224 ps
T810 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3832755438 Mar 28 12:39:33 PM PDT 24 Mar 28 12:39:48 PM PDT 24 2944555199 ps
T811 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1423575587 Mar 28 12:40:00 PM PDT 24 Mar 28 12:40:01 PM PDT 24 6408733 ps
T812 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2101188614 Mar 28 12:40:14 PM PDT 24 Mar 28 12:40:15 PM PDT 24 12636859 ps
T813 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2517419510 Mar 28 12:39:39 PM PDT 24 Mar 28 12:39:44 PM PDT 24 66944105 ps
T164 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3689335955 Mar 28 12:39:35 PM PDT 24 Mar 28 12:58:40 PM PDT 24 64378956029 ps
T175 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2684897236 Mar 28 12:39:48 PM PDT 24 Mar 28 12:40:27 PM PDT 24 664954254 ps
T165 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4241968912 Mar 28 12:39:40 PM PDT 24 Mar 28 12:47:20 PM PDT 24 16396770109 ps
T158 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2205633628 Mar 28 12:39:43 PM PDT 24 Mar 28 12:42:57 PM PDT 24 6138091232 ps
T814 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.664858801 Mar 28 12:39:29 PM PDT 24 Mar 28 12:41:15 PM PDT 24 1122115665 ps
T815 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.552624744 Mar 28 12:39:39 PM PDT 24 Mar 28 12:39:45 PM PDT 24 117652825 ps
T816 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3450494697 Mar 28 12:39:33 PM PDT 24 Mar 28 12:39:41 PM PDT 24 303877632 ps
T817 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1658327787 Mar 28 12:39:40 PM PDT 24 Mar 28 12:39:41 PM PDT 24 8924875 ps
T818 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1536340667 Mar 28 12:40:01 PM PDT 24 Mar 28 12:40:23 PM PDT 24 1072776924 ps
T819 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2018563948 Mar 28 12:40:03 PM PDT 24 Mar 28 12:40:17 PM PDT 24 395637665 ps
T820 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1071170129 Mar 28 12:39:38 PM PDT 24 Mar 28 12:39:47 PM PDT 24 201332995 ps
T360 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1186876683 Mar 28 12:39:38 PM PDT 24 Mar 28 12:47:33 PM PDT 24 24007752854 ps
T821 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2000163646 Mar 28 12:39:39 PM PDT 24 Mar 28 12:39:40 PM PDT 24 8259720 ps
T822 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1171239422 Mar 28 12:39:32 PM PDT 24 Mar 28 12:41:13 PM PDT 24 5663063409 ps
T823 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4194744705 Mar 28 12:40:00 PM PDT 24 Mar 28 12:40:02 PM PDT 24 10751161 ps
T824 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3952006765 Mar 28 12:39:15 PM PDT 24 Mar 28 12:43:22 PM PDT 24 17797390676 ps
T825 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2172162913 Mar 28 12:39:10 PM PDT 24 Mar 28 12:39:16 PM PDT 24 33679097 ps
T826 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1939515483 Mar 28 12:39:38 PM PDT 24 Mar 28 12:39:49 PM PDT 24 262627923 ps

Test location /workspace/coverage/default/8.alert_handler_stress_all.3831502115
Short name T12
Test name
Test status
Simulation time 169475131051 ps
CPU time 2798.24 seconds
Started Mar 28 01:12:36 PM PDT 24
Finished Mar 28 01:59:15 PM PDT 24
Peak memory 289508 kb
Host smart-44850198-f36c-45bf-8ab8-48b870b6da90
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831502115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3831502115
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.458111292
Short name T5
Test name
Test status
Simulation time 227337630291 ps
CPU time 4344.2 seconds
Started Mar 28 01:13:19 PM PDT 24
Finished Mar 28 02:25:43 PM PDT 24
Peak memory 322056 kb
Host smart-69f03894-6539-4175-a4e8-f2d7aff6bd4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458111292 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.458111292
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1928286626
Short name T10
Test name
Test status
Simulation time 948883088 ps
CPU time 25.02 seconds
Started Mar 28 01:12:06 PM PDT 24
Finished Mar 28 01:12:31 PM PDT 24
Peak memory 270584 kb
Host smart-8a8e0159-6a31-4533-a86a-483486e4d612
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1928286626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1928286626
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3092065023
Short name T196
Test name
Test status
Simulation time 138679377 ps
CPU time 9.05 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 12:39:45 PM PDT 24
Peak memory 236528 kb
Host smart-fc4ebc89-4bbf-4c88-8de6-c1b709408f36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3092065023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3092065023
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.960620291
Short name T29
Test name
Test status
Simulation time 29126258534 ps
CPU time 1011.97 seconds
Started Mar 28 01:12:34 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 283068 kb
Host smart-fa75528b-58c8-4caa-b447-adf112f20619
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960620291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.960620291
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2566875110
Short name T32
Test name
Test status
Simulation time 113442359361 ps
CPU time 2092.2 seconds
Started Mar 28 01:14:57 PM PDT 24
Finished Mar 28 01:49:50 PM PDT 24
Peak memory 281784 kb
Host smart-276d8490-6b7f-4c06-99b0-f9e5e74d8d88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566875110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2566875110
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1299854566
Short name T97
Test name
Test status
Simulation time 92253805617 ps
CPU time 995.65 seconds
Started Mar 28 01:13:44 PM PDT 24
Finished Mar 28 01:30:20 PM PDT 24
Peak memory 272104 kb
Host smart-ec563d73-4323-4611-93fc-1ccae6b1c0cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299854566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1299854566
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.815199404
Short name T35
Test name
Test status
Simulation time 102387705814 ps
CPU time 2960.47 seconds
Started Mar 28 01:14:06 PM PDT 24
Finished Mar 28 02:03:27 PM PDT 24
Peak memory 289052 kb
Host smart-5ec3e45e-6c9d-4468-a299-39d5997567cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815199404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.815199404
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.267714740
Short name T134
Test name
Test status
Simulation time 12020123788 ps
CPU time 870.65 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 12:54:06 PM PDT 24
Peak memory 265228 kb
Host smart-9c53de28-9881-4c2e-9c69-aedaf8836040
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267714740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.267714740
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.4091253924
Short name T340
Test name
Test status
Simulation time 122725252624 ps
CPU time 1819.38 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:42:59 PM PDT 24
Peak memory 265400 kb
Host smart-261c6de8-87a8-4c61-b9de-38ef0fa6b9f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091253924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4091253924
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3366017291
Short name T133
Test name
Test status
Simulation time 3808473691 ps
CPU time 307.58 seconds
Started Mar 28 12:39:54 PM PDT 24
Finished Mar 28 12:45:02 PM PDT 24
Peak memory 270356 kb
Host smart-78fe376d-3b3e-4b4d-8736-c34537bd5cf8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3366017291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3366017291
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2060990006
Short name T127
Test name
Test status
Simulation time 2043150530 ps
CPU time 7.58 seconds
Started Mar 28 01:12:52 PM PDT 24
Finished Mar 28 01:13:00 PM PDT 24
Peak memory 240744 kb
Host smart-889ece04-5f56-4479-a572-14b7599517d7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2060990006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2060990006
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3773667250
Short name T86
Test name
Test status
Simulation time 11478063476 ps
CPU time 475.47 seconds
Started Mar 28 01:14:28 PM PDT 24
Finished Mar 28 01:22:24 PM PDT 24
Peak memory 247928 kb
Host smart-438c87bf-35ce-430a-b8de-91c5446bc9ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773667250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3773667250
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2956895445
Short name T152
Test name
Test status
Simulation time 5457181954 ps
CPU time 361.7 seconds
Started Mar 28 12:39:54 PM PDT 24
Finished Mar 28 12:45:56 PM PDT 24
Peak memory 271276 kb
Host smart-db7c2d9d-56bc-4f9f-9767-24710535d193
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2956895445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2956895445
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2772793062
Short name T101
Test name
Test status
Simulation time 78853564036 ps
CPU time 8611.28 seconds
Started Mar 28 01:13:07 PM PDT 24
Finished Mar 28 03:36:40 PM PDT 24
Peak memory 393752 kb
Host smart-6f88491d-7973-4710-973a-4c9b13327e3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772793062 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2772793062
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2190071465
Short name T186
Test name
Test status
Simulation time 1005596037 ps
CPU time 69.57 seconds
Started Mar 28 12:39:53 PM PDT 24
Finished Mar 28 12:41:03 PM PDT 24
Peak memory 240232 kb
Host smart-0076b472-2275-4516-ab33-aea2ca0daa4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2190071465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2190071465
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2313194737
Short name T26
Test name
Test status
Simulation time 123404610091 ps
CPU time 2106.7 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:48:08 PM PDT 24
Peak memory 290024 kb
Host smart-baba44c3-fe0b-4169-b448-0033eda6f32f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313194737 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2313194737
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1180964184
Short name T336
Test name
Test status
Simulation time 10302406793 ps
CPU time 418.57 seconds
Started Mar 28 01:12:39 PM PDT 24
Finished Mar 28 01:19:38 PM PDT 24
Peak memory 248392 kb
Host smart-19045eed-9514-495d-bfcd-02139bda5d40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180964184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1180964184
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3425190310
Short name T142
Test name
Test status
Simulation time 21040886308 ps
CPU time 286.24 seconds
Started Mar 28 12:40:02 PM PDT 24
Finished Mar 28 12:44:48 PM PDT 24
Peak memory 265180 kb
Host smart-81b93957-f1d1-413a-917f-28e831f710c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3425190310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3425190310
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.255338352
Short name T89
Test name
Test status
Simulation time 32999138183 ps
CPU time 2387.2 seconds
Started Mar 28 01:11:51 PM PDT 24
Finished Mar 28 01:51:39 PM PDT 24
Peak memory 281496 kb
Host smart-1ebe7bfc-4fc2-41f5-9fd9-e55217f61246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255338352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.255338352
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.4120821235
Short name T159
Test name
Test status
Simulation time 52648261554 ps
CPU time 912.44 seconds
Started Mar 28 12:39:54 PM PDT 24
Finished Mar 28 12:55:06 PM PDT 24
Peak memory 265112 kb
Host smart-72ae7b67-36d7-4691-ab47-1c93227d774b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120821235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.4120821235
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.737007590
Short name T352
Test name
Test status
Simulation time 27989053 ps
CPU time 1.37 seconds
Started Mar 28 12:39:31 PM PDT 24
Finished Mar 28 12:39:32 PM PDT 24
Peak memory 235620 kb
Host smart-84ffb02f-2900-484f-a282-1dec5a391102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=737007590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.737007590
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1298208869
Short name T70
Test name
Test status
Simulation time 437564555229 ps
CPU time 2593.62 seconds
Started Mar 28 01:12:42 PM PDT 24
Finished Mar 28 01:55:57 PM PDT 24
Peak memory 286752 kb
Host smart-7b0d90e6-c2e8-4597-aedf-532c662e7041
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298208869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1298208869
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1616631741
Short name T4
Test name
Test status
Simulation time 30437148040 ps
CPU time 1512.57 seconds
Started Mar 28 01:11:53 PM PDT 24
Finished Mar 28 01:37:06 PM PDT 24
Peak memory 289840 kb
Host smart-19d20f84-156e-464b-90c1-6ddde2b68349
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616631741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1616631741
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.123090490
Short name T154
Test name
Test status
Simulation time 92313598831 ps
CPU time 1118.11 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:58:10 PM PDT 24
Peak memory 265096 kb
Host smart-b7748b3a-8e1b-4e6c-af25-640b599d2352
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123090490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.123090490
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1624385319
Short name T243
Test name
Test status
Simulation time 144065893026 ps
CPU time 2530.23 seconds
Started Mar 28 01:14:28 PM PDT 24
Finished Mar 28 01:56:38 PM PDT 24
Peak memory 288964 kb
Host smart-aba3eba3-fa2f-44b0-93db-43254668cc19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624385319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1624385319
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2441621619
Short name T313
Test name
Test status
Simulation time 16837760907 ps
CPU time 478.46 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:20:39 PM PDT 24
Peak memory 248084 kb
Host smart-cc3ec175-d1b3-47af-9f11-ca41561c58c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441621619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2441621619
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2176342954
Short name T326
Test name
Test status
Simulation time 55940686764 ps
CPU time 601.18 seconds
Started Mar 28 01:12:42 PM PDT 24
Finished Mar 28 01:22:45 PM PDT 24
Peak memory 248268 kb
Host smart-4b505ba2-5b72-4ad7-b659-1f1551657459
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176342954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2176342954
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3080556354
Short name T139
Test name
Test status
Simulation time 5476250181 ps
CPU time 349.9 seconds
Started Mar 28 12:39:37 PM PDT 24
Finished Mar 28 12:45:27 PM PDT 24
Peak memory 270328 kb
Host smart-0a7d5af7-a06e-4508-9c1c-68d7d6143d43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3080556354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3080556354
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2191379852
Short name T144
Test name
Test status
Simulation time 15502242533 ps
CPU time 1006.82 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:56:07 PM PDT 24
Peak memory 265188 kb
Host smart-85560bd5-83ac-4a1c-9299-e69bda72f492
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191379852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2191379852
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3868137824
Short name T282
Test name
Test status
Simulation time 44123081163 ps
CPU time 2298.07 seconds
Started Mar 28 01:14:58 PM PDT 24
Finished Mar 28 01:53:16 PM PDT 24
Peak memory 288796 kb
Host smart-705be71d-d961-4ed7-b40f-51c34ece06d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868137824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3868137824
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.476208804
Short name T306
Test name
Test status
Simulation time 38755367542 ps
CPU time 2128.82 seconds
Started Mar 28 01:14:05 PM PDT 24
Finished Mar 28 01:49:35 PM PDT 24
Peak memory 273512 kb
Host smart-49397ca7-f30e-45f6-a227-1f5743e6c253
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476208804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.476208804
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2205633628
Short name T158
Test name
Test status
Simulation time 6138091232 ps
CPU time 194.55 seconds
Started Mar 28 12:39:43 PM PDT 24
Finished Mar 28 12:42:57 PM PDT 24
Peak memory 270676 kb
Host smart-f71d9665-4987-4d9c-a258-68b30fbb6c3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2205633628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2205633628
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.313599963
Short name T268
Test name
Test status
Simulation time 9642123924 ps
CPU time 399.3 seconds
Started Mar 28 01:14:23 PM PDT 24
Finished Mar 28 01:21:03 PM PDT 24
Peak memory 247968 kb
Host smart-372f4296-f409-4744-85ac-0c2d8f4c49c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313599963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.313599963
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3872578940
Short name T149
Test name
Test status
Simulation time 16562464843 ps
CPU time 600.13 seconds
Started Mar 28 12:39:29 PM PDT 24
Finished Mar 28 12:49:29 PM PDT 24
Peak memory 265132 kb
Host smart-a23c8e92-3362-4d2d-a09e-fbb8bc5d6dd4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872578940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3872578940
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2455336051
Short name T338
Test name
Test status
Simulation time 48239523059 ps
CPU time 1351.88 seconds
Started Mar 28 01:13:43 PM PDT 24
Finished Mar 28 01:36:15 PM PDT 24
Peak memory 265352 kb
Host smart-69602e5f-5cc2-4360-9840-13ea231ad08b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455336051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2455336051
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.751180230
Short name T270
Test name
Test status
Simulation time 94921278398 ps
CPU time 2977.34 seconds
Started Mar 28 01:14:59 PM PDT 24
Finished Mar 28 02:04:36 PM PDT 24
Peak memory 320188 kb
Host smart-7dee1f71-8716-4250-919b-dbc890d7928b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751180230 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.751180230
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.584384337
Short name T286
Test name
Test status
Simulation time 240270489302 ps
CPU time 4189 seconds
Started Mar 28 01:14:58 PM PDT 24
Finished Mar 28 02:24:48 PM PDT 24
Peak memory 306012 kb
Host smart-576e8ebf-3d37-4355-bbff-d7465d43c6b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584384337 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.584384337
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1800087690
Short name T171
Test name
Test status
Simulation time 9869595 ps
CPU time 1.66 seconds
Started Mar 28 12:39:54 PM PDT 24
Finished Mar 28 12:39:56 PM PDT 24
Peak memory 235668 kb
Host smart-32edd8bf-06e0-4496-a271-23a05e3a3828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1800087690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1800087690
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2070343721
Short name T330
Test name
Test status
Simulation time 10094998678 ps
CPU time 419.22 seconds
Started Mar 28 01:12:51 PM PDT 24
Finished Mar 28 01:19:51 PM PDT 24
Peak memory 247092 kb
Host smart-491aee67-9f4a-4a96-bdaa-47f2c5e30869
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070343721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2070343721
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3956862520
Short name T93
Test name
Test status
Simulation time 9272457260 ps
CPU time 1202.29 seconds
Started Mar 28 01:12:52 PM PDT 24
Finished Mar 28 01:32:54 PM PDT 24
Peak memory 286828 kb
Host smart-3277fbf4-9d4d-4a10-b510-b068d062d3cc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956862520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3956862520
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2381732675
Short name T23
Test name
Test status
Simulation time 2442792268 ps
CPU time 35.61 seconds
Started Mar 28 01:12:37 PM PDT 24
Finished Mar 28 01:13:13 PM PDT 24
Peak memory 249004 kb
Host smart-ba78acc6-cf2a-4a1a-a2a7-d7fd76e098a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23817
32675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2381732675
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3137105309
Short name T135
Test name
Test status
Simulation time 6361992904 ps
CPU time 197.48 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:42:56 PM PDT 24
Peak memory 266340 kb
Host smart-f88cf614-8f47-499b-8bae-6ad3b0f3b63e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3137105309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3137105309
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1721545744
Short name T254
Test name
Test status
Simulation time 8942618275 ps
CPU time 381.59 seconds
Started Mar 28 01:12:59 PM PDT 24
Finished Mar 28 01:19:22 PM PDT 24
Peak memory 246992 kb
Host smart-33bc847c-c56f-4718-aacc-c2b1dbf93831
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721545744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1721545744
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1812881998
Short name T31
Test name
Test status
Simulation time 107724769244 ps
CPU time 1517.58 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 01:38:20 PM PDT 24
Peak memory 272480 kb
Host smart-b9f085d9-8f11-4e9f-b986-580ea9a52950
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812881998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1812881998
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3008709445
Short name T136
Test name
Test status
Simulation time 5160854927 ps
CPU time 348.08 seconds
Started Mar 28 12:40:13 PM PDT 24
Finished Mar 28 12:46:02 PM PDT 24
Peak memory 265060 kb
Host smart-c3ee3a48-a91c-4cc5-a9be-c803174237a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3008709445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3008709445
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2047505302
Short name T47
Test name
Test status
Simulation time 16225138566 ps
CPU time 981.24 seconds
Started Mar 28 01:13:00 PM PDT 24
Finished Mar 28 01:29:22 PM PDT 24
Peak memory 273628 kb
Host smart-1d27dd06-199f-46b3-b1c7-8b29a94f8669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047505302 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2047505302
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3792998030
Short name T21
Test name
Test status
Simulation time 6538465396 ps
CPU time 288.74 seconds
Started Mar 28 01:12:42 PM PDT 24
Finished Mar 28 01:17:33 PM PDT 24
Peak memory 255852 kb
Host smart-e95c49e9-71fb-4618-b1de-7df20f54fb3a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792998030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3792998030
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2689471368
Short name T22
Test name
Test status
Simulation time 249791545199 ps
CPU time 2722.57 seconds
Started Mar 28 01:14:57 PM PDT 24
Finished Mar 28 02:00:21 PM PDT 24
Peak memory 288952 kb
Host smart-43a464a6-8d12-4353-98d0-30d6d74d5bd6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689471368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2689471368
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3268193797
Short name T201
Test name
Test status
Simulation time 38459149 ps
CPU time 3.31 seconds
Started Mar 28 01:11:53 PM PDT 24
Finished Mar 28 01:11:56 PM PDT 24
Peak memory 249116 kb
Host smart-f0747ead-a9d6-49c5-a4d4-b5c5e871e9ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3268193797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3268193797
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2159630731
Short name T203
Test name
Test status
Simulation time 56881711 ps
CPU time 3.98 seconds
Started Mar 28 01:11:49 PM PDT 24
Finished Mar 28 01:11:53 PM PDT 24
Peak memory 249096 kb
Host smart-a4f5cf81-0e39-44fc-b732-d2edc69817bd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2159630731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2159630731
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1202715578
Short name T206
Test name
Test status
Simulation time 81269276 ps
CPU time 3.53 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:12:43 PM PDT 24
Peak memory 249132 kb
Host smart-8649cf63-3475-4cef-8ea3-17253fbd4cbb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1202715578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1202715578
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1727937239
Short name T205
Test name
Test status
Simulation time 18242210 ps
CPU time 2.53 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:12:45 PM PDT 24
Peak memory 249136 kb
Host smart-840a4e5f-9b79-4964-8597-1bf21e646fd0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1727937239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1727937239
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2431306538
Short name T153
Test name
Test status
Simulation time 18062352772 ps
CPU time 1102.24 seconds
Started Mar 28 12:39:37 PM PDT 24
Finished Mar 28 12:58:00 PM PDT 24
Peak memory 265276 kb
Host smart-691e7703-c246-4f89-9dd9-780b0c921708
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431306538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2431306538
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2160203856
Short name T355
Test name
Test status
Simulation time 8183013 ps
CPU time 1.44 seconds
Started Mar 28 12:39:52 PM PDT 24
Finished Mar 28 12:39:54 PM PDT 24
Peak memory 236640 kb
Host smart-282fc51e-8fdb-4d02-bf01-e1927ad1336b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2160203856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2160203856
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3989620294
Short name T311
Test name
Test status
Simulation time 53801142400 ps
CPU time 508.88 seconds
Started Mar 28 01:11:51 PM PDT 24
Finished Mar 28 01:20:20 PM PDT 24
Peak memory 247872 kb
Host smart-5f0ef0e8-ae0d-4e12-82d7-e18f1f06a4b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989620294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3989620294
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2220736011
Short name T275
Test name
Test status
Simulation time 44086539066 ps
CPU time 799.88 seconds
Started Mar 28 01:12:33 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 272680 kb
Host smart-ca13f032-1cb9-465a-9fa2-bd37716e8dae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220736011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2220736011
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3491480090
Short name T288
Test name
Test status
Simulation time 1643070996 ps
CPU time 25.58 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:13:06 PM PDT 24
Peak memory 255084 kb
Host smart-2f56f65d-5b25-4f49-9823-50236e020156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34914
80090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3491480090
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.90050888
Short name T226
Test name
Test status
Simulation time 16754899754 ps
CPU time 352.47 seconds
Started Mar 28 01:13:04 PM PDT 24
Finished Mar 28 01:18:56 PM PDT 24
Peak memory 248128 kb
Host smart-6ddc65bd-92da-4ef2-a8bb-30957ffa43fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90050888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.90050888
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1162364032
Short name T657
Test name
Test status
Simulation time 18719067978 ps
CPU time 1308.26 seconds
Started Mar 28 01:13:19 PM PDT 24
Finished Mar 28 01:35:08 PM PDT 24
Peak memory 285600 kb
Host smart-0f84f2ee-11f4-4275-849b-eaac096ec8ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162364032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1162364032
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1643736610
Short name T296
Test name
Test status
Simulation time 1228811831 ps
CPU time 35.99 seconds
Started Mar 28 01:13:27 PM PDT 24
Finished Mar 28 01:14:03 PM PDT 24
Peak memory 254716 kb
Host smart-89e3641b-d63c-4a16-ad13-db5e8e3dc4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16437
36610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1643736610
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2250525152
Short name T79
Test name
Test status
Simulation time 2315926025 ps
CPU time 127.16 seconds
Started Mar 28 01:14:06 PM PDT 24
Finished Mar 28 01:16:14 PM PDT 24
Peak memory 257088 kb
Host smart-c9b51162-4b6b-48bf-ae94-6f2712a398f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250525152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2250525152
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1788452996
Short name T140
Test name
Test status
Simulation time 14508570451 ps
CPU time 212.99 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:42:54 PM PDT 24
Peak memory 267092 kb
Host smart-a9b4a366-393c-437c-b0ad-35381609e0e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1788452996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1788452996
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1671056431
Short name T169
Test name
Test status
Simulation time 59108229 ps
CPU time 3.78 seconds
Started Mar 28 12:39:37 PM PDT 24
Finished Mar 28 12:39:41 PM PDT 24
Peak memory 235672 kb
Host smart-566b1741-4b7f-46f0-9a64-81aa378fd6b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1671056431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1671056431
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2891198238
Short name T308
Test name
Test status
Simulation time 20740622385 ps
CPU time 469.88 seconds
Started Mar 28 01:14:48 PM PDT 24
Finished Mar 28 01:22:38 PM PDT 24
Peak memory 247832 kb
Host smart-94020b97-f4c4-47b7-836d-32f9f4af9ea1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891198238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2891198238
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.136180291
Short name T27
Test name
Test status
Simulation time 61052722760 ps
CPU time 6264.02 seconds
Started Mar 28 01:13:44 PM PDT 24
Finished Mar 28 02:58:09 PM PDT 24
Peak memory 371884 kb
Host smart-bab17012-6839-4780-956a-fdf77f65230d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136180291 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.136180291
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1033153019
Short name T627
Test name
Test status
Simulation time 9311989395 ps
CPU time 834.03 seconds
Started Mar 28 01:12:36 PM PDT 24
Finished Mar 28 01:26:31 PM PDT 24
Peak memory 273544 kb
Host smart-a2702acd-affe-450f-b034-63687504703c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033153019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1033153019
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1187345061
Short name T264
Test name
Test status
Simulation time 81771181510 ps
CPU time 1436.55 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:36:37 PM PDT 24
Peak memory 289296 kb
Host smart-0736ccfa-3a8a-43cd-b091-51f8bad722b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187345061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1187345061
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2683343885
Short name T562
Test name
Test status
Simulation time 81503883058 ps
CPU time 300.34 seconds
Started Mar 28 01:12:59 PM PDT 24
Finished Mar 28 01:18:00 PM PDT 24
Peak memory 247848 kb
Host smart-7ad6c303-3b5e-41d1-87c4-302cf2f4c61e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683343885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2683343885
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1548160894
Short name T285
Test name
Test status
Simulation time 92107604549 ps
CPU time 2691.24 seconds
Started Mar 28 01:12:54 PM PDT 24
Finished Mar 28 01:57:46 PM PDT 24
Peak memory 289836 kb
Host smart-1d999f63-844f-49bc-9424-3ac352b13301
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548160894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1548160894
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.647720695
Short name T273
Test name
Test status
Simulation time 2992031750 ps
CPU time 160.35 seconds
Started Mar 28 01:13:00 PM PDT 24
Finished Mar 28 01:15:40 PM PDT 24
Peak memory 257124 kb
Host smart-95b0d122-295b-48fe-89e0-2d6393313d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64772
0695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.647720695
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1639583056
Short name T290
Test name
Test status
Simulation time 122862694113 ps
CPU time 4902.52 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 02:34:45 PM PDT 24
Peak memory 305848 kb
Host smart-654e9ae9-5db6-47d6-b63f-b610a17ba599
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639583056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1639583056
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1595258676
Short name T302
Test name
Test status
Simulation time 1032696053 ps
CPU time 58.04 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 01:15:05 PM PDT 24
Peak memory 256000 kb
Host smart-59fa69ed-b55e-4f89-bde0-c28d1848bde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15952
58676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1595258676
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1713650384
Short name T297
Test name
Test status
Simulation time 469211805 ps
CPU time 31.75 seconds
Started Mar 28 01:12:09 PM PDT 24
Finished Mar 28 01:12:41 PM PDT 24
Peak memory 247884 kb
Host smart-78ea2a6d-7eab-4646-91ca-d7e47b4e9487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17136
50384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1713650384
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2890302823
Short name T341
Test name
Test status
Simulation time 16028062819 ps
CPU time 1203.57 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:32:12 PM PDT 24
Peak memory 289492 kb
Host smart-e5075822-5e00-4c68-b915-53fcf6f6b44b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890302823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2890302823
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3104968243
Short name T9
Test name
Test status
Simulation time 685225193 ps
CPU time 10.72 seconds
Started Mar 28 01:11:51 PM PDT 24
Finished Mar 28 01:12:02 PM PDT 24
Peak memory 265504 kb
Host smart-784bc3b5-5589-45d5-a09c-834a9b323db9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3104968243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3104968243
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2084580426
Short name T180
Test name
Test status
Simulation time 646053162 ps
CPU time 43.01 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:40:15 PM PDT 24
Peak memory 239464 kb
Host smart-1afd318f-7ea6-4875-8d34-5526e656a5ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2084580426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2084580426
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.44238121
Short name T179
Test name
Test status
Simulation time 1873287892 ps
CPU time 40.01 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:40:00 PM PDT 24
Peak memory 248436 kb
Host smart-285b9b52-48bb-419d-a4d6-d526291cd2fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=44238121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.44238121
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.825745439
Short name T150
Test name
Test status
Simulation time 784376449 ps
CPU time 92.77 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:41:05 PM PDT 24
Peak memory 265024 kb
Host smart-86bb560f-9633-42d1-9238-fbdd44077e5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=825745439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.825745439
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.4173387333
Short name T174
Test name
Test status
Simulation time 1759199420 ps
CPU time 34.79 seconds
Started Mar 28 12:39:52 PM PDT 24
Finished Mar 28 12:40:27 PM PDT 24
Peak memory 240236 kb
Host smart-a192c45f-188d-4890-a3c1-3ca0a48f2b18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4173387333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.4173387333
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1475807760
Short name T131
Test name
Test status
Simulation time 6197534544 ps
CPU time 462.93 seconds
Started Mar 28 12:40:02 PM PDT 24
Finished Mar 28 12:47:45 PM PDT 24
Peak memory 269616 kb
Host smart-484e1dda-c234-4101-b38e-c2a72280656d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475807760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1475807760
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2899676721
Short name T182
Test name
Test status
Simulation time 40691813 ps
CPU time 2.54 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:36 PM PDT 24
Peak memory 237812 kb
Host smart-44c78eb7-ef5f-4d6c-bb64-8fac8802f639
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2899676721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2899676721
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.446482540
Short name T156
Test name
Test status
Simulation time 11918406295 ps
CPU time 405.49 seconds
Started Mar 28 12:39:51 PM PDT 24
Finished Mar 28 12:46:37 PM PDT 24
Peak memory 265016 kb
Host smart-79dbfb21-210a-4772-99ca-7b50945552a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=446482540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.446482540
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1568624599
Short name T168
Test name
Test status
Simulation time 36720136 ps
CPU time 3.06 seconds
Started Mar 28 12:39:37 PM PDT 24
Finished Mar 28 12:39:40 PM PDT 24
Peak memory 236544 kb
Host smart-31afca04-0cdd-4d00-a21c-b4e8df83d957
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1568624599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1568624599
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.908080785
Short name T176
Test name
Test status
Simulation time 241210615 ps
CPU time 3.04 seconds
Started Mar 28 12:39:40 PM PDT 24
Finished Mar 28 12:39:43 PM PDT 24
Peak memory 236920 kb
Host smart-7c822585-ad9a-452e-92d7-94f4c013e6db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=908080785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.908080785
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1647505925
Short name T181
Test name
Test status
Simulation time 3693044984 ps
CPU time 37.97 seconds
Started Mar 28 12:39:31 PM PDT 24
Finished Mar 28 12:40:09 PM PDT 24
Peak memory 245200 kb
Host smart-a8c26912-e93c-40e5-a6ac-519c74b60750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1647505925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1647505925
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2546632991
Short name T167
Test name
Test status
Simulation time 209591906 ps
CPU time 3.95 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:39:42 PM PDT 24
Peak memory 236680 kb
Host smart-52be1847-14ee-45dc-a1a0-9258ed049079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2546632991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2546632991
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2654563682
Short name T177
Test name
Test status
Simulation time 1793614209 ps
CPU time 35.56 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 12:40:12 PM PDT 24
Peak memory 239464 kb
Host smart-c8b332c6-89f8-4613-912d-13f4d604e50f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2654563682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2654563682
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2684897236
Short name T175
Test name
Test status
Simulation time 664954254 ps
CPU time 39.3 seconds
Started Mar 28 12:39:48 PM PDT 24
Finished Mar 28 12:40:27 PM PDT 24
Peak memory 236872 kb
Host smart-df721b8f-83cf-48f6-879c-15c5e98abc62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2684897236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2684897236
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3710752807
Short name T173
Test name
Test status
Simulation time 2518738935 ps
CPU time 86.54 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 12:41:03 PM PDT 24
Peak memory 236780 kb
Host smart-c36cc88c-9ad3-4c3b-b944-e58ad79d1732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3710752807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3710752807
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.612315857
Short name T188
Test name
Test status
Simulation time 14778623642 ps
CPU time 68.97 seconds
Started Mar 28 12:39:30 PM PDT 24
Finished Mar 28 12:40:39 PM PDT 24
Peak memory 240216 kb
Host smart-e467f02c-8492-4beb-acbb-11ffbcc19f19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=612315857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.612315857
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.43109263
Short name T189
Test name
Test status
Simulation time 600535506 ps
CPU time 42.38 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:40:22 PM PDT 24
Peak memory 240216 kb
Host smart-e09c29e1-f44c-43b0-8f52-66d7137aab09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=43109263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.43109263
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1869082360
Short name T178
Test name
Test status
Simulation time 165241391 ps
CPU time 20.64 seconds
Started Mar 28 12:39:47 PM PDT 24
Finished Mar 28 12:40:08 PM PDT 24
Peak memory 239612 kb
Host smart-160eec16-3184-43b8-9cff-15086be12ada
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1869082360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1869082360
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2772792375
Short name T45
Test name
Test status
Simulation time 771395446 ps
CPU time 24.85 seconds
Started Mar 28 01:12:34 PM PDT 24
Finished Mar 28 01:13:00 PM PDT 24
Peak memory 248808 kb
Host smart-e2438eff-7dd7-4ec6-8a7b-e24ef26c4c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27727
92375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2772792375
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3656313209
Short name T28
Test name
Test status
Simulation time 68033973324 ps
CPU time 3787.65 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 02:15:17 PM PDT 24
Peak memory 305628 kb
Host smart-ee7d0ba4-7a62-40e0-8446-89b7f54d57fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656313209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3656313209
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2589799548
Short name T794
Test name
Test status
Simulation time 3157250881 ps
CPU time 108.52 seconds
Started Mar 28 12:39:34 PM PDT 24
Finished Mar 28 12:41:23 PM PDT 24
Peak memory 236576 kb
Host smart-03df1ef9-7153-4d35-afeb-3c0b9f5dbaba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2589799548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2589799548
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3952006765
Short name T824
Test name
Test status
Simulation time 17797390676 ps
CPU time 246.11 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:43:22 PM PDT 24
Peak memory 236572 kb
Host smart-cd83eda9-4d0b-4e43-9b6a-c49fe034a3d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3952006765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3952006765
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1420168513
Short name T736
Test name
Test status
Simulation time 85756294 ps
CPU time 6.05 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:22 PM PDT 24
Peak memory 240132 kb
Host smart-e420f1f6-02f3-4c0c-9eee-cd183dc1a0e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1420168513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1420168513
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2572368632
Short name T758
Test name
Test status
Simulation time 63456530 ps
CPU time 9.26 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:43 PM PDT 24
Peak memory 244032 kb
Host smart-799a372f-d9fe-4117-9faa-469a32d10352
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572368632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2572368632
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2172162913
Short name T825
Test name
Test status
Simulation time 33679097 ps
CPU time 5.29 seconds
Started Mar 28 12:39:10 PM PDT 24
Finished Mar 28 12:39:16 PM PDT 24
Peak memory 240164 kb
Host smart-b8407e70-d2ac-4607-b38c-ce1c908c6862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2172162913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2172162913
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3219313234
Short name T711
Test name
Test status
Simulation time 18265449 ps
CPU time 1.26 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:22 PM PDT 24
Peak memory 234716 kb
Host smart-53b57651-33df-495b-8c52-d19313d42bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3219313234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3219313234
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.815650697
Short name T735
Test name
Test status
Simulation time 521661419 ps
CPU time 38.34 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:40:10 PM PDT 24
Peak memory 244712 kb
Host smart-ddd915d7-8225-4efc-b705-60e903bf0492
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=815650697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.815650697
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3325273715
Short name T728
Test name
Test status
Simulation time 224349921 ps
CPU time 11.05 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:32 PM PDT 24
Peak memory 247932 kb
Host smart-497f0ee7-730e-42a1-810f-95cfacd27247
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3325273715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3325273715
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3762675831
Short name T717
Test name
Test status
Simulation time 2145704166 ps
CPU time 72.5 seconds
Started Mar 28 12:39:27 PM PDT 24
Finished Mar 28 12:40:39 PM PDT 24
Peak memory 236516 kb
Host smart-7f227355-5f50-4d73-b473-78f57be3ba31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3762675831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3762675831
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.988390527
Short name T749
Test name
Test status
Simulation time 2912850263 ps
CPU time 202.52 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:42:56 PM PDT 24
Peak memory 236516 kb
Host smart-f1474039-d24b-4cfa-82a9-14744b4b1ed6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=988390527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.988390527
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3516368026
Short name T790
Test name
Test status
Simulation time 1914286376 ps
CPU time 8.7 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:39:46 PM PDT 24
Peak memory 240160 kb
Host smart-d8e70ea4-c677-42f7-9d24-d60fcefb733e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3516368026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3516368026
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1837543754
Short name T762
Test name
Test status
Simulation time 59282268 ps
CPU time 5.09 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 12:39:41 PM PDT 24
Peak memory 240300 kb
Host smart-a3006649-5ca7-4f3b-82ce-0bf6e2c7abca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837543754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1837543754
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.427723424
Short name T195
Test name
Test status
Simulation time 19544635 ps
CPU time 3.25 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:36 PM PDT 24
Peak memory 236492 kb
Host smart-f99da158-b2b4-4264-8922-9f224b98b1be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=427723424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.427723424
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4150321173
Short name T739
Test name
Test status
Simulation time 13782082 ps
CPU time 1.29 seconds
Started Mar 28 12:39:35 PM PDT 24
Finished Mar 28 12:39:37 PM PDT 24
Peak memory 236580 kb
Host smart-56911e95-d5f3-4b6a-8255-144167078b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4150321173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.4150321173
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.882498420
Short name T777
Test name
Test status
Simulation time 753379403 ps
CPU time 22.06 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:55 PM PDT 24
Peak memory 248432 kb
Host smart-e3449e03-2dd3-4ccc-9291-a5272d5f1378
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=882498420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.882498420
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3349057536
Short name T709
Test name
Test status
Simulation time 504847360 ps
CPU time 12.91 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:49 PM PDT 24
Peak memory 247832 kb
Host smart-d9784dd3-c61b-45a2-954f-6812c951b015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3349057536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3349057536
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1279535575
Short name T719
Test name
Test status
Simulation time 1287867178 ps
CPU time 15.07 seconds
Started Mar 28 12:39:43 PM PDT 24
Finished Mar 28 12:39:58 PM PDT 24
Peak memory 248452 kb
Host smart-fbef0ca4-9915-4077-b117-e5d5caf2cc47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279535575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1279535575
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3215805017
Short name T727
Test name
Test status
Simulation time 69118599 ps
CPU time 3 seconds
Started Mar 28 12:40:03 PM PDT 24
Finished Mar 28 12:40:06 PM PDT 24
Peak memory 239440 kb
Host smart-cdf0f369-f7f9-49c6-8133-0fdb1c3fe968
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3215805017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3215805017
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2953430851
Short name T715
Test name
Test status
Simulation time 8208643 ps
CPU time 1.39 seconds
Started Mar 28 12:39:34 PM PDT 24
Finished Mar 28 12:39:35 PM PDT 24
Peak memory 234672 kb
Host smart-65f3fa44-af27-4e06-815a-754a62966993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2953430851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2953430851
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.803214379
Short name T781
Test name
Test status
Simulation time 876785293 ps
CPU time 9.99 seconds
Started Mar 28 12:39:59 PM PDT 24
Finished Mar 28 12:40:09 PM PDT 24
Peak memory 248508 kb
Host smart-8dc8dd39-bfe4-4eb3-a0b7-17a6672f8fcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=803214379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.803214379
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2220307328
Short name T151
Test name
Test status
Simulation time 6316998686 ps
CPU time 216.95 seconds
Started Mar 28 12:40:11 PM PDT 24
Finished Mar 28 12:43:48 PM PDT 24
Peak memory 265024 kb
Host smart-1c8355cb-8191-4e31-a24e-950e0e81e7e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2220307328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2220307328
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3229781257
Short name T708
Test name
Test status
Simulation time 425585369 ps
CPU time 15.91 seconds
Started Mar 28 12:40:00 PM PDT 24
Finished Mar 28 12:40:16 PM PDT 24
Peak memory 247068 kb
Host smart-fa103f09-48d5-4ead-b195-9b9dbb34fc2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3229781257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3229781257
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1907594725
Short name T732
Test name
Test status
Simulation time 282360938 ps
CPU time 6.67 seconds
Started Mar 28 12:39:49 PM PDT 24
Finished Mar 28 12:39:55 PM PDT 24
Peak memory 239148 kb
Host smart-f697e452-afd3-456f-a9a0-ba93fbc74275
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907594725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1907594725
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.255281743
Short name T795
Test name
Test status
Simulation time 76081162 ps
CPU time 3.43 seconds
Started Mar 28 12:39:40 PM PDT 24
Finished Mar 28 12:39:48 PM PDT 24
Peak memory 236548 kb
Host smart-adcdac53-0882-47df-8f45-dd84b2da525c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=255281743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.255281743
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1658327787
Short name T817
Test name
Test status
Simulation time 8924875 ps
CPU time 1.72 seconds
Started Mar 28 12:39:40 PM PDT 24
Finished Mar 28 12:39:41 PM PDT 24
Peak memory 236632 kb
Host smart-2a34a50d-24f9-4ee8-b5f6-d9674430769e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1658327787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1658327787
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.903684636
Short name T765
Test name
Test status
Simulation time 721729941 ps
CPU time 44.06 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 12:40:20 PM PDT 24
Peak memory 248412 kb
Host smart-6bc3eb4b-be9f-44f5-80a7-c417e5b4ceb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=903684636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.903684636
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2018563948
Short name T819
Test name
Test status
Simulation time 395637665 ps
CPU time 13.32 seconds
Started Mar 28 12:40:03 PM PDT 24
Finished Mar 28 12:40:17 PM PDT 24
Peak memory 246960 kb
Host smart-aa3f2bfd-3159-46de-bb89-9860742c4f74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2018563948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2018563948
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1436377178
Short name T187
Test name
Test status
Simulation time 2552365193 ps
CPU time 43.16 seconds
Started Mar 28 12:39:51 PM PDT 24
Finished Mar 28 12:40:34 PM PDT 24
Peak memory 239300 kb
Host smart-eff15871-ee12-4483-b79f-7031f3b9f2b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1436377178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1436377178
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2838140186
Short name T753
Test name
Test status
Simulation time 74746809 ps
CPU time 7.06 seconds
Started Mar 28 12:39:28 PM PDT 24
Finished Mar 28 12:39:35 PM PDT 24
Peak memory 239084 kb
Host smart-767c66df-e7e5-46f4-8906-d5ebdecf1303
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838140186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2838140186
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.552624744
Short name T815
Test name
Test status
Simulation time 117652825 ps
CPU time 5.24 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:45 PM PDT 24
Peak memory 235612 kb
Host smart-eaf27153-cce3-4595-aa30-15baeab279f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=552624744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.552624744
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2000163646
Short name T821
Test name
Test status
Simulation time 8259720 ps
CPU time 1.43 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:40 PM PDT 24
Peak memory 236500 kb
Host smart-c450b702-96e9-4b35-a8fd-5255800c0d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2000163646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2000163646
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.723749442
Short name T714
Test name
Test status
Simulation time 3084117048 ps
CPU time 42.45 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:40:21 PM PDT 24
Peak memory 248484 kb
Host smart-412406c8-70bf-4bf4-8042-3ddcf917bd34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=723749442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.723749442
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4241968912
Short name T165
Test name
Test status
Simulation time 16396770109 ps
CPU time 459.99 seconds
Started Mar 28 12:39:40 PM PDT 24
Finished Mar 28 12:47:20 PM PDT 24
Peak memory 264980 kb
Host smart-f0ca92e3-34da-4502-8eeb-42a4c9f536a3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241968912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.4241968912
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3935211852
Short name T776
Test name
Test status
Simulation time 602774524 ps
CPU time 9.84 seconds
Started Mar 28 12:39:35 PM PDT 24
Finished Mar 28 12:39:45 PM PDT 24
Peak memory 248184 kb
Host smart-de7c8821-237d-439a-b050-39d7e706ca66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3935211852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3935211852
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2398370405
Short name T359
Test name
Test status
Simulation time 115823279 ps
CPU time 10.19 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:39:42 PM PDT 24
Peak memory 256660 kb
Host smart-46e872f6-9dbf-4f83-bb0a-f8930e7bf1f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398370405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2398370405
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3674412764
Short name T797
Test name
Test status
Simulation time 60795238 ps
CPU time 5.59 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:45 PM PDT 24
Peak memory 235612 kb
Host smart-b3062bc3-08c4-413b-b1f0-8690c0ed5b2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3674412764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3674412764
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3993384093
Short name T356
Test name
Test status
Simulation time 18911131 ps
CPU time 1.31 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:41 PM PDT 24
Peak memory 236564 kb
Host smart-eaccc850-bc44-4dcb-8ad8-fc8b473c471e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3993384093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3993384093
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.341712857
Short name T712
Test name
Test status
Simulation time 935224672 ps
CPU time 21.92 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:40:00 PM PDT 24
Peak memory 244732 kb
Host smart-c8d4ce3e-a63c-48e7-8fb2-d3956a34ffe4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=341712857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.341712857
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1293031684
Short name T160
Test name
Test status
Simulation time 10649773154 ps
CPU time 151.43 seconds
Started Mar 28 12:39:37 PM PDT 24
Finished Mar 28 12:42:08 PM PDT 24
Peak memory 265116 kb
Host smart-f40c102c-9223-4c8b-8826-022447708b9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1293031684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1293031684
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.22535242
Short name T137
Test name
Test status
Simulation time 7901676872 ps
CPU time 531.49 seconds
Started Mar 28 12:39:51 PM PDT 24
Finished Mar 28 12:48:42 PM PDT 24
Peak memory 269564 kb
Host smart-f5388d51-88fb-417a-9eff-9c04e412f795
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22535242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.22535242
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1938122443
Short name T759
Test name
Test status
Simulation time 172100210 ps
CPU time 13.77 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:39:46 PM PDT 24
Peak memory 248544 kb
Host smart-40a484a7-74d3-4738-b7c1-41dce8525369
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1938122443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1938122443
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3700419714
Short name T771
Test name
Test status
Simulation time 243189909 ps
CPU time 5.82 seconds
Started Mar 28 12:40:02 PM PDT 24
Finished Mar 28 12:40:08 PM PDT 24
Peak memory 240408 kb
Host smart-b7e98945-075c-4db3-a19e-f981b8e0ef07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700419714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3700419714
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3531918573
Short name T766
Test name
Test status
Simulation time 121672094 ps
CPU time 4.69 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:39:43 PM PDT 24
Peak memory 239256 kb
Host smart-08fcc03d-61c1-4cb3-8efc-71ab6b4f2c59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3531918573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3531918573
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2208041841
Short name T718
Test name
Test status
Simulation time 8659842 ps
CPU time 1.4 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:39:39 PM PDT 24
Peak memory 236552 kb
Host smart-285ea8b9-02f4-482b-badd-ddbf9ba3a2dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2208041841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2208041841
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.608682010
Short name T740
Test name
Test status
Simulation time 8438480315 ps
CPU time 37.21 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:40:16 PM PDT 24
Peak memory 244688 kb
Host smart-1ab11f36-c9d2-4957-a57e-3bfb84f350e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=608682010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.608682010
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.769918936
Short name T161
Test name
Test status
Simulation time 102315320482 ps
CPU time 582.06 seconds
Started Mar 28 12:39:54 PM PDT 24
Finished Mar 28 12:49:36 PM PDT 24
Peak memory 265148 kb
Host smart-5747ef9d-fbd8-46ed-9a75-99efbebebea9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769918936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.769918936
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2112272675
Short name T809
Test name
Test status
Simulation time 728781756 ps
CPU time 12.41 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:39:51 PM PDT 24
Peak memory 246512 kb
Host smart-be2b54d0-ec8d-4264-a4da-130fe2d0b9d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2112272675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2112272675
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.476238258
Short name T784
Test name
Test status
Simulation time 43944259 ps
CPU time 7.46 seconds
Started Mar 28 12:40:06 PM PDT 24
Finished Mar 28 12:40:13 PM PDT 24
Peak memory 238932 kb
Host smart-eb2643c5-18e7-499a-a2bb-9091bdaccbfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476238258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.476238258
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.52901981
Short name T761
Test name
Test status
Simulation time 192684410 ps
CPU time 4.95 seconds
Started Mar 28 12:40:02 PM PDT 24
Finished Mar 28 12:40:07 PM PDT 24
Peak memory 240160 kb
Host smart-ec3068c1-f1d8-4df0-9733-9be203de60a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=52901981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.52901981
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1321163028
Short name T800
Test name
Test status
Simulation time 10174452 ps
CPU time 1.65 seconds
Started Mar 28 12:40:02 PM PDT 24
Finished Mar 28 12:40:04 PM PDT 24
Peak memory 236660 kb
Host smart-2f6a412a-250d-45ea-ace6-08a397feafda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1321163028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1321163028
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1547588258
Short name T190
Test name
Test status
Simulation time 713691811 ps
CPU time 46.64 seconds
Started Mar 28 12:40:02 PM PDT 24
Finished Mar 28 12:40:49 PM PDT 24
Peak memory 243912 kb
Host smart-c43c8239-e8e2-4106-868b-b6887d6c9a6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1547588258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1547588258
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.73375737
Short name T163
Test name
Test status
Simulation time 2188542619 ps
CPU time 283.2 seconds
Started Mar 28 12:39:54 PM PDT 24
Finished Mar 28 12:44:38 PM PDT 24
Peak memory 267644 kb
Host smart-c2da15a6-11c7-4627-a419-8f7cc6c13da0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73375737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.73375737
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.4062225407
Short name T723
Test name
Test status
Simulation time 625987747 ps
CPU time 5.37 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:39 PM PDT 24
Peak memory 248492 kb
Host smart-dec2d248-582c-4422-bb1b-6e2c1e3917e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4062225407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.4062225407
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4110032736
Short name T744
Test name
Test status
Simulation time 549287172 ps
CPU time 36.77 seconds
Started Mar 28 12:39:57 PM PDT 24
Finished Mar 28 12:40:34 PM PDT 24
Peak memory 248440 kb
Host smart-c56328e1-adfe-4bb0-99a1-fe82c628f14b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4110032736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4110032736
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.427991822
Short name T764
Test name
Test status
Simulation time 51799403 ps
CPU time 7.44 seconds
Started Mar 28 12:39:51 PM PDT 24
Finished Mar 28 12:39:58 PM PDT 24
Peak memory 256652 kb
Host smart-54f03e08-9fff-4b8c-ba13-1ba9951bcddc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427991822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.427991822
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2935773402
Short name T172
Test name
Test status
Simulation time 15134344 ps
CPU time 1.62 seconds
Started Mar 28 12:40:02 PM PDT 24
Finished Mar 28 12:40:03 PM PDT 24
Peak memory 236620 kb
Host smart-58ab0e42-b57f-4bc7-b763-eeba77de1d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2935773402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2935773402
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1994076258
Short name T802
Test name
Test status
Simulation time 256751418 ps
CPU time 18.09 seconds
Started Mar 28 12:39:37 PM PDT 24
Finished Mar 28 12:39:55 PM PDT 24
Peak memory 244892 kb
Host smart-239eb741-fb20-4830-9925-134d31913a1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1994076258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1994076258
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1412670406
Short name T710
Test name
Test status
Simulation time 101517948 ps
CPU time 3.94 seconds
Started Mar 28 12:39:54 PM PDT 24
Finished Mar 28 12:39:58 PM PDT 24
Peak memory 246996 kb
Host smart-88c1a776-cdf7-402c-a298-a5e31c369b94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1412670406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1412670406
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3265975613
Short name T807
Test name
Test status
Simulation time 52993416 ps
CPU time 9.04 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:49 PM PDT 24
Peak memory 244404 kb
Host smart-352d8f11-f1bd-4a2d-beca-14b688971021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265975613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3265975613
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3152866561
Short name T738
Test name
Test status
Simulation time 1253591167 ps
CPU time 10.16 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:39:49 PM PDT 24
Peak memory 236484 kb
Host smart-64433f3e-0e72-46b3-8faf-aa7d276ec4be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3152866561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3152866561
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4034402845
Short name T713
Test name
Test status
Simulation time 7587692 ps
CPU time 1.44 seconds
Started Mar 28 12:39:57 PM PDT 24
Finished Mar 28 12:39:59 PM PDT 24
Peak memory 236580 kb
Host smart-decd0446-d97d-4307-8ae2-d1416b2cfa35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4034402845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.4034402845
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1095842344
Short name T184
Test name
Test status
Simulation time 6334513070 ps
CPU time 41 seconds
Started Mar 28 12:39:54 PM PDT 24
Finished Mar 28 12:40:35 PM PDT 24
Peak memory 244692 kb
Host smart-0b7df099-68d7-4ffb-9398-ef042616f656
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1095842344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1095842344
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3239039094
Short name T148
Test name
Test status
Simulation time 12773920594 ps
CPU time 566.83 seconds
Started Mar 28 12:40:06 PM PDT 24
Finished Mar 28 12:49:33 PM PDT 24
Peak memory 265092 kb
Host smart-d187ed0c-9bf0-445e-b6f2-f29cbf5d7406
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239039094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3239039094
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1532065341
Short name T767
Test name
Test status
Simulation time 309988651 ps
CPU time 17 seconds
Started Mar 28 12:39:51 PM PDT 24
Finished Mar 28 12:40:08 PM PDT 24
Peak memory 253984 kb
Host smart-a9d4027e-8ec6-4a22-be4f-e5918b7967cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1532065341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1532065341
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3162345542
Short name T769
Test name
Test status
Simulation time 795619558 ps
CPU time 41.77 seconds
Started Mar 28 12:40:05 PM PDT 24
Finished Mar 28 12:40:47 PM PDT 24
Peak memory 239528 kb
Host smart-0f44268f-92af-4933-b03b-a98562c7b661
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3162345542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3162345542
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1071170129
Short name T820
Test name
Test status
Simulation time 201332995 ps
CPU time 8.52 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:39:47 PM PDT 24
Peak memory 240288 kb
Host smart-f458e469-76fd-4b27-8e24-2c2c811823b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071170129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1071170129
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1568186301
Short name T193
Test name
Test status
Simulation time 122614162 ps
CPU time 5.9 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 12:39:42 PM PDT 24
Peak memory 236224 kb
Host smart-982bc2f7-c9c3-4580-aeb7-96f33167c0a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1568186301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1568186301
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.346855144
Short name T734
Test name
Test status
Simulation time 8927468 ps
CPU time 1.45 seconds
Started Mar 28 12:39:31 PM PDT 24
Finished Mar 28 12:39:33 PM PDT 24
Peak memory 236576 kb
Host smart-90c1028e-3a79-4693-b4d8-58d490e5e111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=346855144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.346855144
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2346058795
Short name T805
Test name
Test status
Simulation time 1029179270 ps
CPU time 22.54 seconds
Started Mar 28 12:39:40 PM PDT 24
Finished Mar 28 12:40:02 PM PDT 24
Peak memory 248484 kb
Host smart-9d5ef293-ca22-497f-914f-9d57917061e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2346058795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2346058795
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1049722535
Short name T129
Test name
Test status
Simulation time 3341925292 ps
CPU time 100.2 seconds
Started Mar 28 12:39:40 PM PDT 24
Finished Mar 28 12:41:20 PM PDT 24
Peak memory 265108 kb
Host smart-c7f04202-acb2-4c56-8282-3290f9211d34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1049722535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1049722535
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4007051878
Short name T162
Test name
Test status
Simulation time 18757395903 ps
CPU time 1125.12 seconds
Started Mar 28 12:39:35 PM PDT 24
Finished Mar 28 12:58:21 PM PDT 24
Peak memory 273220 kb
Host smart-781bded8-03f6-47f3-aedf-0ec5b84edbde
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007051878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4007051878
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.196939572
Short name T248
Test name
Test status
Simulation time 679112234 ps
CPU time 11.62 seconds
Started Mar 28 12:39:35 PM PDT 24
Finished Mar 28 12:39:47 PM PDT 24
Peak memory 247912 kb
Host smart-7966e011-0462-4c85-8709-b21aad1a9af9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=196939572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.196939572
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.390464130
Short name T277
Test name
Test status
Simulation time 59928080 ps
CPU time 4.49 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:44 PM PDT 24
Peak memory 235680 kb
Host smart-e557505c-fb9f-4657-bdd7-7a64413182ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=390464130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.390464130
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.451352576
Short name T756
Test name
Test status
Simulation time 123677685 ps
CPU time 8.84 seconds
Started Mar 28 12:39:50 PM PDT 24
Finished Mar 28 12:39:58 PM PDT 24
Peak memory 240364 kb
Host smart-c4c691a5-7285-49ee-a44b-e49807fbd9d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451352576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.451352576
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3478341111
Short name T726
Test name
Test status
Simulation time 577291458 ps
CPU time 4.78 seconds
Started Mar 28 12:39:40 PM PDT 24
Finished Mar 28 12:39:45 PM PDT 24
Peak memory 236416 kb
Host smart-12fbf68b-7197-4af4-af72-50711c01231d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3478341111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3478341111
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2923615796
Short name T763
Test name
Test status
Simulation time 21688121 ps
CPU time 1.93 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:41 PM PDT 24
Peak memory 236572 kb
Host smart-86c9dbb3-0b8a-4874-a414-d3fd4283affc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2923615796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2923615796
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1725713623
Short name T803
Test name
Test status
Simulation time 336356896 ps
CPU time 12.11 seconds
Started Mar 28 12:39:40 PM PDT 24
Finished Mar 28 12:39:52 PM PDT 24
Peak memory 244828 kb
Host smart-5ee9b8d6-33dd-4466-ac0d-0697cf2c5a13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1725713623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1725713623
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3730795973
Short name T166
Test name
Test status
Simulation time 2929535224 ps
CPU time 184.47 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:42:44 PM PDT 24
Peak memory 265128 kb
Host smart-7849b1f7-ed1e-47f5-8beb-0f7d4283660a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3730795973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3730795973
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3689335955
Short name T164
Test name
Test status
Simulation time 64378956029 ps
CPU time 1144.8 seconds
Started Mar 28 12:39:35 PM PDT 24
Finished Mar 28 12:58:40 PM PDT 24
Peak memory 272012 kb
Host smart-32009201-e01a-4a0f-9a05-b0a0995a995b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689335955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3689335955
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1939515483
Short name T826
Test name
Test status
Simulation time 262627923 ps
CPU time 10.44 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:39:49 PM PDT 24
Peak memory 248500 kb
Host smart-455dd101-4dc7-4d62-92b2-b1ce87376302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1939515483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1939515483
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2632455575
Short name T804
Test name
Test status
Simulation time 623094085 ps
CPU time 61.6 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:40:34 PM PDT 24
Peak memory 236644 kb
Host smart-723e3478-2312-45f0-9f12-cb6bca218df1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2632455575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2632455575
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3646723726
Short name T793
Test name
Test status
Simulation time 22886221132 ps
CPU time 390.05 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:46:03 PM PDT 24
Peak memory 236556 kb
Host smart-e3f14057-9bf0-4472-9f6c-07190664258a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3646723726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3646723726
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2216270889
Short name T789
Test name
Test status
Simulation time 39059071 ps
CPU time 5.96 seconds
Started Mar 28 12:39:34 PM PDT 24
Finished Mar 28 12:39:40 PM PDT 24
Peak memory 240132 kb
Host smart-6145bdee-aad7-4b0f-89fe-35ff86747dc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2216270889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2216270889
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.4164651714
Short name T725
Test name
Test status
Simulation time 107514105 ps
CPU time 8.55 seconds
Started Mar 28 12:39:34 PM PDT 24
Finished Mar 28 12:39:43 PM PDT 24
Peak memory 240276 kb
Host smart-dcb49657-bf89-4166-9a62-2c6870fd6115
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164651714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.4164651714
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1246656821
Short name T791
Test name
Test status
Simulation time 529271123 ps
CPU time 8.89 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:48 PM PDT 24
Peak memory 236412 kb
Host smart-b5f0688b-7117-4c34-a6eb-2809bb1dc581
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1246656821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1246656821
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2808216047
Short name T783
Test name
Test status
Simulation time 9937078 ps
CPU time 1.62 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:41 PM PDT 24
Peak memory 236576 kb
Host smart-f855171c-210c-4044-87c5-65143d4c550e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2808216047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2808216047
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3061036428
Short name T194
Test name
Test status
Simulation time 352141497 ps
CPU time 10.3 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:43 PM PDT 24
Peak memory 248436 kb
Host smart-783451e8-7a8e-4c33-9be4-fb56479134bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3061036428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3061036428
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3965426478
Short name T143
Test name
Test status
Simulation time 2955448736 ps
CPU time 196.96 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:42:50 PM PDT 24
Peak memory 264956 kb
Host smart-a7d012a0-1be4-4188-b159-765920caeaaa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3965426478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3965426478
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3832755438
Short name T810
Test name
Test status
Simulation time 2944555199 ps
CPU time 15.67 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:48 PM PDT 24
Peak memory 254348 kb
Host smart-7bdf16aa-d061-4ce5-88eb-ee60f511db8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3832755438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3832755438
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2320808137
Short name T775
Test name
Test status
Simulation time 7494323 ps
CPU time 1.5 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:39:39 PM PDT 24
Peak memory 235688 kb
Host smart-0fc2e448-0c5d-480d-8cdb-d407c6d7fae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2320808137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2320808137
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1655219941
Short name T716
Test name
Test status
Simulation time 13034571 ps
CPU time 1.48 seconds
Started Mar 28 12:39:48 PM PDT 24
Finished Mar 28 12:39:50 PM PDT 24
Peak memory 235688 kb
Host smart-09f579f3-9d62-4b2b-8310-7656d559b42e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1655219941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1655219941
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3284635731
Short name T785
Test name
Test status
Simulation time 11446416 ps
CPU time 1.32 seconds
Started Mar 28 12:39:40 PM PDT 24
Finished Mar 28 12:39:41 PM PDT 24
Peak memory 235760 kb
Host smart-2b5d812f-0403-456d-958a-0d1dffe75cc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3284635731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3284635731
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2484989967
Short name T788
Test name
Test status
Simulation time 61434021 ps
CPU time 1.33 seconds
Started Mar 28 12:39:50 PM PDT 24
Finished Mar 28 12:39:52 PM PDT 24
Peak memory 234704 kb
Host smart-191702e2-a045-4f37-9c2d-8b60af991aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2484989967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2484989967
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2539035353
Short name T720
Test name
Test status
Simulation time 8510492 ps
CPU time 1.47 seconds
Started Mar 28 12:40:05 PM PDT 24
Finished Mar 28 12:40:07 PM PDT 24
Peak memory 236620 kb
Host smart-ca6dd9e3-cda5-4065-955f-8d9cd663bff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2539035353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2539035353
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2274609424
Short name T731
Test name
Test status
Simulation time 11414093 ps
CPU time 1.36 seconds
Started Mar 28 12:39:48 PM PDT 24
Finished Mar 28 12:39:49 PM PDT 24
Peak memory 236580 kb
Host smart-cead9f3a-fed0-4dd9-b827-7a286cd6e3b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2274609424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2274609424
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3802857944
Short name T780
Test name
Test status
Simulation time 8300168 ps
CPU time 1.45 seconds
Started Mar 28 12:39:37 PM PDT 24
Finished Mar 28 12:39:39 PM PDT 24
Peak memory 234684 kb
Host smart-7b659351-1e32-40ed-8d12-a6ff3992c040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3802857944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3802857944
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2524100369
Short name T358
Test name
Test status
Simulation time 7725388 ps
CPU time 1.34 seconds
Started Mar 28 12:39:46 PM PDT 24
Finished Mar 28 12:39:52 PM PDT 24
Peak memory 234764 kb
Host smart-61df634d-c0bf-451e-a606-70ec8a7976bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2524100369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2524100369
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.703379547
Short name T774
Test name
Test status
Simulation time 9393550 ps
CPU time 1.57 seconds
Started Mar 28 12:39:46 PM PDT 24
Finished Mar 28 12:39:48 PM PDT 24
Peak memory 236548 kb
Host smart-d5f5298f-9d65-4f3c-858d-cb6449c6c43b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=703379547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.703379547
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1171239422
Short name T822
Test name
Test status
Simulation time 5663063409 ps
CPU time 101.54 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:41:13 PM PDT 24
Peak memory 236692 kb
Host smart-b7e2858d-e1e7-42d4-ae9c-7b751dd32912
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1171239422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1171239422
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3864235187
Short name T240
Test name
Test status
Simulation time 4408705092 ps
CPU time 247.66 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:43:41 PM PDT 24
Peak memory 236492 kb
Host smart-43e74f09-b497-4a01-ade5-d9f30b08f657
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3864235187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3864235187
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2987422209
Short name T198
Test name
Test status
Simulation time 37815738 ps
CPU time 5.71 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:39:38 PM PDT 24
Peak memory 240172 kb
Host smart-2aa4b53e-84f4-4e09-adc1-5585656b5525
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2987422209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2987422209
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.4080123249
Short name T721
Test name
Test status
Simulation time 255612117 ps
CPU time 10.51 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:39:42 PM PDT 24
Peak memory 255352 kb
Host smart-9514cf3e-c6f6-4445-a8ec-3c7d9a371924
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080123249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.4080123249
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4265870958
Short name T730
Test name
Test status
Simulation time 219449433 ps
CPU time 5.5 seconds
Started Mar 28 12:39:37 PM PDT 24
Finished Mar 28 12:39:43 PM PDT 24
Peak memory 236492 kb
Host smart-8adc2d39-83d7-483d-8f45-0d25ed337a30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4265870958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.4265870958
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.4159964630
Short name T353
Test name
Test status
Simulation time 23059806 ps
CPU time 1.23 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:34 PM PDT 24
Peak memory 236456 kb
Host smart-161d6cc6-1796-4d70-a4a7-b4b569004d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4159964630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.4159964630
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.501313411
Short name T748
Test name
Test status
Simulation time 667265749 ps
CPU time 21.49 seconds
Started Mar 28 12:39:34 PM PDT 24
Finished Mar 28 12:39:55 PM PDT 24
Peak memory 243896 kb
Host smart-16efacfa-de80-440c-98ca-743e49845ac9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=501313411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.501313411
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.687179426
Short name T145
Test name
Test status
Simulation time 822545966 ps
CPU time 103.06 seconds
Started Mar 28 12:39:34 PM PDT 24
Finished Mar 28 12:41:17 PM PDT 24
Peak memory 256816 kb
Host smart-ee55bb41-1538-4244-a1fb-2a0e4accd693
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=687179426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.687179426
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1186876683
Short name T360
Test name
Test status
Simulation time 24007752854 ps
CPU time 475.02 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:47:33 PM PDT 24
Peak memory 267196 kb
Host smart-ac9a721c-a3b3-4bb0-9dd3-5a7841e8a2d4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186876683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1186876683
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1129108649
Short name T737
Test name
Test status
Simulation time 358599032 ps
CPU time 13.5 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:46 PM PDT 24
Peak memory 248580 kb
Host smart-2305354a-9b7c-4a7e-a1b0-ba7218442307
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1129108649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1129108649
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.4041922000
Short name T752
Test name
Test status
Simulation time 9734843 ps
CPU time 1.3 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:39:41 PM PDT 24
Peak memory 235716 kb
Host smart-67f9dfbd-d427-414a-b13f-83916ec967a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4041922000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.4041922000
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2516196024
Short name T729
Test name
Test status
Simulation time 9614344 ps
CPU time 1.43 seconds
Started Mar 28 12:40:02 PM PDT 24
Finished Mar 28 12:40:03 PM PDT 24
Peak memory 234756 kb
Host smart-ee81c648-6302-4f54-9dfc-61e5f8459aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2516196024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2516196024
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1399677828
Short name T770
Test name
Test status
Simulation time 11767425 ps
CPU time 1.26 seconds
Started Mar 28 12:39:47 PM PDT 24
Finished Mar 28 12:39:48 PM PDT 24
Peak memory 236620 kb
Host smart-e083ba78-b221-4124-8c26-8917a2238a3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1399677828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1399677828
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2138954695
Short name T796
Test name
Test status
Simulation time 10430833 ps
CPU time 1.63 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 12:39:38 PM PDT 24
Peak memory 235700 kb
Host smart-99cd8e3c-1386-4e53-96ac-89fd6b62293e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2138954695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2138954695
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.885594178
Short name T357
Test name
Test status
Simulation time 10757132 ps
CPU time 1.33 seconds
Started Mar 28 12:40:02 PM PDT 24
Finished Mar 28 12:40:03 PM PDT 24
Peak memory 236660 kb
Host smart-e8caad34-b27a-406a-962e-a16b63bb0b33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=885594178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.885594178
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3242843943
Short name T249
Test name
Test status
Simulation time 25394442 ps
CPU time 1.34 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:39:33 PM PDT 24
Peak memory 236448 kb
Host smart-b41ba488-b826-42d4-8d64-2564aa812e66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3242843943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3242843943
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1195657678
Short name T722
Test name
Test status
Simulation time 7545593 ps
CPU time 1.23 seconds
Started Mar 28 12:39:45 PM PDT 24
Finished Mar 28 12:39:46 PM PDT 24
Peak memory 236548 kb
Host smart-9847fa74-4236-4f39-9587-cdbf11e729a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1195657678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1195657678
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3564551331
Short name T747
Test name
Test status
Simulation time 10517582 ps
CPU time 1.23 seconds
Started Mar 28 12:39:46 PM PDT 24
Finished Mar 28 12:39:47 PM PDT 24
Peak memory 234660 kb
Host smart-6203bc00-49cd-43bb-8259-aaa48ee8d0e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3564551331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3564551331
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.111922995
Short name T782
Test name
Test status
Simulation time 8438730 ps
CPU time 1.43 seconds
Started Mar 28 12:39:50 PM PDT 24
Finished Mar 28 12:39:52 PM PDT 24
Peak memory 234676 kb
Host smart-f89eb975-ef16-49bf-a15a-e3383f153278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=111922995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.111922995
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1687509621
Short name T183
Test name
Test status
Simulation time 4067349158 ps
CPU time 248.26 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:43:46 PM PDT 24
Peak memory 240244 kb
Host smart-bf45ec80-ec6f-4d9b-8ba6-c019d332706b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1687509621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1687509621
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3177249716
Short name T750
Test name
Test status
Simulation time 8926012234 ps
CPU time 264.28 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:43:58 PM PDT 24
Peak memory 236520 kb
Host smart-615976ce-1fc4-4407-a66b-8b9fd504e5e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3177249716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3177249716
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1860523510
Short name T746
Test name
Test status
Simulation time 480220242 ps
CPU time 10.99 seconds
Started Mar 28 12:39:40 PM PDT 24
Finished Mar 28 12:39:51 PM PDT 24
Peak memory 240080 kb
Host smart-8e72bfea-f743-487b-a391-8c3aa8ad1b86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1860523510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1860523510
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4075294139
Short name T757
Test name
Test status
Simulation time 59802468 ps
CPU time 8.6 seconds
Started Mar 28 12:39:34 PM PDT 24
Finished Mar 28 12:39:43 PM PDT 24
Peak memory 251920 kb
Host smart-9f5a77cb-c16b-461a-b4cf-0aad2bf11578
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075294139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.4075294139
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.85772222
Short name T185
Test name
Test status
Simulation time 125682052 ps
CPU time 5.11 seconds
Started Mar 28 12:39:31 PM PDT 24
Finished Mar 28 12:39:37 PM PDT 24
Peak memory 235584 kb
Host smart-29f435d7-f4c1-42ba-b5da-da36fa5c6024
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=85772222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.85772222
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3470602584
Short name T779
Test name
Test status
Simulation time 501327890 ps
CPU time 39.22 seconds
Started Mar 28 12:39:34 PM PDT 24
Finished Mar 28 12:40:14 PM PDT 24
Peak memory 248456 kb
Host smart-345404c6-d0c8-4aaa-8a47-63c5623e43ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3470602584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3470602584
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.613083667
Short name T157
Test name
Test status
Simulation time 16513455645 ps
CPU time 586.36 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:49:22 PM PDT 24
Peak memory 267772 kb
Host smart-20bcf742-4c19-4642-a0e5-f1a560ffd567
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613083667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.613083667
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3070030317
Short name T786
Test name
Test status
Simulation time 364837585 ps
CPU time 7.76 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:46 PM PDT 24
Peak memory 247224 kb
Host smart-2aac91dc-f39b-4491-b504-723ce85f3d20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3070030317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3070030317
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3184944219
Short name T724
Test name
Test status
Simulation time 20099895 ps
CPU time 1.47 seconds
Started Mar 28 12:40:02 PM PDT 24
Finished Mar 28 12:40:04 PM PDT 24
Peak memory 235932 kb
Host smart-8401ff82-eb9d-4140-bf4e-713efbb7e519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3184944219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3184944219
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2582346150
Short name T751
Test name
Test status
Simulation time 8434071 ps
CPU time 1.43 seconds
Started Mar 28 12:39:46 PM PDT 24
Finished Mar 28 12:39:48 PM PDT 24
Peak memory 236648 kb
Host smart-58f5029e-d26a-42ad-853a-3ee13e5b6d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2582346150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2582346150
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1423575587
Short name T811
Test name
Test status
Simulation time 6408733 ps
CPU time 1.34 seconds
Started Mar 28 12:40:00 PM PDT 24
Finished Mar 28 12:40:01 PM PDT 24
Peak memory 234704 kb
Host smart-39bc2446-ff0f-46e4-8800-29d4ba1ba1df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1423575587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1423575587
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3492498284
Short name T768
Test name
Test status
Simulation time 15829809 ps
CPU time 1.57 seconds
Started Mar 28 12:40:08 PM PDT 24
Finished Mar 28 12:40:10 PM PDT 24
Peak memory 236580 kb
Host smart-c09b2a34-4e69-46d8-af3a-3aa589080817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3492498284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3492498284
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1987065226
Short name T354
Test name
Test status
Simulation time 23527351 ps
CPU time 1.39 seconds
Started Mar 28 12:40:03 PM PDT 24
Finished Mar 28 12:40:04 PM PDT 24
Peak memory 235716 kb
Host smart-2dbfefba-73f9-4825-bde3-74b19c8c5a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1987065226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1987065226
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3551261496
Short name T760
Test name
Test status
Simulation time 25329167 ps
CPU time 1.47 seconds
Started Mar 28 12:40:13 PM PDT 24
Finished Mar 28 12:40:15 PM PDT 24
Peak memory 236580 kb
Host smart-7d70a68c-6965-4c12-8776-92f5270b093d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3551261496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3551261496
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2101188614
Short name T812
Test name
Test status
Simulation time 12636859 ps
CPU time 1.33 seconds
Started Mar 28 12:40:14 PM PDT 24
Finished Mar 28 12:40:15 PM PDT 24
Peak memory 235712 kb
Host smart-b9baf9ad-9cd3-4ad9-8e6c-d6fbd0491b21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2101188614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2101188614
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.680747482
Short name T806
Test name
Test status
Simulation time 20925155 ps
CPU time 1.92 seconds
Started Mar 28 12:40:09 PM PDT 24
Finished Mar 28 12:40:11 PM PDT 24
Peak memory 236588 kb
Host smart-dde9a59a-b6f0-43d0-9d1c-b2962eba20d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=680747482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.680747482
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4194744705
Short name T823
Test name
Test status
Simulation time 10751161 ps
CPU time 1.72 seconds
Started Mar 28 12:40:00 PM PDT 24
Finished Mar 28 12:40:02 PM PDT 24
Peak memory 236548 kb
Host smart-976d3067-adfc-4049-923d-95ec87548319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4194744705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.4194744705
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.424718320
Short name T773
Test name
Test status
Simulation time 14149007 ps
CPU time 1.47 seconds
Started Mar 28 12:40:11 PM PDT 24
Finished Mar 28 12:40:13 PM PDT 24
Peak memory 235668 kb
Host smart-17bd4ee3-52ea-4891-8f51-37a43425fbd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=424718320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.424718320
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2627259578
Short name T742
Test name
Test status
Simulation time 64253368 ps
CPU time 4.9 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 12:39:41 PM PDT 24
Peak memory 240280 kb
Host smart-45366f2e-4183-461e-baaf-7830b2f6c7a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627259578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2627259578
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1815761500
Short name T787
Test name
Test status
Simulation time 362609197 ps
CPU time 7.6 seconds
Started Mar 28 12:39:34 PM PDT 24
Finished Mar 28 12:39:41 PM PDT 24
Peak memory 235624 kb
Host smart-efb13ab5-1a17-4287-9890-fa27825ed583
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1815761500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1815761500
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3578862912
Short name T733
Test name
Test status
Simulation time 19635247 ps
CPU time 1.43 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:35 PM PDT 24
Peak memory 236572 kb
Host smart-8eca869e-ffe1-4726-927e-506c2302b327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3578862912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3578862912
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.329949625
Short name T798
Test name
Test status
Simulation time 168617250 ps
CPU time 22.89 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:40:02 PM PDT 24
Peak memory 244756 kb
Host smart-f51dc06d-19df-4da4-ab12-7d42aa9109d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=329949625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.329949625
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3124205805
Short name T132
Test name
Test status
Simulation time 1934714262 ps
CPU time 147.72 seconds
Started Mar 28 12:39:34 PM PDT 24
Finished Mar 28 12:42:02 PM PDT 24
Peak memory 256752 kb
Host smart-bd413dbe-acc0-4ce7-8022-c7703be4d474
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3124205805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3124205805
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3012002079
Short name T130
Test name
Test status
Simulation time 24302485495 ps
CPU time 514.69 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:48:07 PM PDT 24
Peak memory 265132 kb
Host smart-27ac571d-73fc-43b5-b468-4b985ad7ca34
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012002079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3012002079
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1388514804
Short name T755
Test name
Test status
Simulation time 116717801 ps
CPU time 8.46 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:47 PM PDT 24
Peak memory 248496 kb
Host smart-e41fd685-2b5d-42a8-a7d1-98a3c6aff374
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1388514804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1388514804
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2517419510
Short name T813
Test name
Test status
Simulation time 66944105 ps
CPU time 5.79 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:44 PM PDT 24
Peak memory 236620 kb
Host smart-16b0a88b-492d-4aee-993b-a7873d5a69b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517419510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2517419510
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2190855433
Short name T799
Test name
Test status
Simulation time 120168248 ps
CPU time 8.66 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:48 PM PDT 24
Peak memory 240152 kb
Host smart-9b64f392-f32d-4b4e-810d-87a01a979b03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2190855433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2190855433
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1445091732
Short name T741
Test name
Test status
Simulation time 10669616 ps
CPU time 1.32 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:40 PM PDT 24
Peak memory 235708 kb
Host smart-caab50fc-813b-4b28-ba73-4e4c9f272e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1445091732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1445091732
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2830917560
Short name T772
Test name
Test status
Simulation time 696076011 ps
CPU time 46.4 seconds
Started Mar 28 12:39:53 PM PDT 24
Finished Mar 28 12:40:39 PM PDT 24
Peak memory 244760 kb
Host smart-6030a4fa-0ad7-4626-af23-55fc2b318961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2830917560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2830917560
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.664858801
Short name T814
Test name
Test status
Simulation time 1122115665 ps
CPU time 106.5 seconds
Started Mar 28 12:39:29 PM PDT 24
Finished Mar 28 12:41:15 PM PDT 24
Peak memory 264904 kb
Host smart-4884cf43-a8aa-453f-9bdb-618a291dfca3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=664858801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.664858801
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1358167686
Short name T247
Test name
Test status
Simulation time 418483492 ps
CPU time 14.19 seconds
Started Mar 28 12:39:51 PM PDT 24
Finished Mar 28 12:40:05 PM PDT 24
Peak memory 247804 kb
Host smart-9261735d-d012-4284-af51-177c7bbe2738
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1358167686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1358167686
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3409341735
Short name T745
Test name
Test status
Simulation time 154392985 ps
CPU time 7.82 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:39:40 PM PDT 24
Peak memory 240312 kb
Host smart-3be211d6-0968-445b-9cd2-722294dc4f65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409341735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3409341735
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2115769527
Short name T743
Test name
Test status
Simulation time 289686630 ps
CPU time 8.96 seconds
Started Mar 28 12:39:32 PM PDT 24
Finished Mar 28 12:39:41 PM PDT 24
Peak memory 240136 kb
Host smart-ea81326b-3c84-482e-80aa-db0160c2d4b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2115769527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2115769527
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3167254560
Short name T170
Test name
Test status
Simulation time 12837064 ps
CPU time 1.26 seconds
Started Mar 28 12:39:48 PM PDT 24
Finished Mar 28 12:39:49 PM PDT 24
Peak memory 236548 kb
Host smart-439cfed3-1b5e-4a5c-9aa3-6fb4387d3b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3167254560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3167254560
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3826637571
Short name T192
Test name
Test status
Simulation time 191784725 ps
CPU time 21.55 seconds
Started Mar 28 12:39:40 PM PDT 24
Finished Mar 28 12:40:01 PM PDT 24
Peak memory 248484 kb
Host smart-b167e480-cbfb-41bc-97c7-9f32fad67d4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3826637571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3826637571
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3055702144
Short name T141
Test name
Test status
Simulation time 3964373538 ps
CPU time 131.78 seconds
Started Mar 28 12:39:37 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 256864 kb
Host smart-93370c49-44c1-4d54-bf01-5135d340a979
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3055702144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3055702144
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3194940140
Short name T155
Test name
Test status
Simulation time 16699290656 ps
CPU time 1069.52 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 12:57:26 PM PDT 24
Peak memory 265104 kb
Host smart-4c947da4-a3b3-40a5-8e49-a9b586246456
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194940140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3194940140
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3621443451
Short name T808
Test name
Test status
Simulation time 371560004 ps
CPU time 12.59 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 12:39:51 PM PDT 24
Peak memory 248348 kb
Host smart-66e79eb9-5789-4d64-90a4-bf583d36eca7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3621443451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3621443451
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.778382900
Short name T197
Test name
Test status
Simulation time 121549938 ps
CPU time 4.8 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:39 PM PDT 24
Peak memory 255116 kb
Host smart-53b5070a-2d34-41af-add2-79ef1ef070c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778382900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.778382900
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2798257759
Short name T191
Test name
Test status
Simulation time 93570021 ps
CPU time 3.37 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 12:39:40 PM PDT 24
Peak memory 236492 kb
Host smart-09b6fe1d-0333-4bba-ad42-1f78c828545c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2798257759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2798257759
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.706262056
Short name T801
Test name
Test status
Simulation time 14986915 ps
CPU time 1.26 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:39:39 PM PDT 24
Peak memory 235716 kb
Host smart-5e201efc-05c3-4c8e-9ff2-2b225f55b5df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=706262056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.706262056
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.283919648
Short name T792
Test name
Test status
Simulation time 979243525 ps
CPU time 37.1 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 12:40:15 PM PDT 24
Peak memory 248328 kb
Host smart-f50feeb6-5694-4266-8b62-36da65b408a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=283919648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.283919648
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3977033228
Short name T147
Test name
Test status
Simulation time 14224193238 ps
CPU time 517.17 seconds
Started Mar 28 12:39:57 PM PDT 24
Finished Mar 28 12:48:35 PM PDT 24
Peak memory 265148 kb
Host smart-613002be-08ab-47f6-82b0-f51aabc697b3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977033228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3977033228
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2144414660
Short name T754
Test name
Test status
Simulation time 181554678 ps
CPU time 6.07 seconds
Started Mar 28 12:39:56 PM PDT 24
Finished Mar 28 12:40:02 PM PDT 24
Peak memory 248540 kb
Host smart-a56e5a33-6c33-4ac8-8a72-19964dcea0c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2144414660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2144414660
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3450494697
Short name T816
Test name
Test status
Simulation time 303877632 ps
CPU time 8.16 seconds
Started Mar 28 12:39:33 PM PDT 24
Finished Mar 28 12:39:41 PM PDT 24
Peak memory 240144 kb
Host smart-79612597-ebe7-4406-8eac-b4d53a2b1afe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450494697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3450494697
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3342553444
Short name T361
Test name
Test status
Simulation time 322273653 ps
CPU time 8.49 seconds
Started Mar 28 12:39:47 PM PDT 24
Finished Mar 28 12:39:55 PM PDT 24
Peak memory 236564 kb
Host smart-5c8d7bfa-0929-4cf2-a611-9bcc1c38b5c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3342553444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3342553444
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.230452366
Short name T778
Test name
Test status
Simulation time 7136605 ps
CPU time 1.32 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 12:39:38 PM PDT 24
Peak memory 235696 kb
Host smart-3316841f-91ce-42d7-aeef-c749fb4bc085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=230452366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.230452366
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1536340667
Short name T818
Test name
Test status
Simulation time 1072776924 ps
CPU time 21.92 seconds
Started Mar 28 12:40:01 PM PDT 24
Finished Mar 28 12:40:23 PM PDT 24
Peak memory 244732 kb
Host smart-1180d34a-8bbd-4bbd-a249-d6459632d465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1536340667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1536340667
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3175080860
Short name T138
Test name
Test status
Simulation time 959101707 ps
CPU time 105.31 seconds
Started Mar 28 12:40:02 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 267784 kb
Host smart-e23db4ec-62aa-4c7a-801c-1ea222b45e26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3175080860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3175080860
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3256392566
Short name T146
Test name
Test status
Simulation time 8349688550 ps
CPU time 300.46 seconds
Started Mar 28 12:40:00 PM PDT 24
Finished Mar 28 12:45:00 PM PDT 24
Peak memory 265036 kb
Host smart-5b914794-32e0-4510-ac8a-5ba239cede20
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256392566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3256392566
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1742413701
Short name T707
Test name
Test status
Simulation time 164316432 ps
CPU time 12.8 seconds
Started Mar 28 12:39:54 PM PDT 24
Finished Mar 28 12:40:07 PM PDT 24
Peak memory 248492 kb
Host smart-07e77401-295e-4320-ba27-03ef04c98a14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1742413701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1742413701
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1635096774
Short name T242
Test name
Test status
Simulation time 30451494278 ps
CPU time 2041.21 seconds
Started Mar 28 01:11:49 PM PDT 24
Finished Mar 28 01:45:50 PM PDT 24
Peak memory 289440 kb
Host smart-0147479b-3eb5-41a6-81f8-687cc560af75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635096774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1635096774
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3650895346
Short name T529
Test name
Test status
Simulation time 721123894 ps
CPU time 10.93 seconds
Started Mar 28 01:11:52 PM PDT 24
Finished Mar 28 01:12:03 PM PDT 24
Peak memory 251664 kb
Host smart-deac4102-2b92-4d0f-a553-8d8b2833133b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3650895346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3650895346
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2285778363
Short name T703
Test name
Test status
Simulation time 6574487014 ps
CPU time 62.96 seconds
Started Mar 28 01:11:52 PM PDT 24
Finished Mar 28 01:12:55 PM PDT 24
Peak memory 256780 kb
Host smart-ac590f78-644c-40d1-bb1d-c14b3b021a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22857
78363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2285778363
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2994093373
Short name T509
Test name
Test status
Simulation time 855992171 ps
CPU time 47.07 seconds
Started Mar 28 01:11:52 PM PDT 24
Finished Mar 28 01:12:39 PM PDT 24
Peak memory 248920 kb
Host smart-19fc9264-7ef3-4da6-87f6-2aedb27ecfd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29940
93373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2994093373
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1039706414
Short name T351
Test name
Test status
Simulation time 54074747424 ps
CPU time 1276.9 seconds
Started Mar 28 01:12:04 PM PDT 24
Finished Mar 28 01:33:21 PM PDT 24
Peak memory 289228 kb
Host smart-2a8c5f16-f78a-439f-a4df-59300d66c0ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039706414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1039706414
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2119131549
Short name T442
Test name
Test status
Simulation time 35702221327 ps
CPU time 2141.62 seconds
Started Mar 28 01:11:50 PM PDT 24
Finished Mar 28 01:47:32 PM PDT 24
Peak memory 281796 kb
Host smart-169e458c-d637-452e-a03e-4ef3f0ff95c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119131549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2119131549
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.473975363
Short name T454
Test name
Test status
Simulation time 4133579629 ps
CPU time 165.54 seconds
Started Mar 28 01:11:50 PM PDT 24
Finished Mar 28 01:14:36 PM PDT 24
Peak memory 255896 kb
Host smart-08de1857-f4f7-4398-9a2b-114c85f9f972
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473975363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.473975363
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1838550560
Short name T235
Test name
Test status
Simulation time 991665790 ps
CPU time 39.88 seconds
Started Mar 28 01:11:50 PM PDT 24
Finished Mar 28 01:12:30 PM PDT 24
Peak memory 249092 kb
Host smart-d3c5e0d6-cd4a-4cd3-9a5d-be3425da154a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18385
50560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1838550560
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1697954074
Short name T495
Test name
Test status
Simulation time 212369547 ps
CPU time 10.94 seconds
Started Mar 28 01:11:54 PM PDT 24
Finished Mar 28 01:12:05 PM PDT 24
Peak memory 248780 kb
Host smart-ebfaeea0-e046-47d0-9e69-7a66a366f032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16979
54074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1697954074
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2609389823
Short name T701
Test name
Test status
Simulation time 3296129486 ps
CPU time 40.51 seconds
Started Mar 28 01:11:54 PM PDT 24
Finished Mar 28 01:12:34 PM PDT 24
Peak memory 255584 kb
Host smart-1d65bca1-c660-408e-a531-580679c2c315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26093
89823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2609389823
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.4129523908
Short name T414
Test name
Test status
Simulation time 266301664 ps
CPU time 20.63 seconds
Started Mar 28 01:11:48 PM PDT 24
Finished Mar 28 01:12:09 PM PDT 24
Peak memory 257060 kb
Host smart-66f6dd60-9b03-4d41-b633-ec16ffcce5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41295
23908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.4129523908
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2664934986
Short name T295
Test name
Test status
Simulation time 63587557486 ps
CPU time 3762.04 seconds
Started Mar 28 01:11:49 PM PDT 24
Finished Mar 28 02:14:32 PM PDT 24
Peak memory 298504 kb
Host smart-45d26e91-638a-48c4-9123-7e86d1e79db7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664934986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2664934986
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.887874826
Short name T112
Test name
Test status
Simulation time 51555478068 ps
CPU time 1622.34 seconds
Started Mar 28 01:11:50 PM PDT 24
Finished Mar 28 01:38:52 PM PDT 24
Peak memory 286772 kb
Host smart-37ec4e37-ffb3-4f7f-930e-9d265d7b8bc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887874826 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.887874826
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3617530814
Short name T487
Test name
Test status
Simulation time 244164199 ps
CPU time 12.99 seconds
Started Mar 28 01:11:50 PM PDT 24
Finished Mar 28 01:12:03 PM PDT 24
Peak memory 240692 kb
Host smart-90f5d1d3-e216-47d3-822a-ec4a00da29a3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3617530814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3617530814
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.626472055
Short name T684
Test name
Test status
Simulation time 6103971609 ps
CPU time 99.29 seconds
Started Mar 28 01:11:55 PM PDT 24
Finished Mar 28 01:13:35 PM PDT 24
Peak memory 256732 kb
Host smart-f5514991-53f2-4625-b0f4-bcc302c62315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62647
2055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.626472055
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.4046072035
Short name T85
Test name
Test status
Simulation time 518143266 ps
CPU time 14.91 seconds
Started Mar 28 01:11:50 PM PDT 24
Finished Mar 28 01:12:05 PM PDT 24
Peak memory 255272 kb
Host smart-25cb2642-35e3-4648-9403-6b6dd6567c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40460
72035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.4046072035
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.562242917
Short name T477
Test name
Test status
Simulation time 26668137992 ps
CPU time 1269.35 seconds
Started Mar 28 01:11:50 PM PDT 24
Finished Mar 28 01:33:00 PM PDT 24
Peak memory 288096 kb
Host smart-448d1562-0a2c-49ea-b570-7785ac4617c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562242917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.562242917
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3984050278
Short name T599
Test name
Test status
Simulation time 157938102532 ps
CPU time 2556.48 seconds
Started Mar 28 01:11:53 PM PDT 24
Finished Mar 28 01:54:30 PM PDT 24
Peak memory 288832 kb
Host smart-06e6f4ff-9644-4e50-b406-8371e9c120c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984050278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3984050278
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2784897980
Short name T44
Test name
Test status
Simulation time 688213392 ps
CPU time 12.44 seconds
Started Mar 28 01:11:49 PM PDT 24
Finished Mar 28 01:12:02 PM PDT 24
Peak memory 248880 kb
Host smart-2caac6da-f245-4cba-a664-c0b4e9347077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27848
97980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2784897980
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1538333454
Short name T507
Test name
Test status
Simulation time 657787670 ps
CPU time 25.49 seconds
Started Mar 28 01:11:51 PM PDT 24
Finished Mar 28 01:12:17 PM PDT 24
Peak memory 247248 kb
Host smart-fe6e3968-ca59-40bc-9a08-d81697470d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15383
33454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1538333454
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2548252946
Short name T11
Test name
Test status
Simulation time 231244926 ps
CPU time 13.19 seconds
Started Mar 28 01:11:52 PM PDT 24
Finished Mar 28 01:12:05 PM PDT 24
Peak memory 273532 kb
Host smart-3c937cce-6402-4bc6-b2b4-e28f866d61a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2548252946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2548252946
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.32913309
Short name T518
Test name
Test status
Simulation time 1649262049 ps
CPU time 33 seconds
Started Mar 28 01:11:56 PM PDT 24
Finished Mar 28 01:12:29 PM PDT 24
Peak memory 256004 kb
Host smart-72a2f0af-d3d3-45a3-a7cd-96b217f7d9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32913
309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.32913309
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3352775957
Short name T511
Test name
Test status
Simulation time 93425687 ps
CPU time 2.76 seconds
Started Mar 28 01:11:52 PM PDT 24
Finished Mar 28 01:11:55 PM PDT 24
Peak memory 240620 kb
Host smart-5664ba08-57c0-4dbd-9940-6d52dcc875e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33527
75957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3352775957
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1671150576
Short name T117
Test name
Test status
Simulation time 11387830627 ps
CPU time 1351.3 seconds
Started Mar 28 01:11:51 PM PDT 24
Finished Mar 28 01:34:23 PM PDT 24
Peak memory 284032 kb
Host smart-da5202b9-5eb7-415e-b597-66c0aaeb3cbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671150576 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1671150576
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2465422156
Short name T602
Test name
Test status
Simulation time 72224723 ps
CPU time 5.54 seconds
Started Mar 28 01:12:37 PM PDT 24
Finished Mar 28 01:12:43 PM PDT 24
Peak memory 240596 kb
Host smart-22816cd1-5c74-4a24-b197-1897ddd7009e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2465422156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2465422156
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1323627415
Short name T664
Test name
Test status
Simulation time 19346855266 ps
CPU time 130.29 seconds
Started Mar 28 01:12:37 PM PDT 24
Finished Mar 28 01:14:47 PM PDT 24
Peak memory 256352 kb
Host smart-80bd9db7-309b-465f-b89f-9b711ca328eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13236
27415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1323627415
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3398086917
Short name T430
Test name
Test status
Simulation time 2013878099 ps
CPU time 61.58 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:13:41 PM PDT 24
Peak memory 255576 kb
Host smart-909c2c24-a842-48d6-97e3-42d5b2910009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33980
86917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3398086917
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1147715300
Short name T257
Test name
Test status
Simulation time 24527985539 ps
CPU time 712.66 seconds
Started Mar 28 01:12:37 PM PDT 24
Finished Mar 28 01:24:30 PM PDT 24
Peak memory 272832 kb
Host smart-4cf9280a-bad9-4127-a14b-72fb33811c47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147715300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1147715300
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2577300368
Short name T325
Test name
Test status
Simulation time 12752712224 ps
CPU time 518.8 seconds
Started Mar 28 01:12:38 PM PDT 24
Finished Mar 28 01:21:17 PM PDT 24
Peak memory 247924 kb
Host smart-7199ccac-2f3a-4eec-b46f-d206a5df9472
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577300368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2577300368
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1291328286
Short name T236
Test name
Test status
Simulation time 217520303 ps
CPU time 11.48 seconds
Started Mar 28 01:12:39 PM PDT 24
Finished Mar 28 01:12:51 PM PDT 24
Peak memory 255228 kb
Host smart-97af4013-976d-4f58-9317-a99219fcfe72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12913
28286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1291328286
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1560801729
Short name T625
Test name
Test status
Simulation time 3338148362 ps
CPU time 49.89 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:13:30 PM PDT 24
Peak memory 248952 kb
Host smart-820be46f-869d-4d8d-b1c9-16475c03a2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15608
01729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1560801729
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3181142889
Short name T423
Test name
Test status
Simulation time 6927979542 ps
CPU time 142.26 seconds
Started Mar 28 01:12:34 PM PDT 24
Finished Mar 28 01:14:58 PM PDT 24
Peak memory 257188 kb
Host smart-eaba480c-8238-4d66-a2a3-0eb092e52317
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181142889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3181142889
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2534696737
Short name T212
Test name
Test status
Simulation time 46068498 ps
CPU time 3.5 seconds
Started Mar 28 01:12:39 PM PDT 24
Finished Mar 28 01:12:43 PM PDT 24
Peak memory 249136 kb
Host smart-0f5533f8-fa19-4ae2-a960-20a3314487a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2534696737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2534696737
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2661520132
Short name T128
Test name
Test status
Simulation time 2013760114 ps
CPU time 44.3 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:13:25 PM PDT 24
Peak memory 248832 kb
Host smart-ade29599-6d0d-4c97-9732-b2733a6be751
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2661520132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2661520132
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1136139394
Short name T271
Test name
Test status
Simulation time 38878805323 ps
CPU time 276.21 seconds
Started Mar 28 01:12:35 PM PDT 24
Finished Mar 28 01:17:12 PM PDT 24
Peak memory 257128 kb
Host smart-aa51d5f6-45eb-4bec-b50e-8d3cd486e511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11361
39394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1136139394
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1937254399
Short name T67
Test name
Test status
Simulation time 215901275 ps
CPU time 7.9 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:12:52 PM PDT 24
Peak memory 248532 kb
Host smart-e8302095-916d-4993-93dc-66f528248090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19372
54399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1937254399
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.970878134
Short name T304
Test name
Test status
Simulation time 19904770159 ps
CPU time 1310.21 seconds
Started Mar 28 01:12:37 PM PDT 24
Finished Mar 28 01:34:27 PM PDT 24
Peak memory 289424 kb
Host smart-3d231339-8b5f-4c7a-ba8f-47e5e708fcaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970878134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.970878134
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2028193115
Short name T74
Test name
Test status
Simulation time 36895403443 ps
CPU time 890.72 seconds
Started Mar 28 01:12:39 PM PDT 24
Finished Mar 28 01:27:30 PM PDT 24
Peak memory 266420 kb
Host smart-60492514-4176-4780-ad91-8a36037a2820
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028193115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2028193115
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3427371558
Short name T30
Test name
Test status
Simulation time 2298446914 ps
CPU time 23.55 seconds
Started Mar 28 01:12:35 PM PDT 24
Finished Mar 28 01:13:00 PM PDT 24
Peak memory 248976 kb
Host smart-1bb271a3-1ab5-4899-b9b2-11aedd6fb3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34273
71558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3427371558
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.167913319
Short name T95
Test name
Test status
Simulation time 774952980 ps
CPU time 22.31 seconds
Started Mar 28 01:12:38 PM PDT 24
Finished Mar 28 01:13:00 PM PDT 24
Peak memory 255392 kb
Host smart-4755f1c9-03b4-4e07-b921-beee28d8063b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16791
3319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.167913319
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.4011825468
Short name T363
Test name
Test status
Simulation time 140094354 ps
CPU time 15.68 seconds
Started Mar 28 01:12:34 PM PDT 24
Finished Mar 28 01:12:51 PM PDT 24
Peak memory 255976 kb
Host smart-1f3e3945-0c0e-449a-8f89-55fb5b1cc50f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40118
25468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.4011825468
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1194607927
Short name T566
Test name
Test status
Simulation time 143802907694 ps
CPU time 1862.51 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:43:43 PM PDT 24
Peak memory 283660 kb
Host smart-53cbf106-2810-4d2c-9243-1c5c90f9d345
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194607927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1194607927
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.4239234492
Short name T25
Test name
Test status
Simulation time 35487796645 ps
CPU time 2191.2 seconds
Started Mar 28 01:12:38 PM PDT 24
Finished Mar 28 01:49:09 PM PDT 24
Peak memory 281772 kb
Host smart-17753304-eb78-4619-aafa-7e91f027e487
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239234492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.4239234492
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3878394115
Short name T15
Test name
Test status
Simulation time 383286653 ps
CPU time 17.77 seconds
Started Mar 28 01:12:42 PM PDT 24
Finished Mar 28 01:13:01 PM PDT 24
Peak memory 240572 kb
Host smart-8e692cb4-8aa6-4427-894d-f5dcebb6967e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3878394115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3878394115
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.898895364
Short name T362
Test name
Test status
Simulation time 90744932224 ps
CPU time 306.23 seconds
Started Mar 28 01:12:38 PM PDT 24
Finished Mar 28 01:17:45 PM PDT 24
Peak memory 256752 kb
Host smart-3071af45-8922-476e-8919-b65a3f7304be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89889
5364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.898895364
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.454561145
Short name T80
Test name
Test status
Simulation time 166975715 ps
CPU time 11.81 seconds
Started Mar 28 01:12:39 PM PDT 24
Finished Mar 28 01:12:51 PM PDT 24
Peak memory 248896 kb
Host smart-c8d1457f-2202-4621-b395-8abba0f0c959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45456
1145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.454561145
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1409421068
Short name T622
Test name
Test status
Simulation time 298469115265 ps
CPU time 2764.6 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:58:48 PM PDT 24
Peak memory 289320 kb
Host smart-cb014231-9bcd-44e2-a8ba-82e02a483f6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409421068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1409421068
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.4202363820
Short name T574
Test name
Test status
Simulation time 34090278537 ps
CPU time 825.89 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:26:30 PM PDT 24
Peak memory 273460 kb
Host smart-de8aaa6a-8aae-4c3e-bf9d-d3f2907bcfd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202363820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.4202363820
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3634823256
Short name T437
Test name
Test status
Simulation time 72676810554 ps
CPU time 371.96 seconds
Started Mar 28 01:12:38 PM PDT 24
Finished Mar 28 01:18:51 PM PDT 24
Peak memory 248144 kb
Host smart-ee0b12ed-3a98-4659-95ce-9f62360d0b9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634823256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3634823256
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2395509115
Short name T656
Test name
Test status
Simulation time 1622752769 ps
CPU time 45.43 seconds
Started Mar 28 01:12:38 PM PDT 24
Finished Mar 28 01:13:24 PM PDT 24
Peak memory 256068 kb
Host smart-c6e38d04-e662-4390-aeab-937e5eca2b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23955
09115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2395509115
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2192008752
Short name T587
Test name
Test status
Simulation time 95823022 ps
CPU time 8.31 seconds
Started Mar 28 01:12:42 PM PDT 24
Finished Mar 28 01:12:52 PM PDT 24
Peak memory 247132 kb
Host smart-3b2aa559-5fc3-41d6-9811-62ddc74b6fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21920
08752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2192008752
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2254840922
Short name T276
Test name
Test status
Simulation time 1445620705 ps
CPU time 44.58 seconds
Started Mar 28 01:12:39 PM PDT 24
Finished Mar 28 01:13:24 PM PDT 24
Peak memory 254912 kb
Host smart-8491a287-3df6-4e17-8294-2030f1784d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22548
40922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2254840922
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1703705286
Short name T631
Test name
Test status
Simulation time 74356373 ps
CPU time 9.27 seconds
Started Mar 28 01:12:34 PM PDT 24
Finished Mar 28 01:12:45 PM PDT 24
Peak memory 248824 kb
Host smart-1fd8f6cf-13e1-461c-a4ed-71f0b9570dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17037
05286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1703705286
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.4020976814
Short name T589
Test name
Test status
Simulation time 58497299857 ps
CPU time 2811.58 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:59:32 PM PDT 24
Peak memory 318652 kb
Host smart-2fb884ac-0423-40e3-a469-c7cc04c54aa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020976814 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.4020976814
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.4153000194
Short name T208
Test name
Test status
Simulation time 64928222 ps
CPU time 1.96 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:12:45 PM PDT 24
Peak memory 249096 kb
Host smart-3581a924-64ab-4d4b-88ce-f8a9bd0ed65e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4153000194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.4153000194
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3903428702
Short name T78
Test name
Test status
Simulation time 44562530314 ps
CPU time 2229.74 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:49:52 PM PDT 24
Peak memory 289428 kb
Host smart-ebdb6044-d78a-43a1-8c89-dbed5682806f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903428702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3903428702
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2368855465
Short name T402
Test name
Test status
Simulation time 788049045 ps
CPU time 18.16 seconds
Started Mar 28 01:12:42 PM PDT 24
Finished Mar 28 01:13:02 PM PDT 24
Peak memory 240644 kb
Host smart-afb75364-a8e3-4938-8303-114feaac7386
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2368855465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2368855465
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1330183104
Short name T69
Test name
Test status
Simulation time 2243672779 ps
CPU time 36.42 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:13:19 PM PDT 24
Peak memory 248864 kb
Host smart-5e0d3168-697f-44f9-b6db-9051900b724e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13301
83104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1330183104
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1761794487
Short name T632
Test name
Test status
Simulation time 341933312 ps
CPU time 14.77 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:12:56 PM PDT 24
Peak memory 255572 kb
Host smart-e334074d-5569-4be9-919f-b605e5580428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17617
94487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1761794487
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3074829319
Short name T96
Test name
Test status
Simulation time 13200179003 ps
CPU time 1174.67 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:32:15 PM PDT 24
Peak memory 288716 kb
Host smart-ee15f65c-f725-406b-a80e-b5039c3a63fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074829319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3074829319
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3246905351
Short name T553
Test name
Test status
Simulation time 651535013 ps
CPU time 20.36 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:13:01 PM PDT 24
Peak memory 254728 kb
Host smart-cf4ab8f4-db2d-4d48-970e-1f764edc8776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32469
05351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3246905351
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2267674403
Short name T410
Test name
Test status
Simulation time 878766001 ps
CPU time 53.16 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:13:34 PM PDT 24
Peak memory 247668 kb
Host smart-69049177-0e93-4c13-ab60-dbd35c1dc6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22676
74403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2267674403
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1941732160
Short name T494
Test name
Test status
Simulation time 1706230880 ps
CPU time 26.39 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:13:07 PM PDT 24
Peak memory 256340 kb
Host smart-19b5f9b7-6e60-4ea5-9948-b42064eb3534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19417
32160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1941732160
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2164015697
Short name T469
Test name
Test status
Simulation time 1505468645 ps
CPU time 19.12 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:13:01 PM PDT 24
Peak memory 248968 kb
Host smart-bc89874b-6c5f-4709-a75d-64c819bf0d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21640
15697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2164015697
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2636272627
Short name T250
Test name
Test status
Simulation time 91894772504 ps
CPU time 2409.64 seconds
Started Mar 28 01:12:42 PM PDT 24
Finished Mar 28 01:52:54 PM PDT 24
Peak memory 289232 kb
Host smart-4a4f9b28-8b83-4977-805b-76da78fd411e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636272627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2636272627
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1954568224
Short name T274
Test name
Test status
Simulation time 13172626400 ps
CPU time 987.45 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:29:10 PM PDT 24
Peak memory 273604 kb
Host smart-1aab7489-0e2f-4cfb-a4bb-798d3ad3d45d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954568224 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1954568224
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1248823630
Short name T217
Test name
Test status
Simulation time 21717167 ps
CPU time 2.26 seconds
Started Mar 28 01:12:52 PM PDT 24
Finished Mar 28 01:12:54 PM PDT 24
Peak memory 249164 kb
Host smart-ccd1e542-7460-453d-bf57-2ab5a190cfc5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1248823630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1248823630
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1690051579
Short name T491
Test name
Test status
Simulation time 56742127020 ps
CPU time 1928.43 seconds
Started Mar 28 01:12:34 PM PDT 24
Finished Mar 28 01:44:44 PM PDT 24
Peak memory 284532 kb
Host smart-8e20ccf7-bb45-4237-a635-7e750ea93c3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690051579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1690051579
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.4078169506
Short name T379
Test name
Test status
Simulation time 432313317 ps
CPU time 11.68 seconds
Started Mar 28 01:12:59 PM PDT 24
Finished Mar 28 01:13:12 PM PDT 24
Peak memory 240692 kb
Host smart-f07280ee-78ff-4408-a25b-9cdaaeadfd4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4078169506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.4078169506
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1494142650
Short name T443
Test name
Test status
Simulation time 5184533306 ps
CPU time 263.67 seconds
Started Mar 28 01:12:37 PM PDT 24
Finished Mar 28 01:17:01 PM PDT 24
Peak memory 256340 kb
Host smart-67146ced-6d2f-4236-a3a3-d6440cdacdcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14941
42650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1494142650
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1391432470
Short name T108
Test name
Test status
Simulation time 704107543 ps
CPU time 19.15 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:13:01 PM PDT 24
Peak memory 254480 kb
Host smart-d321112b-d314-4a41-a8b7-b5a04e3d61f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13914
32470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1391432470
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1210161274
Short name T348
Test name
Test status
Simulation time 16163226670 ps
CPU time 1270.03 seconds
Started Mar 28 01:12:56 PM PDT 24
Finished Mar 28 01:34:06 PM PDT 24
Peak memory 281684 kb
Host smart-87ad29a3-5ff5-4ac1-8413-a569ec5aed28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210161274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1210161274
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2640219952
Short name T407
Test name
Test status
Simulation time 8511298388 ps
CPU time 1113.3 seconds
Started Mar 28 01:12:54 PM PDT 24
Finished Mar 28 01:31:27 PM PDT 24
Peak memory 283108 kb
Host smart-9343bc9e-6020-405e-b3a0-3dfef763457c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640219952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2640219952
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3607452526
Short name T223
Test name
Test status
Simulation time 5254153399 ps
CPU time 52.18 seconds
Started Mar 28 01:12:42 PM PDT 24
Finished Mar 28 01:13:36 PM PDT 24
Peak memory 256376 kb
Host smart-9917421c-6eb5-45e8-bad0-b3cd4892e6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36074
52526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3607452526
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.57480702
Short name T105
Test name
Test status
Simulation time 814652930 ps
CPU time 14.71 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:12:56 PM PDT 24
Peak memory 254380 kb
Host smart-2a3f78be-07de-4844-b56c-147ed9bfd230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57480
702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.57480702
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.698326880
Short name T705
Test name
Test status
Simulation time 1086867104 ps
CPU time 57.24 seconds
Started Mar 28 01:12:39 PM PDT 24
Finished Mar 28 01:13:36 PM PDT 24
Peak memory 255600 kb
Host smart-d913c273-1d8c-4033-9db2-34c61d3bb13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69832
6880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.698326880
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2109010359
Short name T244
Test name
Test status
Simulation time 3549636008 ps
CPU time 57.34 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:13:40 PM PDT 24
Peak memory 256108 kb
Host smart-0ea3933f-97a2-4721-872e-44a76a73f900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21090
10359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2109010359
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.630440870
Short name T409
Test name
Test status
Simulation time 15925921233 ps
CPU time 1495.11 seconds
Started Mar 28 01:12:53 PM PDT 24
Finished Mar 28 01:37:49 PM PDT 24
Peak memory 289872 kb
Host smart-7a8520a6-0b94-4277-8e48-37afd221e0d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630440870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.630440870
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.140035038
Short name T216
Test name
Test status
Simulation time 54060851 ps
CPU time 4.54 seconds
Started Mar 28 01:13:03 PM PDT 24
Finished Mar 28 01:13:08 PM PDT 24
Peak memory 249124 kb
Host smart-eaf48731-ae31-4f22-b166-421f997f44c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=140035038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.140035038
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2410551293
Short name T498
Test name
Test status
Simulation time 36931595935 ps
CPU time 2078.36 seconds
Started Mar 28 01:12:57 PM PDT 24
Finished Mar 28 01:47:37 PM PDT 24
Peak memory 273552 kb
Host smart-7433a566-511b-40b4-abf1-79f1582771ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410551293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2410551293
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3337738642
Short name T449
Test name
Test status
Simulation time 269999020 ps
CPU time 23.97 seconds
Started Mar 28 01:12:52 PM PDT 24
Finished Mar 28 01:13:16 PM PDT 24
Peak memory 255460 kb
Host smart-c22ef9d0-c1cb-4758-a4dd-492478e74a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33377
38642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3337738642
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1463900608
Short name T706
Test name
Test status
Simulation time 323338443 ps
CPU time 20.51 seconds
Started Mar 28 01:12:56 PM PDT 24
Finished Mar 28 01:13:17 PM PDT 24
Peak memory 254596 kb
Host smart-29d29410-0d23-4a2f-84ad-a192229c1d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14639
00608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1463900608
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.747530610
Short name T339
Test name
Test status
Simulation time 14661352572 ps
CPU time 1204.08 seconds
Started Mar 28 01:12:51 PM PDT 24
Finished Mar 28 01:32:55 PM PDT 24
Peak memory 289040 kb
Host smart-9a7a0866-7317-4a49-ab97-8ebedd615ba0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747530610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.747530610
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3674118743
Short name T439
Test name
Test status
Simulation time 61167139006 ps
CPU time 1321.53 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 01:35:03 PM PDT 24
Peak memory 288836 kb
Host smart-b360c636-a1b6-46c9-b582-ae6ca7885a41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674118743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3674118743
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.934303979
Short name T335
Test name
Test status
Simulation time 8380618632 ps
CPU time 344.99 seconds
Started Mar 28 01:13:06 PM PDT 24
Finished Mar 28 01:18:51 PM PDT 24
Peak memory 247760 kb
Host smart-ae43d7b5-a0fc-457c-988e-aa20ba4c494e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934303979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.934303979
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2791921207
Short name T699
Test name
Test status
Simulation time 941545092 ps
CPU time 28.32 seconds
Started Mar 28 01:12:57 PM PDT 24
Finished Mar 28 01:13:25 PM PDT 24
Peak memory 255892 kb
Host smart-466ecbe4-7bfa-470e-851a-41526714d170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27919
21207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2791921207
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3007037510
Short name T620
Test name
Test status
Simulation time 783560244 ps
CPU time 10.82 seconds
Started Mar 28 01:12:53 PM PDT 24
Finished Mar 28 01:13:04 PM PDT 24
Peak memory 248880 kb
Host smart-b6a4d3a2-3645-411c-a1a5-e2cccecf293f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30070
37510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3007037510
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1916726782
Short name T287
Test name
Test status
Simulation time 2486144294 ps
CPU time 33.19 seconds
Started Mar 28 01:12:53 PM PDT 24
Finished Mar 28 01:13:26 PM PDT 24
Peak memory 255620 kb
Host smart-38be3390-491d-4bac-84b0-9c1b3f637bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19167
26782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1916726782
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2984417763
Short name T571
Test name
Test status
Simulation time 1536018999 ps
CPU time 28.14 seconds
Started Mar 28 01:12:52 PM PDT 24
Finished Mar 28 01:13:20 PM PDT 24
Peak memory 249052 kb
Host smart-6a356311-6371-4f51-908c-74b2533252d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29844
17763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2984417763
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2030251746
Short name T292
Test name
Test status
Simulation time 42450592283 ps
CPU time 2794.86 seconds
Started Mar 28 01:12:58 PM PDT 24
Finished Mar 28 01:59:34 PM PDT 24
Peak memory 298228 kb
Host smart-b33f8247-48e8-47b5-a20e-39d7cf80296b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030251746 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2030251746
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.810869702
Short name T214
Test name
Test status
Simulation time 52299090 ps
CPU time 2.72 seconds
Started Mar 28 01:12:56 PM PDT 24
Finished Mar 28 01:12:59 PM PDT 24
Peak memory 249072 kb
Host smart-5a13f838-9007-4515-81c4-be130be8368c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=810869702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.810869702
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3437292031
Short name T94
Test name
Test status
Simulation time 28737489078 ps
CPU time 1622.41 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 01:40:04 PM PDT 24
Peak memory 266236 kb
Host smart-02824a56-7410-43ed-9725-c6a55b908bf0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437292031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3437292031
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.242110552
Short name T592
Test name
Test status
Simulation time 3074871122 ps
CPU time 22.16 seconds
Started Mar 28 01:12:56 PM PDT 24
Finished Mar 28 01:13:19 PM PDT 24
Peak memory 248888 kb
Host smart-bdb1833d-f73c-4452-9d83-09ebbe7eead0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=242110552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.242110552
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.4172108108
Short name T688
Test name
Test status
Simulation time 7982135989 ps
CPU time 165.26 seconds
Started Mar 28 01:12:53 PM PDT 24
Finished Mar 28 01:15:39 PM PDT 24
Peak memory 257144 kb
Host smart-f591178c-a994-41a0-ac7f-64193000725c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41721
08108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.4172108108
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3779538226
Short name T678
Test name
Test status
Simulation time 488919077 ps
CPU time 16.24 seconds
Started Mar 28 01:12:55 PM PDT 24
Finished Mar 28 01:13:11 PM PDT 24
Peak memory 248884 kb
Host smart-9798b8b1-12d0-4137-a2fa-03ed02264e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37795
38226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3779538226
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.625369481
Short name T305
Test name
Test status
Simulation time 99413605369 ps
CPU time 1508.55 seconds
Started Mar 28 01:12:56 PM PDT 24
Finished Mar 28 01:38:05 PM PDT 24
Peak memory 273392 kb
Host smart-bbe9cf5f-4722-44fb-9601-83b6acf7ab9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625369481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.625369481
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3965681480
Short name T681
Test name
Test status
Simulation time 22827701708 ps
CPU time 690.21 seconds
Started Mar 28 01:12:53 PM PDT 24
Finished Mar 28 01:24:24 PM PDT 24
Peak memory 273032 kb
Host smart-b1324165-f098-40e4-86df-2329803665c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965681480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3965681480
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2031808793
Short name T486
Test name
Test status
Simulation time 12027402005 ps
CPU time 49.48 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 01:13:51 PM PDT 24
Peak memory 248980 kb
Host smart-fe108d6b-5b95-4309-9c2b-c2abaaceed26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20318
08793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2031808793
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2898313038
Short name T550
Test name
Test status
Simulation time 1015431413 ps
CPU time 31.08 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 01:13:33 PM PDT 24
Peak memory 255828 kb
Host smart-d2e78618-1403-4553-aa77-fbe868219e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28983
13038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2898313038
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1700897436
Short name T299
Test name
Test status
Simulation time 233464334 ps
CPU time 28.77 seconds
Started Mar 28 01:12:53 PM PDT 24
Finished Mar 28 01:13:22 PM PDT 24
Peak memory 247716 kb
Host smart-9fb078e2-dd93-4964-a0b4-e3dcc7988a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17008
97436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1700897436
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.990748999
Short name T603
Test name
Test status
Simulation time 321344848 ps
CPU time 6.31 seconds
Started Mar 28 01:12:59 PM PDT 24
Finished Mar 28 01:13:06 PM PDT 24
Peak memory 248808 kb
Host smart-a87787f0-510e-47e1-9d3b-0cabc6bc7030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99074
8999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.990748999
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2522993073
Short name T46
Test name
Test status
Simulation time 21115297424 ps
CPU time 936.04 seconds
Started Mar 28 01:12:52 PM PDT 24
Finished Mar 28 01:28:28 PM PDT 24
Peak memory 281824 kb
Host smart-3fa60d5a-95d8-4e22-92f8-7fd3ee59fcd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522993073 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2522993073
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1849601093
Short name T209
Test name
Test status
Simulation time 43080366 ps
CPU time 2.49 seconds
Started Mar 28 01:12:56 PM PDT 24
Finished Mar 28 01:12:59 PM PDT 24
Peak memory 249136 kb
Host smart-a9acdd9e-7ed4-4fb0-b082-6bafe28aecd9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1849601093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1849601093
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3554708202
Short name T596
Test name
Test status
Simulation time 12035250694 ps
CPU time 1243.63 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 01:33:46 PM PDT 24
Peak memory 283652 kb
Host smart-c9eefe45-9407-479c-8a17-d8e6815cd400
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554708202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3554708202
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3597409815
Short name T636
Test name
Test status
Simulation time 1912892026 ps
CPU time 36.24 seconds
Started Mar 28 01:12:53 PM PDT 24
Finished Mar 28 01:13:29 PM PDT 24
Peak memory 240476 kb
Host smart-7274d05e-7f8a-4df1-a0f3-079786aa1af6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3597409815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3597409815
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3437392617
Short name T444
Test name
Test status
Simulation time 1443096366 ps
CPU time 60.08 seconds
Started Mar 28 01:12:52 PM PDT 24
Finished Mar 28 01:13:52 PM PDT 24
Peak memory 256812 kb
Host smart-fd5890d0-d3b1-4fe0-9b50-16e2835b6dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34373
92617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3437392617
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.4023006354
Short name T109
Test name
Test status
Simulation time 153744793 ps
CPU time 13.96 seconds
Started Mar 28 01:12:53 PM PDT 24
Finished Mar 28 01:13:07 PM PDT 24
Peak memory 256024 kb
Host smart-a85f77c2-f2f6-4923-9c49-e95b4c46a3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40230
06354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.4023006354
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.795939893
Short name T319
Test name
Test status
Simulation time 39222032942 ps
CPU time 2346.98 seconds
Started Mar 28 01:13:03 PM PDT 24
Finished Mar 28 01:52:11 PM PDT 24
Peak memory 288952 kb
Host smart-5076c0f8-7f88-4c57-83fc-3d08bb2b2812
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795939893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.795939893
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3083467247
Short name T3
Test name
Test status
Simulation time 54315561785 ps
CPU time 2575.62 seconds
Started Mar 28 01:12:54 PM PDT 24
Finished Mar 28 01:55:50 PM PDT 24
Peak memory 289088 kb
Host smart-5e8bac63-5993-4c89-9ce8-38ccc8d16b8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083467247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3083467247
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1735662230
Short name T537
Test name
Test status
Simulation time 51462041 ps
CPU time 4.2 seconds
Started Mar 28 01:12:52 PM PDT 24
Finished Mar 28 01:12:56 PM PDT 24
Peak memory 240564 kb
Host smart-32327c2c-fea1-44b4-81a0-123070120589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17356
62230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1735662230
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1837556193
Short name T564
Test name
Test status
Simulation time 1912380455 ps
CPU time 33.99 seconds
Started Mar 28 01:12:51 PM PDT 24
Finished Mar 28 01:13:25 PM PDT 24
Peak memory 255592 kb
Host smart-60691358-d204-41c4-986e-930a70b54207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18375
56193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1837556193
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1728824136
Short name T83
Test name
Test status
Simulation time 488745141 ps
CPU time 17.71 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 01:13:20 PM PDT 24
Peak memory 255188 kb
Host smart-e5c2af0a-df60-423d-8eb1-c040614a6d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17288
24136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1728824136
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1338297075
Short name T63
Test name
Test status
Simulation time 663410078 ps
CPU time 40.21 seconds
Started Mar 28 01:12:55 PM PDT 24
Finished Mar 28 01:13:36 PM PDT 24
Peak memory 256048 kb
Host smart-d5de3e1b-d6d7-4409-ae09-9dd503e1a18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13382
97075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1338297075
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2919936587
Short name T51
Test name
Test status
Simulation time 69658396836 ps
CPU time 2000.39 seconds
Started Mar 28 01:12:58 PM PDT 24
Finished Mar 28 01:46:19 PM PDT 24
Peak memory 289204 kb
Host smart-15e43521-69d9-4eee-bab1-32d9e17e7a10
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919936587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2919936587
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4058540788
Short name T199
Test name
Test status
Simulation time 22024787 ps
CPU time 3.03 seconds
Started Mar 28 01:12:58 PM PDT 24
Finished Mar 28 01:13:01 PM PDT 24
Peak memory 249136 kb
Host smart-61ad1ade-68f1-456d-a35b-b9d0ef970c9a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4058540788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4058540788
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.835333316
Short name T102
Test name
Test status
Simulation time 33044953347 ps
CPU time 1284.76 seconds
Started Mar 28 01:12:56 PM PDT 24
Finished Mar 28 01:34:22 PM PDT 24
Peak memory 287732 kb
Host smart-972de70a-7569-4265-8527-a2432f46db48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835333316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.835333316
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.126450176
Short name T394
Test name
Test status
Simulation time 997997325 ps
CPU time 10.39 seconds
Started Mar 28 01:13:05 PM PDT 24
Finished Mar 28 01:13:16 PM PDT 24
Peak memory 248896 kb
Host smart-3305ab71-8428-4e1f-8ce8-b7fa5f34bee0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=126450176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.126450176
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3714386268
Short name T530
Test name
Test status
Simulation time 1049605334 ps
CPU time 18.77 seconds
Started Mar 28 01:12:57 PM PDT 24
Finished Mar 28 01:13:16 PM PDT 24
Peak memory 254800 kb
Host smart-022c623e-ee75-4d42-923d-3fdac1d0e2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37143
86268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3714386268
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3653509981
Short name T616
Test name
Test status
Simulation time 352996146 ps
CPU time 11.77 seconds
Started Mar 28 01:12:53 PM PDT 24
Finished Mar 28 01:13:05 PM PDT 24
Peak memory 254328 kb
Host smart-d6f1d594-bf82-47fd-8490-80e681e15a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36535
09981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3653509981
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3778945661
Short name T557
Test name
Test status
Simulation time 34684798351 ps
CPU time 2184.64 seconds
Started Mar 28 01:13:06 PM PDT 24
Finished Mar 28 01:49:31 PM PDT 24
Peak memory 288948 kb
Host smart-acd51d4a-6f43-4dd9-b79b-cc7e782d0b1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778945661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3778945661
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.13796723
Short name T612
Test name
Test status
Simulation time 67139300441 ps
CPU time 1009.07 seconds
Started Mar 28 01:12:56 PM PDT 24
Finished Mar 28 01:29:46 PM PDT 24
Peak memory 272340 kb
Host smart-440268b9-37b2-436f-9d94-c651bf06cc76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13796723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.13796723
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.115163574
Short name T619
Test name
Test status
Simulation time 35001592305 ps
CPU time 360.71 seconds
Started Mar 28 01:12:56 PM PDT 24
Finished Mar 28 01:18:57 PM PDT 24
Peak memory 247936 kb
Host smart-46c73912-98f0-4fa3-9062-cb8cafdbe120
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115163574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.115163574
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1413325197
Short name T527
Test name
Test status
Simulation time 2047635917 ps
CPU time 55.82 seconds
Started Mar 28 01:12:52 PM PDT 24
Finished Mar 28 01:13:48 PM PDT 24
Peak memory 249292 kb
Host smart-5df4de88-8b39-4e86-9636-41bb02363c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14133
25197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1413325197
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.4215329190
Short name T508
Test name
Test status
Simulation time 773353294 ps
CPU time 13.21 seconds
Started Mar 28 01:12:59 PM PDT 24
Finished Mar 28 01:13:13 PM PDT 24
Peak memory 253476 kb
Host smart-4e57eba1-83fb-4bf1-83d6-6c24c1734e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42153
29190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4215329190
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1310158730
Short name T475
Test name
Test status
Simulation time 175242323 ps
CPU time 11.94 seconds
Started Mar 28 01:13:04 PM PDT 24
Finished Mar 28 01:13:16 PM PDT 24
Peak memory 248888 kb
Host smart-ecec646e-0f71-4143-94ea-47e68f605f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13101
58730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1310158730
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2349420413
Short name T658
Test name
Test status
Simulation time 1419570491 ps
CPU time 5.12 seconds
Started Mar 28 01:12:50 PM PDT 24
Finished Mar 28 01:12:56 PM PDT 24
Peak memory 240664 kb
Host smart-e07eb9fc-b303-4e6c-b315-ae628ea00d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23494
20413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2349420413
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.929588959
Short name T476
Test name
Test status
Simulation time 15313815323 ps
CPU time 1711.58 seconds
Started Mar 28 01:13:03 PM PDT 24
Finished Mar 28 01:41:35 PM PDT 24
Peak memory 289964 kb
Host smart-943cdb2c-d53f-45e1-a903-2fcc6b74c4fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929588959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.929588959
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.201571328
Short name T84
Test name
Test status
Simulation time 54125460181 ps
CPU time 6113.91 seconds
Started Mar 28 01:12:58 PM PDT 24
Finished Mar 28 02:54:53 PM PDT 24
Peak memory 371524 kb
Host smart-2281130f-f855-421b-9c4c-a10618f78682
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201571328 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.201571328
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.832312330
Short name T204
Test name
Test status
Simulation time 38476636 ps
CPU time 3.66 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:13:05 PM PDT 24
Peak memory 248908 kb
Host smart-30892eab-03bd-4c0d-9212-20b7243453dd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=832312330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.832312330
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2357772648
Short name T582
Test name
Test status
Simulation time 53988898143 ps
CPU time 3255.1 seconds
Started Mar 28 01:12:52 PM PDT 24
Finished Mar 28 02:07:08 PM PDT 24
Peak memory 288832 kb
Host smart-e57fe237-0ace-4cc8-aa1e-f7be526de913
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357772648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2357772648
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2634551686
Short name T367
Test name
Test status
Simulation time 4448310353 ps
CPU time 13.1 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:13:15 PM PDT 24
Peak memory 249000 kb
Host smart-c9ad021c-8cec-4c82-ad17-55ab5f8ee1e1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2634551686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2634551686
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3790918155
Short name T659
Test name
Test status
Simulation time 4076435123 ps
CPU time 32.06 seconds
Started Mar 28 01:13:00 PM PDT 24
Finished Mar 28 01:13:32 PM PDT 24
Peak memory 256032 kb
Host smart-993f8997-159c-4de8-a973-e0119ee7c643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37909
18155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3790918155
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2963362660
Short name T347
Test name
Test status
Simulation time 119988482174 ps
CPU time 3260.35 seconds
Started Mar 28 01:13:03 PM PDT 24
Finished Mar 28 02:07:24 PM PDT 24
Peak memory 289052 kb
Host smart-8592df25-406c-474b-9fd3-54f9d2c450f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963362660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2963362660
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4008765166
Short name T16
Test name
Test status
Simulation time 173379417079 ps
CPU time 2530.61 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 01:55:13 PM PDT 24
Peak memory 284012 kb
Host smart-79ee849f-c0f2-4ba9-9a52-6ce4187c0fb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008765166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4008765166
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.486451914
Short name T318
Test name
Test status
Simulation time 10811780962 ps
CPU time 446.95 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:20:29 PM PDT 24
Peak memory 247672 kb
Host smart-aa18d6a4-75a5-45be-83b8-ed91ce267b39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486451914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.486451914
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3175211238
Short name T378
Test name
Test status
Simulation time 703964640 ps
CPU time 24.94 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:13:26 PM PDT 24
Peak memory 248876 kb
Host smart-a4f8d62f-6ed3-4fa0-8a5c-e5adabbdf5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31752
11238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3175211238
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2928538448
Short name T115
Test name
Test status
Simulation time 485702525 ps
CPU time 25.67 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:13:27 PM PDT 24
Peak memory 255864 kb
Host smart-27873881-b1d0-46cf-aa84-5f731889db09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29285
38448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2928538448
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2254827271
Short name T510
Test name
Test status
Simulation time 2816266962 ps
CPU time 38.63 seconds
Started Mar 28 01:12:58 PM PDT 24
Finished Mar 28 01:13:38 PM PDT 24
Peak memory 255588 kb
Host smart-133ca435-45d2-4657-9d92-e764c6d3e12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22548
27271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2254827271
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2749263940
Short name T611
Test name
Test status
Simulation time 1808673490 ps
CPU time 54.09 seconds
Started Mar 28 01:13:00 PM PDT 24
Finished Mar 28 01:13:54 PM PDT 24
Peak memory 248884 kb
Host smart-36fd6b5b-52b6-442f-a512-4bdc4189e148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27492
63940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2749263940
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2188225711
Short name T653
Test name
Test status
Simulation time 4160588905 ps
CPU time 388.1 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 01:19:31 PM PDT 24
Peak memory 257108 kb
Host smart-f250c52b-51b6-4080-b372-b1ad5837dd15
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188225711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2188225711
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1201214750
Short name T202
Test name
Test status
Simulation time 49265127 ps
CPU time 3.71 seconds
Started Mar 28 01:12:05 PM PDT 24
Finished Mar 28 01:12:09 PM PDT 24
Peak memory 249124 kb
Host smart-77274a9b-5675-4e5d-a673-9efef344b697
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1201214750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1201214750
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1824042236
Short name T389
Test name
Test status
Simulation time 158111658300 ps
CPU time 2624.95 seconds
Started Mar 28 01:11:53 PM PDT 24
Finished Mar 28 01:55:38 PM PDT 24
Peak memory 289248 kb
Host smart-5afe64ed-20ac-4ba9-830e-9dd3ecb073d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824042236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1824042236
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1410421606
Short name T515
Test name
Test status
Simulation time 3237219886 ps
CPU time 39.79 seconds
Started Mar 28 01:12:05 PM PDT 24
Finished Mar 28 01:12:45 PM PDT 24
Peak memory 240680 kb
Host smart-2dd069b8-a37e-46dc-8383-9a97b6213cb2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1410421606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1410421606
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.4009561524
Short name T376
Test name
Test status
Simulation time 2515841336 ps
CPU time 66.68 seconds
Started Mar 28 01:11:48 PM PDT 24
Finished Mar 28 01:12:54 PM PDT 24
Peak memory 256820 kb
Host smart-e8aa0d14-e7c8-4a12-a3cc-549660c9d0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40095
61524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.4009561524
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.4056154273
Short name T34
Test name
Test status
Simulation time 367932590 ps
CPU time 16.68 seconds
Started Mar 28 01:11:52 PM PDT 24
Finished Mar 28 01:12:09 PM PDT 24
Peak memory 248680 kb
Host smart-d5793c4e-eb32-47c6-9b74-822606585f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40561
54273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.4056154273
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3891318101
Short name T484
Test name
Test status
Simulation time 16907847810 ps
CPU time 1120.29 seconds
Started Mar 28 01:11:56 PM PDT 24
Finished Mar 28 01:30:36 PM PDT 24
Peak memory 271932 kb
Host smart-413f28cd-01c6-4a4a-913b-6f659529429c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891318101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3891318101
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3367141517
Short name T633
Test name
Test status
Simulation time 73979240391 ps
CPU time 2648.41 seconds
Started Mar 28 01:11:51 PM PDT 24
Finished Mar 28 01:56:00 PM PDT 24
Peak memory 288644 kb
Host smart-76d6edc8-5946-4cde-a5cc-3469b9cc00b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367141517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3367141517
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1273746103
Short name T472
Test name
Test status
Simulation time 8832806476 ps
CPU time 367.64 seconds
Started Mar 28 01:11:51 PM PDT 24
Finished Mar 28 01:17:59 PM PDT 24
Peak memory 256336 kb
Host smart-bf0dc39f-daa8-4716-b37b-39c7c82c6b7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273746103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1273746103
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3234599037
Short name T365
Test name
Test status
Simulation time 1732430820 ps
CPU time 48.74 seconds
Started Mar 28 01:11:51 PM PDT 24
Finished Mar 28 01:12:40 PM PDT 24
Peak memory 248912 kb
Host smart-2624a003-f2b3-43d0-9a37-daba3a797f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32345
99037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3234599037
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3358741084
Short name T413
Test name
Test status
Simulation time 1327719601 ps
CPU time 22.24 seconds
Started Mar 28 01:11:50 PM PDT 24
Finished Mar 28 01:12:12 PM PDT 24
Peak memory 247648 kb
Host smart-6cd683c7-e577-4aa6-ab22-175b68edcb7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33587
41084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3358741084
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.4019136356
Short name T219
Test name
Test status
Simulation time 3638358002 ps
CPU time 51.9 seconds
Started Mar 28 01:11:52 PM PDT 24
Finished Mar 28 01:12:44 PM PDT 24
Peak memory 248352 kb
Host smart-59748ac9-ef34-42f2-8936-13c4667fa598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40191
36356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.4019136356
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2423486316
Short name T534
Test name
Test status
Simulation time 1420561657 ps
CPU time 44.95 seconds
Started Mar 28 01:11:50 PM PDT 24
Finished Mar 28 01:12:35 PM PDT 24
Peak memory 249116 kb
Host smart-a981d125-b2cb-4a66-ba4f-f4d98b43e6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24234
86316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2423486316
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.349289144
Short name T604
Test name
Test status
Simulation time 62757042713 ps
CPU time 1705 seconds
Started Mar 28 01:12:07 PM PDT 24
Finished Mar 28 01:40:32 PM PDT 24
Peak memory 287712 kb
Host smart-b038d88a-0807-4a32-8ad3-b22fb5b430b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349289144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.349289144
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2872750963
Short name T60
Test name
Test status
Simulation time 10794463232 ps
CPU time 778.29 seconds
Started Mar 28 01:12:56 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 273660 kb
Host smart-8e4abfa2-7169-461b-a7da-bbe5f2d078b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872750963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2872750963
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2705375359
Short name T245
Test name
Test status
Simulation time 4948296490 ps
CPU time 121.19 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 01:15:04 PM PDT 24
Peak memory 257108 kb
Host smart-bc7b5eee-0108-487e-94ad-13851e18fb9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27053
75359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2705375359
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1067512398
Short name T533
Test name
Test status
Simulation time 1960080977 ps
CPU time 26.65 seconds
Started Mar 28 01:13:05 PM PDT 24
Finished Mar 28 01:13:31 PM PDT 24
Peak memory 249140 kb
Host smart-cfb2c455-bf7c-4008-adbc-9faaefa05895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10675
12398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1067512398
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2602372562
Short name T303
Test name
Test status
Simulation time 35871193494 ps
CPU time 1144.41 seconds
Started Mar 28 01:13:03 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 265380 kb
Host smart-54435b89-9a1f-4ce9-8401-b43c3a155a66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602372562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2602372562
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3176456402
Short name T396
Test name
Test status
Simulation time 41701203653 ps
CPU time 1328.71 seconds
Started Mar 28 01:13:05 PM PDT 24
Finished Mar 28 01:35:13 PM PDT 24
Peak memory 273072 kb
Host smart-4163f60b-bf6d-439d-81b6-ab9ab05057e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176456402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3176456402
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.116642503
Short name T594
Test name
Test status
Simulation time 5472592831 ps
CPU time 121.15 seconds
Started Mar 28 01:13:03 PM PDT 24
Finished Mar 28 01:15:05 PM PDT 24
Peak memory 248204 kb
Host smart-8902d26f-bbe2-4d1b-a6b7-80e49d256a11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116642503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.116642503
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2853471340
Short name T13
Test name
Test status
Simulation time 569867437 ps
CPU time 27.48 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:13:28 PM PDT 24
Peak memory 256044 kb
Host smart-ad92b084-7eb1-450a-9eae-5b5c95f5272f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28534
71340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2853471340
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.613778516
Short name T579
Test name
Test status
Simulation time 991094939 ps
CPU time 51.69 seconds
Started Mar 28 01:13:04 PM PDT 24
Finished Mar 28 01:13:56 PM PDT 24
Peak memory 248752 kb
Host smart-dd51a237-3712-40ed-b8f2-33c54ee345e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61377
8516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.613778516
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3494108421
Short name T54
Test name
Test status
Simulation time 1782795429 ps
CPU time 39.74 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 01:13:42 PM PDT 24
Peak memory 254772 kb
Host smart-82c8a788-2b90-446b-b2af-c790ba994e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34941
08421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3494108421
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2355929888
Short name T107
Test name
Test status
Simulation time 321239795 ps
CPU time 28.69 seconds
Started Mar 28 01:12:54 PM PDT 24
Finished Mar 28 01:13:23 PM PDT 24
Peak memory 248908 kb
Host smart-3a2ac850-5d23-4ae9-993a-59d241e06271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23559
29888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2355929888
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2445125082
Short name T260
Test name
Test status
Simulation time 77273560968 ps
CPU time 2177.34 seconds
Started Mar 28 01:12:55 PM PDT 24
Finished Mar 28 01:49:13 PM PDT 24
Peak memory 289788 kb
Host smart-1d848fcf-547a-4e0a-92ab-c02717c8e0a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445125082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2445125082
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3621894113
Short name T451
Test name
Test status
Simulation time 39872036093 ps
CPU time 1228.59 seconds
Started Mar 28 01:13:00 PM PDT 24
Finished Mar 28 01:33:29 PM PDT 24
Peak memory 281772 kb
Host smart-97fd6642-235f-428f-8fc4-902b97ad82fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621894113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3621894113
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4051489703
Short name T568
Test name
Test status
Simulation time 3903773874 ps
CPU time 218.71 seconds
Started Mar 28 01:13:04 PM PDT 24
Finished Mar 28 01:16:42 PM PDT 24
Peak memory 256908 kb
Host smart-f935979b-b103-4946-9520-2af2a93ec002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40514
89703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4051489703
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2632351208
Short name T576
Test name
Test status
Simulation time 1946236845 ps
CPU time 57.25 seconds
Started Mar 28 01:12:54 PM PDT 24
Finished Mar 28 01:13:52 PM PDT 24
Peak memory 255480 kb
Host smart-b9af570a-be36-4a62-a27b-0d91d56a482d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26323
51208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2632351208
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1078699647
Short name T343
Test name
Test status
Simulation time 193569490986 ps
CPU time 2383.69 seconds
Started Mar 28 01:13:04 PM PDT 24
Finished Mar 28 01:52:48 PM PDT 24
Peak memory 286420 kb
Host smart-73506fbe-5efc-48cb-9be2-2ceb0fe92dc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078699647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1078699647
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.753795427
Short name T479
Test name
Test status
Simulation time 16352472675 ps
CPU time 1071.81 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:30:53 PM PDT 24
Peak memory 265396 kb
Host smart-6f99e5b9-5584-492f-ab8f-0d704d1c7181
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753795427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.753795427
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1876655751
Short name T524
Test name
Test status
Simulation time 412159448 ps
CPU time 9.83 seconds
Started Mar 28 01:13:00 PM PDT 24
Finished Mar 28 01:13:10 PM PDT 24
Peak memory 248900 kb
Host smart-38fb5187-de28-485d-a366-6dade06be283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18766
55751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1876655751
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2785845280
Short name T580
Test name
Test status
Simulation time 1880906810 ps
CPU time 49.23 seconds
Started Mar 28 01:12:59 PM PDT 24
Finished Mar 28 01:13:49 PM PDT 24
Peak memory 248756 kb
Host smart-0d5a17df-c8a7-488a-bebf-9035cca922a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27858
45280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2785845280
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1244677753
Short name T301
Test name
Test status
Simulation time 306048780 ps
CPU time 20.27 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:13:21 PM PDT 24
Peak memory 247420 kb
Host smart-663e8219-e6f3-47f9-a680-230a88d35927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12446
77753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1244677753
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3837879330
Short name T382
Test name
Test status
Simulation time 22578515 ps
CPU time 3.65 seconds
Started Mar 28 01:13:04 PM PDT 24
Finished Mar 28 01:13:08 PM PDT 24
Peak memory 240664 kb
Host smart-981b0fb6-846c-4961-b725-11c4540c36a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38378
79330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3837879330
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3702648955
Short name T693
Test name
Test status
Simulation time 53109932375 ps
CPU time 1158.82 seconds
Started Mar 28 01:12:57 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 273052 kb
Host smart-698219b5-df55-44b5-908c-5a83a3a23847
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702648955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3702648955
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.72139433
Short name T609
Test name
Test status
Simulation time 6833885910 ps
CPU time 67.05 seconds
Started Mar 28 01:13:03 PM PDT 24
Finished Mar 28 01:14:11 PM PDT 24
Peak memory 256844 kb
Host smart-2824c165-7da4-424f-bd8f-9d9ee295c546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72139
433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.72139433
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4033676462
Short name T685
Test name
Test status
Simulation time 2730457440 ps
CPU time 53.07 seconds
Started Mar 28 01:12:57 PM PDT 24
Finished Mar 28 01:13:51 PM PDT 24
Peak memory 248908 kb
Host smart-fda116e8-4c0b-4c95-9ffd-08d3cdd90c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40336
76462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4033676462
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.956562964
Short name T644
Test name
Test status
Simulation time 159477680182 ps
CPU time 2330.58 seconds
Started Mar 28 01:12:57 PM PDT 24
Finished Mar 28 01:51:48 PM PDT 24
Peak memory 288960 kb
Host smart-d31f7c31-5d55-4ad6-bebb-97ed23224288
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956562964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.956562964
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.617023937
Short name T492
Test name
Test status
Simulation time 33803427423 ps
CPU time 2254.22 seconds
Started Mar 28 01:13:04 PM PDT 24
Finished Mar 28 01:50:38 PM PDT 24
Peak memory 287356 kb
Host smart-1faed50b-5b86-4984-8080-3e982e06d578
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617023937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.617023937
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.4054256715
Short name T675
Test name
Test status
Simulation time 7028652158 ps
CPU time 145.68 seconds
Started Mar 28 01:13:02 PM PDT 24
Finished Mar 28 01:15:28 PM PDT 24
Peak memory 248144 kb
Host smart-3ac18d57-5d5d-4502-a237-64dd2c3de39b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054256715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.4054256715
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2603033233
Short name T558
Test name
Test status
Simulation time 470853590 ps
CPU time 7.9 seconds
Started Mar 28 01:12:59 PM PDT 24
Finished Mar 28 01:13:08 PM PDT 24
Peak memory 248668 kb
Host smart-ed184125-b769-4688-8a75-47ef19154d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26030
33233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2603033233
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2148125442
Short name T104
Test name
Test status
Simulation time 598172414 ps
CPU time 33.32 seconds
Started Mar 28 01:13:04 PM PDT 24
Finished Mar 28 01:13:37 PM PDT 24
Peak memory 248900 kb
Host smart-430226d3-e1f8-4fcd-9a6b-120987cab6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21481
25442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2148125442
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1742914452
Short name T591
Test name
Test status
Simulation time 292165136 ps
CPU time 18.57 seconds
Started Mar 28 01:12:57 PM PDT 24
Finished Mar 28 01:13:16 PM PDT 24
Peak memory 254348 kb
Host smart-8885f573-ceb1-4406-9919-15aa74b1c26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17429
14452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1742914452
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2697056706
Short name T416
Test name
Test status
Simulation time 287733277 ps
CPU time 24.03 seconds
Started Mar 28 01:13:00 PM PDT 24
Finished Mar 28 01:13:24 PM PDT 24
Peak memory 249108 kb
Host smart-f529b747-80d3-43f2-ade1-0145441a7725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26970
56706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2697056706
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3162354999
Short name T293
Test name
Test status
Simulation time 264726381671 ps
CPU time 3909.08 seconds
Started Mar 28 01:13:06 PM PDT 24
Finished Mar 28 02:18:16 PM PDT 24
Peak memory 305660 kb
Host smart-b3b88d96-4a15-4a5b-a36c-258beb8cbf5f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162354999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3162354999
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.945751414
Short name T385
Test name
Test status
Simulation time 10633661056 ps
CPU time 770.34 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:25:52 PM PDT 24
Peak memory 266172 kb
Host smart-f90e8c55-0f62-41e3-8744-273df4a2a07a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945751414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.945751414
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.618018145
Short name T690
Test name
Test status
Simulation time 381616154 ps
CPU time 21.02 seconds
Started Mar 28 01:12:55 PM PDT 24
Finished Mar 28 01:13:16 PM PDT 24
Peak memory 248764 kb
Host smart-2d47f345-be58-444f-8a56-acf9e8e496de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61801
8145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.618018145
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3634555080
Short name T621
Test name
Test status
Simulation time 899066698 ps
CPU time 34.11 seconds
Started Mar 28 01:13:00 PM PDT 24
Finished Mar 28 01:13:34 PM PDT 24
Peak memory 255612 kb
Host smart-9260f63e-9f26-4ef8-ae0a-4fcd202d720f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36345
55080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3634555080
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2491575537
Short name T543
Test name
Test status
Simulation time 147660481984 ps
CPU time 673.05 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:24:14 PM PDT 24
Peak memory 273532 kb
Host smart-f18d89f6-f49e-4081-9eaf-6b2f14b92a0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491575537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2491575537
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3446717619
Short name T411
Test name
Test status
Simulation time 25609352066 ps
CPU time 1792.95 seconds
Started Mar 28 01:13:00 PM PDT 24
Finished Mar 28 01:42:54 PM PDT 24
Peak memory 283800 kb
Host smart-e3eb5fc1-7ccf-4b4f-b8ec-252887276f3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446717619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3446717619
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3678869730
Short name T337
Test name
Test status
Simulation time 5666320182 ps
CPU time 242.96 seconds
Started Mar 28 01:13:00 PM PDT 24
Finished Mar 28 01:17:03 PM PDT 24
Peak memory 248284 kb
Host smart-9bc6675c-84c4-438a-92ea-d8331fd574c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678869730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3678869730
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.833749961
Short name T125
Test name
Test status
Simulation time 3036540788 ps
CPU time 30.82 seconds
Started Mar 28 01:12:59 PM PDT 24
Finished Mar 28 01:13:31 PM PDT 24
Peak memory 256108 kb
Host smart-84ac1d92-eeb7-4bdf-a725-8ea74fda83c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83374
9961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.833749961
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3000800597
Short name T581
Test name
Test status
Simulation time 7526678577 ps
CPU time 37.09 seconds
Started Mar 28 01:12:57 PM PDT 24
Finished Mar 28 01:13:35 PM PDT 24
Peak memory 248608 kb
Host smart-0bf0c070-63ff-4afa-aa4a-0d77e8b35489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30008
00597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3000800597
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2118548037
Short name T280
Test name
Test status
Simulation time 548889481 ps
CPU time 32.31 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:13:34 PM PDT 24
Peak memory 248880 kb
Host smart-da3d559f-7d9b-4bf9-82e5-9a032447d1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21185
48037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2118548037
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2952402855
Short name T696
Test name
Test status
Simulation time 260326997 ps
CPU time 17.49 seconds
Started Mar 28 01:13:01 PM PDT 24
Finished Mar 28 01:13:19 PM PDT 24
Peak memory 255544 kb
Host smart-5282210c-6a1a-4c27-a135-f3581f7750fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29524
02855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2952402855
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.4043668785
Short name T600
Test name
Test status
Simulation time 33777753198 ps
CPU time 1934.29 seconds
Started Mar 28 01:13:08 PM PDT 24
Finished Mar 28 01:45:23 PM PDT 24
Peak memory 272984 kb
Host smart-7f9c0508-5a51-49d3-9eba-55c2a3825f83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043668785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.4043668785
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.368442464
Short name T387
Test name
Test status
Simulation time 6936445791 ps
CPU time 216.78 seconds
Started Mar 28 01:13:18 PM PDT 24
Finished Mar 28 01:16:55 PM PDT 24
Peak memory 256752 kb
Host smart-0c53d2d6-c031-4dc4-b80c-7f2b1d51d653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36844
2464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.368442464
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.996810770
Short name T606
Test name
Test status
Simulation time 974182518 ps
CPU time 15.41 seconds
Started Mar 28 01:13:10 PM PDT 24
Finished Mar 28 01:13:25 PM PDT 24
Peak memory 254720 kb
Host smart-f935b166-ab27-4ac6-a6b2-00b869074ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99681
0770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.996810770
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1509356292
Short name T499
Test name
Test status
Simulation time 95486389678 ps
CPU time 1069.39 seconds
Started Mar 28 01:13:18 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 289064 kb
Host smart-ff9ce364-3aec-4f6d-b57d-139c2abe43e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509356292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1509356292
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1062640474
Short name T598
Test name
Test status
Simulation time 54840363626 ps
CPU time 1200.8 seconds
Started Mar 28 01:13:10 PM PDT 24
Finished Mar 28 01:33:11 PM PDT 24
Peak memory 289676 kb
Host smart-9f8fdfd8-3db5-4494-9ff6-cc7f47fbd4d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062640474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1062640474
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3786162717
Short name T315
Test name
Test status
Simulation time 18207213723 ps
CPU time 179.89 seconds
Started Mar 28 01:13:09 PM PDT 24
Finished Mar 28 01:16:09 PM PDT 24
Peak memory 248988 kb
Host smart-b9478a78-55dd-4713-84ef-c6e5b4d359d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786162717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3786162717
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.456644744
Short name T465
Test name
Test status
Simulation time 3067257921 ps
CPU time 38.29 seconds
Started Mar 28 01:13:08 PM PDT 24
Finished Mar 28 01:13:46 PM PDT 24
Peak memory 256032 kb
Host smart-18250790-f206-4d2c-9539-3b84b74e923a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45664
4744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.456644744
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3171254412
Short name T421
Test name
Test status
Simulation time 3488188982 ps
CPU time 43.98 seconds
Started Mar 28 01:13:08 PM PDT 24
Finished Mar 28 01:13:52 PM PDT 24
Peak memory 256324 kb
Host smart-8ae56fd5-4acd-48e1-91ab-3004a0393e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31712
54412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3171254412
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1882477874
Short name T607
Test name
Test status
Simulation time 183952906 ps
CPU time 11.67 seconds
Started Mar 28 01:13:09 PM PDT 24
Finished Mar 28 01:13:20 PM PDT 24
Peak memory 252784 kb
Host smart-9ce2a775-2bb6-45dd-b51e-e91d5adce361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18824
77874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1882477874
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2938995385
Short name T624
Test name
Test status
Simulation time 1191124878 ps
CPU time 23.96 seconds
Started Mar 28 01:13:17 PM PDT 24
Finished Mar 28 01:13:41 PM PDT 24
Peak memory 248896 kb
Host smart-66c4eaf7-2ae1-4d6e-a591-c45ed530106a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29389
95385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2938995385
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.880628218
Short name T73
Test name
Test status
Simulation time 4523195326 ps
CPU time 170.76 seconds
Started Mar 28 01:13:09 PM PDT 24
Finished Mar 28 01:16:00 PM PDT 24
Peak memory 257096 kb
Host smart-0f6f2adf-320c-454d-9604-f1238052dd11
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880628218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.880628218
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.4193731199
Short name T99
Test name
Test status
Simulation time 112988472470 ps
CPU time 1902.34 seconds
Started Mar 28 01:13:17 PM PDT 24
Finished Mar 28 01:45:00 PM PDT 24
Peak memory 284704 kb
Host smart-c330f23b-cb0d-4458-8e30-1052504daf9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193731199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4193731199
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1124729047
Short name T398
Test name
Test status
Simulation time 2364335570 ps
CPU time 77.1 seconds
Started Mar 28 01:13:08 PM PDT 24
Finished Mar 28 01:14:25 PM PDT 24
Peak memory 256924 kb
Host smart-0321bbd2-5015-4aac-b3fe-dc367a39fd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11247
29047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1124729047
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4271922845
Short name T404
Test name
Test status
Simulation time 88496053 ps
CPU time 8.92 seconds
Started Mar 28 01:13:04 PM PDT 24
Finished Mar 28 01:13:13 PM PDT 24
Peak memory 253072 kb
Host smart-5373d91a-338d-4b2c-a87b-902a94afae96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42719
22845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4271922845
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2676197490
Short name T255
Test name
Test status
Simulation time 146269383971 ps
CPU time 1356.67 seconds
Started Mar 28 01:13:12 PM PDT 24
Finished Mar 28 01:35:49 PM PDT 24
Peak memory 272836 kb
Host smart-3c6c2b62-780c-49d7-a446-e51931bd1e5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676197490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2676197490
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2063358750
Short name T312
Test name
Test status
Simulation time 38923705756 ps
CPU time 396.27 seconds
Started Mar 28 01:13:13 PM PDT 24
Finished Mar 28 01:19:50 PM PDT 24
Peak memory 254564 kb
Host smart-f9ad80fc-976b-45b1-a021-75c6f91a852e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063358750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2063358750
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.4069719962
Short name T61
Test name
Test status
Simulation time 580412823 ps
CPU time 38.19 seconds
Started Mar 28 01:13:19 PM PDT 24
Finished Mar 28 01:13:58 PM PDT 24
Peak memory 248908 kb
Host smart-5677f4ee-104e-4dbe-b851-d94f7b07910e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40697
19962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.4069719962
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.222271791
Short name T634
Test name
Test status
Simulation time 136780958 ps
CPU time 9.31 seconds
Started Mar 28 01:13:09 PM PDT 24
Finished Mar 28 01:13:18 PM PDT 24
Peak memory 253012 kb
Host smart-d3cdc081-7963-4a7c-93a1-23685760ddc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22227
1791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.222271791
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3437987595
Short name T618
Test name
Test status
Simulation time 741189814 ps
CPU time 41.06 seconds
Started Mar 28 01:13:07 PM PDT 24
Finished Mar 28 01:13:49 PM PDT 24
Peak memory 248860 kb
Host smart-3151bd1b-f366-4e3b-a99e-3b031c2461b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34379
87595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3437987595
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2391800419
Short name T397
Test name
Test status
Simulation time 1390191696 ps
CPU time 43.78 seconds
Started Mar 28 01:13:19 PM PDT 24
Finished Mar 28 01:14:04 PM PDT 24
Peak memory 256060 kb
Host smart-d3a8821e-f39b-42fb-9042-5e0b2b275839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23918
00419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2391800419
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2133501618
Short name T91
Test name
Test status
Simulation time 52109834877 ps
CPU time 3173.93 seconds
Started Mar 28 01:13:09 PM PDT 24
Finished Mar 28 02:06:03 PM PDT 24
Peak memory 289896 kb
Host smart-ac6283a2-1f59-4129-af0f-ae7ff8141a06
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133501618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2133501618
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3337308310
Short name T447
Test name
Test status
Simulation time 53638169487 ps
CPU time 1310.23 seconds
Started Mar 28 01:13:07 PM PDT 24
Finished Mar 28 01:34:58 PM PDT 24
Peak memory 285548 kb
Host smart-4d73dc32-5fe7-4be5-8ac0-ce7f06af3171
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337308310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3337308310
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.504751343
Short name T682
Test name
Test status
Simulation time 1740722151 ps
CPU time 102.29 seconds
Started Mar 28 01:13:09 PM PDT 24
Finished Mar 28 01:14:51 PM PDT 24
Peak memory 256908 kb
Host smart-f9a8e735-ea5a-44c5-9acb-a4491449bc14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50475
1343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.504751343
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1401586727
Short name T371
Test name
Test status
Simulation time 2782225214 ps
CPU time 53.92 seconds
Started Mar 28 01:13:07 PM PDT 24
Finished Mar 28 01:14:01 PM PDT 24
Peak memory 256164 kb
Host smart-b85a2921-ba5b-4de4-af10-ffb34ca83044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14015
86727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1401586727
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1150908863
Short name T227
Test name
Test status
Simulation time 114361418555 ps
CPU time 3248.32 seconds
Started Mar 28 01:13:19 PM PDT 24
Finished Mar 28 02:07:28 PM PDT 24
Peak memory 281536 kb
Host smart-244f9be0-0b74-4658-a091-fa4b670e2e48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150908863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1150908863
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.883897253
Short name T661
Test name
Test status
Simulation time 17825257031 ps
CPU time 840.55 seconds
Started Mar 28 01:13:07 PM PDT 24
Finished Mar 28 01:27:08 PM PDT 24
Peak memory 265384 kb
Host smart-bf120bf4-5ba6-4248-9ada-d34a93b0df1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883897253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.883897253
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1208936010
Short name T702
Test name
Test status
Simulation time 4181623361 ps
CPU time 176.73 seconds
Started Mar 28 01:13:06 PM PDT 24
Finished Mar 28 01:16:03 PM PDT 24
Peak memory 247856 kb
Host smart-673be95a-bd06-4fa8-a085-2e0e18d30d8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208936010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1208936010
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.4018521654
Short name T595
Test name
Test status
Simulation time 3026005572 ps
CPU time 28.47 seconds
Started Mar 28 01:13:09 PM PDT 24
Finished Mar 28 01:13:37 PM PDT 24
Peak memory 248856 kb
Host smart-d4337fcd-6bf2-422f-9dc2-a5b60daa3d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40185
21654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.4018521654
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3166942637
Short name T384
Test name
Test status
Simulation time 2702360198 ps
CPU time 9.88 seconds
Started Mar 28 01:13:19 PM PDT 24
Finished Mar 28 01:13:30 PM PDT 24
Peak memory 250216 kb
Host smart-2ea81ac0-7d81-4f62-96d3-f4ced395168f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31669
42637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3166942637
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2451708333
Short name T458
Test name
Test status
Simulation time 6900512006 ps
CPU time 53.25 seconds
Started Mar 28 01:13:09 PM PDT 24
Finished Mar 28 01:14:02 PM PDT 24
Peak memory 248836 kb
Host smart-d9f78770-bd9a-4a85-a48a-1626d24aba10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24517
08333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2451708333
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2163837053
Short name T17
Test name
Test status
Simulation time 1328691010 ps
CPU time 78.07 seconds
Started Mar 28 01:13:19 PM PDT 24
Finished Mar 28 01:14:38 PM PDT 24
Peak memory 248896 kb
Host smart-093b4b47-ef6b-4a37-8a1f-2ffa30bb49f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21638
37053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2163837053
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2705577180
Short name T504
Test name
Test status
Simulation time 124877456451 ps
CPU time 3670.52 seconds
Started Mar 28 01:13:09 PM PDT 24
Finished Mar 28 02:14:20 PM PDT 24
Peak memory 289868 kb
Host smart-b34f17fc-02ec-4761-8038-ce28f9479f3a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705577180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2705577180
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.642101095
Short name T429
Test name
Test status
Simulation time 101776426880 ps
CPU time 1681.57 seconds
Started Mar 28 01:13:26 PM PDT 24
Finished Mar 28 01:41:27 PM PDT 24
Peak memory 269672 kb
Host smart-e2bfbaff-1373-4ff5-b836-c27b55333331
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642101095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.642101095
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2316182680
Short name T2
Test name
Test status
Simulation time 2011756607 ps
CPU time 46.44 seconds
Started Mar 28 01:13:25 PM PDT 24
Finished Mar 28 01:14:12 PM PDT 24
Peak memory 248716 kb
Host smart-7089a90e-a244-4ce7-b914-e1a4b0c401e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23161
82680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2316182680
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2228570053
Short name T474
Test name
Test status
Simulation time 242742760 ps
CPU time 4.57 seconds
Started Mar 28 01:13:25 PM PDT 24
Finished Mar 28 01:13:30 PM PDT 24
Peak memory 240664 kb
Host smart-e1c21a6e-384e-41a0-8e52-19caa3ff63e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22285
70053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2228570053
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3580239284
Short name T321
Test name
Test status
Simulation time 85059722550 ps
CPU time 2276.2 seconds
Started Mar 28 01:13:27 PM PDT 24
Finished Mar 28 01:51:24 PM PDT 24
Peak memory 289888 kb
Host smart-4cfe2080-ed4b-4ba2-947b-77835f24e8ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580239284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3580239284
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1582730219
Short name T415
Test name
Test status
Simulation time 53739328999 ps
CPU time 1673.78 seconds
Started Mar 28 01:13:25 PM PDT 24
Finished Mar 28 01:41:19 PM PDT 24
Peak memory 273492 kb
Host smart-3c5db0d7-e5b8-4c58-94bf-6124f7df06c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582730219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1582730219
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1861283606
Short name T548
Test name
Test status
Simulation time 10928041074 ps
CPU time 197.71 seconds
Started Mar 28 01:13:28 PM PDT 24
Finished Mar 28 01:16:46 PM PDT 24
Peak memory 247892 kb
Host smart-7beb1436-1e7d-47a4-a88b-987d85e1b8fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861283606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1861283606
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1906951852
Short name T662
Test name
Test status
Simulation time 395016600 ps
CPU time 12.6 seconds
Started Mar 28 01:13:09 PM PDT 24
Finished Mar 28 01:13:22 PM PDT 24
Peak memory 252908 kb
Host smart-c183d16a-5a6d-4e5a-8f4e-11ac49a2c116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19069
51852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1906951852
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3890040874
Short name T573
Test name
Test status
Simulation time 86254209 ps
CPU time 6.52 seconds
Started Mar 28 01:13:26 PM PDT 24
Finished Mar 28 01:13:33 PM PDT 24
Peak memory 240480 kb
Host smart-98f43486-87e6-4c80-9cbb-419d47c252f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38900
40874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3890040874
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.96934947
Short name T464
Test name
Test status
Simulation time 1175224521 ps
CPU time 36.43 seconds
Started Mar 28 01:13:17 PM PDT 24
Finished Mar 28 01:13:53 PM PDT 24
Peak memory 256368 kb
Host smart-ba89bf00-a07a-4bf1-8206-5c867de983c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96934
947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.96934947
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2899120625
Short name T119
Test name
Test status
Simulation time 109385482664 ps
CPU time 1867.97 seconds
Started Mar 28 01:13:26 PM PDT 24
Finished Mar 28 01:44:34 PM PDT 24
Peak memory 282684 kb
Host smart-f67c60a3-03c0-475f-896d-6e08972f3965
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899120625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2899120625
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2106448270
Short name T556
Test name
Test status
Simulation time 102869685751 ps
CPU time 1500.99 seconds
Started Mar 28 01:13:25 PM PDT 24
Finished Mar 28 01:38:27 PM PDT 24
Peak memory 288212 kb
Host smart-ded3f07f-cb09-440e-883b-1078d674a56d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106448270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2106448270
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3180573675
Short name T232
Test name
Test status
Simulation time 7354960261 ps
CPU time 118.75 seconds
Started Mar 28 01:13:23 PM PDT 24
Finished Mar 28 01:15:22 PM PDT 24
Peak memory 256884 kb
Host smart-e89045c0-c416-4a89-8f78-d1addb338191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31805
73675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3180573675
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3199951106
Short name T81
Test name
Test status
Simulation time 1155575574 ps
CPU time 44.83 seconds
Started Mar 28 01:13:23 PM PDT 24
Finished Mar 28 01:14:08 PM PDT 24
Peak memory 248580 kb
Host smart-79d0e6b5-43a8-4623-bfde-1fd1aa4c5625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31999
51106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3199951106
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.651028187
Short name T14
Test name
Test status
Simulation time 33408832924 ps
CPU time 2064.99 seconds
Started Mar 28 01:13:25 PM PDT 24
Finished Mar 28 01:47:51 PM PDT 24
Peak memory 289940 kb
Host smart-ece01366-531b-4617-9de0-aec1bec561c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651028187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.651028187
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.176054694
Short name T424
Test name
Test status
Simulation time 10952038652 ps
CPU time 1219.43 seconds
Started Mar 28 01:13:25 PM PDT 24
Finished Mar 28 01:33:45 PM PDT 24
Peak memory 286392 kb
Host smart-bd4c9c60-fca5-4414-ab42-d95ae2925791
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176054694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.176054694
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3298165162
Short name T545
Test name
Test status
Simulation time 34276584214 ps
CPU time 319.51 seconds
Started Mar 28 01:13:25 PM PDT 24
Finished Mar 28 01:18:44 PM PDT 24
Peak memory 247164 kb
Host smart-750c78d3-2e1e-4bd2-b2be-4f9287734f63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298165162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3298165162
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2740021206
Short name T526
Test name
Test status
Simulation time 331392441 ps
CPU time 28.95 seconds
Started Mar 28 01:13:26 PM PDT 24
Finished Mar 28 01:13:55 PM PDT 24
Peak memory 248896 kb
Host smart-b6080d5a-cb2b-43c3-b2a6-78197f3d0d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27400
21206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2740021206
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.4217486359
Short name T626
Test name
Test status
Simulation time 148277225 ps
CPU time 6.97 seconds
Started Mar 28 01:13:24 PM PDT 24
Finished Mar 28 01:13:31 PM PDT 24
Peak memory 251896 kb
Host smart-3e0ae022-4278-439b-b5a9-230a646582f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42174
86359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.4217486359
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3077771206
Short name T294
Test name
Test status
Simulation time 1083862126 ps
CPU time 15.53 seconds
Started Mar 28 01:13:23 PM PDT 24
Finished Mar 28 01:13:39 PM PDT 24
Peak memory 248880 kb
Host smart-a872f9d2-8b9a-4719-9ac3-e5250531c8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30777
71206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3077771206
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1344115899
Short name T450
Test name
Test status
Simulation time 1412990360 ps
CPU time 20.03 seconds
Started Mar 28 01:13:30 PM PDT 24
Finished Mar 28 01:13:50 PM PDT 24
Peak memory 248884 kb
Host smart-f107a33b-bbd7-44e9-bab7-a454e75a285d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13441
15899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1344115899
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2032671278
Short name T120
Test name
Test status
Simulation time 299766119709 ps
CPU time 2141.52 seconds
Started Mar 28 01:13:25 PM PDT 24
Finished Mar 28 01:49:07 PM PDT 24
Peak memory 297812 kb
Host smart-e97ed0da-cd37-4f50-9fcc-de8810f5eb4c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032671278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2032671278
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.895614413
Short name T116
Test name
Test status
Simulation time 54256605705 ps
CPU time 1635.97 seconds
Started Mar 28 01:13:27 PM PDT 24
Finished Mar 28 01:40:44 PM PDT 24
Peak memory 273584 kb
Host smart-23b4eb94-2df4-44de-b999-080a7a88901c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895614413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.895614413
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.4002880205
Short name T372
Test name
Test status
Simulation time 133553789 ps
CPU time 7.58 seconds
Started Mar 28 01:13:24 PM PDT 24
Finished Mar 28 01:13:32 PM PDT 24
Peak memory 253436 kb
Host smart-80c2e871-09f5-4748-a065-a1f61e07bff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40028
80205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.4002880205
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.440154436
Short name T428
Test name
Test status
Simulation time 1723397185 ps
CPU time 33.03 seconds
Started Mar 28 01:13:26 PM PDT 24
Finished Mar 28 01:13:59 PM PDT 24
Peak memory 255728 kb
Host smart-032206d7-530e-488d-8ad5-4301401162ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44015
4436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.440154436
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1231815192
Short name T593
Test name
Test status
Simulation time 108015727811 ps
CPU time 3069.12 seconds
Started Mar 28 01:13:46 PM PDT 24
Finished Mar 28 02:04:56 PM PDT 24
Peak memory 288988 kb
Host smart-5967517d-aa18-4cba-a132-0bf12e3a8f5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231815192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1231815192
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3057517034
Short name T446
Test name
Test status
Simulation time 32457950915 ps
CPU time 718.79 seconds
Started Mar 28 01:13:42 PM PDT 24
Finished Mar 28 01:25:41 PM PDT 24
Peak memory 272656 kb
Host smart-37092883-0cdc-4bda-956f-bea59727bbfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057517034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3057517034
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1898396557
Short name T320
Test name
Test status
Simulation time 4428468035 ps
CPU time 189.12 seconds
Started Mar 28 01:13:34 PM PDT 24
Finished Mar 28 01:16:43 PM PDT 24
Peak memory 248052 kb
Host smart-d795cbe2-5ad8-4cc2-83c3-c8febaed529f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898396557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1898396557
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1119729897
Short name T575
Test name
Test status
Simulation time 2804894987 ps
CPU time 46.36 seconds
Started Mar 28 01:13:26 PM PDT 24
Finished Mar 28 01:14:12 PM PDT 24
Peak memory 248984 kb
Host smart-ee0246d9-876a-45a8-a817-5509482401a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11197
29897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1119729897
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2427150275
Short name T532
Test name
Test status
Simulation time 21588411 ps
CPU time 2.89 seconds
Started Mar 28 01:13:27 PM PDT 24
Finished Mar 28 01:13:30 PM PDT 24
Peak memory 239128 kb
Host smart-fca00822-6a98-4ac9-ad06-b1f49069bf1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24271
50275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2427150275
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3654867697
Short name T279
Test name
Test status
Simulation time 285026429 ps
CPU time 4.72 seconds
Started Mar 28 01:13:28 PM PDT 24
Finished Mar 28 01:13:33 PM PDT 24
Peak memory 240680 kb
Host smart-d27cda25-8647-4a6e-aa1d-98fada1073e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36548
67697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3654867697
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1623845417
Short name T503
Test name
Test status
Simulation time 4529260360 ps
CPU time 39.57 seconds
Started Mar 28 01:13:24 PM PDT 24
Finished Mar 28 01:14:04 PM PDT 24
Peak memory 249040 kb
Host smart-e5d07fc2-2fb9-4a3a-8cac-8d6cd04b909f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16238
45417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1623845417
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2291525494
Short name T262
Test name
Test status
Simulation time 9774728043 ps
CPU time 264.91 seconds
Started Mar 28 01:13:42 PM PDT 24
Finished Mar 28 01:18:07 PM PDT 24
Peak memory 257196 kb
Host smart-e00028f4-9819-41a6-970e-0dccf3735f1e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291525494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2291525494
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4073687427
Short name T239
Test name
Test status
Simulation time 50606156673 ps
CPU time 249.98 seconds
Started Mar 28 01:13:46 PM PDT 24
Finished Mar 28 01:17:56 PM PDT 24
Peak memory 268436 kb
Host smart-8fc6fa92-8500-498d-9596-310eecbca09d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073687427 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4073687427
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1657574290
Short name T215
Test name
Test status
Simulation time 113651405 ps
CPU time 2.94 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:12:11 PM PDT 24
Peak memory 249036 kb
Host smart-4640e1ff-c0fd-47ef-8113-6b190d7ad45e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1657574290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1657574290
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1166415454
Short name T565
Test name
Test status
Simulation time 121921263072 ps
CPU time 1958.81 seconds
Started Mar 28 01:12:06 PM PDT 24
Finished Mar 28 01:44:45 PM PDT 24
Peak memory 273568 kb
Host smart-db911d36-b508-4e84-b181-3cb89c48e859
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166415454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1166415454
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3545409537
Short name T392
Test name
Test status
Simulation time 2266299393 ps
CPU time 93.12 seconds
Started Mar 28 01:12:07 PM PDT 24
Finished Mar 28 01:13:40 PM PDT 24
Peak memory 248956 kb
Host smart-dfb8e06e-9dd7-472e-882c-042ad2c80710
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3545409537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3545409537
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.161312434
Short name T473
Test name
Test status
Simulation time 242759366 ps
CPU time 13.21 seconds
Started Mar 28 01:12:06 PM PDT 24
Finished Mar 28 01:12:19 PM PDT 24
Peak memory 254300 kb
Host smart-ff6cc7d3-7b1e-4700-af8e-d0b5eaa65116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16131
2434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.161312434
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2665864467
Short name T668
Test name
Test status
Simulation time 687477099 ps
CPU time 4.02 seconds
Started Mar 28 01:12:06 PM PDT 24
Finished Mar 28 01:12:10 PM PDT 24
Peak memory 239084 kb
Host smart-53b634af-d176-413a-b632-8f11375a8efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26658
64467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2665864467
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3960465317
Short name T350
Test name
Test status
Simulation time 42191942140 ps
CPU time 654.83 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:23:03 PM PDT 24
Peak memory 265364 kb
Host smart-955df6a2-1502-4510-b9c1-2a4307f2de57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960465317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3960465317
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2467626140
Short name T229
Test name
Test status
Simulation time 84658216044 ps
CPU time 857.25 seconds
Started Mar 28 01:12:56 PM PDT 24
Finished Mar 28 01:27:14 PM PDT 24
Peak memory 272896 kb
Host smart-886b07df-4549-42a0-aacb-a5f93b351ba3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467626140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2467626140
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1478727635
Short name T324
Test name
Test status
Simulation time 58638912208 ps
CPU time 504.41 seconds
Started Mar 28 01:12:07 PM PDT 24
Finished Mar 28 01:20:32 PM PDT 24
Peak memory 247900 kb
Host smart-0a3b7183-2953-4fa7-a876-e7dcd845073b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478727635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1478727635
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2372125997
Short name T485
Test name
Test status
Simulation time 639347888 ps
CPU time 23.93 seconds
Started Mar 28 01:12:07 PM PDT 24
Finished Mar 28 01:12:31 PM PDT 24
Peak memory 248920 kb
Host smart-9792e71d-a07e-45e6-8c1c-e0292b0c05aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23721
25997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2372125997
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.600583588
Short name T654
Test name
Test status
Simulation time 653412758 ps
CPU time 37.3 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:12:46 PM PDT 24
Peak memory 255932 kb
Host smart-3da329a4-8163-4ba4-bcf7-bea4f669f4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60058
3588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.600583588
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1481262637
Short name T38
Test name
Test status
Simulation time 640008576 ps
CPU time 18.53 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:12:27 PM PDT 24
Peak memory 266592 kb
Host smart-935e0ae1-3541-4085-85e1-0d121d3a93e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1481262637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1481262637
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.214009146
Short name T431
Test name
Test status
Simulation time 284015807 ps
CPU time 16.69 seconds
Started Mar 28 01:12:06 PM PDT 24
Finished Mar 28 01:12:23 PM PDT 24
Peak memory 247164 kb
Host smart-2cd920ca-0a63-4fca-87c4-1fab45eda11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21400
9146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.214009146
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3641011306
Short name T391
Test name
Test status
Simulation time 304911498 ps
CPU time 22.53 seconds
Started Mar 28 01:12:06 PM PDT 24
Finished Mar 28 01:12:29 PM PDT 24
Peak memory 255488 kb
Host smart-15943ddd-2c8c-4739-8e9e-50fa572ccce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36410
11306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3641011306
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1595065758
Short name T253
Test name
Test status
Simulation time 46796011029 ps
CPU time 3094.72 seconds
Started Mar 28 01:12:06 PM PDT 24
Finished Mar 28 02:03:41 PM PDT 24
Peak memory 298168 kb
Host smart-de5a0c14-12cb-42de-ab93-ef924d0fc060
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595065758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1595065758
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.4280443303
Short name T637
Test name
Test status
Simulation time 171116262095 ps
CPU time 3124.73 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 02:04:13 PM PDT 24
Peak memory 303268 kb
Host smart-dc88a505-7c42-4fca-96a7-a777c5231cc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280443303 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.4280443303
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2179584141
Short name T601
Test name
Test status
Simulation time 5462485037 ps
CPU time 103.95 seconds
Started Mar 28 01:13:44 PM PDT 24
Finished Mar 28 01:15:28 PM PDT 24
Peak memory 250020 kb
Host smart-eeec9000-12e3-4958-be48-562610b7823d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21795
84141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2179584141
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3758909273
Short name T671
Test name
Test status
Simulation time 729210472 ps
CPU time 34.63 seconds
Started Mar 28 01:13:45 PM PDT 24
Finished Mar 28 01:14:20 PM PDT 24
Peak memory 249312 kb
Host smart-2abc11d3-adc2-40fa-a5ea-a963456c6d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37589
09273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3758909273
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1231224193
Short name T567
Test name
Test status
Simulation time 51075040303 ps
CPU time 1415.61 seconds
Started Mar 28 01:13:42 PM PDT 24
Finished Mar 28 01:37:18 PM PDT 24
Peak memory 289952 kb
Host smart-b65e7f9e-5f75-4ba4-9897-90915813a8e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231224193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1231224193
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2934136364
Short name T642
Test name
Test status
Simulation time 12433893053 ps
CPU time 517.34 seconds
Started Mar 28 01:13:45 PM PDT 24
Finished Mar 28 01:22:23 PM PDT 24
Peak memory 247152 kb
Host smart-30e70f46-d6a2-415f-8d9b-f4c3565280f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934136364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2934136364
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1650593175
Short name T453
Test name
Test status
Simulation time 1537759804 ps
CPU time 44.77 seconds
Started Mar 28 01:13:42 PM PDT 24
Finished Mar 28 01:14:27 PM PDT 24
Peak memory 248900 kb
Host smart-a942ec21-0bef-4339-8e19-433be8b4568c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16505
93175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1650593175
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.238257660
Short name T263
Test name
Test status
Simulation time 1645364079 ps
CPU time 40.89 seconds
Started Mar 28 01:13:50 PM PDT 24
Finished Mar 28 01:14:31 PM PDT 24
Peak memory 254236 kb
Host smart-9b1aa214-8563-464e-b4a1-7e3afd2053f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23825
7660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.238257660
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3020143118
Short name T436
Test name
Test status
Simulation time 503045818 ps
CPU time 32.27 seconds
Started Mar 28 01:13:45 PM PDT 24
Finished Mar 28 01:14:18 PM PDT 24
Peak memory 248768 kb
Host smart-d171fa80-f9f4-40c2-8609-1f614e353164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30201
43118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3020143118
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3483646588
Short name T560
Test name
Test status
Simulation time 17558077204 ps
CPU time 52.08 seconds
Started Mar 28 01:13:44 PM PDT 24
Finished Mar 28 01:14:36 PM PDT 24
Peak memory 249140 kb
Host smart-083b1be1-1664-4390-91ce-999e17db26c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
46588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3483646588
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3417007256
Short name T698
Test name
Test status
Simulation time 708268378 ps
CPU time 11.04 seconds
Started Mar 28 01:13:46 PM PDT 24
Finished Mar 28 01:13:57 PM PDT 24
Peak memory 252716 kb
Host smart-ca6f295c-43e3-4c2d-86e6-614ce62a6073
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417007256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3417007256
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2703466586
Short name T694
Test name
Test status
Simulation time 117969606932 ps
CPU time 5474.24 seconds
Started Mar 28 01:13:45 PM PDT 24
Finished Mar 28 02:45:00 PM PDT 24
Peak memory 322528 kb
Host smart-aa0aab12-73dd-4657-a8c0-16a74fd5fe8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703466586 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2703466586
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3562204033
Short name T386
Test name
Test status
Simulation time 42758598110 ps
CPU time 1490.05 seconds
Started Mar 28 01:13:52 PM PDT 24
Finished Mar 28 01:38:43 PM PDT 24
Peak memory 265360 kb
Host smart-7c6e3b1f-0f12-4bcb-ba1b-253c1d7f947d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562204033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3562204033
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2179155939
Short name T641
Test name
Test status
Simulation time 26026464419 ps
CPU time 161.26 seconds
Started Mar 28 01:13:44 PM PDT 24
Finished Mar 28 01:16:26 PM PDT 24
Peak memory 249884 kb
Host smart-25ee9479-f631-4c25-8a1a-f47b7b6e6359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21791
55939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2179155939
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2460516841
Short name T234
Test name
Test status
Simulation time 3842948636 ps
CPU time 52.77 seconds
Started Mar 28 01:13:43 PM PDT 24
Finished Mar 28 01:14:36 PM PDT 24
Peak memory 255604 kb
Host smart-8e74a1ac-a8ee-4834-9f8e-d7235e1635f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24605
16841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2460516841
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.769504686
Short name T1
Test name
Test status
Simulation time 68459985109 ps
CPU time 1531.48 seconds
Started Mar 28 01:13:46 PM PDT 24
Finished Mar 28 01:39:17 PM PDT 24
Peak memory 281760 kb
Host smart-3d5fab01-32af-4b71-940d-0e1f754e913b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769504686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.769504686
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1557927562
Short name T489
Test name
Test status
Simulation time 9530347441 ps
CPU time 906.29 seconds
Started Mar 28 01:13:48 PM PDT 24
Finished Mar 28 01:28:54 PM PDT 24
Peak memory 272972 kb
Host smart-8de43813-cd6e-4460-8a06-fac32bcb8e76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557927562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1557927562
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1275667270
Short name T333
Test name
Test status
Simulation time 7460770164 ps
CPU time 321.09 seconds
Started Mar 28 01:13:46 PM PDT 24
Finished Mar 28 01:19:07 PM PDT 24
Peak memory 247924 kb
Host smart-074f0e24-3490-445a-8ee5-44b6b9aeb139
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275667270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1275667270
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1811402785
Short name T370
Test name
Test status
Simulation time 2696457252 ps
CPU time 14.1 seconds
Started Mar 28 01:13:44 PM PDT 24
Finished Mar 28 01:13:58 PM PDT 24
Peak memory 256072 kb
Host smart-81dfacb3-08d4-4d07-bbf5-663571d59b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18114
02785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1811402785
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1010664057
Short name T563
Test name
Test status
Simulation time 616538575 ps
CPU time 29.28 seconds
Started Mar 28 01:13:46 PM PDT 24
Finished Mar 28 01:14:15 PM PDT 24
Peak memory 255680 kb
Host smart-efb802f1-deb0-47ab-8583-8d3af223af95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10106
64057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1010664057
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2703102707
Short name T64
Test name
Test status
Simulation time 692557118 ps
CPU time 9.27 seconds
Started Mar 28 01:13:45 PM PDT 24
Finished Mar 28 01:13:54 PM PDT 24
Peak memory 247476 kb
Host smart-9248c815-3f1a-46c9-b502-a0d195cabe41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27031
02707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2703102707
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2224178645
Short name T221
Test name
Test status
Simulation time 1508608389 ps
CPU time 25.73 seconds
Started Mar 28 01:13:45 PM PDT 24
Finished Mar 28 01:14:11 PM PDT 24
Peak memory 248740 kb
Host smart-06bcc1f6-e380-44c6-b1b0-d6786b81844a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22241
78645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2224178645
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.402006411
Short name T635
Test name
Test status
Simulation time 30315378338 ps
CPU time 553.98 seconds
Started Mar 28 01:13:49 PM PDT 24
Finished Mar 28 01:23:04 PM PDT 24
Peak memory 264796 kb
Host smart-a008561e-5d51-4e29-9c32-b306a2d79913
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402006411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.402006411
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1073845827
Short name T552
Test name
Test status
Simulation time 2269133007 ps
CPU time 132.21 seconds
Started Mar 28 01:13:43 PM PDT 24
Finished Mar 28 01:15:55 PM PDT 24
Peak memory 256840 kb
Host smart-4b51abcd-ce19-4b59-8d97-9a0e647617fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10738
45827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1073845827
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2182683523
Short name T666
Test name
Test status
Simulation time 1147298722 ps
CPU time 16.95 seconds
Started Mar 28 01:13:46 PM PDT 24
Finished Mar 28 01:14:03 PM PDT 24
Peak memory 248828 kb
Host smart-5165055b-2fc4-4ff6-92fa-60db57fa0271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21826
83523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2182683523
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2263606388
Short name T68
Test name
Test status
Simulation time 197668569675 ps
CPU time 2933.86 seconds
Started Mar 28 01:13:44 PM PDT 24
Finished Mar 28 02:02:38 PM PDT 24
Peak memory 288832 kb
Host smart-519bbd46-0960-473b-9fd5-f0bbd8c84558
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263606388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2263606388
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2569013868
Short name T578
Test name
Test status
Simulation time 29286199991 ps
CPU time 1762.74 seconds
Started Mar 28 01:13:43 PM PDT 24
Finished Mar 28 01:43:06 PM PDT 24
Peak memory 272952 kb
Host smart-2d5091b5-44ed-45c3-92cf-c124108e4daf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569013868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2569013868
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3830859880
Short name T8
Test name
Test status
Simulation time 12165295438 ps
CPU time 240.74 seconds
Started Mar 28 01:13:46 PM PDT 24
Finished Mar 28 01:17:47 PM PDT 24
Peak memory 255328 kb
Host smart-a113bdb2-eb4e-448c-91e5-66ff6473e499
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830859880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3830859880
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.4200119710
Short name T406
Test name
Test status
Simulation time 282147569 ps
CPU time 5.29 seconds
Started Mar 28 01:13:44 PM PDT 24
Finished Mar 28 01:13:49 PM PDT 24
Peak memory 240608 kb
Host smart-f0613e4c-71b7-4a0f-8f57-753eb84da375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42001
19710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.4200119710
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3695068634
Short name T369
Test name
Test status
Simulation time 44372262 ps
CPU time 5.3 seconds
Started Mar 28 01:13:44 PM PDT 24
Finished Mar 28 01:13:49 PM PDT 24
Peak memory 247344 kb
Host smart-43f3bd6b-70a5-459a-b199-77f7aac3e20a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36950
68634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3695068634
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.795593953
Short name T646
Test name
Test status
Simulation time 954032544 ps
CPU time 11.62 seconds
Started Mar 28 01:13:44 PM PDT 24
Finished Mar 28 01:13:56 PM PDT 24
Peak memory 251944 kb
Host smart-36bfdab9-3db1-40ab-b256-a2eb043f4abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79559
3953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.795593953
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1866245999
Short name T521
Test name
Test status
Simulation time 304053425 ps
CPU time 25.89 seconds
Started Mar 28 01:13:45 PM PDT 24
Finished Mar 28 01:14:11 PM PDT 24
Peak memory 248948 kb
Host smart-69ba7041-bf5a-44a8-b03a-d2cfac2be6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18662
45999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1866245999
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2284215711
Short name T417
Test name
Test status
Simulation time 4063358259 ps
CPU time 93.15 seconds
Started Mar 28 01:13:44 PM PDT 24
Finished Mar 28 01:15:17 PM PDT 24
Peak memory 257136 kb
Host smart-dec45666-c577-43f0-a2ac-1783bf12266a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284215711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2284215711
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1272856777
Short name T118
Test name
Test status
Simulation time 451282562761 ps
CPU time 2137.69 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 01:49:45 PM PDT 24
Peak memory 273540 kb
Host smart-f448a4fb-f008-4569-815b-7ff7715b9fd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272856777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1272856777
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.104862410
Short name T559
Test name
Test status
Simulation time 409798940 ps
CPU time 30.11 seconds
Started Mar 28 01:13:50 PM PDT 24
Finished Mar 28 01:14:20 PM PDT 24
Peak memory 256740 kb
Host smart-44f1bb58-bf71-4f8e-8b79-606b13669880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10486
2410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.104862410
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3282109731
Short name T433
Test name
Test status
Simulation time 514387208 ps
CPU time 32.56 seconds
Started Mar 28 01:13:45 PM PDT 24
Finished Mar 28 01:14:17 PM PDT 24
Peak memory 249136 kb
Host smart-093d8e7d-7766-4227-86ad-eaa07a7aa563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32821
09731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3282109731
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3658719370
Short name T456
Test name
Test status
Simulation time 43308524476 ps
CPU time 2424.79 seconds
Started Mar 28 01:14:06 PM PDT 24
Finished Mar 28 01:54:32 PM PDT 24
Peak memory 289452 kb
Host smart-a3094b9e-9b98-41d8-8ded-96c09dc78178
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658719370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3658719370
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1001960249
Short name T307
Test name
Test status
Simulation time 30335509943 ps
CPU time 332.07 seconds
Started Mar 28 01:14:08 PM PDT 24
Finished Mar 28 01:19:41 PM PDT 24
Peak memory 247932 kb
Host smart-2401731c-181f-4bff-98c2-6f06cbb649ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001960249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1001960249
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1267089457
Short name T525
Test name
Test status
Simulation time 3583966543 ps
CPU time 50.93 seconds
Started Mar 28 01:13:45 PM PDT 24
Finished Mar 28 01:14:36 PM PDT 24
Peak memory 256184 kb
Host smart-080a4ca9-d53e-4762-b33e-be7685a85cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12670
89457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1267089457
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2361166499
Short name T123
Test name
Test status
Simulation time 947111958 ps
CPU time 20.53 seconds
Started Mar 28 01:13:49 PM PDT 24
Finished Mar 28 01:14:10 PM PDT 24
Peak memory 247048 kb
Host smart-82430b09-8645-4fde-b266-085425ecc625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23611
66499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2361166499
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.898257055
Short name T461
Test name
Test status
Simulation time 1566261139 ps
CPU time 28.24 seconds
Started Mar 28 01:14:05 PM PDT 24
Finished Mar 28 01:14:35 PM PDT 24
Peak memory 254548 kb
Host smart-49955f1c-a696-4ff1-a1cf-7b1fdeecf7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89825
7055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.898257055
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2617175492
Short name T427
Test name
Test status
Simulation time 1040973497 ps
CPU time 26.3 seconds
Started Mar 28 01:13:45 PM PDT 24
Finished Mar 28 01:14:11 PM PDT 24
Peak memory 255548 kb
Host smart-b6a6ddd9-b36d-47cd-b5b1-12852090e5c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26171
75492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2617175492
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4039969342
Short name T37
Test name
Test status
Simulation time 12344367316 ps
CPU time 1377.17 seconds
Started Mar 28 01:14:05 PM PDT 24
Finished Mar 28 01:37:03 PM PDT 24
Peak memory 289972 kb
Host smart-eeb1867a-1365-4837-be4c-2db81266b9d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039969342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4039969342
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.4101165202
Short name T110
Test name
Test status
Simulation time 142352143644 ps
CPU time 3763.97 seconds
Started Mar 28 01:14:08 PM PDT 24
Finished Mar 28 02:16:52 PM PDT 24
Peak memory 305712 kb
Host smart-8f75687f-348d-4f58-a4b4-76949ce2f644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101165202 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.4101165202
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1292114691
Short name T418
Test name
Test status
Simulation time 38749745586 ps
CPU time 2214.07 seconds
Started Mar 28 01:14:08 PM PDT 24
Finished Mar 28 01:51:02 PM PDT 24
Peak memory 287520 kb
Host smart-73db3f04-6341-4b3a-834e-0911e610be78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292114691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1292114691
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1786418154
Short name T233
Test name
Test status
Simulation time 4529405266 ps
CPU time 240.51 seconds
Started Mar 28 01:14:06 PM PDT 24
Finished Mar 28 01:18:07 PM PDT 24
Peak memory 250020 kb
Host smart-31113d0b-89a9-4f66-a67f-6e8dd881b4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17864
18154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1786418154
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2227053045
Short name T615
Test name
Test status
Simulation time 175045417 ps
CPU time 13.37 seconds
Started Mar 28 01:14:08 PM PDT 24
Finished Mar 28 01:14:22 PM PDT 24
Peak memory 254348 kb
Host smart-4a8fd943-6e1a-4b0b-bcac-cfce33c71964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22270
53045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2227053045
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1834524518
Short name T516
Test name
Test status
Simulation time 60811361931 ps
CPU time 1216.36 seconds
Started Mar 28 01:14:05 PM PDT 24
Finished Mar 28 01:34:22 PM PDT 24
Peak memory 283416 kb
Host smart-298e691b-a4b6-4fa0-b3f2-3eb420fc6f3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834524518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1834524518
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1544177895
Short name T531
Test name
Test status
Simulation time 14313013909 ps
CPU time 663.4 seconds
Started Mar 28 01:14:04 PM PDT 24
Finished Mar 28 01:25:08 PM PDT 24
Peak memory 265604 kb
Host smart-5b574f15-f92b-48ef-befa-1048092ed4f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544177895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1544177895
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2863388895
Short name T613
Test name
Test status
Simulation time 25666098601 ps
CPU time 496.62 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 01:22:24 PM PDT 24
Peak memory 248156 kb
Host smart-4489b4b5-31d3-43e4-9ef4-e8fa075b01d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863388895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2863388895
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1382813656
Short name T126
Test name
Test status
Simulation time 48497336 ps
CPU time 4.16 seconds
Started Mar 28 01:14:05 PM PDT 24
Finished Mar 28 01:14:10 PM PDT 24
Peak memory 240676 kb
Host smart-4e250371-ea6d-4192-838d-f0c4b02a6c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13828
13656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1382813656
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1575515818
Short name T522
Test name
Test status
Simulation time 135133818 ps
CPU time 15.81 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 01:14:23 PM PDT 24
Peak memory 255480 kb
Host smart-94a002a1-47a1-4f49-bf01-1f0038ade88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15755
15818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1575515818
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2107523469
Short name T300
Test name
Test status
Simulation time 814354231 ps
CPU time 48.05 seconds
Started Mar 28 01:14:08 PM PDT 24
Finished Mar 28 01:14:57 PM PDT 24
Peak memory 247504 kb
Host smart-fb21fc66-41e1-4167-93fe-dc67286a01fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21075
23469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2107523469
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2751478117
Short name T647
Test name
Test status
Simulation time 21862323898 ps
CPU time 77.72 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 01:15:26 PM PDT 24
Peak memory 249044 kb
Host smart-61ba49e9-6186-4321-b5a4-97cd144a2952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27514
78117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2751478117
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2248497549
Short name T651
Test name
Test status
Simulation time 32824988129 ps
CPU time 1452.77 seconds
Started Mar 28 01:14:04 PM PDT 24
Finished Mar 28 01:38:17 PM PDT 24
Peak memory 289784 kb
Host smart-00adc628-7b9e-4161-9b47-43fb80641e24
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248497549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2248497549
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1284183302
Short name T310
Test name
Test status
Simulation time 23062371490 ps
CPU time 1311.47 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 01:35:59 PM PDT 24
Peak memory 289680 kb
Host smart-0d4190f2-a069-4e05-802d-4f1626a5bd58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284183302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1284183302
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2499483617
Short name T584
Test name
Test status
Simulation time 14896747781 ps
CPU time 74.87 seconds
Started Mar 28 01:14:05 PM PDT 24
Finished Mar 28 01:15:21 PM PDT 24
Peak memory 248816 kb
Host smart-abb89914-964b-4702-b793-94b3db474601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24994
83617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2499483617
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3593934690
Short name T122
Test name
Test status
Simulation time 448736831 ps
CPU time 21.19 seconds
Started Mar 28 01:14:09 PM PDT 24
Finished Mar 28 01:14:30 PM PDT 24
Peak memory 249040 kb
Host smart-e6a9e5a3-7b71-41d2-82ba-58f80bb1927f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35939
34690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3593934690
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.729858069
Short name T482
Test name
Test status
Simulation time 45422839911 ps
CPU time 910.71 seconds
Started Mar 28 01:14:08 PM PDT 24
Finished Mar 28 01:29:19 PM PDT 24
Peak memory 270452 kb
Host smart-dcda04c3-811b-4774-82bb-46791f58602d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729858069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.729858069
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1985922634
Short name T331
Test name
Test status
Simulation time 10843361920 ps
CPU time 120.05 seconds
Started Mar 28 01:14:08 PM PDT 24
Finished Mar 28 01:16:09 PM PDT 24
Peak memory 248232 kb
Host smart-89f93010-dbe4-4f8c-8818-6811b5bc9eec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985922634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1985922634
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2187823120
Short name T588
Test name
Test status
Simulation time 519363600 ps
CPU time 10.72 seconds
Started Mar 28 01:14:05 PM PDT 24
Finished Mar 28 01:14:17 PM PDT 24
Peak memory 248960 kb
Host smart-979af309-dbec-4f37-92e5-0c1b5b4415c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21878
23120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2187823120
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2072835311
Short name T572
Test name
Test status
Simulation time 4308817022 ps
CPU time 55.46 seconds
Started Mar 28 01:14:05 PM PDT 24
Finished Mar 28 01:15:01 PM PDT 24
Peak memory 255136 kb
Host smart-cc3207f7-2378-4497-9a93-012aa74fedb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20728
35311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2072835311
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2981408794
Short name T434
Test name
Test status
Simulation time 362463092 ps
CPU time 6.62 seconds
Started Mar 28 01:14:06 PM PDT 24
Finished Mar 28 01:14:14 PM PDT 24
Peak memory 248768 kb
Host smart-45c49f60-5c6a-481d-b757-da9d703642c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29814
08794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2981408794
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2626427677
Short name T366
Test name
Test status
Simulation time 607879186 ps
CPU time 20.04 seconds
Started Mar 28 01:14:06 PM PDT 24
Finished Mar 28 01:14:26 PM PDT 24
Peak memory 248792 kb
Host smart-56da0fe2-649b-48f4-a9b2-36724fb50181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26264
27677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2626427677
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2234883764
Short name T267
Test name
Test status
Simulation time 34107629440 ps
CPU time 4396.12 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 02:27:24 PM PDT 24
Peak memory 333028 kb
Host smart-1ee0bbd5-da89-40d1-9023-78250f0bd9f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234883764 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2234883764
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1964583131
Short name T459
Test name
Test status
Simulation time 309305289371 ps
CPU time 1699.96 seconds
Started Mar 28 01:14:05 PM PDT 24
Finished Mar 28 01:42:25 PM PDT 24
Peak memory 289952 kb
Host smart-136c9300-6325-420b-8502-54f168f3d532
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964583131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1964583131
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2565851397
Short name T523
Test name
Test status
Simulation time 7251509443 ps
CPU time 136.47 seconds
Started Mar 28 01:14:05 PM PDT 24
Finished Mar 28 01:16:22 PM PDT 24
Peak memory 251056 kb
Host smart-1dcbb8d5-4366-4b73-bac1-bf3845e554f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25658
51397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2565851397
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.535324201
Short name T281
Test name
Test status
Simulation time 2884695030 ps
CPU time 46.67 seconds
Started Mar 28 01:14:08 PM PDT 24
Finished Mar 28 01:14:55 PM PDT 24
Peak memory 255560 kb
Host smart-a88290b4-8d83-4389-9913-de9ccef43577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53532
4201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.535324201
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2398432447
Short name T224
Test name
Test status
Simulation time 144919422503 ps
CPU time 1521.47 seconds
Started Mar 28 01:14:08 PM PDT 24
Finished Mar 28 01:39:30 PM PDT 24
Peak memory 281596 kb
Host smart-94ed9dd6-d069-4b2e-b3e4-d8ae118badbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398432447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2398432447
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.262097027
Short name T425
Test name
Test status
Simulation time 60507649918 ps
CPU time 1329.87 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 01:36:17 PM PDT 24
Peak memory 273592 kb
Host smart-eddbdb47-e4cb-4047-9560-a9c5c734d311
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262097027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.262097027
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2582534155
Short name T6
Test name
Test status
Simulation time 27250797620 ps
CPU time 369.7 seconds
Started Mar 28 01:14:09 PM PDT 24
Finished Mar 28 01:20:19 PM PDT 24
Peak memory 247972 kb
Host smart-80ea6b0b-93d2-452f-8eb1-7a7f9499a8b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582534155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2582534155
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.4005395986
Short name T505
Test name
Test status
Simulation time 3555793492 ps
CPU time 47.3 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 01:14:55 PM PDT 24
Peak memory 248780 kb
Host smart-fe066bd6-fa19-4673-a9ed-9c543395cbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40053
95986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.4005395986
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2359821393
Short name T48
Test name
Test status
Simulation time 2302039779 ps
CPU time 45.97 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 01:14:54 PM PDT 24
Peak memory 255488 kb
Host smart-2962dbef-7393-4fd4-bc9e-5ccd1b0a4af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23598
21393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2359821393
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.4210068278
Short name T374
Test name
Test status
Simulation time 139021730 ps
CPU time 5.07 seconds
Started Mar 28 01:14:09 PM PDT 24
Finished Mar 28 01:14:14 PM PDT 24
Peak memory 248860 kb
Host smart-7b93e9ec-b2d6-4042-8e7d-d1f43a65300e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42100
68278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.4210068278
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2350674311
Short name T103
Test name
Test status
Simulation time 85391102399 ps
CPU time 2091.35 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 01:48:59 PM PDT 24
Peak memory 289404 kb
Host smart-3feed333-db5b-4d59-a479-7fb0d614feb1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350674311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2350674311
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.50833536
Short name T500
Test name
Test status
Simulation time 23000148808 ps
CPU time 1063.76 seconds
Started Mar 28 01:14:23 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 288736 kb
Host smart-e4c98382-0d5a-4763-a1a7-bff75a3b5a54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50833536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.50833536
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1877077544
Short name T478
Test name
Test status
Simulation time 3378141144 ps
CPU time 152.46 seconds
Started Mar 28 01:14:10 PM PDT 24
Finished Mar 28 01:16:42 PM PDT 24
Peak memory 256920 kb
Host smart-f1afae68-7991-40fb-983a-e31fc07d6786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18770
77544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1877077544
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.301066095
Short name T502
Test name
Test status
Simulation time 220109040 ps
CPU time 18.37 seconds
Started Mar 28 01:14:06 PM PDT 24
Finished Mar 28 01:14:25 PM PDT 24
Peak memory 248892 kb
Host smart-ba5c91e5-66d1-4cfc-9f5b-df66a8f6a80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30106
6095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.301066095
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2620249425
Short name T583
Test name
Test status
Simulation time 98092967301 ps
CPU time 2737.18 seconds
Started Mar 28 01:14:23 PM PDT 24
Finished Mar 28 02:00:01 PM PDT 24
Peak memory 286456 kb
Host smart-c3fcf33b-558e-462a-8335-1514cefd4940
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620249425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2620249425
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2558680834
Short name T692
Test name
Test status
Simulation time 8746721138 ps
CPU time 963.56 seconds
Started Mar 28 01:14:23 PM PDT 24
Finished Mar 28 01:30:27 PM PDT 24
Peak memory 289452 kb
Host smart-1e229d3a-9ca4-415e-99fd-d2d6fc70dd40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558680834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2558680834
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3772999685
Short name T334
Test name
Test status
Simulation time 30841915563 ps
CPU time 623.13 seconds
Started Mar 28 01:14:23 PM PDT 24
Finished Mar 28 01:24:46 PM PDT 24
Peak memory 248220 kb
Host smart-34ed1d31-a503-4c8c-b017-12334b492234
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772999685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3772999685
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2070024340
Short name T49
Test name
Test status
Simulation time 1963452855 ps
CPU time 31.05 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 01:14:38 PM PDT 24
Peak memory 248880 kb
Host smart-d98e2461-998c-49da-92aa-f9f61b4d3f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20700
24340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2070024340
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1207685345
Short name T266
Test name
Test status
Simulation time 654819627 ps
CPU time 24.38 seconds
Started Mar 28 01:14:07 PM PDT 24
Finished Mar 28 01:14:32 PM PDT 24
Peak memory 255368 kb
Host smart-d30d8735-821f-4de4-ac77-f481e0acbe55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12076
85345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1207685345
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3299963086
Short name T640
Test name
Test status
Simulation time 1193041089 ps
CPU time 7.14 seconds
Started Mar 28 01:14:06 PM PDT 24
Finished Mar 28 01:14:14 PM PDT 24
Peak memory 249556 kb
Host smart-3908e886-4731-411d-b8ef-10abc333b9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32999
63086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3299963086
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.986357824
Short name T679
Test name
Test status
Simulation time 165660610 ps
CPU time 12.17 seconds
Started Mar 28 01:14:06 PM PDT 24
Finished Mar 28 01:14:19 PM PDT 24
Peak memory 254004 kb
Host smart-14c1c399-8601-4a97-a53e-7b54fb92b0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98635
7824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.986357824
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3354803343
Short name T517
Test name
Test status
Simulation time 15576634520 ps
CPU time 275.95 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:19:00 PM PDT 24
Peak memory 257156 kb
Host smart-9a994b2e-5c82-4d27-bbe2-706bd7050561
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354803343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3354803343
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.4021751486
Short name T377
Test name
Test status
Simulation time 13894105414 ps
CPU time 1252.83 seconds
Started Mar 28 01:14:23 PM PDT 24
Finished Mar 28 01:35:16 PM PDT 24
Peak memory 282804 kb
Host smart-1d30e275-c263-4bba-aa86-ca368bedb9ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021751486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.4021751486
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.4213709993
Short name T252
Test name
Test status
Simulation time 10789588815 ps
CPU time 165.54 seconds
Started Mar 28 01:14:29 PM PDT 24
Finished Mar 28 01:17:14 PM PDT 24
Peak memory 257044 kb
Host smart-aa538455-f246-44d5-8776-83434cccf10b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42137
09993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.4213709993
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.851205281
Short name T368
Test name
Test status
Simulation time 470695043 ps
CPU time 36.94 seconds
Started Mar 28 01:14:22 PM PDT 24
Finished Mar 28 01:14:59 PM PDT 24
Peak memory 255400 kb
Host smart-a2d88705-0190-426c-8faa-cc162d44dcf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85120
5281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.851205281
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1572492985
Short name T490
Test name
Test status
Simulation time 39953340935 ps
CPU time 841.3 seconds
Started Mar 28 01:14:27 PM PDT 24
Finished Mar 28 01:28:29 PM PDT 24
Peak memory 270724 kb
Host smart-84a35a38-1b16-40a0-b8ce-05c6451fd03e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572492985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1572492985
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.93917113
Short name T674
Test name
Test status
Simulation time 36690917692 ps
CPU time 1353.33 seconds
Started Mar 28 01:14:37 PM PDT 24
Finished Mar 28 01:37:11 PM PDT 24
Peak memory 289048 kb
Host smart-1556494a-9018-4680-b380-9fc174bb3a64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93917113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.93917113
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1775468147
Short name T680
Test name
Test status
Simulation time 288539897 ps
CPU time 24.15 seconds
Started Mar 28 01:14:27 PM PDT 24
Finished Mar 28 01:14:51 PM PDT 24
Peak memory 255596 kb
Host smart-ea9b9bd4-f063-4da2-8653-3f6294b0f932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17754
68147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1775468147
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2424382526
Short name T670
Test name
Test status
Simulation time 1107178366 ps
CPU time 26.31 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:14:51 PM PDT 24
Peak memory 247752 kb
Host smart-32100c06-fd4c-491e-9f4a-555938a29df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24243
82526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2424382526
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.844579890
Short name T278
Test name
Test status
Simulation time 980925282 ps
CPU time 64.16 seconds
Started Mar 28 01:14:36 PM PDT 24
Finished Mar 28 01:15:41 PM PDT 24
Peak memory 254816 kb
Host smart-85583279-8265-4fc8-8d9e-ce68988ae1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84457
9890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.844579890
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2264347046
Short name T435
Test name
Test status
Simulation time 3983225869 ps
CPU time 37.01 seconds
Started Mar 28 01:14:27 PM PDT 24
Finished Mar 28 01:15:05 PM PDT 24
Peak memory 256304 kb
Host smart-2fccc954-731f-43f8-8a32-e569f987d86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22643
47046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2264347046
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.608651464
Short name T466
Test name
Test status
Simulation time 66207860946 ps
CPU time 1808.59 seconds
Started Mar 28 01:14:26 PM PDT 24
Finished Mar 28 01:44:35 PM PDT 24
Peak memory 282216 kb
Host smart-16e44cea-f6e2-48e9-bd6c-02a79c8b8c1e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608651464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.608651464
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.415323290
Short name T514
Test name
Test status
Simulation time 19194874432 ps
CPU time 1217.82 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:34:42 PM PDT 24
Peak memory 272568 kb
Host smart-456318aa-7a20-42f0-a7b1-b342ce1a6f9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415323290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.415323290
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.309444264
Short name T605
Test name
Test status
Simulation time 8495573522 ps
CPU time 127.99 seconds
Started Mar 28 01:14:28 PM PDT 24
Finished Mar 28 01:16:36 PM PDT 24
Peak memory 250064 kb
Host smart-4f3c91d0-1000-4c56-96c2-aa724000c7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30944
4264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.309444264
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.224225033
Short name T395
Test name
Test status
Simulation time 654464192 ps
CPU time 34.33 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:14:58 PM PDT 24
Peak memory 248920 kb
Host smart-117b7db9-64ae-4f98-840e-b5a6d4f652c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22422
5033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.224225033
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1552104286
Short name T349
Test name
Test status
Simulation time 19619649011 ps
CPU time 826.1 seconds
Started Mar 28 01:14:36 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 272940 kb
Host smart-8160e4fc-f6ba-4a9b-8ab9-3373ef58b9c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552104286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1552104286
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1254061492
Short name T493
Test name
Test status
Simulation time 131677546060 ps
CPU time 2030.1 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:48:15 PM PDT 24
Peak memory 281780 kb
Host smart-258cf01f-059d-445c-a251-3934e7dde1a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254061492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1254061492
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.746610411
Short name T309
Test name
Test status
Simulation time 71081452741 ps
CPU time 742.59 seconds
Started Mar 28 01:14:23 PM PDT 24
Finished Mar 28 01:26:46 PM PDT 24
Peak memory 248080 kb
Host smart-18b9bca5-3a4b-442d-a23f-8350c637de98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746610411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.746610411
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2585142107
Short name T448
Test name
Test status
Simulation time 533401584 ps
CPU time 39.75 seconds
Started Mar 28 01:14:28 PM PDT 24
Finished Mar 28 01:15:07 PM PDT 24
Peak memory 248892 kb
Host smart-9e6e18d6-f20a-4fe1-8ab6-4977454af474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25851
42107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2585142107
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1448454622
Short name T50
Test name
Test status
Simulation time 9991662085 ps
CPU time 51.97 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:15:16 PM PDT 24
Peak memory 256296 kb
Host smart-d4abb70c-a39b-414a-ae33-3930130d5c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14484
54622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1448454622
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3233061330
Short name T590
Test name
Test status
Simulation time 216947986 ps
CPU time 15.83 seconds
Started Mar 28 01:14:36 PM PDT 24
Finished Mar 28 01:14:53 PM PDT 24
Peak memory 247320 kb
Host smart-41bba4e1-87e3-4804-a05a-ac8a6542f001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32330
61330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3233061330
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.160396928
Short name T467
Test name
Test status
Simulation time 193178161 ps
CPU time 14.51 seconds
Started Mar 28 01:14:22 PM PDT 24
Finished Mar 28 01:14:37 PM PDT 24
Peak memory 248872 kb
Host smart-25e915dc-34ae-40fa-b92e-bc9f0e6bb088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16039
6928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.160396928
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3748716509
Short name T673
Test name
Test status
Simulation time 2658916486 ps
CPU time 18.99 seconds
Started Mar 28 01:14:25 PM PDT 24
Finished Mar 28 01:14:44 PM PDT 24
Peak memory 248924 kb
Host smart-afde710e-66c6-48e5-bd4e-7e947afbb0ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748716509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3748716509
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1158494254
Short name T238
Test name
Test status
Simulation time 51423628241 ps
CPU time 1510.46 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:39:35 PM PDT 24
Peak memory 282932 kb
Host smart-3ed7b97c-d886-460e-b35e-8605c0b9883e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158494254 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1158494254
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2241172176
Short name T213
Test name
Test status
Simulation time 203562334 ps
CPU time 4.38 seconds
Started Mar 28 01:12:13 PM PDT 24
Finished Mar 28 01:12:17 PM PDT 24
Peak memory 249124 kb
Host smart-8543bd28-82f1-4142-8314-724e99d22df1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2241172176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2241172176
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1600577167
Short name T496
Test name
Test status
Simulation time 58641332146 ps
CPU time 886.88 seconds
Started Mar 28 01:12:07 PM PDT 24
Finished Mar 28 01:26:54 PM PDT 24
Peak memory 269920 kb
Host smart-f5a2d6c8-7b84-4d6b-88d8-f538731563c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600577167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1600577167
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.659934192
Short name T408
Test name
Test status
Simulation time 361060621 ps
CPU time 6.4 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:12:15 PM PDT 24
Peak memory 240640 kb
Host smart-344db49b-a413-403d-b310-5336a988859e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=659934192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.659934192
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.957100397
Short name T695
Test name
Test status
Simulation time 5678183624 ps
CPU time 177.59 seconds
Started Mar 28 01:12:06 PM PDT 24
Finished Mar 28 01:15:04 PM PDT 24
Peak memory 255564 kb
Host smart-9b43215c-ab4d-4aad-a937-21fc643bb44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95710
0397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.957100397
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3944468575
Short name T220
Test name
Test status
Simulation time 269543698 ps
CPU time 4.58 seconds
Started Mar 28 01:12:07 PM PDT 24
Finished Mar 28 01:12:12 PM PDT 24
Peak memory 251676 kb
Host smart-ca50a852-3abf-4a4e-8d6e-c0bc95316a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39444
68575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3944468575
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.22899893
Short name T342
Test name
Test status
Simulation time 138545133580 ps
CPU time 1044.28 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:29:33 PM PDT 24
Peak memory 272540 kb
Host smart-a33244e5-bc61-4084-8f96-115f663ff212
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22899893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.22899893
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.53216063
Short name T513
Test name
Test status
Simulation time 10797849368 ps
CPU time 1329.35 seconds
Started Mar 28 01:12:07 PM PDT 24
Finished Mar 28 01:34:16 PM PDT 24
Peak memory 289096 kb
Host smart-fe1b8d52-b4d3-4963-9f8b-ee9a1ca9b58e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53216063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.53216063
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3489874126
Short name T665
Test name
Test status
Simulation time 24167112640 ps
CPU time 247.98 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:16:16 PM PDT 24
Peak memory 248148 kb
Host smart-c4e8aa28-585d-4006-b3e0-84bbfefb647a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489874126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3489874126
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2959442586
Short name T506
Test name
Test status
Simulation time 467070797 ps
CPU time 22.41 seconds
Started Mar 28 01:12:07 PM PDT 24
Finished Mar 28 01:12:30 PM PDT 24
Peak memory 255004 kb
Host smart-1e6c5f80-4630-4d77-a849-a58940e7a69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29594
42586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2959442586
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1651332923
Short name T88
Test name
Test status
Simulation time 3270509380 ps
CPU time 45.93 seconds
Started Mar 28 01:12:09 PM PDT 24
Finished Mar 28 01:12:55 PM PDT 24
Peak memory 256156 kb
Host smart-4f8c03af-6a30-4be3-b9d7-7d1c3f9602e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16513
32923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1651332923
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3641620435
Short name T39
Test name
Test status
Simulation time 300012194 ps
CPU time 13.28 seconds
Started Mar 28 01:12:07 PM PDT 24
Finished Mar 28 01:12:20 PM PDT 24
Peak memory 273620 kb
Host smart-9365e028-b143-4729-8059-a5d69d44ea28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3641620435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3641620435
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3085216315
Short name T700
Test name
Test status
Simulation time 28435151 ps
CPU time 3.45 seconds
Started Mar 28 01:12:09 PM PDT 24
Finished Mar 28 01:12:12 PM PDT 24
Peak memory 239084 kb
Host smart-00002422-5a2c-4a65-b16a-cfd69bebead7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30852
16315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3085216315
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3402446409
Short name T528
Test name
Test status
Simulation time 555340589 ps
CPU time 31.99 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:12:40 PM PDT 24
Peak memory 248928 kb
Host smart-f9ee3b7d-2a9e-4b2e-a735-67ea0cea62f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34024
46409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3402446409
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2405519205
Short name T462
Test name
Test status
Simulation time 7056048405 ps
CPU time 471.29 seconds
Started Mar 28 01:12:13 PM PDT 24
Finished Mar 28 01:20:04 PM PDT 24
Peak memory 257204 kb
Host smart-79e22b0d-b7e7-4259-bd73-30cc9ba0afe5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405519205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2405519205
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2852394584
Short name T628
Test name
Test status
Simulation time 8021256984 ps
CPU time 853.36 seconds
Started Mar 28 01:14:22 PM PDT 24
Finished Mar 28 01:28:36 PM PDT 24
Peak memory 267512 kb
Host smart-88705229-911d-413e-990a-0014e38e48ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852394584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2852394584
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.898302248
Short name T65
Test name
Test status
Simulation time 1618004205 ps
CPU time 91.26 seconds
Started Mar 28 01:14:23 PM PDT 24
Finished Mar 28 01:15:55 PM PDT 24
Peak memory 256564 kb
Host smart-1f6f5834-86e3-4524-a2c3-568f3073943c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89830
2248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.898302248
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1018865817
Short name T20
Test name
Test status
Simulation time 3772383324 ps
CPU time 52.77 seconds
Started Mar 28 01:14:27 PM PDT 24
Finished Mar 28 01:15:20 PM PDT 24
Peak memory 248972 kb
Host smart-53d1dd29-5ab6-4822-b1a6-a9147a881a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10188
65817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1018865817
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.574870010
Short name T346
Test name
Test status
Simulation time 36649500462 ps
CPU time 754.56 seconds
Started Mar 28 01:14:27 PM PDT 24
Finished Mar 28 01:27:02 PM PDT 24
Peak memory 268452 kb
Host smart-73941260-1eb4-41b0-900d-74c4436f9afb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574870010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.574870010
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2032891448
Short name T259
Test name
Test status
Simulation time 16776127967 ps
CPU time 754.63 seconds
Started Mar 28 01:14:27 PM PDT 24
Finished Mar 28 01:27:02 PM PDT 24
Peak memory 273124 kb
Host smart-8e4bd704-0c11-47d4-8d0b-fc44f9c05944
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032891448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2032891448
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2053641484
Short name T329
Test name
Test status
Simulation time 47592542457 ps
CPU time 423.65 seconds
Started Mar 28 01:14:30 PM PDT 24
Finished Mar 28 01:21:33 PM PDT 24
Peak memory 248212 kb
Host smart-e215fa7b-a4cf-415a-a0e9-fc49dcc3661e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053641484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2053641484
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.4115060397
Short name T623
Test name
Test status
Simulation time 822874154 ps
CPU time 15.2 seconds
Started Mar 28 01:14:28 PM PDT 24
Finished Mar 28 01:14:43 PM PDT 24
Peak memory 248856 kb
Host smart-75e627e2-7f1a-46a8-ba19-303eb0d2383d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41150
60397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.4115060397
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.436572270
Short name T87
Test name
Test status
Simulation time 186031690 ps
CPU time 15.9 seconds
Started Mar 28 01:14:23 PM PDT 24
Finished Mar 28 01:14:39 PM PDT 24
Peak memory 255536 kb
Host smart-47e29cab-b275-4253-bc62-f9c0da55f00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43657
2270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.436572270
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1328315458
Short name T57
Test name
Test status
Simulation time 1352607039 ps
CPU time 39.79 seconds
Started Mar 28 01:14:26 PM PDT 24
Finished Mar 28 01:15:06 PM PDT 24
Peak memory 255456 kb
Host smart-9a043911-6a03-402c-9fe1-569ad9e4419f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13283
15458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1328315458
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2723509106
Short name T19
Test name
Test status
Simulation time 483462550 ps
CPU time 21.63 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:14:46 PM PDT 24
Peak memory 248880 kb
Host smart-f4750f06-df8b-49ed-a540-155e8a098d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27235
09106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2723509106
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1481168349
Short name T71
Test name
Test status
Simulation time 31171170679 ps
CPU time 1481.79 seconds
Started Mar 28 01:14:26 PM PDT 24
Finished Mar 28 01:39:08 PM PDT 24
Peak memory 289936 kb
Host smart-39c95206-b163-4e74-a3d5-163f8ae62ff7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481168349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1481168349
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1035399812
Short name T291
Test name
Test status
Simulation time 12083159444 ps
CPU time 1184.72 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:34:09 PM PDT 24
Peak memory 281852 kb
Host smart-7e6d2bd0-8592-43cb-9fd4-38d8ad1cb6e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035399812 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1035399812
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.761692853
Short name T483
Test name
Test status
Simulation time 73679322200 ps
CPU time 2445.36 seconds
Started Mar 28 01:14:25 PM PDT 24
Finished Mar 28 01:55:11 PM PDT 24
Peak memory 288324 kb
Host smart-e4809e13-1c9a-457d-a337-e07a277a2842
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761692853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.761692853
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2652034048
Short name T541
Test name
Test status
Simulation time 885985750 ps
CPU time 42.07 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:15:06 PM PDT 24
Peak memory 248668 kb
Host smart-6e73afbf-a3a7-414d-bb34-43bc3e1f72a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26520
34048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2652034048
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.133200373
Short name T652
Test name
Test status
Simulation time 297986728 ps
CPU time 9.62 seconds
Started Mar 28 01:14:32 PM PDT 24
Finished Mar 28 01:14:42 PM PDT 24
Peak memory 249204 kb
Host smart-60b17b90-d7d3-4884-8204-15c133eac2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13320
0373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.133200373
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2133029894
Short name T643
Test name
Test status
Simulation time 180337072483 ps
CPU time 1444.82 seconds
Started Mar 28 01:14:36 PM PDT 24
Finished Mar 28 01:38:42 PM PDT 24
Peak memory 288900 kb
Host smart-41b6ef07-5560-44db-84e1-957155a02938
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133029894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2133029894
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1330864791
Short name T114
Test name
Test status
Simulation time 32218871941 ps
CPU time 758.52 seconds
Started Mar 28 01:14:25 PM PDT 24
Finished Mar 28 01:27:04 PM PDT 24
Peak memory 266392 kb
Host smart-f4068743-eb41-493a-86bd-7aabcc292326
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330864791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1330864791
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3473710787
Short name T33
Test name
Test status
Simulation time 2208843120 ps
CPU time 25.89 seconds
Started Mar 28 01:14:23 PM PDT 24
Finished Mar 28 01:14:49 PM PDT 24
Peak memory 248948 kb
Host smart-cb516306-775d-418e-ac2a-2ddc23459f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34737
10787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3473710787
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3090593320
Short name T261
Test name
Test status
Simulation time 2929468945 ps
CPU time 35.47 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:15:00 PM PDT 24
Peak memory 257076 kb
Host smart-2b641ad0-5726-4760-9f85-e3c7ec48304b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30905
93320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3090593320
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1120799855
Short name T289
Test name
Test status
Simulation time 358028083 ps
CPU time 20.41 seconds
Started Mar 28 01:14:28 PM PDT 24
Finished Mar 28 01:14:48 PM PDT 24
Peak memory 249260 kb
Host smart-ee4aebba-ab0a-4cc4-bfcc-3381e627783b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11207
99855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1120799855
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1616069465
Short name T689
Test name
Test status
Simulation time 675089283 ps
CPU time 22.52 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:14:47 PM PDT 24
Peak memory 248904 kb
Host smart-028e3d94-7902-4388-a484-8a423166ae34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16160
69465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1616069465
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.181395064
Short name T77
Test name
Test status
Simulation time 45524134104 ps
CPU time 2912.76 seconds
Started Mar 28 01:14:27 PM PDT 24
Finished Mar 28 02:03:00 PM PDT 24
Peak memory 289852 kb
Host smart-7c3072b6-5222-4bd0-9bc2-18ff54eee1d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181395064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.181395064
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2675357056
Short name T52
Test name
Test status
Simulation time 71624011765 ps
CPU time 3609.3 seconds
Started Mar 28 01:14:29 PM PDT 24
Finished Mar 28 02:14:39 PM PDT 24
Peak memory 305708 kb
Host smart-c47db567-4557-4b5a-8819-e7fe4756c253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675357056 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2675357056
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2270405732
Short name T121
Test name
Test status
Simulation time 43743469254 ps
CPU time 2371.29 seconds
Started Mar 28 01:14:36 PM PDT 24
Finished Mar 28 01:54:09 PM PDT 24
Peak memory 281772 kb
Host smart-9b6ac9f4-60ac-4af3-a466-4f4fc45909a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270405732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2270405732
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3589399937
Short name T246
Test name
Test status
Simulation time 22792641052 ps
CPU time 217.49 seconds
Started Mar 28 01:14:30 PM PDT 24
Finished Mar 28 01:18:08 PM PDT 24
Peak memory 256464 kb
Host smart-956960aa-58a6-453d-b366-21024310c5ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35893
99937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3589399937
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2999315365
Short name T441
Test name
Test status
Simulation time 871448029 ps
CPU time 66.82 seconds
Started Mar 28 01:14:29 PM PDT 24
Finished Mar 28 01:15:36 PM PDT 24
Peak memory 255936 kb
Host smart-2172fa5a-da08-4701-91f5-51512852fd94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29993
15365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2999315365
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1178779688
Short name T554
Test name
Test status
Simulation time 21961863146 ps
CPU time 639.42 seconds
Started Mar 28 01:14:26 PM PDT 24
Finished Mar 28 01:25:05 PM PDT 24
Peak memory 265360 kb
Host smart-5d7209ce-7586-412e-af3a-acd2ac393a03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178779688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1178779688
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1149013478
Short name T322
Test name
Test status
Simulation time 14928239371 ps
CPU time 130.83 seconds
Started Mar 28 01:14:24 PM PDT 24
Finished Mar 28 01:16:35 PM PDT 24
Peak memory 248384 kb
Host smart-7212c15a-2469-4493-bb9b-b52d189edc0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149013478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1149013478
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.661203089
Short name T42
Test name
Test status
Simulation time 220767377 ps
CPU time 14.99 seconds
Started Mar 28 01:14:32 PM PDT 24
Finished Mar 28 01:14:47 PM PDT 24
Peak memory 252912 kb
Host smart-04042ab8-b009-4f80-b1be-b0916d6b0cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66120
3089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.661203089
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1843400452
Short name T455
Test name
Test status
Simulation time 1103708047 ps
CPU time 24.68 seconds
Started Mar 28 01:14:28 PM PDT 24
Finished Mar 28 01:14:53 PM PDT 24
Peak memory 248876 kb
Host smart-75f92d4b-6c45-4d40-a17e-c97c73dad227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18434
00452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1843400452
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3071581977
Short name T667
Test name
Test status
Simulation time 285855733 ps
CPU time 21.25 seconds
Started Mar 28 01:14:28 PM PDT 24
Finished Mar 28 01:14:50 PM PDT 24
Peak memory 247408 kb
Host smart-4b0eb13f-683c-46f6-8476-fa8173f534bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30715
81977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3071581977
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3360732366
Short name T401
Test name
Test status
Simulation time 2794057628 ps
CPU time 49.5 seconds
Started Mar 28 01:14:36 PM PDT 24
Finished Mar 28 01:15:27 PM PDT 24
Peak memory 248764 kb
Host smart-606e88a9-d926-463e-b029-2aa15bd96f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33607
32366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3360732366
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1707559020
Short name T535
Test name
Test status
Simulation time 220349388560 ps
CPU time 3654.82 seconds
Started Mar 28 01:14:23 PM PDT 24
Finished Mar 28 02:15:19 PM PDT 24
Peak memory 289780 kb
Host smart-d66e71e7-e786-4fec-8a11-52d31dc928c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707559020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1707559020
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.73921489
Short name T420
Test name
Test status
Simulation time 61459403036 ps
CPU time 1464.21 seconds
Started Mar 28 01:14:45 PM PDT 24
Finished Mar 28 01:39:10 PM PDT 24
Peak memory 289348 kb
Host smart-e7bcb748-ead4-437e-a883-e1d1b891cfd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73921489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.73921489
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3231356083
Short name T403
Test name
Test status
Simulation time 366373902 ps
CPU time 32.55 seconds
Started Mar 28 01:14:47 PM PDT 24
Finished Mar 28 01:15:20 PM PDT 24
Peak memory 256776 kb
Host smart-d4964ab3-c994-45e1-b7ce-15ef62391fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32313
56083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3231356083
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2710644745
Short name T75
Test name
Test status
Simulation time 1886157387 ps
CPU time 63.43 seconds
Started Mar 28 01:14:51 PM PDT 24
Finished Mar 28 01:15:54 PM PDT 24
Peak memory 248604 kb
Host smart-ee70e8ca-2c3b-4cac-bea8-c3a1558903ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27106
44745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2710644745
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3896655183
Short name T697
Test name
Test status
Simulation time 40510349726 ps
CPU time 2144.93 seconds
Started Mar 28 01:14:43 PM PDT 24
Finished Mar 28 01:50:28 PM PDT 24
Peak memory 283324 kb
Host smart-225279fb-2318-4b24-b4da-9ae81235c145
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896655183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3896655183
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2870539833
Short name T66
Test name
Test status
Simulation time 17665572803 ps
CPU time 1019.45 seconds
Started Mar 28 01:14:44 PM PDT 24
Finished Mar 28 01:31:44 PM PDT 24
Peak memory 267532 kb
Host smart-ad71c684-6b53-4162-b062-9bc950cd4b62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870539833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2870539833
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1464163416
Short name T317
Test name
Test status
Simulation time 28113152105 ps
CPU time 123.09 seconds
Started Mar 28 01:14:44 PM PDT 24
Finished Mar 28 01:16:47 PM PDT 24
Peak memory 247912 kb
Host smart-861ba0b5-228f-444f-adad-4ad76a6e9f1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464163416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1464163416
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3559458028
Short name T36
Test name
Test status
Simulation time 927187038 ps
CPU time 20.37 seconds
Started Mar 28 01:14:44 PM PDT 24
Finished Mar 28 01:15:04 PM PDT 24
Peak memory 257068 kb
Host smart-1e62c3e9-d7a3-496b-b11e-e731a90b7afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35594
58028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3559458028
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2427894022
Short name T405
Test name
Test status
Simulation time 472447070 ps
CPU time 14.29 seconds
Started Mar 28 01:14:45 PM PDT 24
Finished Mar 28 01:14:59 PM PDT 24
Peak memory 249272 kb
Host smart-afcc74f2-8399-488b-9ce0-e6e49eac559a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24278
94022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2427894022
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3633796839
Short name T676
Test name
Test status
Simulation time 170217456 ps
CPU time 9.5 seconds
Started Mar 28 01:14:45 PM PDT 24
Finished Mar 28 01:14:55 PM PDT 24
Peak memory 248820 kb
Host smart-8e27177f-9014-4953-864e-f1cbd6f43a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36337
96839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3633796839
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2757605606
Short name T390
Test name
Test status
Simulation time 1065211771 ps
CPU time 59.62 seconds
Started Mar 28 01:14:22 PM PDT 24
Finished Mar 28 01:15:22 PM PDT 24
Peak memory 256496 kb
Host smart-8ae58b35-aa87-4111-9432-81c5d90fed97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27576
05606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2757605606
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.396760662
Short name T488
Test name
Test status
Simulation time 29364204158 ps
CPU time 1719.3 seconds
Started Mar 28 01:14:44 PM PDT 24
Finished Mar 28 01:43:24 PM PDT 24
Peak memory 273584 kb
Host smart-638b3ffe-d51c-4ddb-ad40-3a0f306da6d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396760662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.396760662
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1015065504
Short name T62
Test name
Test status
Simulation time 26918694505 ps
CPU time 646.4 seconds
Started Mar 28 01:14:45 PM PDT 24
Finished Mar 28 01:25:32 PM PDT 24
Peak memory 273576 kb
Host smart-81e1ce86-554a-46c3-8706-0ff0c765a299
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015065504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1015065504
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1824921715
Short name T241
Test name
Test status
Simulation time 1842333433 ps
CPU time 148.44 seconds
Started Mar 28 01:14:45 PM PDT 24
Finished Mar 28 01:17:13 PM PDT 24
Peak memory 256896 kb
Host smart-0450d96a-117a-436a-a56a-305b7627903f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18249
21715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1824921715
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.799796765
Short name T400
Test name
Test status
Simulation time 218980024 ps
CPU time 19.99 seconds
Started Mar 28 01:14:45 PM PDT 24
Finished Mar 28 01:15:05 PM PDT 24
Peak memory 247948 kb
Host smart-2320b1a3-803c-41cd-9385-a95f5c5a5391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79979
6765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.799796765
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1739429343
Short name T332
Test name
Test status
Simulation time 23720966725 ps
CPU time 1339.51 seconds
Started Mar 28 01:14:44 PM PDT 24
Finished Mar 28 01:37:04 PM PDT 24
Peak memory 265372 kb
Host smart-92421348-d372-47f2-9801-c212646d4b0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739429343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1739429343
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.900503306
Short name T225
Test name
Test status
Simulation time 37647495054 ps
CPU time 2563.11 seconds
Started Mar 28 01:14:45 PM PDT 24
Finished Mar 28 01:57:28 PM PDT 24
Peak memory 289200 kb
Host smart-5944c56f-dcef-47e0-8cb7-41533060ac45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900503306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.900503306
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.544681709
Short name T231
Test name
Test status
Simulation time 6431013109 ps
CPU time 266.93 seconds
Started Mar 28 01:14:44 PM PDT 24
Finished Mar 28 01:19:12 PM PDT 24
Peak memory 247884 kb
Host smart-b388536e-f244-485f-b6f9-fe2388656857
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544681709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.544681709
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.778216190
Short name T40
Test name
Test status
Simulation time 823753176 ps
CPU time 55.38 seconds
Started Mar 28 01:14:44 PM PDT 24
Finished Mar 28 01:15:39 PM PDT 24
Peak memory 256104 kb
Host smart-a15b7813-1cdb-4f27-8b41-1c567e5615c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77821
6190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.778216190
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.542448823
Short name T520
Test name
Test status
Simulation time 71076805 ps
CPU time 7.38 seconds
Started Mar 28 01:14:44 PM PDT 24
Finished Mar 28 01:14:52 PM PDT 24
Peak memory 254204 kb
Host smart-5a953b99-ef64-42d8-87d0-745c4563ae7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54244
8823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.542448823
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.875049789
Short name T638
Test name
Test status
Simulation time 245590398 ps
CPU time 25.12 seconds
Started Mar 28 01:14:48 PM PDT 24
Finished Mar 28 01:15:13 PM PDT 24
Peak memory 255984 kb
Host smart-0a3affb0-153d-4a35-87c7-13a4ab41552e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87504
9789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.875049789
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.647082165
Short name T373
Test name
Test status
Simulation time 1011209786 ps
CPU time 8.73 seconds
Started Mar 28 01:14:45 PM PDT 24
Finished Mar 28 01:14:53 PM PDT 24
Peak memory 248896 kb
Host smart-1dccdd70-2917-488d-a55a-02050f21480b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64708
2165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.647082165
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2451670285
Short name T113
Test name
Test status
Simulation time 23947819836 ps
CPU time 347.03 seconds
Started Mar 28 01:14:45 PM PDT 24
Finished Mar 28 01:20:33 PM PDT 24
Peak memory 257128 kb
Host smart-4b109dff-ac9b-4253-9a5b-8016cee38f22
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451670285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2451670285
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3907882974
Short name T551
Test name
Test status
Simulation time 144911670250 ps
CPU time 2559.84 seconds
Started Mar 28 01:14:50 PM PDT 24
Finished Mar 28 01:57:30 PM PDT 24
Peak memory 289224 kb
Host smart-8d71f406-a88e-4053-b78f-25cee6bc1675
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907882974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3907882974
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1555037920
Short name T704
Test name
Test status
Simulation time 3542069719 ps
CPU time 174.45 seconds
Started Mar 28 01:14:46 PM PDT 24
Finished Mar 28 01:17:40 PM PDT 24
Peak memory 249900 kb
Host smart-b69f51ec-0c3b-4dac-844f-1e75d52c320e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15550
37920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1555037920
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1824028630
Short name T672
Test name
Test status
Simulation time 1289299629 ps
CPU time 31.05 seconds
Started Mar 28 01:14:47 PM PDT 24
Finished Mar 28 01:15:18 PM PDT 24
Peak memory 255448 kb
Host smart-d65b5774-bef8-4618-8add-7bcdd8a5f33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18240
28630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1824028630
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.915039465
Short name T539
Test name
Test status
Simulation time 20043430118 ps
CPU time 1793.96 seconds
Started Mar 28 01:14:48 PM PDT 24
Finished Mar 28 01:44:42 PM PDT 24
Peak memory 289304 kb
Host smart-5b47387e-76db-4fc7-bc96-0c9bb45a9128
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915039465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.915039465
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.828983605
Short name T649
Test name
Test status
Simulation time 158106321994 ps
CPU time 1633.52 seconds
Started Mar 28 01:14:58 PM PDT 24
Finished Mar 28 01:42:12 PM PDT 24
Peak memory 273388 kb
Host smart-ba7f54e0-1ca1-4f13-a591-4c3b8363dec4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828983605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.828983605
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3301019173
Short name T272
Test name
Test status
Simulation time 1726666357 ps
CPU time 48.64 seconds
Started Mar 28 01:14:45 PM PDT 24
Finished Mar 28 01:15:34 PM PDT 24
Peak memory 248836 kb
Host smart-cd34f242-e6b1-4b76-9fe2-6fb954239a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33010
19173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3301019173
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.476622986
Short name T258
Test name
Test status
Simulation time 1943442406 ps
CPU time 29.15 seconds
Started Mar 28 01:14:45 PM PDT 24
Finished Mar 28 01:15:15 PM PDT 24
Peak memory 253728 kb
Host smart-f4e8185a-133b-4be2-b118-4d7273ac9dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47662
2986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.476622986
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.754488378
Short name T660
Test name
Test status
Simulation time 995288300 ps
CPU time 54.66 seconds
Started Mar 28 01:14:46 PM PDT 24
Finished Mar 28 01:15:41 PM PDT 24
Peak memory 255736 kb
Host smart-d92a586b-a26d-4dbd-a15d-146910094f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75448
8378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.754488378
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1676660978
Short name T438
Test name
Test status
Simulation time 123948182 ps
CPU time 3.48 seconds
Started Mar 28 01:14:46 PM PDT 24
Finished Mar 28 01:14:50 PM PDT 24
Peak memory 240688 kb
Host smart-763b4b92-0640-4b66-942e-82377b337fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16766
60978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1676660978
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.557540213
Short name T445
Test name
Test status
Simulation time 4123305567 ps
CPU time 221.28 seconds
Started Mar 28 01:14:59 PM PDT 24
Finished Mar 28 01:18:41 PM PDT 24
Peak memory 252052 kb
Host smart-99a20fa9-14c3-4728-9ecd-36fd0d85cdba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55754
0213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.557540213
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.505525749
Short name T76
Test name
Test status
Simulation time 2110573037 ps
CPU time 32.59 seconds
Started Mar 28 01:14:46 PM PDT 24
Finished Mar 28 01:15:19 PM PDT 24
Peak memory 248912 kb
Host smart-674791e4-1451-40f6-9945-c90eb866b65d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50552
5749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.505525749
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3903954689
Short name T344
Test name
Test status
Simulation time 152231940193 ps
CPU time 1973.55 seconds
Started Mar 28 01:14:56 PM PDT 24
Finished Mar 28 01:47:51 PM PDT 24
Peak memory 289040 kb
Host smart-dc4c2407-4120-42a2-a92a-a0bb113224f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903954689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3903954689
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2095631546
Short name T419
Test name
Test status
Simulation time 8459958785 ps
CPU time 812.72 seconds
Started Mar 28 01:15:05 PM PDT 24
Finished Mar 28 01:28:38 PM PDT 24
Peak memory 265440 kb
Host smart-1fb50306-4289-4bbc-b129-0b26d1144a52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095631546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2095631546
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2208435224
Short name T328
Test name
Test status
Simulation time 36766870342 ps
CPU time 410.8 seconds
Started Mar 28 01:15:04 PM PDT 24
Finished Mar 28 01:21:55 PM PDT 24
Peak memory 247808 kb
Host smart-3444313e-44cf-49a6-af6a-483c465f0c63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208435224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2208435224
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3895816032
Short name T655
Test name
Test status
Simulation time 99484490 ps
CPU time 8.3 seconds
Started Mar 28 01:14:47 PM PDT 24
Finished Mar 28 01:14:56 PM PDT 24
Peak memory 248912 kb
Host smart-12c8653b-935c-4aff-bc00-beb5cd2e322a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38958
16032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3895816032
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.91731432
Short name T561
Test name
Test status
Simulation time 1284683503 ps
CPU time 23.06 seconds
Started Mar 28 01:14:47 PM PDT 24
Finished Mar 28 01:15:11 PM PDT 24
Peak memory 253244 kb
Host smart-0c87ca0a-3776-4753-8157-2f594c82cce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91731
432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.91731432
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.4244761618
Short name T72
Test name
Test status
Simulation time 1308189771 ps
CPU time 24.58 seconds
Started Mar 28 01:14:47 PM PDT 24
Finished Mar 28 01:15:12 PM PDT 24
Peak memory 248864 kb
Host smart-b1d8b28a-cbcb-4473-b04d-83f539914411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42447
61618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.4244761618
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.443935777
Short name T542
Test name
Test status
Simulation time 521497480 ps
CPU time 26.17 seconds
Started Mar 28 01:14:47 PM PDT 24
Finished Mar 28 01:15:14 PM PDT 24
Peak memory 256112 kb
Host smart-d6a97e19-e8cf-4a45-8c70-9df82a357af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44393
5777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.443935777
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1795988039
Short name T645
Test name
Test status
Simulation time 46079330310 ps
CPU time 2884.52 seconds
Started Mar 28 01:15:05 PM PDT 24
Finished Mar 28 02:03:10 PM PDT 24
Peak memory 284932 kb
Host smart-7ca9036c-6cb4-4aeb-979d-e729b02775b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795988039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1795988039
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2280563564
Short name T512
Test name
Test status
Simulation time 5949725440 ps
CPU time 342.79 seconds
Started Mar 28 01:15:01 PM PDT 24
Finished Mar 28 01:20:44 PM PDT 24
Peak memory 256856 kb
Host smart-8f988d10-0a43-448c-ad5d-6708cf86dd1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22805
63564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2280563564
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1835262525
Short name T440
Test name
Test status
Simulation time 996999656 ps
CPU time 58.89 seconds
Started Mar 28 01:14:58 PM PDT 24
Finished Mar 28 01:15:57 PM PDT 24
Peak memory 248980 kb
Host smart-f222b274-ff3d-422e-a9da-05bb3fb5c148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18352
62525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1835262525
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2169964461
Short name T345
Test name
Test status
Simulation time 8023695072 ps
CPU time 753.73 seconds
Started Mar 28 01:14:57 PM PDT 24
Finished Mar 28 01:27:31 PM PDT 24
Peak memory 269512 kb
Host smart-3200f560-86d9-4847-82e8-c6d097852ad7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169964461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2169964461
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.777052946
Short name T630
Test name
Test status
Simulation time 122455933267 ps
CPU time 1833.36 seconds
Started Mar 28 01:14:57 PM PDT 24
Finished Mar 28 01:45:32 PM PDT 24
Peak memory 273572 kb
Host smart-7bf27355-baf8-41d6-879e-60755e8f2068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777052946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.777052946
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.377014942
Short name T228
Test name
Test status
Simulation time 4355486502 ps
CPU time 196.25 seconds
Started Mar 28 01:14:57 PM PDT 24
Finished Mar 28 01:18:14 PM PDT 24
Peak memory 248276 kb
Host smart-840cc962-b5f1-4238-83b2-a698a11c7103
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377014942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.377014942
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3334007349
Short name T570
Test name
Test status
Simulation time 623330218 ps
CPU time 35.83 seconds
Started Mar 28 01:14:59 PM PDT 24
Finished Mar 28 01:15:35 PM PDT 24
Peak memory 256128 kb
Host smart-d397c412-9186-4d7f-8c36-1e3b2bdfb7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33340
07349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3334007349
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2293923569
Short name T43
Test name
Test status
Simulation time 855508709 ps
CPU time 37.43 seconds
Started Mar 28 01:14:59 PM PDT 24
Finished Mar 28 01:15:37 PM PDT 24
Peak memory 255236 kb
Host smart-6baa9aeb-6c3f-4f76-bcff-508f36087ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22939
23569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2293923569
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.487422312
Short name T218
Test name
Test status
Simulation time 147197954 ps
CPU time 9.83 seconds
Started Mar 28 01:15:01 PM PDT 24
Finished Mar 28 01:15:11 PM PDT 24
Peak memory 247388 kb
Host smart-3f953f77-b701-4f28-b432-414b3709e4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48742
2312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.487422312
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1322195682
Short name T639
Test name
Test status
Simulation time 54793039 ps
CPU time 2.91 seconds
Started Mar 28 01:14:58 PM PDT 24
Finished Mar 28 01:15:01 PM PDT 24
Peak memory 240752 kb
Host smart-4e5f7bcf-a457-4398-bf3c-830d46177ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13221
95682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1322195682
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1428443166
Short name T629
Test name
Test status
Simulation time 14716380328 ps
CPU time 1285.68 seconds
Started Mar 28 01:14:58 PM PDT 24
Finished Mar 28 01:36:24 PM PDT 24
Peak memory 288964 kb
Host smart-e1e292f6-69e4-4de2-8f36-ce09873507fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428443166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1428443166
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.453683191
Short name T677
Test name
Test status
Simulation time 27698793459 ps
CPU time 1827.36 seconds
Started Mar 28 01:14:57 PM PDT 24
Finished Mar 28 01:45:25 PM PDT 24
Peak memory 283896 kb
Host smart-65818ba4-2f71-4556-86c2-fff9220e8390
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453683191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.453683191
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3769377209
Short name T468
Test name
Test status
Simulation time 2652349662 ps
CPU time 132.48 seconds
Started Mar 28 01:14:58 PM PDT 24
Finished Mar 28 01:17:11 PM PDT 24
Peak memory 256652 kb
Host smart-79038a66-156a-4ba6-bd07-9ad7da7e75fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37693
77209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3769377209
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.479037489
Short name T617
Test name
Test status
Simulation time 1116212415 ps
CPU time 34.58 seconds
Started Mar 28 01:15:07 PM PDT 24
Finished Mar 28 01:15:42 PM PDT 24
Peak memory 248800 kb
Host smart-311e2874-8744-4460-92d7-694fc2796808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47903
7489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.479037489
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.913098836
Short name T586
Test name
Test status
Simulation time 34708015771 ps
CPU time 1607.91 seconds
Started Mar 28 01:14:59 PM PDT 24
Finished Mar 28 01:41:47 PM PDT 24
Peak memory 289928 kb
Host smart-c01e2944-e8ce-4d77-876c-23861058bd71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913098836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.913098836
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1525237591
Short name T614
Test name
Test status
Simulation time 92662998919 ps
CPU time 926.83 seconds
Started Mar 28 01:15:00 PM PDT 24
Finished Mar 28 01:30:27 PM PDT 24
Peak memory 272760 kb
Host smart-b137a8a1-1e00-4df1-9f16-0492fbb16166
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525237591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1525237591
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.676113016
Short name T316
Test name
Test status
Simulation time 76637401664 ps
CPU time 750.64 seconds
Started Mar 28 01:14:59 PM PDT 24
Finished Mar 28 01:27:30 PM PDT 24
Peak memory 248192 kb
Host smart-5f6565be-464b-4a50-a88a-7cb34256bfdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676113016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.676113016
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2041171509
Short name T412
Test name
Test status
Simulation time 16732910670 ps
CPU time 52.12 seconds
Started Mar 28 01:15:04 PM PDT 24
Finished Mar 28 01:15:57 PM PDT 24
Peak memory 257224 kb
Host smart-20bc7248-dad1-4953-92cc-82e5c5afcb03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20411
71509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2041171509
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.4137220644
Short name T100
Test name
Test status
Simulation time 1033904906 ps
CPU time 58.19 seconds
Started Mar 28 01:15:03 PM PDT 24
Finished Mar 28 01:16:02 PM PDT 24
Peak memory 248760 kb
Host smart-beb8b73d-b2b8-4f94-ba23-09cf89d54710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41372
20644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.4137220644
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2575902174
Short name T298
Test name
Test status
Simulation time 549563801 ps
CPU time 32.27 seconds
Started Mar 28 01:14:59 PM PDT 24
Finished Mar 28 01:15:32 PM PDT 24
Peak memory 255196 kb
Host smart-f9239e2f-7797-479a-957e-57ca1676d63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25759
02174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2575902174
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2587177409
Short name T669
Test name
Test status
Simulation time 1185569651 ps
CPU time 32.79 seconds
Started Mar 28 01:15:07 PM PDT 24
Finished Mar 28 01:15:40 PM PDT 24
Peak memory 248884 kb
Host smart-877b669a-9b3d-4016-996f-051856be412d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25871
77409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2587177409
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2416980113
Short name T432
Test name
Test status
Simulation time 186481021527 ps
CPU time 1419.1 seconds
Started Mar 28 01:15:03 PM PDT 24
Finished Mar 28 01:38:43 PM PDT 24
Peak memory 287884 kb
Host smart-732fdb21-5d5c-4f7f-8a1b-316f207ad4c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416980113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2416980113
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3705310216
Short name T111
Test name
Test status
Simulation time 37316669627 ps
CPU time 4139.1 seconds
Started Mar 28 01:14:57 PM PDT 24
Finished Mar 28 02:23:57 PM PDT 24
Peak memory 322044 kb
Host smart-b3f6f56c-c635-400b-97eb-97ee358a70c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705310216 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3705310216
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2954758326
Short name T457
Test name
Test status
Simulation time 204946939930 ps
CPU time 2723.15 seconds
Started Mar 28 01:15:00 PM PDT 24
Finished Mar 28 02:00:23 PM PDT 24
Peak memory 281568 kb
Host smart-b4ef2030-b948-46de-925e-4d76892fcdc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954758326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2954758326
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2023027329
Short name T364
Test name
Test status
Simulation time 10903587163 ps
CPU time 301.95 seconds
Started Mar 28 01:15:07 PM PDT 24
Finished Mar 28 01:20:09 PM PDT 24
Peak memory 251052 kb
Host smart-c64767e0-53fc-474c-87a3-bbb266e88770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20230
27329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2023027329
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3954029908
Short name T501
Test name
Test status
Simulation time 302058704 ps
CPU time 14.46 seconds
Started Mar 28 01:15:00 PM PDT 24
Finished Mar 28 01:15:14 PM PDT 24
Peak memory 248716 kb
Host smart-48ccf6fc-b0ad-45ed-a61c-053fc2a5285b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39540
29908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3954029908
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2602878686
Short name T327
Test name
Test status
Simulation time 208450643458 ps
CPU time 2108.03 seconds
Started Mar 28 01:15:07 PM PDT 24
Finished Mar 28 01:50:16 PM PDT 24
Peak memory 289116 kb
Host smart-fa9660cd-1e37-4f95-a19f-1dfc9de1aa48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602878686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2602878686
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1882221927
Short name T544
Test name
Test status
Simulation time 34132060071 ps
CPU time 734.22 seconds
Started Mar 28 01:15:00 PM PDT 24
Finished Mar 28 01:27:14 PM PDT 24
Peak memory 265268 kb
Host smart-5f05732e-70c3-41b8-92bd-8c8975ea3c24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882221927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1882221927
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2770062571
Short name T691
Test name
Test status
Simulation time 3678244189 ps
CPU time 158.73 seconds
Started Mar 28 01:14:57 PM PDT 24
Finished Mar 28 01:17:37 PM PDT 24
Peak memory 248012 kb
Host smart-f0d8efe5-27fb-4c84-b2a3-3f881947ddad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770062571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2770062571
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2941485315
Short name T24
Test name
Test status
Simulation time 148287753 ps
CPU time 7.42 seconds
Started Mar 28 01:15:07 PM PDT 24
Finished Mar 28 01:15:15 PM PDT 24
Peak memory 252512 kb
Host smart-68110899-49cf-48f1-97ee-a8bd0a59f3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29414
85315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2941485315
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.4020334748
Short name T98
Test name
Test status
Simulation time 1841326010 ps
CPU time 43.25 seconds
Started Mar 28 01:14:59 PM PDT 24
Finished Mar 28 01:15:42 PM PDT 24
Peak memory 256048 kb
Host smart-c8cca1af-8a6f-40ae-bdd8-bf0c3c8cd0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40203
34748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.4020334748
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.583373916
Short name T519
Test name
Test status
Simulation time 200353540 ps
CPU time 16.29 seconds
Started Mar 28 01:14:58 PM PDT 24
Finished Mar 28 01:15:14 PM PDT 24
Peak memory 254332 kb
Host smart-e27c2e61-55ce-4403-8289-966663dc15e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58337
3916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.583373916
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1397146043
Short name T380
Test name
Test status
Simulation time 116471529 ps
CPU time 5.26 seconds
Started Mar 28 01:15:00 PM PDT 24
Finished Mar 28 01:15:05 PM PDT 24
Peak memory 240704 kb
Host smart-b3d5c4fe-de0f-4305-b47b-a5bd1ab86f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13971
46043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1397146043
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3034064942
Short name T251
Test name
Test status
Simulation time 149391289494 ps
CPU time 2278.7 seconds
Started Mar 28 01:14:58 PM PDT 24
Finished Mar 28 01:52:57 PM PDT 24
Peak memory 289648 kb
Host smart-16b5cc11-ed18-4ef4-86dd-eb4b5b7289b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034064942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3034064942
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1567953078
Short name T41
Test name
Test status
Simulation time 22244145 ps
CPU time 2.25 seconds
Started Mar 28 01:12:12 PM PDT 24
Finished Mar 28 01:12:14 PM PDT 24
Peak memory 249020 kb
Host smart-6119d384-ca5e-443a-8720-3a6a656f32cf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1567953078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1567953078
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.4221682432
Short name T56
Test name
Test status
Simulation time 32806495956 ps
CPU time 2149.89 seconds
Started Mar 28 01:12:09 PM PDT 24
Finished Mar 28 01:47:59 PM PDT 24
Peak memory 281744 kb
Host smart-b22979df-e70e-4b56-9441-86088a94bed4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221682432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.4221682432
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1432097988
Short name T460
Test name
Test status
Simulation time 2126216083 ps
CPU time 90.45 seconds
Started Mar 28 01:12:15 PM PDT 24
Finished Mar 28 01:13:45 PM PDT 24
Peak memory 248900 kb
Host smart-7970e08b-98cd-4609-8d77-5d520c66faa8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1432097988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1432097988
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.4138350717
Short name T422
Test name
Test status
Simulation time 47586634157 ps
CPU time 160.55 seconds
Started Mar 28 01:12:09 PM PDT 24
Finished Mar 28 01:14:49 PM PDT 24
Peak memory 256548 kb
Host smart-70acaed7-5352-4cf4-a924-7b9c315979bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41383
50717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.4138350717
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3457071257
Short name T18
Test name
Test status
Simulation time 1689615540 ps
CPU time 48.73 seconds
Started Mar 28 01:12:10 PM PDT 24
Finished Mar 28 01:12:59 PM PDT 24
Peak memory 248900 kb
Host smart-6999c51a-8e38-485d-8634-45c3a9444fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34570
71257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3457071257
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1622440958
Short name T610
Test name
Test status
Simulation time 26489636482 ps
CPU time 1472.54 seconds
Started Mar 28 01:12:12 PM PDT 24
Finished Mar 28 01:36:45 PM PDT 24
Peak memory 288948 kb
Host smart-7e63aedf-264d-49f4-9d68-ffc86f034746
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622440958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1622440958
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.333747926
Short name T687
Test name
Test status
Simulation time 25375975556 ps
CPU time 1029.21 seconds
Started Mar 28 01:12:07 PM PDT 24
Finished Mar 28 01:29:17 PM PDT 24
Peak memory 284512 kb
Host smart-f4d73958-764a-4674-a9c9-9f064123324e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333747926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.333747926
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3144584989
Short name T538
Test name
Test status
Simulation time 14548355091 ps
CPU time 578.58 seconds
Started Mar 28 01:12:12 PM PDT 24
Finished Mar 28 01:21:51 PM PDT 24
Peak memory 248072 kb
Host smart-eb8d014f-febd-4e46-aced-455eb4474d84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144584989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3144584989
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3667191268
Short name T55
Test name
Test status
Simulation time 495615532 ps
CPU time 39.43 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:12:48 PM PDT 24
Peak memory 256308 kb
Host smart-199eac8f-22e2-44ad-93c9-13807d2d0dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36671
91268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3667191268
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1720653544
Short name T577
Test name
Test status
Simulation time 69539540 ps
CPU time 7.22 seconds
Started Mar 28 01:12:10 PM PDT 24
Finished Mar 28 01:12:17 PM PDT 24
Peak memory 254140 kb
Host smart-e8c5fb77-04f5-4da0-b66b-475777c9f879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17206
53544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1720653544
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3876065595
Short name T549
Test name
Test status
Simulation time 8834587937 ps
CPU time 25.34 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:12:33 PM PDT 24
Peak memory 256284 kb
Host smart-fe45c1e6-1ef2-464e-aeae-84c3f112f96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38760
65595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3876065595
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.4018126520
Short name T546
Test name
Test status
Simulation time 303719157902 ps
CPU time 7085.7 seconds
Started Mar 28 01:12:07 PM PDT 24
Finished Mar 28 03:10:14 PM PDT 24
Peak memory 305972 kb
Host smart-93b2aa3e-4839-43b7-9482-5317089f31ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018126520 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.4018126520
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.924269390
Short name T210
Test name
Test status
Simulation time 15329158 ps
CPU time 2.55 seconds
Started Mar 28 01:12:10 PM PDT 24
Finished Mar 28 01:12:13 PM PDT 24
Peak memory 249128 kb
Host smart-a9e3cb69-2709-4737-a157-9aa08e25c808
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=924269390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.924269390
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.452051776
Short name T648
Test name
Test status
Simulation time 100439885727 ps
CPU time 1789.76 seconds
Started Mar 28 01:12:11 PM PDT 24
Finished Mar 28 01:42:01 PM PDT 24
Peak memory 273584 kb
Host smart-ac5d999f-fb41-4dc1-9a6a-438fb5e7a11e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452051776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.452051776
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2980901795
Short name T381
Test name
Test status
Simulation time 756449198 ps
CPU time 16.64 seconds
Started Mar 28 01:12:09 PM PDT 24
Finished Mar 28 01:12:26 PM PDT 24
Peak memory 240648 kb
Host smart-39ea5df4-8bd3-4afe-b59d-1f7c8069f672
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2980901795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2980901795
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4092574612
Short name T375
Test name
Test status
Simulation time 427597779 ps
CPU time 22.41 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:12:30 PM PDT 24
Peak memory 248436 kb
Host smart-cd1f370a-0982-4445-bdc3-54d143ef6e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40925
74612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4092574612
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.544147419
Short name T650
Test name
Test status
Simulation time 283178310 ps
CPU time 16.71 seconds
Started Mar 28 01:12:09 PM PDT 24
Finished Mar 28 01:12:25 PM PDT 24
Peak memory 253524 kb
Host smart-26c69c0c-cd7e-4be4-baa3-0a3470deff3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54414
7419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.544147419
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2426908992
Short name T383
Test name
Test status
Simulation time 88173761856 ps
CPU time 1390.62 seconds
Started Mar 28 01:12:11 PM PDT 24
Finished Mar 28 01:35:22 PM PDT 24
Peak memory 273512 kb
Host smart-ae40f422-98ef-4a14-aa62-8d3ef6a47c64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426908992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2426908992
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3299769964
Short name T7
Test name
Test status
Simulation time 8414419941 ps
CPU time 175.17 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:15:03 PM PDT 24
Peak memory 247060 kb
Host smart-07d8230b-bf7d-4d3f-aa62-cb35948be3da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299769964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3299769964
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2453292892
Short name T222
Test name
Test status
Simulation time 145972848 ps
CPU time 5.33 seconds
Started Mar 28 01:12:09 PM PDT 24
Finished Mar 28 01:12:14 PM PDT 24
Peak memory 248928 kb
Host smart-00000ff2-8d17-4e45-ab13-7ade8d735c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24532
92892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2453292892
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1866269883
Short name T230
Test name
Test status
Simulation time 699668053 ps
CPU time 20.38 seconds
Started Mar 28 01:12:09 PM PDT 24
Finished Mar 28 01:12:29 PM PDT 24
Peak memory 255924 kb
Host smart-ff930fc1-c2f9-4001-a406-dd08845be395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18662
69883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1866269883
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.847506607
Short name T82
Test name
Test status
Simulation time 5497251195 ps
CPU time 32.34 seconds
Started Mar 28 01:12:10 PM PDT 24
Finished Mar 28 01:12:42 PM PDT 24
Peak memory 256192 kb
Host smart-be151948-a76c-4a39-ae74-1e5f3e23ae4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84750
6607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.847506607
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1140624676
Short name T452
Test name
Test status
Simulation time 269273097 ps
CPU time 21.74 seconds
Started Mar 28 01:12:08 PM PDT 24
Finished Mar 28 01:12:30 PM PDT 24
Peak memory 248712 kb
Host smart-f25b6e28-7a22-46df-be90-f2e2913bba29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11406
24676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1140624676
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.85834780
Short name T265
Test name
Test status
Simulation time 59166632621 ps
CPU time 2208.7 seconds
Started Mar 28 01:12:07 PM PDT 24
Finished Mar 28 01:48:56 PM PDT 24
Peak memory 281752 kb
Host smart-469c4a88-205a-43b9-b1d6-f87436ad165e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85834780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handl
er_stress_all.85834780
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3606392391
Short name T58
Test name
Test status
Simulation time 385588999642 ps
CPU time 5534.24 seconds
Started Mar 28 01:12:10 PM PDT 24
Finished Mar 28 02:44:25 PM PDT 24
Peak memory 338360 kb
Host smart-e2c4ca3e-1aa9-4817-8a5c-a88546ca0c8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606392391 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3606392391
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1124793015
Short name T211
Test name
Test status
Simulation time 38702630 ps
CPU time 2.39 seconds
Started Mar 28 01:12:32 PM PDT 24
Finished Mar 28 01:12:35 PM PDT 24
Peak memory 249088 kb
Host smart-0ed5ba2c-de1f-47ec-8c19-551670a5b4c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1124793015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1124793015
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.248580117
Short name T481
Test name
Test status
Simulation time 10475830026 ps
CPU time 939.86 seconds
Started Mar 28 01:12:35 PM PDT 24
Finished Mar 28 01:28:16 PM PDT 24
Peak memory 269564 kb
Host smart-ea8af32f-c103-41b2-bd1a-bf759db97511
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248580117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.248580117
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.4256519261
Short name T608
Test name
Test status
Simulation time 1213285854 ps
CPU time 48.78 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:13:29 PM PDT 24
Peak memory 248864 kb
Host smart-63e5edcf-80e4-4e80-8e8e-c3b5f7fb070a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4256519261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.4256519261
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.391944445
Short name T256
Test name
Test status
Simulation time 1868427941 ps
CPU time 82.01 seconds
Started Mar 28 01:12:38 PM PDT 24
Finished Mar 28 01:14:00 PM PDT 24
Peak memory 256768 kb
Host smart-d0e67978-0dcc-4781-b6ad-259b868d620f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39194
4445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.391944445
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.646102950
Short name T686
Test name
Test status
Simulation time 1052401657 ps
CPU time 54.1 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:13:37 PM PDT 24
Peak memory 256048 kb
Host smart-c0004f44-aff7-498a-989a-2dfce1f96ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64610
2950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.646102950
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3641999302
Short name T323
Test name
Test status
Simulation time 12691522405 ps
CPU time 672.22 seconds
Started Mar 28 01:12:34 PM PDT 24
Finished Mar 28 01:23:48 PM PDT 24
Peak memory 265296 kb
Host smart-b270d010-1897-4076-a4e2-6d675fa9f84f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641999302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3641999302
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2417437633
Short name T585
Test name
Test status
Simulation time 119488303451 ps
CPU time 1937.57 seconds
Started Mar 28 01:12:37 PM PDT 24
Finished Mar 28 01:44:55 PM PDT 24
Peak memory 281832 kb
Host smart-c66b1a78-18d4-4271-9dd9-e85ac9cfbda0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417437633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2417437633
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.950612530
Short name T569
Test name
Test status
Simulation time 371204020 ps
CPU time 24.62 seconds
Started Mar 28 01:12:09 PM PDT 24
Finished Mar 28 01:12:33 PM PDT 24
Peak memory 248868 kb
Host smart-4dd7707f-303f-4eaf-87d6-d31af7c767b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95061
2530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.950612530
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4152517820
Short name T426
Test name
Test status
Simulation time 80323817 ps
CPU time 6.8 seconds
Started Mar 28 01:12:35 PM PDT 24
Finished Mar 28 01:12:43 PM PDT 24
Peak memory 251432 kb
Host smart-3ebdfdc0-3635-4776-b2b8-db933c640524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41525
17820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4152517820
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3171405116
Short name T283
Test name
Test status
Simulation time 800643420 ps
CPU time 28.17 seconds
Started Mar 28 01:12:39 PM PDT 24
Finished Mar 28 01:13:08 PM PDT 24
Peak memory 247384 kb
Host smart-8c29c4d3-6437-4fcf-a6e8-cc3408e678d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31714
05116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3171405116
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1608446197
Short name T536
Test name
Test status
Simulation time 1054577744 ps
CPU time 27.41 seconds
Started Mar 28 01:12:10 PM PDT 24
Finished Mar 28 01:12:37 PM PDT 24
Peak memory 255672 kb
Host smart-06a26076-9438-44fa-b5d9-1a9666e39a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16084
46197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1608446197
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3510853956
Short name T207
Test name
Test status
Simulation time 44370505 ps
CPU time 2.54 seconds
Started Mar 28 01:12:38 PM PDT 24
Finished Mar 28 01:12:41 PM PDT 24
Peak memory 249096 kb
Host smart-829c78f7-4a89-43c2-a247-5ccfc7db682b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3510853956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3510853956
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1553745265
Short name T53
Test name
Test status
Simulation time 40732781917 ps
CPU time 2330.83 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:51:32 PM PDT 24
Peak memory 273192 kb
Host smart-6cde23dc-f682-4a4f-9a6b-6aa2d552feb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553745265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1553745265
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2146587206
Short name T399
Test name
Test status
Simulation time 856641496 ps
CPU time 12.05 seconds
Started Mar 28 01:12:36 PM PDT 24
Finished Mar 28 01:12:49 PM PDT 24
Peak memory 248856 kb
Host smart-b0e434e0-bc82-472c-a4d1-e85a3e2936f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2146587206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2146587206
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2515213051
Short name T540
Test name
Test status
Simulation time 20942461537 ps
CPU time 292.95 seconds
Started Mar 28 01:12:33 PM PDT 24
Finished Mar 28 01:17:27 PM PDT 24
Peak memory 257040 kb
Host smart-264439b4-87a9-4eae-9d15-831812c1a016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25152
13051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2515213051
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.870508855
Short name T683
Test name
Test status
Simulation time 706765793 ps
CPU time 43.23 seconds
Started Mar 28 01:12:34 PM PDT 24
Finished Mar 28 01:13:19 PM PDT 24
Peak memory 248792 kb
Host smart-5577ee39-9cc4-4b02-917c-a74b3db7f9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87050
8855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.870508855
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2815805967
Short name T269
Test name
Test status
Simulation time 15596704523 ps
CPU time 1330.75 seconds
Started Mar 28 01:12:34 PM PDT 24
Finished Mar 28 01:34:46 PM PDT 24
Peak memory 281712 kb
Host smart-29cf695f-8126-46da-b3ad-ad1f451bce6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815805967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2815805967
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1692824340
Short name T124
Test name
Test status
Simulation time 25467244407 ps
CPU time 812.34 seconds
Started Mar 28 01:12:39 PM PDT 24
Finished Mar 28 01:26:12 PM PDT 24
Peak memory 272936 kb
Host smart-1a72940e-4ad0-40e3-a749-a676b339184c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692824340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1692824340
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.741214058
Short name T663
Test name
Test status
Simulation time 30580366114 ps
CPU time 523.65 seconds
Started Mar 28 01:12:32 PM PDT 24
Finished Mar 28 01:21:16 PM PDT 24
Peak memory 248160 kb
Host smart-db575f24-a76e-478a-9a9e-fd30056c7d17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741214058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.741214058
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3773771439
Short name T471
Test name
Test status
Simulation time 1566387029 ps
CPU time 26.01 seconds
Started Mar 28 01:12:39 PM PDT 24
Finished Mar 28 01:13:05 PM PDT 24
Peak memory 248824 kb
Host smart-f4106073-4b09-4a56-a0a5-90b4c77fc371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37737
71439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3773771439
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1093731712
Short name T480
Test name
Test status
Simulation time 1202537415 ps
CPU time 28.13 seconds
Started Mar 28 01:12:37 PM PDT 24
Finished Mar 28 01:13:06 PM PDT 24
Peak memory 248472 kb
Host smart-8af7a2b0-dcdb-4109-8232-9103c414c527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10937
31712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1093731712
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1869403466
Short name T284
Test name
Test status
Simulation time 262627623 ps
CPU time 29.66 seconds
Started Mar 28 01:12:37 PM PDT 24
Finished Mar 28 01:13:07 PM PDT 24
Peak memory 256676 kb
Host smart-f2411996-9502-4d79-a53f-0c2f8d2ec298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18694
03466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1869403466
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1904547910
Short name T106
Test name
Test status
Simulation time 239864473 ps
CPU time 15.99 seconds
Started Mar 28 01:12:35 PM PDT 24
Finished Mar 28 01:12:52 PM PDT 24
Peak memory 248904 kb
Host smart-b1001b91-b5bb-4f9c-864d-af6f0711bd83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19045
47910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1904547910
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.291038081
Short name T92
Test name
Test status
Simulation time 593996900371 ps
CPU time 1909.68 seconds
Started Mar 28 01:12:35 PM PDT 24
Finished Mar 28 01:44:26 PM PDT 24
Peak memory 290012 kb
Host smart-722db609-655b-45b2-9ba4-611b1d8c675a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291038081 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.291038081
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3406575168
Short name T200
Test name
Test status
Simulation time 46380371 ps
CPU time 3.75 seconds
Started Mar 28 01:12:36 PM PDT 24
Finished Mar 28 01:12:40 PM PDT 24
Peak memory 249068 kb
Host smart-0cded2f3-4c22-4266-bc4e-bcb3bbac7c76
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3406575168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3406575168
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2180098095
Short name T59
Test name
Test status
Simulation time 96901063529 ps
CPU time 2832.33 seconds
Started Mar 28 01:12:39 PM PDT 24
Finished Mar 28 01:59:52 PM PDT 24
Peak memory 289220 kb
Host smart-68abde86-b87c-43f2-8699-db508e5be594
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180098095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2180098095
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1361465382
Short name T497
Test name
Test status
Simulation time 5137585731 ps
CPU time 50.96 seconds
Started Mar 28 01:12:35 PM PDT 24
Finished Mar 28 01:13:27 PM PDT 24
Peak memory 249000 kb
Host smart-ffa0f186-0ecf-49a4-aa11-c58135400488
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1361465382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1361465382
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3649096184
Short name T393
Test name
Test status
Simulation time 14705259261 ps
CPU time 239.86 seconds
Started Mar 28 01:12:35 PM PDT 24
Finished Mar 28 01:16:36 PM PDT 24
Peak memory 251024 kb
Host smart-9a3b7398-8605-4b36-a9c2-89f2dac636b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36490
96184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3649096184
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.4043631309
Short name T388
Test name
Test status
Simulation time 2710886462 ps
CPU time 12.99 seconds
Started Mar 28 01:12:35 PM PDT 24
Finished Mar 28 01:12:49 PM PDT 24
Peak memory 251916 kb
Host smart-054af982-5245-4371-8f71-32409f2e819c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40436
31309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.4043631309
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3375388516
Short name T90
Test name
Test status
Simulation time 175674240905 ps
CPU time 1473.11 seconds
Started Mar 28 01:12:36 PM PDT 24
Finished Mar 28 01:37:10 PM PDT 24
Peak memory 289460 kb
Host smart-d7ffd37a-e319-4a7d-960a-e1512124f89e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375388516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3375388516
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1828389139
Short name T314
Test name
Test status
Simulation time 6763325933 ps
CPU time 245.01 seconds
Started Mar 28 01:12:41 PM PDT 24
Finished Mar 28 01:16:48 PM PDT 24
Peak memory 247124 kb
Host smart-cc2a1e16-5b63-4651-9669-64acee184db3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828389139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1828389139
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1625516838
Short name T597
Test name
Test status
Simulation time 3423732452 ps
CPU time 52.23 seconds
Started Mar 28 01:12:37 PM PDT 24
Finished Mar 28 01:13:30 PM PDT 24
Peak memory 248932 kb
Host smart-7c75a1e4-d476-489e-a7b2-f2e71e7af767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16255
16838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1625516838
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1540757385
Short name T547
Test name
Test status
Simulation time 5099427897 ps
CPU time 63.77 seconds
Started Mar 28 01:12:33 PM PDT 24
Finished Mar 28 01:13:37 PM PDT 24
Peak memory 256732 kb
Host smart-7d6b10cf-3f2b-4cb1-a688-6111c1827379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15407
57385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1540757385
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.457368267
Short name T463
Test name
Test status
Simulation time 2420743237 ps
CPU time 39.58 seconds
Started Mar 28 01:12:40 PM PDT 24
Finished Mar 28 01:13:20 PM PDT 24
Peak memory 256024 kb
Host smart-7e48a014-5a78-4234-9f9d-c15198b83ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45736
8267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.457368267
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.837026182
Short name T470
Test name
Test status
Simulation time 1605405882 ps
CPU time 28.66 seconds
Started Mar 28 01:12:36 PM PDT 24
Finished Mar 28 01:13:05 PM PDT 24
Peak memory 248852 kb
Host smart-22536a0f-6e4d-468c-9d03-77ee33d00a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83702
6182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.837026182
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3271040296
Short name T555
Test name
Test status
Simulation time 8581928922 ps
CPU time 940.66 seconds
Started Mar 28 01:12:36 PM PDT 24
Finished Mar 28 01:28:17 PM PDT 24
Peak memory 271540 kb
Host smart-b3828134-fe07-495b-a4d6-7f01fd7bdd97
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271040296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3271040296
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.916092343
Short name T237
Test name
Test status
Simulation time 18083407559 ps
CPU time 1169.17 seconds
Started Mar 28 01:12:36 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 272508 kb
Host smart-8f97f090-1da3-4bf3-b5ad-dff66a0ea8ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916092343 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.916092343
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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