Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	82077	1			T14	21		T5	5		T10	2073
class_i[0x1]	39329	1			T14	2079		T4	11		T6	7
class_i[0x2]	46799	1			T14	6		T4	5		T5	1
class_i[0x3]	75461	1			T14	44		T10	5		T12	2

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	61888	1			T14	687		T4	3		T5	1
alert[0x1]	61474	1			T14	12		T4	1		T5	5
alert[0x2]	59324	1			T14	26		T4	4		T10	505
alert[0x3]	60980	1			T14	1425		T4	8		T10	569

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

243366

1

T14

2150

T4

11

T5

4

esc_ping_fail

300

1

T4

5

T5

2

T6

9

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	61810	1			T14	687		T4	2		T10	488
esc_integrity_fail	alert[0x1]	61394	1			T14	12		T5	4		T10	516
esc_integrity_fail	alert[0x2]	59249	1			T14	26		T4	3		T10	505
esc_integrity_fail	alert[0x3]	60913	1			T14	1425		T4	6		T10	569
esc_ping_fail	alert[0x0]	78	1			T4	1		T5	1		T6	3
esc_ping_fail	alert[0x1]	80	1			T4	1		T5	1		T6	3
esc_ping_fail	alert[0x2]	75	1			T4	1		T6	2		T12	2
esc_ping_fail	alert[0x3]	67	1			T4	2		T6	1		T12	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	81990	1			T14	21		T5	4		T10	2073
esc_integrity_fail	class_i[0x1]	39252	1			T14	2079		T4	11		T11	109
esc_integrity_fail	class_i[0x2]	46733	1			T14	6		T12	3		T129	9
esc_integrity_fail	class_i[0x3]	75391	1			T14	44		T10	5		T12	1
esc_ping_fail	class_i[0x0]	87	1			T5	1		T6	1		T12	1
esc_ping_fail	class_i[0x1]	77	1			T6	7		T12	3		T129	4
esc_ping_fail	class_i[0x2]	66	1			T4	5		T5	1		T6	1
esc_ping_fail	class_i[0x3]	70	1			T12	1		T13	8		T292	3