Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	744510807	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	744510807	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	744510807	744359385	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	744510807	744359385	0	0
tb.dut.EdnKnownO_A	0	0	744510807	744359385	0	0
tb.dut.EscPKnownO_A	0	0	744510807	744359385	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	744510807	60	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	744510807	60	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	744510807	60	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	744510807	60	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	744510807	60	0	0
tb.dut.IrqAKnownO_A	0	0	744510807	744359385	0	0
tb.dut.IrqBKnownO_A	0	0	744510807	744359385	0	0
tb.dut.IrqCKnownO_A	0	0	744510807	744359385	0	0
tb.dut.IrqDKnownO_A	0	0	744510807	744359385	0	0
tb.dut.TlAReadyKnownO_A	0	0	744510807	744359385	0	0
tb.dut.TlDValidKnownO_A	0	0	744510807	744359385	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	766227355	2943497	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	766227355	6853	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	766227355	8164	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	766227355	6693	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	766227355	8730	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	766227355	6939	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	766227355	8251	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	766227355	8041	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	766227355	6753	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	766227355	7149	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	766227355	7093	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	766227355	6202	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	766227355	8699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	766227355	7313	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	766227355	6287	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	766227355	7769	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	766227355	8049	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	766227355	9759	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	766227355	6337	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	766227355	9182	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	766227355	7252	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	766227355	9214	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	766227355	6064	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	766227355	8090	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	766227355	6070	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	766227355	7290	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	766227355	6994	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	766227355	6809	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	766227355	8571	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	766227355	6736	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	766227355	6849	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	766227355	8275	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	766227355	6782	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	766227355	6216	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	766227355	6793	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	766227355	6307	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	766227355	7268	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	766227355	8325	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	766227355	6253	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	766227355	7215	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	766227355	7955	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	766227355	7455	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	766227355	6273	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	766227355	6624	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	766227355	6208	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	766227355	7106	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	766227355	6249	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	766227355	6657	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	766227355	7641	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	766227355	6718	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	766227355	7283	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	766227355	7528	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	766227355	5992	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	766227355	6147	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	766227355	5896	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	766227355	7106	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	766227355	6039	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	766227355	7541	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	766227355	6756	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	766227355	7359	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	766227355	6253	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	766227355	9599	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	766227355	7412	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	766227355	5891	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	766227355	7584	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	766227355	8256	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	766227355	8454	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	766227355	7167	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	766227355	7711	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	766227355	5988	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	766227355	11517	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	766227355	7814	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	766227355	7623	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	766227355	7895	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	766227355	6768	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	766227355	8625	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	766227355	6139	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	766227355	6128	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	766227355	6092	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	744510807	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	744510807	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	744510807	60	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	744510807	1711	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	744510807	279037	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	744510807	367527903	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	744510807	225	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	744510807	923	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	744510807	42	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	744510807	447	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	744396728	287359398	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	744510807	1004	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	744510807	987	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	744510807	963	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	744510807	945	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	744510807	498	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	744510807	65228	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	744510807	396	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	744510807	57	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	744510807	1105	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	744510807	925	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	744510807	744359385	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	744510807	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	744510807	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	744510807	60	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	744510807	3215	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	744510807	153229	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	744510807	426090811	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	744510807	143	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	744510807	499	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	744510807	15	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	744510807	208	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	744396728	335270656	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	744510807	574	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	744510807	571	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	744510807	567	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	744510807	558	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	744510807	700	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	744510807	93896	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	744510807	605	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	744510807	75	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	744510807	1041	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	744510807	861	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	744510807	744359385	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	744510807	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	744510807	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	744510807	60	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	744510807	4622	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	744510807	147927	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	744510807	429916074	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	744510807	200	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	744510807	455	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	744510807	20	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	744510807	192	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	744396728	360138639	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	744510807	538	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	744510807	532	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	744510807	527	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	744510807	519	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	744510807	691	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	744510807	85875	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	744510807	594	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	744510807	74	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	744510807	1071	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	744510807	891	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	744510807	744359385	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	744510807	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	744510807	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	744510807	60	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	744510807	4192	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	744510807	172371	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	744510807	461998600	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	744510807	199	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	744510807	459	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	744510807	22	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	744510807	186	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	744396728	390611465	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	744510807	531	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	744510807	517	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	744510807	512	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	744510807	504	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	744510807	782	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	744510807	83636	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	744510807	702	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	744510807	56	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	744510807	1049	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	744510807	869	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	744510807	744359385	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	766227355	129229652	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	766227355	765607131	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	766227355	765607131	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	766227355	194246085	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	766227355	765607131	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	766227355	765607131	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	831	831	0	0
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