Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
361632 |
1 |
|
|
T1 |
1259 |
|
T2 |
1917 |
|
T3 |
1977 |
all_values[1] |
361632 |
1 |
|
|
T1 |
1259 |
|
T2 |
1917 |
|
T3 |
1977 |
all_values[2] |
361632 |
1 |
|
|
T1 |
1259 |
|
T2 |
1917 |
|
T3 |
1977 |
all_values[3] |
361632 |
1 |
|
|
T1 |
1259 |
|
T2 |
1917 |
|
T3 |
1977 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
720547 |
1 |
|
|
T1 |
2544 |
|
T2 |
3805 |
|
T3 |
3929 |
auto[1] |
725981 |
1 |
|
|
T1 |
2492 |
|
T2 |
3863 |
|
T3 |
3979 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
873610 |
1 |
|
|
T1 |
3630 |
|
T2 |
3868 |
|
T3 |
3977 |
auto[1] |
572918 |
1 |
|
|
T1 |
1406 |
|
T2 |
3800 |
|
T3 |
3931 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
103363 |
1 |
|
|
T1 |
659 |
|
T2 |
459 |
|
T3 |
471 |
all_values[0] |
auto[0] |
auto[1] |
76219 |
1 |
|
|
T1 |
2 |
|
T2 |
448 |
|
T3 |
466 |
all_values[0] |
auto[1] |
auto[0] |
105291 |
1 |
|
|
T1 |
597 |
|
T2 |
514 |
|
T3 |
521 |
all_values[0] |
auto[1] |
auto[1] |
76759 |
1 |
|
|
T1 |
1 |
|
T2 |
496 |
|
T3 |
519 |
all_values[1] |
auto[0] |
auto[0] |
109740 |
1 |
|
|
T1 |
351 |
|
T2 |
486 |
|
T3 |
482 |
all_values[1] |
auto[0] |
auto[1] |
70443 |
1 |
|
|
T1 |
257 |
|
T2 |
473 |
|
T3 |
482 |
all_values[1] |
auto[1] |
auto[0] |
110856 |
1 |
|
|
T1 |
370 |
|
T2 |
483 |
|
T3 |
508 |
all_values[1] |
auto[1] |
auto[1] |
70593 |
1 |
|
|
T1 |
281 |
|
T2 |
475 |
|
T3 |
505 |
all_values[2] |
auto[0] |
auto[0] |
111296 |
1 |
|
|
T1 |
356 |
|
T2 |
495 |
|
T3 |
521 |
all_values[2] |
auto[0] |
auto[1] |
69609 |
1 |
|
|
T1 |
271 |
|
T2 |
482 |
|
T3 |
509 |
all_values[2] |
auto[1] |
auto[0] |
111858 |
1 |
|
|
T1 |
349 |
|
T2 |
470 |
|
T3 |
477 |
all_values[2] |
auto[1] |
auto[1] |
68869 |
1 |
|
|
T1 |
283 |
|
T2 |
470 |
|
T3 |
470 |
all_values[3] |
auto[0] |
auto[0] |
109703 |
1 |
|
|
T1 |
484 |
|
T2 |
481 |
|
T3 |
503 |
all_values[3] |
auto[0] |
auto[1] |
70174 |
1 |
|
|
T1 |
164 |
|
T2 |
481 |
|
T3 |
495 |
all_values[3] |
auto[1] |
auto[0] |
111503 |
1 |
|
|
T1 |
464 |
|
T2 |
480 |
|
T3 |
494 |
all_values[3] |
auto[1] |
auto[1] |
70252 |
1 |
|
|
T1 |
147 |
|
T2 |
475 |
|
T3 |
485 |