Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	361632	1			T1	1259		T2	1917		T3	1977
all_pins[1]	361632	1			T1	1259		T2	1917		T3	1977
all_pins[2]	361632	1			T1	1259		T2	1917		T3	1977
all_pins[3]	361632	1			T1	1259		T2	1917		T3	1977

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1160055	1			T1	4324		T2	5752		T3	5929
values[0x1]	286473	1			T1	712		T2	1916		T3	1979
transitions[0x0=>0x1]	191238	1			T1	508		T2	1206		T3	1250
transitions[0x1=>0x0]	191481	1			T1	508		T2	1206		T3	1251

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	284873	1			T1	1258		T2	1421		T3	1458
all_pins[0]	values[0x1]	76759	1			T1	1		T2	496		T3	519
all_pins[0]	transitions[0x0=>0x1]	76136	1			T1	1		T2	496		T3	518
all_pins[0]	transitions[0x1=>0x0]	69872	1			T1	147		T2	475		T3	485
all_pins[1]	values[0x0]	291039	1			T1	978		T2	1442		T3	1472
all_pins[1]	values[0x1]	70593	1			T1	281		T2	475		T3	505
all_pins[1]	transitions[0x0=>0x1]	38203	1			T1	280		T2	230		T3	251
all_pins[1]	transitions[0x1=>0x0]	44369	1			T2	251		T3	265		T14	240
all_pins[2]	values[0x0]	292763	1			T1	976		T2	1447		T3	1507
all_pins[2]	values[0x1]	68869	1			T1	283		T2	470		T3	470
all_pins[2]	transitions[0x0=>0x1]	37719	1			T1	148		T2	236		T3	229
all_pins[2]	transitions[0x1=>0x0]	39443	1			T1	146		T2	241		T3	264
all_pins[3]	values[0x0]	291380	1			T1	1112		T2	1442		T3	1492
all_pins[3]	values[0x1]	70252	1			T1	147		T2	475		T3	485
all_pins[3]	transitions[0x0=>0x1]	39180	1			T1	79		T2	244		T3	252
all_pins[3]	transitions[0x1=>0x0]	37797	1			T1	215		T2	239		T3	237