Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	89692	1			T2	1210		T3	701		T14	39
accum_cnt_1000	219614	1			T1	643		T2	1066		T3	652
accum_cnt_100	27619	1			T1	167		T2	59		T3	40
accum_cnt_50	54821	1			T1	89		T2	46		T3	29
accum_cnt_10	177006	1			T1	1956		T2	1471		T3	1488
accum_cnt_0	460061	1			T1	957		T2	1441		T3	2971

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	266806	1			T1	953		T2	1443		T3	1484
class_index[0x1]	266806	1			T1	953		T2	1443		T3	1484
class_index[0x2]	266806	1			T1	953		T2	1443		T3	1484
class_index[0x3]	266806	1			T1	953		T2	1443		T3	1484

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	29479	1			T2	728		T3	701		T10	91
class_index[0x0]	accum_cnt_1000	58149	1			T2	631		T3	652		T14	25
class_index[0x0]	accum_cnt_100	8498	1			T2	36		T3	40		T14	62
class_index[0x0]	accum_cnt_50	17109	1			T2	29		T3	29		T14	871
class_index[0x0]	accum_cnt_10	39170	1			T2	15		T3	6		T14	26
class_index[0x0]	accum_cnt_0	96346	1			T1	953		T2	4		T3	1
class_index[0x1]	accum_cnt_2000	17936	1			T14	39		T23	638		T76	333
class_index[0x1]	accum_cnt_1000	58332	1			T14	22		T10	460		T19	135
class_index[0x1]	accum_cnt_100	6825	1			T14	20		T10	54		T40	13
class_index[0x1]	accum_cnt_50	11874	1			T14	34		T10	52		T40	16
class_index[0x1]	accum_cnt_10	45157	1			T1	951		T2	6		T14	78
class_index[0x1]	accum_cnt_0	121560	1			T1	2		T2	1437		T3	1484
class_index[0x2]	accum_cnt_2000	21546	1			T43	470		T94	613		T75	44
class_index[0x2]	accum_cnt_1000	52976	1			T14	26		T18	26		T43	537
class_index[0x2]	accum_cnt_100	6885	1			T14	17		T18	27		T11	1
class_index[0x2]	accum_cnt_50	11322	1			T14	15		T17	12		T18	22
class_index[0x2]	accum_cnt_10	46358	1			T1	953		T2	1443		T3	1482
class_index[0x2]	accum_cnt_0	122412	1			T3	2		T14	174		T15	27
class_index[0x3]	accum_cnt_2000	20731	1			T2	482		T42	144		T43	521
class_index[0x3]	accum_cnt_1000	50157	1			T1	643		T2	435		T14	774
class_index[0x3]	accum_cnt_100	5411	1			T1	167		T2	23		T14	72
class_index[0x3]	accum_cnt_50	14516	1			T1	89		T2	17		T14	69
class_index[0x3]	accum_cnt_10	46321	1			T1	52		T2	7		T14	35
class_index[0x3]	accum_cnt_0	119743	1			T1	2		T3	1484		T14	115