Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2655	1			T42	28		T19	6		T24	224
alert[0x1]	7965	1			T12	1		T19	2120		T25	10
alert[0x2]	4865	1			T10	85		T13	1		T42	34
alert[0x3]	2263	1			T6	1		T12	2		T25	78
alert[0x4]	2590	1			T6	1		T42	12		T129	1
alert[0x5]	5819	1			T14	15		T42	435		T24	928
alert[0x6]	8073	1			T14	117		T42	1		T43	1
alert[0x7]	4738	1			T11	8		T42	77		T25	6
alert[0x8]	1898	1			T10	2		T43	5		T25	328
alert[0x9]	5867	1			T6	1		T19	17		T25	54
alert[0xa]	6369	1			T14	4		T6	1		T19	6
alert[0xb]	17235	1			T14	170		T4	1		T10	212
alert[0xc]	5238	1			T14	15		T6	1		T43	2
alert[0xd]	5167	1			T14	69		T4	1		T10	19
alert[0xe]	6050	1			T14	13		T12	1		T42	178
alert[0xf]	6144	1			T4	1		T13	1		T19	185
alert[0x10]	9002	1			T12	1		T91	1		T46	245
alert[0x11]	6271	1			T13	1		T42	43		T27	23
alert[0x12]	3360	1			T42	264		T43	1		T91	1
alert[0x13]	4105	1			T14	1		T10	30		T13	1
alert[0x14]	2223	1			T4	1		T13	1		T42	173
alert[0x15]	10326	1			T1	1		T11	7		T73	1
alert[0x16]	4398	1			T11	1		T42	185		T19	38
alert[0x17]	3210	1			T14	197		T5	1		T42	15
alert[0x18]	6755	1			T6	2		T42	45		T43	1
alert[0x19]	2245	1			T13	1		T42	54		T27	71
alert[0x1a]	12217	1			T14	1120		T4	1		T43	10
alert[0x1b]	1987	1			T14	62		T6	1		T12	1
alert[0x1c]	6230	1			T4	1		T10	1449		T12	1
alert[0x1d]	5810	1			T14	103		T11	469		T25	188
alert[0x1e]	4891	1			T4	1		T91	1		T75	116
alert[0x1f]	5780	1			T14	6		T4	1		T10	336
alert[0x20]	2429	1			T14	24		T6	1		T91	2
alert[0x21]	3240	1			T6	2		T43	6		T27	20
alert[0x22]	1417	1			T42	7		T19	206		T25	11
alert[0x23]	5923	1			T14	16		T10	1168		T11	15
alert[0x24]	1629	1			T5	1		T6	1		T13	2
alert[0x25]	5651	1			T10	479		T12	1		T129	1
alert[0x26]	4208	1			T10	242		T11	1		T13	1
alert[0x27]	4260	1			T4	1		T72	1		T25	2
alert[0x28]	3401	1			T10	73		T12	1		T13	1
alert[0x29]	2772	1			T42	11		T19	60		T25	2
alert[0x2a]	9036	1			T129	1		T75	46		T24	63
alert[0x2b]	3011	1			T13	1		T42	124		T72	1
alert[0x2c]	6750	1			T4	1		T46	298		T72	1
alert[0x2d]	3296	1			T4	2		T6	1		T42	31
alert[0x2e]	5170	1			T14	319		T13	1		T42	7
alert[0x2f]	4555	1			T19	45		T25	243		T287	14
alert[0x30]	3328	1			T14	460		T6	1		T44	2
alert[0x31]	4651	1			T10	34		T27	189		T265	202
alert[0x32]	2431	1			T4	1		T91	1		T75	513
alert[0x33]	4850	1			T13	1		T25	474		T24	47
alert[0x34]	7159	1			T4	1		T13	1		T42	9
alert[0x35]	7043	1			T14	3		T13	1		T42	162
alert[0x36]	5719	1			T14	19		T10	20		T6	2
alert[0x37]	4365	1			T4	2		T43	3		T24	12
alert[0x38]	4737	1			T14	157		T4	1		T5	1
alert[0x39]	8522	1			T10	41		T6	1		T11	3
alert[0x3a]	5440	1			T4	1		T10	5		T42	181
alert[0x3b]	5226	1			T10	344		T6	1		T12	1
alert[0x3c]	3208	1			T10	68		T91	1		T25	16
alert[0x3d]	9468	1			T42	13		T19	27		T73	2
alert[0x3e]	2270	1			T42	10		T25	70		T75	170
alert[0x3f]	3597	1			T10	6		T42	121		T19	90
alert[0x40]	6131	1			T19	153		T24	2053		T27	27

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	122884	1			T1	1		T14	2		T4	3
class_i[0x1]	72742	1			T14	2		T4	7		T5	1
class_i[0x2]	65057	1			T14	2886		T4	3		T5	1
class_i[0x3]	75956	1			T4	5		T6	3		T12	10

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

335891

1

T14

2890

T10

4613

T11

505

alert_ping_fail

748

1

T1

1

T4

18

T5

3

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2646	1			T42	28		T19	6		T24	224
alert_integrity_fail	alert[0x1]	7951	1			T19	2120		T25	10		T27	12
alert_integrity_fail	alert[0x2]	4858	1			T10	85		T42	34		T19	301
alert_integrity_fail	alert[0x3]	2252	1			T25	78		T75	62		T287	2
alert_integrity_fail	alert[0x4]	2582	1			T42	12		T75	126		T24	3
alert_integrity_fail	alert[0x5]	5801	1			T14	15		T42	435		T24	928
alert_integrity_fail	alert[0x6]	8064	1			T14	117		T42	1		T43	1
alert_integrity_fail	alert[0x7]	4727	1			T11	8		T42	77		T25	6
alert_integrity_fail	alert[0x8]	1888	1			T10	2		T43	5		T25	328
alert_integrity_fail	alert[0x9]	5859	1			T19	17		T25	54		T75	4
alert_integrity_fail	alert[0xa]	6354	1			T14	4		T19	6		T25	6
alert_integrity_fail	alert[0xb]	17226	1			T14	170		T10	212		T42	103
alert_integrity_fail	alert[0xc]	5228	1			T14	15		T43	2		T24	323
alert_integrity_fail	alert[0xd]	5157	1			T14	69		T10	19		T42	19
alert_integrity_fail	alert[0xe]	6040	1			T14	13		T42	178		T19	4
alert_integrity_fail	alert[0xf]	6133	1			T19	185		T25	173		T287	1
alert_integrity_fail	alert[0x10]	8991	1			T46	245		T25	18		T75	138
alert_integrity_fail	alert[0x11]	6263	1			T42	43		T27	23		T47	698
alert_integrity_fail	alert[0x12]	3353	1			T42	264		T43	1		T27	48
alert_integrity_fail	alert[0x13]	4094	1			T14	1		T10	30		T42	40
alert_integrity_fail	alert[0x14]	2215	1			T42	173		T27	13		T288	178
alert_integrity_fail	alert[0x15]	10318	1			T11	7		T24	309		T27	145
alert_integrity_fail	alert[0x16]	4390	1			T11	1		T42	185		T19	38
alert_integrity_fail	alert[0x17]	3197	1			T14	197		T42	15		T75	11
alert_integrity_fail	alert[0x18]	6742	1			T42	45		T43	1		T27	247
alert_integrity_fail	alert[0x19]	2237	1			T42	54		T27	71		T265	35
alert_integrity_fail	alert[0x1a]	12208	1			T14	1120		T43	10		T19	16
alert_integrity_fail	alert[0x1b]	1968	1			T14	62		T42	13		T19	11
alert_integrity_fail	alert[0x1c]	6218	1			T10	1449		T42	5		T19	3
alert_integrity_fail	alert[0x1d]	5799	1			T14	103		T11	469		T25	188
alert_integrity_fail	alert[0x1e]	4878	1			T75	116		T24	1013		T288	446
alert_integrity_fail	alert[0x1f]	5757	1			T14	6		T10	336		T42	50
alert_integrity_fail	alert[0x20]	2417	1			T14	24		T27	1		T54	7
alert_integrity_fail	alert[0x21]	3226	1			T43	6		T27	20		T288	1
alert_integrity_fail	alert[0x22]	1407	1			T42	7		T19	206		T25	11
alert_integrity_fail	alert[0x23]	5915	1			T14	16		T10	1168		T11	15
alert_integrity_fail	alert[0x24]	1619	1			T42	139		T43	2		T75	20
alert_integrity_fail	alert[0x25]	5637	1			T10	479		T288	62		T265	135
alert_integrity_fail	alert[0x26]	4196	1			T10	242		T11	1		T47	528
alert_integrity_fail	alert[0x27]	4248	1			T25	2		T75	6		T86	5
alert_integrity_fail	alert[0x28]	3383	1			T10	73		T19	15		T75	1
alert_integrity_fail	alert[0x29]	2760	1			T42	11		T19	60		T25	2
alert_integrity_fail	alert[0x2a]	9023	1			T75	46		T24	63		T288	19
alert_integrity_fail	alert[0x2b]	2995	1			T42	124		T77	108		T288	20
alert_integrity_fail	alert[0x2c]	6735	1			T46	298		T27	32		T78	2
alert_integrity_fail	alert[0x2d]	3280	1			T42	31		T19	94		T75	1
alert_integrity_fail	alert[0x2e]	5156	1			T14	319		T42	7		T19	12
alert_integrity_fail	alert[0x2f]	4548	1			T19	45		T25	243		T287	14
alert_integrity_fail	alert[0x30]	3312	1			T14	460		T46	119		T25	12
alert_integrity_fail	alert[0x31]	4646	1			T10	34		T27	189		T265	202
alert_integrity_fail	alert[0x32]	2420	1			T75	513		T78	10		T47	21
alert_integrity_fail	alert[0x33]	4842	1			T25	474		T24	47		T47	121
alert_integrity_fail	alert[0x34]	7147	1			T42	9		T19	33		T25	94
alert_integrity_fail	alert[0x35]	7027	1			T14	3		T42	162		T25	23
alert_integrity_fail	alert[0x36]	5701	1			T14	19		T10	20		T11	1
alert_integrity_fail	alert[0x37]	4353	1			T43	3		T24	12		T50	137
alert_integrity_fail	alert[0x38]	4717	1			T14	157		T42	377		T75	53
alert_integrity_fail	alert[0x39]	8508	1			T10	41		T11	3		T25	161
alert_integrity_fail	alert[0x3a]	5428	1			T10	5		T42	181		T43	1
alert_integrity_fail	alert[0x3b]	5213	1			T10	344		T19	7		T75	1
alert_integrity_fail	alert[0x3c]	3202	1			T10	68		T25	16		T75	129
alert_integrity_fail	alert[0x3d]	9458	1			T42	13		T19	27		T75	505
alert_integrity_fail	alert[0x3e]	2262	1			T42	10		T25	70		T75	170
alert_integrity_fail	alert[0x3f]	3591	1			T10	6		T42	121		T19	90
alert_integrity_fail	alert[0x40]	6125	1			T19	153		T24	2053		T27	27
alert_ping_fail	alert[0x0]	9	1			T289	1		T290	1		T291	1
alert_ping_fail	alert[0x1]	14	1			T12	1		T292	1		T293	1
alert_ping_fail	alert[0x2]	7	1			T13	1		T294	1		T295	1
alert_ping_fail	alert[0x3]	11	1			T6	1		T12	2		T296	2
alert_ping_fail	alert[0x4]	8	1			T6	1		T129	1		T297	1
alert_ping_fail	alert[0x5]	18	1			T292	1		T297	1		T118	1
alert_ping_fail	alert[0x6]	9	1			T298	1		T299	1		T293	1
alert_ping_fail	alert[0x7]	11	1			T129	1		T297	1		T289	1
alert_ping_fail	alert[0x8]	10	1			T300	3		T301	1		T302	1
alert_ping_fail	alert[0x9]	8	1			T6	1		T297	1		T289	1
alert_ping_fail	alert[0xa]	15	1			T6	1		T286	1		T293	1
alert_ping_fail	alert[0xb]	9	1			T4	1		T72	1		T292	2
alert_ping_fail	alert[0xc]	10	1			T6	1		T91	1		T297	1
alert_ping_fail	alert[0xd]	10	1			T4	1		T6	1		T91	1
alert_ping_fail	alert[0xe]	10	1			T12	1		T303	1		T289	1
alert_ping_fail	alert[0xf]	11	1			T4	1		T13	1		T129	1
alert_ping_fail	alert[0x10]	11	1			T12	1		T91	1		T129	1
alert_ping_fail	alert[0x11]	8	1			T13	1		T303	1		T304	2
alert_ping_fail	alert[0x12]	7	1			T91	1		T129	1		T299	1
alert_ping_fail	alert[0x13]	11	1			T13	1		T129	1		T293	1
alert_ping_fail	alert[0x14]	8	1			T4	1		T13	1		T91	1
alert_ping_fail	alert[0x15]	8	1			T1	1		T73	1		T305	1
alert_ping_fail	alert[0x16]	8	1			T91	1		T303	1		T306	1
alert_ping_fail	alert[0x17]	13	1			T5	1		T72	1		T73	2
alert_ping_fail	alert[0x18]	13	1			T6	2		T295	1		T307	2
alert_ping_fail	alert[0x19]	8	1			T13	1		T298	1		T301	1
alert_ping_fail	alert[0x1a]	9	1			T4	1		T91	1		T296	1
alert_ping_fail	alert[0x1b]	19	1			T6	1		T12	1		T13	1
alert_ping_fail	alert[0x1c]	12	1			T4	1		T12	1		T308	1
alert_ping_fail	alert[0x1d]	11	1			T73	2		T304	2		T294	1
alert_ping_fail	alert[0x1e]	13	1			T4	1		T91	1		T229	1
alert_ping_fail	alert[0x1f]	23	1			T4	1		T13	1		T91	1
alert_ping_fail	alert[0x20]	12	1			T6	1		T91	2		T129	2
alert_ping_fail	alert[0x21]	14	1			T6	2		T216	1		T299	1
alert_ping_fail	alert[0x22]	10	1			T294	1		T295	1		T309	1
alert_ping_fail	alert[0x23]	8	1			T91	1		T304	1		T310	1
alert_ping_fail	alert[0x24]	10	1			T5	1		T6	1		T13	2
alert_ping_fail	alert[0x25]	14	1			T12	1		T129	1		T297	1
alert_ping_fail	alert[0x26]	12	1			T13	1		T129	1		T296	3
alert_ping_fail	alert[0x27]	12	1			T4	1		T72	1		T129	1
alert_ping_fail	alert[0x28]	18	1			T12	1		T13	1		T118	1
alert_ping_fail	alert[0x29]	12	1			T129	1		T292	1		T304	1
alert_ping_fail	alert[0x2a]	13	1			T129	1		T216	1		T222	1
alert_ping_fail	alert[0x2b]	16	1			T13	1		T72	1		T311	1
alert_ping_fail	alert[0x2c]	15	1			T4	1		T72	1		T285	1
alert_ping_fail	alert[0x2d]	16	1			T4	2		T6	1		T223	1
alert_ping_fail	alert[0x2e]	14	1			T13	1		T223	1		T299	1
alert_ping_fail	alert[0x2f]	7	1			T297	1		T118	1		T293	1
alert_ping_fail	alert[0x30]	16	1			T6	1		T44	2		T296	1
alert_ping_fail	alert[0x31]	5	1			T303	1		T291	2		T312	1
alert_ping_fail	alert[0x32]	11	1			T4	1		T91	1		T293	1
alert_ping_fail	alert[0x33]	8	1			T13	1		T289	1		T310	1
alert_ping_fail	alert[0x34]	12	1			T4	1		T13	1		T229	1
alert_ping_fail	alert[0x35]	16	1			T13	1		T73	1		T229	1
alert_ping_fail	alert[0x36]	18	1			T6	2		T12	1		T72	1
alert_ping_fail	alert[0x37]	12	1			T4	2		T297	1		T289	1
alert_ping_fail	alert[0x38]	20	1			T4	1		T5	1		T6	2
alert_ping_fail	alert[0x39]	14	1			T6	1		T12	1		T299	1
alert_ping_fail	alert[0x3a]	12	1			T4	1		T294	1		T300	1
alert_ping_fail	alert[0x3b]	13	1			T6	1		T12	1		T13	1
alert_ping_fail	alert[0x3c]	6	1			T91	1		T299	2		T313	1
alert_ping_fail	alert[0x3d]	10	1			T73	2		T292	1		T296	1
alert_ping_fail	alert[0x3e]	8	1			T229	1		T296	1		T299	1
alert_ping_fail	alert[0x3f]	6	1			T296	1		T308	1		T290	1
alert_ping_fail	alert[0x40]	6	1			T310	1		T300	1		T314	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	122729	1			T14	2		T10	4609		T11	489
alert_integrity_fail	class_i[0x1]	72562	1			T14	2		T11	16		T42	10
alert_integrity_fail	class_i[0x2]	64848	1			T14	2886		T10	4		T19	36
alert_integrity_fail	class_i[0x3]	75752	1			T42	3043		T43	3		T19	39
alert_ping_fail	class_i[0x0]	155	1			T1	1		T4	3		T5	1
alert_ping_fail	class_i[0x1]	180	1			T4	7		T5	1		T6	2
alert_ping_fail	class_i[0x2]	209	1			T4	3		T5	1		T6	1
alert_ping_fail	class_i[0x3]	204	1			T4	5		T6	3		T12	10