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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.71 100.00 100.00 100.00 99.38 99.40


Total test records in report: 831
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T767 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.108542660 Mar 31 12:30:01 PM PDT 24 Mar 31 12:30:05 PM PDT 24 61198482 ps
T160 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2918415178 Mar 31 12:29:43 PM PDT 24 Mar 31 12:45:40 PM PDT 24 110175039857 ps
T768 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2894433362 Mar 31 12:29:44 PM PDT 24 Mar 31 12:29:48 PM PDT 24 266015798 ps
T769 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.896847094 Mar 31 12:30:14 PM PDT 24 Mar 31 12:30:16 PM PDT 24 7575754 ps
T161 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.379337882 Mar 31 12:30:11 PM PDT 24 Mar 31 12:34:48 PM PDT 24 8113131844 ps
T157 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2068352000 Mar 31 12:29:54 PM PDT 24 Mar 31 12:33:33 PM PDT 24 11558072881 ps
T770 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1638783232 Mar 31 12:29:59 PM PDT 24 Mar 31 12:30:01 PM PDT 24 9809580 ps
T187 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.440754245 Mar 31 12:29:46 PM PDT 24 Mar 31 12:30:51 PM PDT 24 964452115 ps
T771 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4002403998 Mar 31 12:29:57 PM PDT 24 Mar 31 12:29:59 PM PDT 24 9876776 ps
T772 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2956893874 Mar 31 12:31:13 PM PDT 24 Mar 31 12:31:23 PM PDT 24 150177515 ps
T773 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.557031247 Mar 31 12:29:56 PM PDT 24 Mar 31 12:30:03 PM PDT 24 97876660 ps
T774 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1365952184 Mar 31 12:29:58 PM PDT 24 Mar 31 12:30:03 PM PDT 24 91974926 ps
T775 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1767192275 Mar 31 12:30:15 PM PDT 24 Mar 31 12:30:16 PM PDT 24 11780726 ps
T776 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2429167662 Mar 31 12:29:54 PM PDT 24 Mar 31 12:30:04 PM PDT 24 291322558 ps
T777 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3066295478 Mar 31 12:30:03 PM PDT 24 Mar 31 12:30:05 PM PDT 24 11895140 ps
T778 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1670027568 Mar 31 12:29:56 PM PDT 24 Mar 31 12:29:58 PM PDT 24 9913843 ps
T779 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1777993085 Mar 31 12:29:40 PM PDT 24 Mar 31 12:29:45 PM PDT 24 162824738 ps
T780 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2225951795 Mar 31 12:30:57 PM PDT 24 Mar 31 12:33:46 PM PDT 24 6805279010 ps
T156 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4094849170 Mar 31 12:29:44 PM PDT 24 Mar 31 12:31:34 PM PDT 24 4460829981 ps
T781 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.837926731 Mar 31 12:29:40 PM PDT 24 Mar 31 12:29:50 PM PDT 24 581410984 ps
T172 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2303936759 Mar 31 12:30:05 PM PDT 24 Mar 31 12:30:53 PM PDT 24 443493808 ps
T782 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2200342015 Mar 31 12:29:53 PM PDT 24 Mar 31 12:30:06 PM PDT 24 441962881 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2852223618 Mar 31 12:29:40 PM PDT 24 Mar 31 12:29:45 PM PDT 24 32115834 ps
T784 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3544417149 Mar 31 12:29:58 PM PDT 24 Mar 31 12:30:00 PM PDT 24 6776239 ps
T785 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1761401254 Mar 31 12:29:44 PM PDT 24 Mar 31 12:29:50 PM PDT 24 39640362 ps
T786 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.488117201 Mar 31 12:29:40 PM PDT 24 Mar 31 12:30:00 PM PDT 24 460906500 ps
T787 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2948774525 Mar 31 12:29:37 PM PDT 24 Mar 31 12:29:41 PM PDT 24 41220296 ps
T788 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.621058683 Mar 31 12:30:56 PM PDT 24 Mar 31 12:31:08 PM PDT 24 88431286 ps
T345 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3002559697 Mar 31 12:29:45 PM PDT 24 Mar 31 12:46:58 PM PDT 24 15348231849 ps
T789 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1822722896 Mar 31 12:30:09 PM PDT 24 Mar 31 12:30:28 PM PDT 24 255913845 ps
T790 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3340276447 Mar 31 12:29:43 PM PDT 24 Mar 31 12:32:06 PM PDT 24 4731448076 ps
T791 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.4027968324 Mar 31 12:29:51 PM PDT 24 Mar 31 12:29:58 PM PDT 24 1418486987 ps
T792 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1470056194 Mar 31 12:29:43 PM PDT 24 Mar 31 12:30:24 PM PDT 24 701542315 ps
T793 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.4251966471 Mar 31 12:29:44 PM PDT 24 Mar 31 12:29:50 PM PDT 24 772671093 ps
T794 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1826110795 Mar 31 12:29:55 PM PDT 24 Mar 31 12:30:03 PM PDT 24 314277347 ps
T795 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4112574711 Mar 31 12:29:44 PM PDT 24 Mar 31 12:29:56 PM PDT 24 353940578 ps
T796 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.487280850 Mar 31 12:30:13 PM PDT 24 Mar 31 12:30:14 PM PDT 24 28075078 ps
T181 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1307841567 Mar 31 12:29:43 PM PDT 24 Mar 31 12:30:04 PM PDT 24 2424517261 ps
T797 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.522124135 Mar 31 12:30:14 PM PDT 24 Mar 31 12:30:37 PM PDT 24 353234781 ps
T798 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4001506572 Mar 31 12:29:57 PM PDT 24 Mar 31 12:29:58 PM PDT 24 8437245 ps
T158 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1865264114 Mar 31 12:29:52 PM PDT 24 Mar 31 12:35:17 PM PDT 24 2490177677 ps
T799 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3694794891 Mar 31 12:30:17 PM PDT 24 Mar 31 12:30:18 PM PDT 24 10222459 ps
T800 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2715370821 Mar 31 12:29:55 PM PDT 24 Mar 31 12:30:32 PM PDT 24 673655406 ps
T801 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2537155375 Mar 31 12:29:42 PM PDT 24 Mar 31 12:33:46 PM PDT 24 3973640381 ps
T184 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.736275205 Mar 31 12:31:01 PM PDT 24 Mar 31 12:31:05 PM PDT 24 91700888 ps
T802 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2322186059 Mar 31 12:30:03 PM PDT 24 Mar 31 12:30:05 PM PDT 24 6729960 ps
T803 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.611492624 Mar 31 12:29:42 PM PDT 24 Mar 31 12:30:00 PM PDT 24 4956158049 ps
T804 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2785376879 Mar 31 12:29:42 PM PDT 24 Mar 31 12:31:20 PM PDT 24 2045914901 ps
T805 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2238778606 Mar 31 12:29:57 PM PDT 24 Mar 31 12:29:58 PM PDT 24 37463668 ps
T806 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3933978206 Mar 31 12:30:09 PM PDT 24 Mar 31 12:30:10 PM PDT 24 22648259 ps
T807 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1455934852 Mar 31 12:30:01 PM PDT 24 Mar 31 12:30:12 PM PDT 24 345099734 ps
T808 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2849931450 Mar 31 12:29:39 PM PDT 24 Mar 31 12:29:41 PM PDT 24 98721457 ps
T809 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3975036183 Mar 31 12:29:42 PM PDT 24 Mar 31 12:29:46 PM PDT 24 44016148 ps
T810 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.4247167969 Mar 31 12:29:42 PM PDT 24 Mar 31 12:29:52 PM PDT 24 252381723 ps
T811 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2653813244 Mar 31 12:30:03 PM PDT 24 Mar 31 12:30:05 PM PDT 24 20169945 ps
T183 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3398777900 Mar 31 12:29:46 PM PDT 24 Mar 31 12:29:50 PM PDT 24 60960551 ps
T812 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3755461722 Mar 31 12:30:15 PM PDT 24 Mar 31 12:30:18 PM PDT 24 42201927 ps
T813 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3841298496 Mar 31 12:30:07 PM PDT 24 Mar 31 12:30:08 PM PDT 24 11277220 ps
T814 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1650144635 Mar 31 12:30:02 PM PDT 24 Mar 31 12:30:09 PM PDT 24 332966843 ps
T815 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2472083342 Mar 31 12:29:56 PM PDT 24 Mar 31 12:30:02 PM PDT 24 118785688 ps
T816 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3532180932 Mar 31 12:31:14 PM PDT 24 Mar 31 12:31:18 PM PDT 24 112969611 ps
T817 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3015105778 Mar 31 12:29:40 PM PDT 24 Mar 31 12:29:53 PM PDT 24 248227057 ps
T818 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.906016661 Mar 31 12:30:11 PM PDT 24 Mar 31 12:30:13 PM PDT 24 10631367 ps
T819 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3301765201 Mar 31 12:29:59 PM PDT 24 Mar 31 12:30:00 PM PDT 24 12057828 ps
T162 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2869390004 Mar 31 12:29:46 PM PDT 24 Mar 31 12:40:07 PM PDT 24 22310734443 ps
T148 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2950678888 Mar 31 12:31:09 PM PDT 24 Mar 31 12:32:40 PM PDT 24 8870682764 ps
T820 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3883384246 Mar 31 12:29:39 PM PDT 24 Mar 31 12:29:47 PM PDT 24 246952138 ps
T182 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.445024768 Mar 31 12:29:55 PM PDT 24 Mar 31 12:30:14 PM PDT 24 808861512 ps
T180 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1580240551 Mar 31 12:30:13 PM PDT 24 Mar 31 12:30:15 PM PDT 24 61485084 ps
T821 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.885244176 Mar 31 12:29:52 PM PDT 24 Mar 31 12:30:06 PM PDT 24 283880449 ps
T163 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2511803454 Mar 31 12:30:19 PM PDT 24 Mar 31 12:39:02 PM PDT 24 56869736210 ps
T822 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2606077788 Mar 31 12:31:09 PM PDT 24 Mar 31 12:31:42 PM PDT 24 2444348706 ps
T823 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3645346715 Mar 31 12:29:45 PM PDT 24 Mar 31 12:29:50 PM PDT 24 32029122 ps
T824 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2562147705 Mar 31 12:31:23 PM PDT 24 Mar 31 12:31:24 PM PDT 24 18993933 ps
T825 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1281331084 Mar 31 12:30:17 PM PDT 24 Mar 31 12:30:18 PM PDT 24 11640249 ps
T826 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3413379966 Mar 31 12:29:44 PM PDT 24 Mar 31 12:29:46 PM PDT 24 10972938 ps
T827 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2132235009 Mar 31 12:29:33 PM PDT 24 Mar 31 12:34:50 PM PDT 24 2308193178 ps
T828 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3609676129 Mar 31 12:30:06 PM PDT 24 Mar 31 12:30:11 PM PDT 24 250163356 ps
T829 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4048635121 Mar 31 12:29:40 PM PDT 24 Mar 31 12:33:39 PM PDT 24 4446386866 ps
T830 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3961876017 Mar 31 12:30:12 PM PDT 24 Mar 31 12:32:24 PM PDT 24 2310508415 ps
T831 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1749027656 Mar 31 12:29:46 PM PDT 24 Mar 31 12:29:48 PM PDT 24 8023825 ps

Test location /workspace/coverage/default/39.alert_handler_stress_all.1548316138
Short name T14
Test name
Test status
Simulation time 43052509470 ps
CPU time 2362.69 seconds
Started Mar 31 12:51:09 PM PDT 24
Finished Mar 31 01:30:33 PM PDT 24
Peak memory 286976 kb
Host smart-0d4015de-1dfb-4363-99ad-4225d5c42d36
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548316138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1548316138
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1543173324
Short name T24
Test name
Test status
Simulation time 193112100126 ps
CPU time 3290.21 seconds
Started Mar 31 12:51:01 PM PDT 24
Finished Mar 31 01:45:52 PM PDT 24
Peak memory 305668 kb
Host smart-647fbe3c-cdcd-4892-82d2-2ffa383b6b95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543173324 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1543173324
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.556137720
Short name T7
Test name
Test status
Simulation time 435291590 ps
CPU time 23.84 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 12:48:46 PM PDT 24
Peak memory 273572 kb
Host smart-a4f09e38-be93-4882-8fdb-0931fc81d672
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=556137720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.556137720
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1985840514
Short name T3
Test name
Test status
Simulation time 215924565923 ps
CPU time 3548.39 seconds
Started Mar 31 12:49:35 PM PDT 24
Finished Mar 31 01:48:44 PM PDT 24
Peak memory 289164 kb
Host smart-940df77a-dcf7-4e9f-aa9e-0e132cd25088
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985840514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1985840514
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1146666076
Short name T167
Test name
Test status
Simulation time 1855914701 ps
CPU time 28.07 seconds
Started Mar 31 12:30:56 PM PDT 24
Finished Mar 31 12:31:24 PM PDT 24
Peak memory 240124 kb
Host smart-434a829f-91ce-408b-92d0-5dabac560ed5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1146666076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1146666076
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3396308306
Short name T19
Test name
Test status
Simulation time 77425222595 ps
CPU time 5904.23 seconds
Started Mar 31 12:48:53 PM PDT 24
Finished Mar 31 02:27:18 PM PDT 24
Peak memory 371624 kb
Host smart-a1e5a5ef-48aa-4eac-bbf0-6154ba157f6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396308306 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3396308306
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3307857590
Short name T137
Test name
Test status
Simulation time 4373466595 ps
CPU time 301.83 seconds
Started Mar 31 12:29:46 PM PDT 24
Finished Mar 31 12:34:48 PM PDT 24
Peak memory 270604 kb
Host smart-beef8635-9bcf-483d-9d83-584ab4c9d452
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3307857590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3307857590
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.4279461723
Short name T115
Test name
Test status
Simulation time 173696157416 ps
CPU time 2688.23 seconds
Started Mar 31 12:52:34 PM PDT 24
Finished Mar 31 01:37:23 PM PDT 24
Peak memory 289956 kb
Host smart-43e99e93-e20e-470a-a8bf-911f5bf41038
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279461723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.4279461723
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1622963626
Short name T44
Test name
Test status
Simulation time 154591529312 ps
CPU time 2315.92 seconds
Started Mar 31 12:51:38 PM PDT 24
Finished Mar 31 01:30:14 PM PDT 24
Peak memory 289000 kb
Host smart-bb82562f-78ea-4260-a271-29eeb7739f95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622963626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1622963626
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2141425774
Short name T98
Test name
Test status
Simulation time 38419816565 ps
CPU time 3979.71 seconds
Started Mar 31 12:49:23 PM PDT 24
Finished Mar 31 01:55:43 PM PDT 24
Peak memory 338280 kb
Host smart-e49097cd-8588-4e08-970e-83734d2b0b48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141425774 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2141425774
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2402699170
Short name T50
Test name
Test status
Simulation time 59004689056 ps
CPU time 7010.84 seconds
Started Mar 31 12:49:26 PM PDT 24
Finished Mar 31 02:46:17 PM PDT 24
Peak memory 371428 kb
Host smart-1099e313-80f7-40b0-87e5-efdd3525876c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402699170 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2402699170
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3500649059
Short name T105
Test name
Test status
Simulation time 36837402027 ps
CPU time 1058.75 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 01:06:01 PM PDT 24
Peak memory 281680 kb
Host smart-b320e317-98e4-4774-b7f1-7ab811ed9417
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500649059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3500649059
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3112914148
Short name T152
Test name
Test status
Simulation time 46585428615 ps
CPU time 986.13 seconds
Started Mar 31 12:29:46 PM PDT 24
Finished Mar 31 12:46:13 PM PDT 24
Peak memory 265504 kb
Host smart-ce9c6bfa-9fa8-467a-8a13-d359639239c6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112914148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3112914148
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2898613568
Short name T64
Test name
Test status
Simulation time 1046614623 ps
CPU time 45.55 seconds
Started Mar 31 12:48:21 PM PDT 24
Finished Mar 31 12:49:07 PM PDT 24
Peak memory 240680 kb
Host smart-4a97b7ff-66cc-4926-adfa-1145a520fe76
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2898613568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2898613568
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2899308901
Short name T143
Test name
Test status
Simulation time 10745903215 ps
CPU time 311.96 seconds
Started Mar 31 12:29:47 PM PDT 24
Finished Mar 31 12:34:59 PM PDT 24
Peak memory 266080 kb
Host smart-c1357ab1-72c0-46a3-93c5-42d43a4d0ce2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2899308901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2899308901
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1016312255
Short name T23
Test name
Test status
Simulation time 42525811402 ps
CPU time 1312.05 seconds
Started Mar 31 12:48:40 PM PDT 24
Finished Mar 31 01:10:32 PM PDT 24
Peak memory 288152 kb
Host smart-06d874db-df84-4192-98b7-57daadbd32e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016312255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1016312255
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.911075350
Short name T6
Test name
Test status
Simulation time 48250101068 ps
CPU time 648.58 seconds
Started Mar 31 12:48:56 PM PDT 24
Finished Mar 31 12:59:44 PM PDT 24
Peak memory 247884 kb
Host smart-b7cb4275-0af4-455f-a4ad-f79bc30c610e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911075350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.911075350
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1895293856
Short name T154
Test name
Test status
Simulation time 4442069849 ps
CPU time 652.54 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:40:37 PM PDT 24
Peak memory 272032 kb
Host smart-a8caf129-98dd-4278-bd88-f356939ff378
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895293856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1895293856
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1614947309
Short name T336
Test name
Test status
Simulation time 39692984 ps
CPU time 1.47 seconds
Started Mar 31 12:30:19 PM PDT 24
Finished Mar 31 12:30:21 PM PDT 24
Peak memory 236712 kb
Host smart-dcb9d843-ea57-4436-ae0e-754b86351e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1614947309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1614947309
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1801345188
Short name T327
Test name
Test status
Simulation time 138668636010 ps
CPU time 2092.65 seconds
Started Mar 31 12:49:52 PM PDT 24
Finished Mar 31 01:24:45 PM PDT 24
Peak memory 283364 kb
Host smart-6b717de0-1bd9-4956-8911-ec56d6c1f16a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801345188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1801345188
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2294521428
Short name T27
Test name
Test status
Simulation time 117695765861 ps
CPU time 7094.07 seconds
Started Mar 31 12:48:27 PM PDT 24
Finished Mar 31 02:46:41 PM PDT 24
Peak memory 338512 kb
Host smart-6802a830-ed94-4fb9-a64f-5c0992fa97bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294521428 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2294521428
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1962490716
Short name T140
Test name
Test status
Simulation time 7509694396 ps
CPU time 720.38 seconds
Started Mar 31 12:30:03 PM PDT 24
Finished Mar 31 12:42:03 PM PDT 24
Peak memory 273052 kb
Host smart-d2ec0ffb-c442-4d76-a97f-5461af3f93f4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962490716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1962490716
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3905290018
Short name T286
Test name
Test status
Simulation time 870170032607 ps
CPU time 2286.84 seconds
Started Mar 31 12:48:27 PM PDT 24
Finished Mar 31 01:26:34 PM PDT 24
Peak memory 288868 kb
Host smart-d3b09338-96b5-4031-9ee2-a4b39d1ab24b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905290018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3905290018
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1882747977
Short name T130
Test name
Test status
Simulation time 23368283061 ps
CPU time 166.33 seconds
Started Mar 31 12:29:42 PM PDT 24
Finished Mar 31 12:32:28 PM PDT 24
Peak memory 265104 kb
Host smart-d8696e20-e760-40a6-9ad0-0919a298c5dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1882747977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1882747977
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3030533457
Short name T13
Test name
Test status
Simulation time 12842465756 ps
CPU time 544.24 seconds
Started Mar 31 12:48:41 PM PDT 24
Finished Mar 31 12:57:45 PM PDT 24
Peak memory 248112 kb
Host smart-2084ba3a-0813-43a5-9cae-0fae58079ed6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030533457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3030533457
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.431543549
Short name T331
Test name
Test status
Simulation time 36919917726 ps
CPU time 2053.94 seconds
Started Mar 31 12:51:28 PM PDT 24
Finished Mar 31 01:25:42 PM PDT 24
Peak memory 273512 kb
Host smart-55e1fa39-9ee7-4f95-96ee-2fba5068a9c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431543549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.431543549
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1061594817
Short name T136
Test name
Test status
Simulation time 92575310894 ps
CPU time 292.54 seconds
Started Mar 31 12:29:42 PM PDT 24
Finished Mar 31 12:34:35 PM PDT 24
Peak memory 272824 kb
Host smart-1b56115f-782f-4bd0-a61d-348e08c16a61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1061594817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1061594817
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.4041254620
Short name T100
Test name
Test status
Simulation time 41603323458 ps
CPU time 2488.05 seconds
Started Mar 31 12:48:25 PM PDT 24
Finished Mar 31 01:29:54 PM PDT 24
Peak memory 289316 kb
Host smart-f5350f8a-a7bb-446f-9c2f-6dbdecd934d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041254620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.4041254620
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.4198380411
Short name T91
Test name
Test status
Simulation time 8370754336 ps
CPU time 345 seconds
Started Mar 31 12:48:44 PM PDT 24
Finished Mar 31 12:54:30 PM PDT 24
Peak memory 247224 kb
Host smart-ec79d7a2-edc5-4e2f-9a70-4488fda590ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198380411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.4198380411
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1505387437
Short name T144
Test name
Test status
Simulation time 14131898078 ps
CPU time 265.61 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:34:10 PM PDT 24
Peak memory 265176 kb
Host smart-8e47214f-b435-43f3-aa16-3e80dca7fb4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1505387437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1505387437
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3002559697
Short name T345
Test name
Test status
Simulation time 15348231849 ps
CPU time 1033.03 seconds
Started Mar 31 12:29:45 PM PDT 24
Finished Mar 31 12:46:58 PM PDT 24
Peak memory 265200 kb
Host smart-daf66b89-d761-41ac-b4ae-557669081835
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002559697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3002559697
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1683386005
Short name T291
Test name
Test status
Simulation time 8778995624 ps
CPU time 380.18 seconds
Started Mar 31 12:49:45 PM PDT 24
Finished Mar 31 12:56:06 PM PDT 24
Peak memory 247112 kb
Host smart-4eb674a8-35ce-49c6-8f3d-191cfa015c73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683386005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1683386005
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.793342521
Short name T337
Test name
Test status
Simulation time 9483452 ps
CPU time 1.61 seconds
Started Mar 31 12:29:46 PM PDT 24
Finished Mar 31 12:29:48 PM PDT 24
Peak memory 235788 kb
Host smart-f841154b-c1d7-4855-aa90-598aae8622a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=793342521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.793342521
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.721227438
Short name T323
Test name
Test status
Simulation time 166550558085 ps
CPU time 1134.42 seconds
Started Mar 31 12:48:20 PM PDT 24
Finished Mar 31 01:07:15 PM PDT 24
Peak memory 265280 kb
Host smart-4e3ad15e-f28c-4953-8f50-c4ccdc8588ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721227438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.721227438
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.603739222
Short name T242
Test name
Test status
Simulation time 49215901758 ps
CPU time 1359.8 seconds
Started Mar 31 12:48:51 PM PDT 24
Finished Mar 31 01:11:31 PM PDT 24
Peak memory 289220 kb
Host smart-7abdea43-1b21-44b1-841a-5be1f570d45c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603739222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.603739222
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2230062133
Short name T313
Test name
Test status
Simulation time 12098426011 ps
CPU time 483.07 seconds
Started Mar 31 12:49:05 PM PDT 24
Finished Mar 31 12:57:09 PM PDT 24
Peak memory 247880 kb
Host smart-c7113921-0727-431b-a0bd-b5873448a720
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230062133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2230062133
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2318781337
Short name T174
Test name
Test status
Simulation time 2273182799 ps
CPU time 34.53 seconds
Started Mar 31 12:29:58 PM PDT 24
Finished Mar 31 12:30:32 PM PDT 24
Peak memory 240304 kb
Host smart-5b1b27ab-3d47-497a-aff0-bff299b2127b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2318781337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2318781337
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3842969506
Short name T150
Test name
Test status
Simulation time 18908741231 ps
CPU time 263.75 seconds
Started Mar 31 12:30:12 PM PDT 24
Finished Mar 31 12:34:36 PM PDT 24
Peak memory 270040 kb
Host smart-fb1f21ff-f7de-4c83-8b25-394eb6eac62f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842969506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3842969506
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.728475980
Short name T33
Test name
Test status
Simulation time 1839623739 ps
CPU time 33.66 seconds
Started Mar 31 12:48:13 PM PDT 24
Finished Mar 31 12:48:47 PM PDT 24
Peak memory 255524 kb
Host smart-488e7295-339e-49f5-95e7-dffbfacf45c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72847
5980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.728475980
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2588475722
Short name T319
Test name
Test status
Simulation time 32896687905 ps
CPU time 1506.54 seconds
Started Mar 31 12:50:05 PM PDT 24
Finished Mar 31 01:15:12 PM PDT 24
Peak memory 289016 kb
Host smart-4d298b2e-4ad4-4bad-aabd-df3dcaabce4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588475722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2588475722
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.322123269
Short name T598
Test name
Test status
Simulation time 11143665622 ps
CPU time 454.56 seconds
Started Mar 31 12:50:33 PM PDT 24
Finished Mar 31 12:58:08 PM PDT 24
Peak memory 248224 kb
Host smart-f2f94fef-8bd9-4e0b-bb68-6a3231e89290
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322123269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.322123269
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.919627237
Short name T296
Test name
Test status
Simulation time 57036310257 ps
CPU time 568.69 seconds
Started Mar 31 12:51:19 PM PDT 24
Finished Mar 31 01:00:48 PM PDT 24
Peak memory 248228 kb
Host smart-a135973c-15bd-42a8-bc0e-c3fe95489932
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919627237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.919627237
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2068352000
Short name T157
Test name
Test status
Simulation time 11558072881 ps
CPU time 218.86 seconds
Started Mar 31 12:29:54 PM PDT 24
Finished Mar 31 12:33:33 PM PDT 24
Peak memory 265052 kb
Host smart-ff825740-d529-4852-acfa-77b5e5b8fb28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2068352000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2068352000
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1513809874
Short name T59
Test name
Test status
Simulation time 97303849325 ps
CPU time 3097.71 seconds
Started Mar 31 12:48:45 PM PDT 24
Finished Mar 31 01:40:24 PM PDT 24
Peak memory 289456 kb
Host smart-ba47021e-2db0-41da-a721-fe4a9a4f2364
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513809874 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1513809874
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1314112013
Short name T280
Test name
Test status
Simulation time 36735027659 ps
CPU time 1858.81 seconds
Started Mar 31 12:49:02 PM PDT 24
Finished Mar 31 01:20:01 PM PDT 24
Peak memory 284144 kb
Host smart-5eabe6e9-4e6d-461a-bc5a-38a5a76b41b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314112013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1314112013
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.105968946
Short name T240
Test name
Test status
Simulation time 98039724974 ps
CPU time 2916.23 seconds
Started Mar 31 12:49:23 PM PDT 24
Finished Mar 31 01:37:59 PM PDT 24
Peak memory 298164 kb
Host smart-43c69877-bd44-49a0-9ae7-48fc616c3656
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105968946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.105968946
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1146894948
Short name T302
Test name
Test status
Simulation time 213451909962 ps
CPU time 3113.69 seconds
Started Mar 31 12:48:43 PM PDT 24
Finished Mar 31 01:40:38 PM PDT 24
Peak memory 289016 kb
Host smart-548c402e-f760-49f8-8235-e75b024c0cfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146894948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1146894948
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4235112175
Short name T178
Test name
Test status
Simulation time 107122072 ps
CPU time 3.04 seconds
Started Mar 31 12:31:02 PM PDT 24
Finished Mar 31 12:31:05 PM PDT 24
Peak memory 236980 kb
Host smart-4315a696-bc59-4c96-8e5f-f5b41e203a10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4235112175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.4235112175
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2973454164
Short name T131
Test name
Test status
Simulation time 12037671413 ps
CPU time 478.28 seconds
Started Mar 31 12:30:13 PM PDT 24
Finished Mar 31 12:38:12 PM PDT 24
Peak memory 268016 kb
Host smart-cd4696fb-a793-4e5e-af09-efa554a7c259
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973454164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2973454164
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2260061711
Short name T207
Test name
Test status
Simulation time 15853713 ps
CPU time 2.47 seconds
Started Mar 31 12:48:23 PM PDT 24
Finished Mar 31 12:48:26 PM PDT 24
Peak memory 249028 kb
Host smart-5c40d661-2602-433d-8bb2-dac28b9da214
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2260061711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2260061711
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1612103711
Short name T70
Test name
Test status
Simulation time 144913724 ps
CPU time 2.94 seconds
Started Mar 31 12:48:23 PM PDT 24
Finished Mar 31 12:48:26 PM PDT 24
Peak memory 249056 kb
Host smart-aa25b3c2-7ef2-4818-9303-96857455d7d8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1612103711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1612103711
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3012043355
Short name T206
Test name
Test status
Simulation time 48653303 ps
CPU time 3.76 seconds
Started Mar 31 12:48:55 PM PDT 24
Finished Mar 31 12:48:59 PM PDT 24
Peak memory 257228 kb
Host smart-463a0c2c-7a11-4378-97a5-6442e927ca00
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3012043355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3012043355
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3302871543
Short name T203
Test name
Test status
Simulation time 56097544 ps
CPU time 2.32 seconds
Started Mar 31 12:48:54 PM PDT 24
Finished Mar 31 12:48:57 PM PDT 24
Peak memory 249052 kb
Host smart-4205a829-ed8d-4e5f-a53f-489b25528cb8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3302871543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3302871543
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.4255115875
Short name T4
Test name
Test status
Simulation time 59790411208 ps
CPU time 562.07 seconds
Started Mar 31 12:49:26 PM PDT 24
Finished Mar 31 12:58:48 PM PDT 24
Peak memory 255600 kb
Host smart-0d26efa5-3f9b-43a4-afc7-91115ac45bdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255115875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.4255115875
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3699283627
Short name T77
Test name
Test status
Simulation time 167576054248 ps
CPU time 2052.65 seconds
Started Mar 31 12:49:44 PM PDT 24
Finished Mar 31 01:23:58 PM PDT 24
Peak memory 283800 kb
Host smart-e0263aca-6729-4eb7-8c8e-d6963e791357
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699283627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3699283627
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2534272862
Short name T248
Test name
Test status
Simulation time 40965115692 ps
CPU time 2602.28 seconds
Started Mar 31 12:49:52 PM PDT 24
Finished Mar 31 01:33:14 PM PDT 24
Peak memory 289824 kb
Host smart-0bc7c69f-4448-4d2c-9790-881aaa94ea5b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534272862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2534272862
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2995802035
Short name T253
Test name
Test status
Simulation time 277627369175 ps
CPU time 6574.43 seconds
Started Mar 31 12:51:18 PM PDT 24
Finished Mar 31 02:40:53 PM PDT 24
Peak memory 317472 kb
Host smart-7fdaa081-92c9-41bf-8742-1de76433ae64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995802035 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2995802035
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1771255922
Short name T260
Test name
Test status
Simulation time 17818321105 ps
CPU time 1690.31 seconds
Started Mar 31 12:51:38 PM PDT 24
Finished Mar 31 01:19:49 PM PDT 24
Peak memory 289376 kb
Host smart-165565c9-93db-437e-b86a-b676dd7c1624
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771255922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1771255922
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2674887165
Short name T261
Test name
Test status
Simulation time 89462642591 ps
CPU time 829.73 seconds
Started Mar 31 12:52:05 PM PDT 24
Finished Mar 31 01:05:55 PM PDT 24
Peak memory 272900 kb
Host smart-b9dc3313-bfa4-464b-9e0e-c546472bbe6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674887165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2674887165
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1778784250
Short name T146
Test name
Test status
Simulation time 15428904659 ps
CPU time 143.51 seconds
Started Mar 31 12:29:38 PM PDT 24
Finished Mar 31 12:32:02 PM PDT 24
Peak memory 265300 kb
Host smart-4b347d2c-bdd8-44bf-9c65-c58675cdc04e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1778784250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1778784250
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.379337882
Short name T161
Test name
Test status
Simulation time 8113131844 ps
CPU time 276.91 seconds
Started Mar 31 12:30:11 PM PDT 24
Finished Mar 31 12:34:48 PM PDT 24
Peak memory 266564 kb
Host smart-1920782d-89cc-46b7-af33-1382de285773
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379337882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.379337882
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.37416093
Short name T22
Test name
Test status
Simulation time 1859813389 ps
CPU time 53.22 seconds
Started Mar 31 12:50:33 PM PDT 24
Finished Mar 31 12:51:26 PM PDT 24
Peak memory 248884 kb
Host smart-10911521-c5cf-4466-8f9f-7329c9c19f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37416
093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.37416093
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3187559274
Short name T718
Test name
Test status
Simulation time 14119632 ps
CPU time 1.77 seconds
Started Mar 31 12:30:23 PM PDT 24
Finished Mar 31 12:30:25 PM PDT 24
Peak memory 236616 kb
Host smart-e36fe9f4-10a7-4b2c-a039-a54177cce9d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3187559274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3187559274
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3089752002
Short name T108
Test name
Test status
Simulation time 42564853362 ps
CPU time 1273.42 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 01:09:35 PM PDT 24
Peak memory 289376 kb
Host smart-b60f3cac-1959-49f7-a865-324f3950db50
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089752002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3089752002
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.424762596
Short name T316
Test name
Test status
Simulation time 8649454041 ps
CPU time 698.89 seconds
Started Mar 31 12:48:47 PM PDT 24
Finished Mar 31 01:00:26 PM PDT 24
Peak memory 265384 kb
Host smart-8bfb35e6-518d-4d91-a3b9-a0ae19338a03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424762596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.424762596
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1464048275
Short name T267
Test name
Test status
Simulation time 394314734339 ps
CPU time 5974.86 seconds
Started Mar 31 12:49:13 PM PDT 24
Finished Mar 31 02:28:49 PM PDT 24
Peak memory 339016 kb
Host smart-046e9fb7-39dd-4506-bc7b-478a51471d3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464048275 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1464048275
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2194282387
Short name T226
Test name
Test status
Simulation time 28076912329 ps
CPU time 1628.44 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 01:15:31 PM PDT 24
Peak memory 289016 kb
Host smart-9a3e8fb2-56a2-4b24-856b-b71b52248682
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194282387 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2194282387
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2881063390
Short name T299
Test name
Test status
Simulation time 52527748907 ps
CPU time 532.57 seconds
Started Mar 31 12:49:52 PM PDT 24
Finished Mar 31 12:58:45 PM PDT 24
Peak memory 247876 kb
Host smart-b3a28ab0-c5d1-4b93-bf36-6ff3a01b19ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881063390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2881063390
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.675716753
Short name T283
Test name
Test status
Simulation time 20775233884 ps
CPU time 1526.37 seconds
Started Mar 31 12:49:59 PM PDT 24
Finished Mar 31 01:15:25 PM PDT 24
Peak memory 273364 kb
Host smart-595de1d4-15f9-41a3-b248-fb1cf7514106
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675716753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.675716753
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.4064991236
Short name T238
Test name
Test status
Simulation time 138216468424 ps
CPU time 2425.61 seconds
Started Mar 31 12:50:03 PM PDT 24
Finished Mar 31 01:30:29 PM PDT 24
Peak memory 298168 kb
Host smart-c2de2f5e-db44-4102-a57f-c0fdd7b3ca34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064991236 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.4064991236
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4032126077
Short name T668
Test name
Test status
Simulation time 15012923264 ps
CPU time 660.17 seconds
Started Mar 31 12:50:07 PM PDT 24
Finished Mar 31 01:01:07 PM PDT 24
Peak memory 248108 kb
Host smart-ac32fcef-27df-43b0-bf14-ec5932168ff0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032126077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4032126077
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2460961990
Short name T239
Test name
Test status
Simulation time 43223253781 ps
CPU time 4345.86 seconds
Started Mar 31 12:50:03 PM PDT 24
Finished Mar 31 02:02:30 PM PDT 24
Peak memory 354924 kb
Host smart-13bda819-4d5a-440f-8ee3-e538b1e524c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460961990 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2460961990
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.374898097
Short name T262
Test name
Test status
Simulation time 2785029032 ps
CPU time 103.73 seconds
Started Mar 31 12:48:23 PM PDT 24
Finished Mar 31 12:50:07 PM PDT 24
Peak memory 256996 kb
Host smart-507c2458-abc0-4401-967d-3d32c592ad72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37489
8097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.374898097
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.4034698532
Short name T228
Test name
Test status
Simulation time 29399252588 ps
CPU time 1401.82 seconds
Started Mar 31 12:48:21 PM PDT 24
Finished Mar 31 01:11:43 PM PDT 24
Peak memory 289064 kb
Host smart-d42cbf8d-e0ec-4b05-933c-a33d0e3f7bde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034698532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.4034698532
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3449928631
Short name T29
Test name
Test status
Simulation time 422510121 ps
CPU time 13.24 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 12:48:35 PM PDT 24
Peak memory 269700 kb
Host smart-a1145916-398c-4d4d-9f09-0bdc39ec1477
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3449928631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3449928631
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2419474361
Short name T287
Test name
Test status
Simulation time 265813479 ps
CPU time 27.91 seconds
Started Mar 31 12:49:24 PM PDT 24
Finished Mar 31 12:49:53 PM PDT 24
Peak memory 254652 kb
Host smart-3f1785e3-1a39-474d-9939-e504e4c2b916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24194
74361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2419474361
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.4096380776
Short name T617
Test name
Test status
Simulation time 331347788 ps
CPU time 10.91 seconds
Started Mar 31 12:48:52 PM PDT 24
Finished Mar 31 12:49:03 PM PDT 24
Peak memory 252588 kb
Host smart-880571a9-912f-41cb-8922-c9dc73efa826
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096380776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.4096380776
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4094849170
Short name T156
Test name
Test status
Simulation time 4460829981 ps
CPU time 109.32 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:31:34 PM PDT 24
Peak memory 265096 kb
Host smart-c3786d1a-31db-45e6-9a2f-1a7618068db4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4094849170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.4094849170
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.855727368
Short name T173
Test name
Test status
Simulation time 4130809164 ps
CPU time 70.17 seconds
Started Mar 31 12:30:09 PM PDT 24
Finished Mar 31 12:31:19 PM PDT 24
Peak memory 246116 kb
Host smart-eea25d18-9f33-4e54-ae98-1454ca43ad25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=855727368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.855727368
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.320945001
Short name T134
Test name
Test status
Simulation time 1873979688 ps
CPU time 136.69 seconds
Started Mar 31 12:30:13 PM PDT 24
Finished Mar 31 12:32:30 PM PDT 24
Peak memory 256932 kb
Host smart-02089282-b46a-4055-ba59-05af4353c02b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=320945001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.320945001
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1144652913
Short name T165
Test name
Test status
Simulation time 102703369 ps
CPU time 2.61 seconds
Started Mar 31 12:30:11 PM PDT 24
Finished Mar 31 12:30:14 PM PDT 24
Peak memory 235752 kb
Host smart-28c3fd4d-5bf4-43a3-b381-18c9c5e1a4cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1144652913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1144652913
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2303936759
Short name T172
Test name
Test status
Simulation time 443493808 ps
CPU time 47.83 seconds
Started Mar 31 12:30:05 PM PDT 24
Finished Mar 31 12:30:53 PM PDT 24
Peak memory 245168 kb
Host smart-070007a4-f1b4-4d8a-acca-3d29f35b0643
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2303936759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2303936759
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2074019997
Short name T171
Test name
Test status
Simulation time 465335709 ps
CPU time 3.8 seconds
Started Mar 31 12:29:55 PM PDT 24
Finished Mar 31 12:29:59 PM PDT 24
Peak memory 237000 kb
Host smart-23f6325b-cfbf-43f0-8ccb-9f46a0a20bf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2074019997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2074019997
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3973634814
Short name T175
Test name
Test status
Simulation time 1209468282 ps
CPU time 40.74 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:30:21 PM PDT 24
Peak memory 236760 kb
Host smart-18627787-60ad-400d-b355-34ff416a6573
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3973634814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3973634814
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.4256546260
Short name T159
Test name
Test status
Simulation time 4456823854 ps
CPU time 309.01 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:34:53 PM PDT 24
Peak memory 265044 kb
Host smart-3be835e1-d7db-4926-88ee-4dfa53984769
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256546260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.4256546260
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.736275205
Short name T184
Test name
Test status
Simulation time 91700888 ps
CPU time 3.9 seconds
Started Mar 31 12:31:01 PM PDT 24
Finished Mar 31 12:31:05 PM PDT 24
Peak memory 236776 kb
Host smart-ea4ad348-e5f9-41d7-bfd2-ab639d94bb5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=736275205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.736275205
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1155463219
Short name T149
Test name
Test status
Simulation time 7239026069 ps
CPU time 139.58 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:32:16 PM PDT 24
Peak memory 256904 kb
Host smart-3128e35a-ddd3-4ef0-a099-8ec55d977346
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1155463219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1155463219
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1541422621
Short name T176
Test name
Test status
Simulation time 21155656 ps
CPU time 2.37 seconds
Started Mar 31 12:30:09 PM PDT 24
Finished Mar 31 12:30:11 PM PDT 24
Peak memory 236676 kb
Host smart-0eb7acad-0539-4923-983c-a64ef5986ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1541422621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1541422621
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.578157310
Short name T179
Test name
Test status
Simulation time 118862756 ps
CPU time 6.16 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:02 PM PDT 24
Peak memory 235824 kb
Host smart-4fb89b52-d4e1-4cca-8fb0-74314dfe66fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=578157310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.578157310
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3398777900
Short name T183
Test name
Test status
Simulation time 60960551 ps
CPU time 3.33 seconds
Started Mar 31 12:29:46 PM PDT 24
Finished Mar 31 12:29:50 PM PDT 24
Peak memory 236584 kb
Host smart-87d58954-4384-41f2-8ca1-5f5395545e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3398777900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3398777900
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1580240551
Short name T180
Test name
Test status
Simulation time 61485084 ps
CPU time 2.17 seconds
Started Mar 31 12:30:13 PM PDT 24
Finished Mar 31 12:30:15 PM PDT 24
Peak memory 235828 kb
Host smart-37f34e0d-57fa-4d1c-b828-033ac49cd412
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1580240551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1580240551
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.445024768
Short name T182
Test name
Test status
Simulation time 808861512 ps
CPU time 19.26 seconds
Started Mar 31 12:29:55 PM PDT 24
Finished Mar 31 12:30:14 PM PDT 24
Peak memory 236828 kb
Host smart-96bb5e12-1b3a-40fa-a20c-33136f8e86ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=445024768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.445024768
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.440754245
Short name T187
Test name
Test status
Simulation time 964452115 ps
CPU time 64.58 seconds
Started Mar 31 12:29:46 PM PDT 24
Finished Mar 31 12:30:51 PM PDT 24
Peak memory 239468 kb
Host smart-403eb910-0495-4cbf-b95d-91d0ede035a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=440754245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.440754245
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1442987437
Short name T188
Test name
Test status
Simulation time 214372146 ps
CPU time 4.36 seconds
Started Mar 31 12:30:36 PM PDT 24
Finished Mar 31 12:30:41 PM PDT 24
Peak memory 235756 kb
Host smart-d217d1b4-ad3f-4071-8604-547bfe2278d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1442987437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1442987437
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3433605233
Short name T177
Test name
Test status
Simulation time 93791344 ps
CPU time 5.1 seconds
Started Mar 31 12:29:45 PM PDT 24
Finished Mar 31 12:29:50 PM PDT 24
Peak memory 237204 kb
Host smart-053214da-d32a-4178-867d-0ec59c5509ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3433605233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3433605233
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1916671766
Short name T738
Test name
Test status
Simulation time 6871337237 ps
CPU time 112.45 seconds
Started Mar 31 12:29:39 PM PDT 24
Finished Mar 31 12:31:32 PM PDT 24
Peak memory 240256 kb
Host smart-f1d0510f-fdcb-4361-a50d-cd748e9433e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1916671766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1916671766
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2225951795
Short name T780
Test name
Test status
Simulation time 6805279010 ps
CPU time 169.04 seconds
Started Mar 31 12:30:57 PM PDT 24
Finished Mar 31 12:33:46 PM PDT 24
Peak memory 236448 kb
Host smart-076d6ce8-0038-45f6-8ebb-625efba61890
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2225951795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2225951795
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1761401254
Short name T785
Test name
Test status
Simulation time 39640362 ps
CPU time 5.84 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:29:50 PM PDT 24
Peak memory 240296 kb
Host smart-929a3f9b-5692-47e5-b5f1-ea11cf94c605
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1761401254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1761401254
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3532180932
Short name T816
Test name
Test status
Simulation time 112969611 ps
CPU time 4.68 seconds
Started Mar 31 12:31:14 PM PDT 24
Finished Mar 31 12:31:18 PM PDT 24
Peak memory 238780 kb
Host smart-b65c9244-d272-4792-b681-f81152617041
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532180932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3532180932
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1238524275
Short name T186
Test name
Test status
Simulation time 176233480 ps
CPU time 4.27 seconds
Started Mar 31 12:29:36 PM PDT 24
Finished Mar 31 12:29:40 PM PDT 24
Peak memory 235664 kb
Host smart-969fe0e6-799e-436c-bd5f-2346655488ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1238524275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1238524275
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2849931450
Short name T808
Test name
Test status
Simulation time 98721457 ps
CPU time 1.35 seconds
Started Mar 31 12:29:39 PM PDT 24
Finished Mar 31 12:29:41 PM PDT 24
Peak memory 236476 kb
Host smart-76134159-c141-4695-be7e-e371f6077bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2849931450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2849931450
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.621058683
Short name T788
Test name
Test status
Simulation time 88431286 ps
CPU time 12.22 seconds
Started Mar 31 12:30:56 PM PDT 24
Finished Mar 31 12:31:08 PM PDT 24
Peak memory 240136 kb
Host smart-b6b899e4-f896-4274-a495-2bdaba20a911
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=621058683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.621058683
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2956893874
Short name T772
Test name
Test status
Simulation time 150177515 ps
CPU time 9.66 seconds
Started Mar 31 12:31:13 PM PDT 24
Finished Mar 31 12:31:23 PM PDT 24
Peak memory 246336 kb
Host smart-ba287fb3-8159-4628-9f54-1cc3dbc250e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2956893874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2956893874
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2537155375
Short name T801
Test name
Test status
Simulation time 3973640381 ps
CPU time 243.06 seconds
Started Mar 31 12:29:42 PM PDT 24
Finished Mar 31 12:33:46 PM PDT 24
Peak memory 239072 kb
Host smart-c89ac692-6fdc-45c0-ac32-bc23a2b821b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2537155375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2537155375
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2785376879
Short name T804
Test name
Test status
Simulation time 2045914901 ps
CPU time 97.63 seconds
Started Mar 31 12:29:42 PM PDT 24
Finished Mar 31 12:31:20 PM PDT 24
Peak memory 236528 kb
Host smart-c7dba4f7-0252-44e7-9ad2-dd35852a039e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2785376879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2785376879
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1809063670
Short name T765
Test name
Test status
Simulation time 805821195 ps
CPU time 5.69 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:29:45 PM PDT 24
Peak memory 240192 kb
Host smart-4cc6dd73-d7e4-4bb9-a12d-7422244a75e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1809063670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1809063670
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3802119630
Short name T726
Test name
Test status
Simulation time 162283384 ps
CPU time 6.54 seconds
Started Mar 31 12:29:46 PM PDT 24
Finished Mar 31 12:29:53 PM PDT 24
Peak memory 239940 kb
Host smart-53daec94-714d-4821-a0e3-ab7c1599eb15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802119630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3802119630
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2850604345
Short name T732
Test name
Test status
Simulation time 28616842 ps
CPU time 3.61 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:29:44 PM PDT 24
Peak memory 236516 kb
Host smart-7cd2457c-9c96-424f-a03d-0bd54fc35f8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2850604345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2850604345
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3413379966
Short name T826
Test name
Test status
Simulation time 10972938 ps
CPU time 1.27 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:29:46 PM PDT 24
Peak memory 235736 kb
Host smart-8d3599a5-d49b-4f28-9836-ef6a4050429d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3413379966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3413379966
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.611492624
Short name T803
Test name
Test status
Simulation time 4956158049 ps
CPU time 17.81 seconds
Started Mar 31 12:29:42 PM PDT 24
Finished Mar 31 12:30:00 PM PDT 24
Peak memory 244764 kb
Host smart-de5cd9f5-87b2-416b-babe-a043e0088867
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=611492624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.611492624
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3340951267
Short name T153
Test name
Test status
Simulation time 4338644384 ps
CPU time 152.9 seconds
Started Mar 31 12:29:37 PM PDT 24
Finished Mar 31 12:32:10 PM PDT 24
Peak memory 266096 kb
Host smart-09a7a37f-f708-4b95-a3f3-5f568cde9f01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3340951267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3340951267
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2918415178
Short name T160
Test name
Test status
Simulation time 110175039857 ps
CPU time 957.11 seconds
Started Mar 31 12:29:43 PM PDT 24
Finished Mar 31 12:45:40 PM PDT 24
Peak memory 265152 kb
Host smart-25457ddd-abc9-46bd-aef3-7962f2b8c4d2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918415178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2918415178
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3883384246
Short name T820
Test name
Test status
Simulation time 246952138 ps
CPU time 8.51 seconds
Started Mar 31 12:29:39 PM PDT 24
Finished Mar 31 12:29:47 PM PDT 24
Peak memory 248488 kb
Host smart-9233b3ef-5aeb-40ec-86ec-aea18dc9d4b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3883384246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3883384246
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1826110795
Short name T794
Test name
Test status
Simulation time 314277347 ps
CPU time 7.48 seconds
Started Mar 31 12:29:55 PM PDT 24
Finished Mar 31 12:30:03 PM PDT 24
Peak memory 240144 kb
Host smart-8b5cdf15-990a-4122-a996-35fc16486f64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826110795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1826110795
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1365952184
Short name T774
Test name
Test status
Simulation time 91974926 ps
CPU time 4.75 seconds
Started Mar 31 12:29:58 PM PDT 24
Finished Mar 31 12:30:03 PM PDT 24
Peak memory 236528 kb
Host smart-23ec5781-f2a7-40e8-92e7-cbc44e17f28b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1365952184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1365952184
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3092633224
Short name T757
Test name
Test status
Simulation time 9129544 ps
CPU time 1.22 seconds
Started Mar 31 12:29:53 PM PDT 24
Finished Mar 31 12:29:54 PM PDT 24
Peak memory 234704 kb
Host smart-58ff4ec9-33b6-4d10-8ca7-b7df3ab392e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3092633224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3092633224
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3900881169
Short name T735
Test name
Test status
Simulation time 332455653 ps
CPU time 21.5 seconds
Started Mar 31 12:29:42 PM PDT 24
Finished Mar 31 12:30:04 PM PDT 24
Peak memory 240260 kb
Host smart-45a2e540-8d15-4914-b954-3922e9000e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3900881169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3900881169
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4081629191
Short name T347
Test name
Test status
Simulation time 8394545661 ps
CPU time 525.85 seconds
Started Mar 31 12:29:46 PM PDT 24
Finished Mar 31 12:38:32 PM PDT 24
Peak memory 269720 kb
Host smart-04856193-d5d5-4eca-a769-b97abcd1f48e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081629191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.4081629191
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3218376324
Short name T709
Test name
Test status
Simulation time 281916233 ps
CPU time 20.2 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:30:00 PM PDT 24
Peak memory 248436 kb
Host smart-b79bc3ac-0f78-4215-a1e2-d655bb5549a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3218376324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3218376324
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2730117715
Short name T227
Test name
Test status
Simulation time 138753206 ps
CPU time 5.29 seconds
Started Mar 31 12:29:53 PM PDT 24
Finished Mar 31 12:29:59 PM PDT 24
Peak memory 237680 kb
Host smart-772ad340-eb91-4684-9b4b-cb7ebc66ee53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730117715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2730117715
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.108542660
Short name T767
Test name
Test status
Simulation time 61198482 ps
CPU time 4.47 seconds
Started Mar 31 12:30:01 PM PDT 24
Finished Mar 31 12:30:05 PM PDT 24
Peak memory 235656 kb
Host smart-7d4bcb87-f797-4210-b0eb-288491e53d8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=108542660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.108542660
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3758408575
Short name T751
Test name
Test status
Simulation time 3460886228 ps
CPU time 17.78 seconds
Started Mar 31 12:29:54 PM PDT 24
Finished Mar 31 12:30:12 PM PDT 24
Peak memory 243956 kb
Host smart-88bb64b8-2cfc-4635-b0d0-ca66993b0184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3758408575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3758408575
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2973725312
Short name T142
Test name
Test status
Simulation time 1792591661 ps
CPU time 99.01 seconds
Started Mar 31 12:30:11 PM PDT 24
Finished Mar 31 12:31:50 PM PDT 24
Peak memory 265084 kb
Host smart-55ec0016-9117-4c31-9bcc-e3a30bab2e5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2973725312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2973725312
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2666892283
Short name T147
Test name
Test status
Simulation time 9324380982 ps
CPU time 324.3 seconds
Started Mar 31 12:29:43 PM PDT 24
Finished Mar 31 12:35:08 PM PDT 24
Peak memory 272748 kb
Host smart-15daf19e-3fa0-4f1f-affa-433c269b982e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666892283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2666892283
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2633377257
Short name T756
Test name
Test status
Simulation time 73803740 ps
CPU time 7.3 seconds
Started Mar 31 12:29:45 PM PDT 24
Finished Mar 31 12:29:52 PM PDT 24
Peak memory 248628 kb
Host smart-d4c6d109-474f-4232-b13b-419c9c1450c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2633377257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2633377257
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1829088483
Short name T744
Test name
Test status
Simulation time 57133603 ps
CPU time 4.71 seconds
Started Mar 31 12:29:51 PM PDT 24
Finished Mar 31 12:29:55 PM PDT 24
Peak memory 239524 kb
Host smart-f9070eaf-c365-4888-8f4e-450f00d979f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829088483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1829088483
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3975036183
Short name T809
Test name
Test status
Simulation time 44016148 ps
CPU time 3.22 seconds
Started Mar 31 12:29:42 PM PDT 24
Finished Mar 31 12:29:46 PM PDT 24
Peak memory 236532 kb
Host smart-f66ebdeb-0b81-4657-9eb5-2ca346046a46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3975036183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3975036183
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2538069501
Short name T762
Test name
Test status
Simulation time 51118285 ps
CPU time 1.39 seconds
Started Mar 31 12:29:46 PM PDT 24
Finished Mar 31 12:29:48 PM PDT 24
Peak memory 235736 kb
Host smart-ba547ce3-6932-4bc0-acbb-49111ff666d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2538069501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2538069501
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.479504823
Short name T193
Test name
Test status
Simulation time 252919348 ps
CPU time 17.02 seconds
Started Mar 31 12:29:47 PM PDT 24
Finished Mar 31 12:30:04 PM PDT 24
Peak memory 248464 kb
Host smart-9542a052-c7a1-48ef-ac8f-c45c1e31b67f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=479504823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.479504823
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2869390004
Short name T162
Test name
Test status
Simulation time 22310734443 ps
CPU time 620.46 seconds
Started Mar 31 12:29:46 PM PDT 24
Finished Mar 31 12:40:07 PM PDT 24
Peak memory 271976 kb
Host smart-1a22a8eb-49a7-48d8-8bbc-7e74a0cae0ca
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869390004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2869390004
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.880465836
Short name T734
Test name
Test status
Simulation time 131804549 ps
CPU time 7.85 seconds
Started Mar 31 12:30:16 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 248516 kb
Host smart-4f26ce95-2f13-41d5-817a-e7894471b84c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=880465836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.880465836
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.4132519978
Short name T166
Test name
Test status
Simulation time 2176504891 ps
CPU time 35.08 seconds
Started Mar 31 12:30:06 PM PDT 24
Finished Mar 31 12:30:41 PM PDT 24
Peak memory 236952 kb
Host smart-0eedcc17-ff2d-47c9-bbed-bb65948cffb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4132519978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.4132519978
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.4247167969
Short name T810
Test name
Test status
Simulation time 252381723 ps
CPU time 10.36 seconds
Started Mar 31 12:29:42 PM PDT 24
Finished Mar 31 12:29:52 PM PDT 24
Peak memory 256680 kb
Host smart-600fbe2e-5c0a-497a-8162-e6d1639e93db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247167969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.4247167969
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3115826478
Short name T235
Test name
Test status
Simulation time 65306254 ps
CPU time 4.99 seconds
Started Mar 31 12:29:42 PM PDT 24
Finished Mar 31 12:29:47 PM PDT 24
Peak memory 236624 kb
Host smart-43edf126-e189-4acb-9360-32904bbe7993
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3115826478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3115826478
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1278588661
Short name T341
Test name
Test status
Simulation time 25645886 ps
CPU time 1.58 seconds
Started Mar 31 12:29:45 PM PDT 24
Finished Mar 31 12:29:47 PM PDT 24
Peak memory 235732 kb
Host smart-cfe1dd92-15b7-40cf-96b3-0d52c1497b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1278588661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1278588661
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.593659315
Short name T739
Test name
Test status
Simulation time 90947718 ps
CPU time 11.92 seconds
Started Mar 31 12:30:12 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 244752 kb
Host smart-a480ca70-8f3a-4a2d-a551-03e6f48bb691
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=593659315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.593659315
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1739930375
Short name T138
Test name
Test status
Simulation time 7465910001 ps
CPU time 179.29 seconds
Started Mar 31 12:29:42 PM PDT 24
Finished Mar 31 12:32:42 PM PDT 24
Peak memory 265188 kb
Host smart-080d5290-27ee-44ff-afcb-eab85313d21e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1739930375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1739930375
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1822722896
Short name T789
Test name
Test status
Simulation time 255913845 ps
CPU time 18.51 seconds
Started Mar 31 12:30:09 PM PDT 24
Finished Mar 31 12:30:28 PM PDT 24
Peak memory 248596 kb
Host smart-3d9d57cf-28c4-424a-a230-f1ac26900236
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1822722896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1822722896
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3330381849
Short name T714
Test name
Test status
Simulation time 83543400 ps
CPU time 6.28 seconds
Started Mar 31 12:29:54 PM PDT 24
Finished Mar 31 12:30:01 PM PDT 24
Peak memory 239780 kb
Host smart-75cd0f1d-e968-4c08-9522-42f94a993aa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330381849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3330381849
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1325872406
Short name T749
Test name
Test status
Simulation time 562255619 ps
CPU time 4.62 seconds
Started Mar 31 12:30:05 PM PDT 24
Finished Mar 31 12:30:10 PM PDT 24
Peak memory 236524 kb
Host smart-709d05ad-c76c-475e-b8a1-759d8828a863
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1325872406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1325872406
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2679946823
Short name T753
Test name
Test status
Simulation time 33040943 ps
CPU time 2.52 seconds
Started Mar 31 12:30:18 PM PDT 24
Finished Mar 31 12:30:21 PM PDT 24
Peak memory 236600 kb
Host smart-f8f6d300-2f55-4190-8184-5968480782c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2679946823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2679946823
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.945187840
Short name T752
Test name
Test status
Simulation time 961838958 ps
CPU time 15.49 seconds
Started Mar 31 12:29:46 PM PDT 24
Finished Mar 31 12:30:02 PM PDT 24
Peak memory 248444 kb
Host smart-6a29d306-62a7-4d41-ad42-d1f193d9e822
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=945187840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.945187840
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.885244176
Short name T821
Test name
Test status
Simulation time 283880449 ps
CPU time 13.56 seconds
Started Mar 31 12:29:52 PM PDT 24
Finished Mar 31 12:30:06 PM PDT 24
Peak memory 252620 kb
Host smart-206b644d-c254-4b13-bf4c-5055544a3b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=885244176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.885244176
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2803598443
Short name T715
Test name
Test status
Simulation time 198604903 ps
CPU time 8.25 seconds
Started Mar 31 12:30:11 PM PDT 24
Finished Mar 31 12:30:20 PM PDT 24
Peak memory 239440 kb
Host smart-1dea0220-25e7-4087-9fa5-2af521fd5807
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803598443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2803598443
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3609676129
Short name T828
Test name
Test status
Simulation time 250163356 ps
CPU time 5.08 seconds
Started Mar 31 12:30:06 PM PDT 24
Finished Mar 31 12:30:11 PM PDT 24
Peak memory 236624 kb
Host smart-d308a204-7e92-4a08-bbf8-0493838fbe32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3609676129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3609676129
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1767192275
Short name T775
Test name
Test status
Simulation time 11780726 ps
CPU time 1.3 seconds
Started Mar 31 12:30:15 PM PDT 24
Finished Mar 31 12:30:16 PM PDT 24
Peak memory 236720 kb
Host smart-842d8054-a448-4c41-8bfc-ab33a13e8b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1767192275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1767192275
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1640414222
Short name T194
Test name
Test status
Simulation time 521109372 ps
CPU time 37.48 seconds
Started Mar 31 12:29:52 PM PDT 24
Finished Mar 31 12:30:29 PM PDT 24
Peak memory 248388 kb
Host smart-bc873d57-47fd-4245-8816-2c8027be0c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1640414222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1640414222
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1838704016
Short name T346
Test name
Test status
Simulation time 28373516975 ps
CPU time 408.89 seconds
Started Mar 31 12:30:14 PM PDT 24
Finished Mar 31 12:37:03 PM PDT 24
Peak memory 268416 kb
Host smart-6d514e88-ba58-4130-9dc3-8432404ea643
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838704016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1838704016
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1650144635
Short name T814
Test name
Test status
Simulation time 332966843 ps
CPU time 6.93 seconds
Started Mar 31 12:30:02 PM PDT 24
Finished Mar 31 12:30:09 PM PDT 24
Peak memory 248540 kb
Host smart-5f36ec7c-b166-44e9-a59d-565f783d984b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1650144635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1650144635
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3755461722
Short name T812
Test name
Test status
Simulation time 42201927 ps
CPU time 2.57 seconds
Started Mar 31 12:30:15 PM PDT 24
Finished Mar 31 12:30:18 PM PDT 24
Peak memory 236700 kb
Host smart-3907e033-eb60-41ce-a184-f365f2b49ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3755461722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3755461722
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3580816315
Short name T763
Test name
Test status
Simulation time 453969386 ps
CPU time 8.44 seconds
Started Mar 31 12:29:54 PM PDT 24
Finished Mar 31 12:30:03 PM PDT 24
Peak memory 239144 kb
Host smart-7a0a1f9c-11b9-4b8b-afa8-66302af0552a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580816315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3580816315
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.4027968324
Short name T791
Test name
Test status
Simulation time 1418486987 ps
CPU time 7.22 seconds
Started Mar 31 12:29:51 PM PDT 24
Finished Mar 31 12:29:58 PM PDT 24
Peak memory 240208 kb
Host smart-10104a1e-37a7-482b-ab0e-95f8c2ff6cd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4027968324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.4027968324
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3841298496
Short name T813
Test name
Test status
Simulation time 11277220 ps
CPU time 1.35 seconds
Started Mar 31 12:30:07 PM PDT 24
Finished Mar 31 12:30:08 PM PDT 24
Peak memory 236704 kb
Host smart-148479e9-1763-4a46-bf39-1545a1cc9775
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3841298496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3841298496
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2186073092
Short name T190
Test name
Test status
Simulation time 343489598 ps
CPU time 11.72 seconds
Started Mar 31 12:29:55 PM PDT 24
Finished Mar 31 12:30:06 PM PDT 24
Peak memory 244800 kb
Host smart-e374fd4b-268b-4fc8-bde0-2dbd9ba9a4fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2186073092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2186073092
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3109535080
Short name T155
Test name
Test status
Simulation time 808253873 ps
CPU time 100.94 seconds
Started Mar 31 12:29:54 PM PDT 24
Finished Mar 31 12:31:35 PM PDT 24
Peak memory 265032 kb
Host smart-6e4cc4fb-d64f-4aa9-98a0-cdd9fdb2233b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3109535080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3109535080
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1743171030
Short name T151
Test name
Test status
Simulation time 24395618625 ps
CPU time 862.24 seconds
Started Mar 31 12:29:54 PM PDT 24
Finished Mar 31 12:44:17 PM PDT 24
Peak memory 265244 kb
Host smart-f70c5fd2-eb05-4305-8a08-bb81b30f82db
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743171030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1743171030
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.388631614
Short name T723
Test name
Test status
Simulation time 333644358 ps
CPU time 11.41 seconds
Started Mar 31 12:30:11 PM PDT 24
Finished Mar 31 12:30:23 PM PDT 24
Peak memory 252904 kb
Host smart-29bba4c0-485b-48ac-9cc4-2d450d1ec2e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=388631614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.388631614
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.390304012
Short name T724
Test name
Test status
Simulation time 280488760 ps
CPU time 5.23 seconds
Started Mar 31 12:29:52 PM PDT 24
Finished Mar 31 12:29:57 PM PDT 24
Peak memory 240332 kb
Host smart-56142e6f-dc92-4d37-8897-d5023dfdce50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390304012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.390304012
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.469379379
Short name T761
Test name
Test status
Simulation time 19857581 ps
CPU time 3.36 seconds
Started Mar 31 12:30:11 PM PDT 24
Finished Mar 31 12:30:14 PM PDT 24
Peak memory 240152 kb
Host smart-b55d93e1-6362-4f0d-9954-3d6e66487927
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=469379379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.469379379
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.522124135
Short name T797
Test name
Test status
Simulation time 353234781 ps
CPU time 22.44 seconds
Started Mar 31 12:30:14 PM PDT 24
Finished Mar 31 12:30:37 PM PDT 24
Peak memory 244896 kb
Host smart-0000313e-bca3-4641-b839-d6f7dde0f2c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=522124135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.522124135
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2429167662
Short name T776
Test name
Test status
Simulation time 291322558 ps
CPU time 9.42 seconds
Started Mar 31 12:29:54 PM PDT 24
Finished Mar 31 12:30:04 PM PDT 24
Peak memory 248056 kb
Host smart-6cb2eee4-76ae-4f3b-ae71-23bfb55cd5da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2429167662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2429167662
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2706847674
Short name T344
Test name
Test status
Simulation time 266530837 ps
CPU time 12 seconds
Started Mar 31 12:29:55 PM PDT 24
Finished Mar 31 12:30:07 PM PDT 24
Peak memory 251632 kb
Host smart-b8a551e8-8588-41b9-97e0-1b1d3bd2c946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706847674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2706847674
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.862894619
Short name T758
Test name
Test status
Simulation time 648180738 ps
CPU time 5.31 seconds
Started Mar 31 12:29:54 PM PDT 24
Finished Mar 31 12:30:00 PM PDT 24
Peak memory 240104 kb
Host smart-9f0bb211-ad1a-4aad-b6ff-acc6dd9639ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=862894619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.862894619
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2091232856
Short name T722
Test name
Test status
Simulation time 6290700 ps
CPU time 1.4 seconds
Started Mar 31 12:29:52 PM PDT 24
Finished Mar 31 12:29:54 PM PDT 24
Peak memory 236580 kb
Host smart-c1e4d6bf-d0eb-4a4b-9d02-07728740b1f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2091232856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2091232856
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2715370821
Short name T800
Test name
Test status
Simulation time 673655406 ps
CPU time 37.18 seconds
Started Mar 31 12:29:55 PM PDT 24
Finished Mar 31 12:30:32 PM PDT 24
Peak memory 248428 kb
Host smart-b6fd8790-a2a5-4cb7-ad79-4782e453eff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2715370821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2715370821
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3961876017
Short name T830
Test name
Test status
Simulation time 2310508415 ps
CPU time 131.69 seconds
Started Mar 31 12:30:12 PM PDT 24
Finished Mar 31 12:32:24 PM PDT 24
Peak memory 256848 kb
Host smart-cc6aaf2f-d670-42eb-9a79-6193539e4d04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3961876017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3961876017
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3889432560
Short name T716
Test name
Test status
Simulation time 106191924 ps
CPU time 11.78 seconds
Started Mar 31 12:30:20 PM PDT 24
Finished Mar 31 12:30:32 PM PDT 24
Peak memory 254108 kb
Host smart-ec694a58-0d04-4757-a62e-31c230bfe3e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3889432560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3889432560
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.557031247
Short name T773
Test name
Test status
Simulation time 97876660 ps
CPU time 7.48 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:03 PM PDT 24
Peak memory 252264 kb
Host smart-cfa8824e-3757-4382-8324-908b3b188395
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557031247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.557031247
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2472083342
Short name T815
Test name
Test status
Simulation time 118785688 ps
CPU time 4.93 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:02 PM PDT 24
Peak memory 240208 kb
Host smart-234aed85-d32d-4d3c-bc7d-4ef80f0ea72b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2472083342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2472083342
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1164964714
Short name T725
Test name
Test status
Simulation time 36856714 ps
CPU time 1.3 seconds
Started Mar 31 12:29:57 PM PDT 24
Finished Mar 31 12:29:58 PM PDT 24
Peak memory 236692 kb
Host smart-ad290dd2-e5fc-4249-8b01-b44aff91b842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1164964714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1164964714
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2745709460
Short name T736
Test name
Test status
Simulation time 495944113 ps
CPU time 33.35 seconds
Started Mar 31 12:30:07 PM PDT 24
Finished Mar 31 12:30:41 PM PDT 24
Peak memory 248496 kb
Host smart-8dc95a54-3af6-45bc-97dd-f7c9047ec320
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2745709460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2745709460
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.787928273
Short name T764
Test name
Test status
Simulation time 622332617 ps
CPU time 23.4 seconds
Started Mar 31 12:30:06 PM PDT 24
Finished Mar 31 12:30:29 PM PDT 24
Peak memory 254152 kb
Host smart-8945d5b0-3f7d-4303-9c31-c6eac641eb73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=787928273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.787928273
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.453773332
Short name T748
Test name
Test status
Simulation time 54227950665 ps
CPU time 293.87 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:34:34 PM PDT 24
Peak memory 239280 kb
Host smart-e1bdfe4a-5879-4667-b287-760515d94973
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=453773332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.453773332
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2848201592
Short name T727
Test name
Test status
Simulation time 3385828128 ps
CPU time 189.07 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:32:50 PM PDT 24
Peak memory 240264 kb
Host smart-343e9446-e974-4a57-92c6-ce5c0798f613
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2848201592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2848201592
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.4260004548
Short name T719
Test name
Test status
Simulation time 195466171 ps
CPU time 8.74 seconds
Started Mar 31 12:29:38 PM PDT 24
Finished Mar 31 12:29:47 PM PDT 24
Peak memory 240128 kb
Host smart-f92c6521-8d42-4828-8193-62bbfee6821d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4260004548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.4260004548
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.4251966471
Short name T793
Test name
Test status
Simulation time 772671093 ps
CPU time 5.45 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:29:50 PM PDT 24
Peak memory 239732 kb
Host smart-20643bae-cd64-4b25-bd11-ac86eb467154
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251966471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.4251966471
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3422265315
Short name T192
Test name
Test status
Simulation time 121522521 ps
CPU time 5.73 seconds
Started Mar 31 12:31:01 PM PDT 24
Finished Mar 31 12:31:07 PM PDT 24
Peak memory 236380 kb
Host smart-6a28d078-dfa0-4d9e-9124-7dd0875d220c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3422265315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3422265315
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1530911403
Short name T170
Test name
Test status
Simulation time 7486385 ps
CPU time 1.4 seconds
Started Mar 31 12:29:46 PM PDT 24
Finished Mar 31 12:29:48 PM PDT 24
Peak memory 236620 kb
Host smart-d40301ac-8f21-4d25-bad4-561a8bce94ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1530911403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1530911403
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.488117201
Short name T786
Test name
Test status
Simulation time 460906500 ps
CPU time 19.94 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:30:00 PM PDT 24
Peak memory 243860 kb
Host smart-34d5ceaa-df1e-4bc1-a075-9c7756dcedc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=488117201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.488117201
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2950678888
Short name T148
Test name
Test status
Simulation time 8870682764 ps
CPU time 90.6 seconds
Started Mar 31 12:31:09 PM PDT 24
Finished Mar 31 12:32:40 PM PDT 24
Peak memory 264948 kb
Host smart-d53dfaff-97a6-4787-921e-2031dd97b4c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2950678888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2950678888
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2132235009
Short name T827
Test name
Test status
Simulation time 2308193178 ps
CPU time 316.65 seconds
Started Mar 31 12:29:33 PM PDT 24
Finished Mar 31 12:34:50 PM PDT 24
Peak memory 265132 kb
Host smart-fbc70c08-9514-4abe-9e96-d78521149a3c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132235009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2132235009
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2852223618
Short name T783
Test name
Test status
Simulation time 32115834 ps
CPU time 4.4 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:29:45 PM PDT 24
Peak memory 248132 kb
Host smart-537925ad-c427-4d74-bb31-fdc2488c2950
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2852223618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2852223618
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3544613212
Short name T338
Test name
Test status
Simulation time 7850373 ps
CPU time 1.34 seconds
Started Mar 31 12:30:06 PM PDT 24
Finished Mar 31 12:30:07 PM PDT 24
Peak memory 236584 kb
Host smart-f23f6df0-b8e0-4899-aa22-775bffd5536d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3544613212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3544613212
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4001506572
Short name T798
Test name
Test status
Simulation time 8437245 ps
CPU time 1.34 seconds
Started Mar 31 12:29:57 PM PDT 24
Finished Mar 31 12:29:58 PM PDT 24
Peak memory 235748 kb
Host smart-2ce4fdf6-e9f6-4cd7-947e-a39e105f7c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4001506572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.4001506572
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3551409407
Short name T340
Test name
Test status
Simulation time 12233736 ps
CPU time 1.35 seconds
Started Mar 31 12:30:09 PM PDT 24
Finished Mar 31 12:30:11 PM PDT 24
Peak memory 236716 kb
Host smart-a2a8ec77-08ca-4d90-964c-8526fe398108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3551409407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3551409407
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2238778606
Short name T805
Test name
Test status
Simulation time 37463668 ps
CPU time 1.36 seconds
Started Mar 31 12:29:57 PM PDT 24
Finished Mar 31 12:29:58 PM PDT 24
Peak memory 236476 kb
Host smart-c919c923-e730-49bc-977a-c67ae171589d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2238778606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2238778606
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2546712335
Short name T717
Test name
Test status
Simulation time 11732273 ps
CPU time 1.3 seconds
Started Mar 31 12:31:03 PM PDT 24
Finished Mar 31 12:31:04 PM PDT 24
Peak memory 235768 kb
Host smart-a9603cc0-4b01-4e59-af37-0716127af27b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2546712335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2546712335
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1670027568
Short name T778
Test name
Test status
Simulation time 9913843 ps
CPU time 1.37 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:29:58 PM PDT 24
Peak memory 236608 kb
Host smart-adb7904a-1a44-4fc3-a498-f1e01cc368cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1670027568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1670027568
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1708027562
Short name T730
Test name
Test status
Simulation time 6819241 ps
CPU time 1.43 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:31:24 PM PDT 24
Peak memory 235608 kb
Host smart-70028d11-3bdd-466c-a8fe-f8ae2f858c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1708027562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1708027562
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2015344364
Short name T728
Test name
Test status
Simulation time 18606891 ps
CPU time 1.86 seconds
Started Mar 31 12:29:57 PM PDT 24
Finished Mar 31 12:29:59 PM PDT 24
Peak memory 235584 kb
Host smart-9d3b785e-3a64-42e1-8096-644de5a53135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2015344364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2015344364
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1176764002
Short name T759
Test name
Test status
Simulation time 9270129 ps
CPU time 1.41 seconds
Started Mar 31 12:30:09 PM PDT 24
Finished Mar 31 12:30:16 PM PDT 24
Peak memory 235712 kb
Host smart-7cce8c4c-954d-4968-a5a7-7e53e46c7e5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1176764002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1176764002
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4002403998
Short name T771
Test name
Test status
Simulation time 9876776 ps
CPU time 1.58 seconds
Started Mar 31 12:29:57 PM PDT 24
Finished Mar 31 12:29:59 PM PDT 24
Peak memory 235752 kb
Host smart-4e025786-c828-4fde-be2d-5e4ca2ce1f5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4002403998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.4002403998
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3340276447
Short name T790
Test name
Test status
Simulation time 4731448076 ps
CPU time 143.59 seconds
Started Mar 31 12:29:43 PM PDT 24
Finished Mar 31 12:32:06 PM PDT 24
Peak memory 236620 kb
Host smart-3f811c6e-1502-4cef-960c-c76fbed4310a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3340276447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3340276447
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1784037325
Short name T742
Test name
Test status
Simulation time 23675767035 ps
CPU time 179.53 seconds
Started Mar 31 12:29:47 PM PDT 24
Finished Mar 31 12:32:47 PM PDT 24
Peak memory 240276 kb
Host smart-61e18d35-9ea9-41f9-a91e-877c855125b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1784037325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1784037325
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4054347933
Short name T191
Test name
Test status
Simulation time 141483385 ps
CPU time 5.87 seconds
Started Mar 31 12:29:41 PM PDT 24
Finished Mar 31 12:29:47 PM PDT 24
Peak memory 240268 kb
Host smart-803c1e91-6d60-4e00-8c83-6c0a6ec529f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4054347933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.4054347933
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2286765699
Short name T343
Test name
Test status
Simulation time 201690050 ps
CPU time 5.1 seconds
Started Mar 31 12:29:47 PM PDT 24
Finished Mar 31 12:29:52 PM PDT 24
Peak memory 256804 kb
Host smart-5fb750f0-6404-4371-9b15-3a270f32cb89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286765699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2286765699
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3927051179
Short name T233
Test name
Test status
Simulation time 61210802 ps
CPU time 4.9 seconds
Started Mar 31 12:29:41 PM PDT 24
Finished Mar 31 12:29:47 PM PDT 24
Peak memory 239396 kb
Host smart-49725473-b2dd-4dad-92f9-03eba248225c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3927051179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3927051179
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1413230185
Short name T766
Test name
Test status
Simulation time 8452812 ps
CPU time 1.45 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:29:45 PM PDT 24
Peak memory 234664 kb
Host smart-8a0085af-c518-435a-88d8-8ad5cf8fa389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1413230185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1413230185
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2502831087
Short name T746
Test name
Test status
Simulation time 178615541 ps
CPU time 11.64 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:29:55 PM PDT 24
Peak memory 240364 kb
Host smart-5b5e63a6-f341-40bf-b705-f1649551b8bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2502831087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2502831087
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1865264114
Short name T158
Test name
Test status
Simulation time 2490177677 ps
CPU time 325.35 seconds
Started Mar 31 12:29:52 PM PDT 24
Finished Mar 31 12:35:17 PM PDT 24
Peak memory 265184 kb
Host smart-ef53fb3b-9a02-4474-880f-4dfd62b9cec1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865264114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1865264114
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1063340391
Short name T711
Test name
Test status
Simulation time 179634980 ps
CPU time 6.77 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:29:51 PM PDT 24
Peak memory 248420 kb
Host smart-5ec99b5c-863f-4021-afa6-0a17d5ab9010
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1063340391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1063340391
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2255018664
Short name T731
Test name
Test status
Simulation time 19469300 ps
CPU time 1.4 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:29:58 PM PDT 24
Peak memory 236572 kb
Host smart-04ff79d9-e581-4411-8329-f16efc9197b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2255018664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2255018664
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1638783232
Short name T770
Test name
Test status
Simulation time 9809580 ps
CPU time 1.5 seconds
Started Mar 31 12:29:59 PM PDT 24
Finished Mar 31 12:30:01 PM PDT 24
Peak memory 235748 kb
Host smart-1e1c5488-0ac0-4131-a95b-7063a0dedaad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1638783232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1638783232
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2653813244
Short name T811
Test name
Test status
Simulation time 20169945 ps
CPU time 1.46 seconds
Started Mar 31 12:30:03 PM PDT 24
Finished Mar 31 12:30:05 PM PDT 24
Peak memory 236624 kb
Host smart-17f43656-5746-4b56-9bb3-1c5695346111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2653813244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2653813244
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3933978206
Short name T806
Test name
Test status
Simulation time 22648259 ps
CPU time 1.31 seconds
Started Mar 31 12:30:09 PM PDT 24
Finished Mar 31 12:30:10 PM PDT 24
Peak memory 234740 kb
Host smart-7291ddda-a1a1-4df3-84bf-9c2bbb717792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3933978206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3933978206
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.487280850
Short name T796
Test name
Test status
Simulation time 28075078 ps
CPU time 1.27 seconds
Started Mar 31 12:30:13 PM PDT 24
Finished Mar 31 12:30:14 PM PDT 24
Peak memory 236708 kb
Host smart-67aa9986-71c6-4795-92a5-55636bb159c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=487280850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.487280850
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.620175047
Short name T169
Test name
Test status
Simulation time 10907836 ps
CPU time 1.62 seconds
Started Mar 31 12:29:58 PM PDT 24
Finished Mar 31 12:30:00 PM PDT 24
Peak memory 235824 kb
Host smart-9b2a03a6-9911-410f-b2ae-c193a163d1bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=620175047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.620175047
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.4172531740
Short name T168
Test name
Test status
Simulation time 24118479 ps
CPU time 1.41 seconds
Started Mar 31 12:29:58 PM PDT 24
Finished Mar 31 12:30:01 PM PDT 24
Peak memory 235748 kb
Host smart-305859de-6492-4233-b963-049fc7d16eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4172531740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.4172531740
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2933948075
Short name T741
Test name
Test status
Simulation time 10396748 ps
CPU time 1.66 seconds
Started Mar 31 12:30:03 PM PDT 24
Finished Mar 31 12:30:05 PM PDT 24
Peak memory 235728 kb
Host smart-3581430b-4e25-4e70-9b37-c8f4d34a4517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2933948075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2933948075
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1129917055
Short name T710
Test name
Test status
Simulation time 9126070 ps
CPU time 1.29 seconds
Started Mar 31 12:30:18 PM PDT 24
Finished Mar 31 12:30:20 PM PDT 24
Peak memory 236712 kb
Host smart-b2c6adee-e945-4f87-a5db-6f2a98a31097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1129917055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1129917055
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2322186059
Short name T802
Test name
Test status
Simulation time 6729960 ps
CPU time 1.52 seconds
Started Mar 31 12:30:03 PM PDT 24
Finished Mar 31 12:30:05 PM PDT 24
Peak memory 236596 kb
Host smart-90b75597-8d19-4114-ac52-cefa64dad03f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2322186059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2322186059
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.434838604
Short name T740
Test name
Test status
Simulation time 1108565085 ps
CPU time 58.79 seconds
Started Mar 31 12:29:38 PM PDT 24
Finished Mar 31 12:30:37 PM PDT 24
Peak memory 240112 kb
Host smart-9a60ea14-7071-4b6d-a1ff-6c5c0c484e1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=434838604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.434838604
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4048635121
Short name T829
Test name
Test status
Simulation time 4446386866 ps
CPU time 239.08 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:33:39 PM PDT 24
Peak memory 236596 kb
Host smart-24c3ff1c-5e78-4e24-b36d-f228fcdd5cb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4048635121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.4048635121
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2948774525
Short name T787
Test name
Test status
Simulation time 41220296 ps
CPU time 3.57 seconds
Started Mar 31 12:29:37 PM PDT 24
Finished Mar 31 12:29:41 PM PDT 24
Peak memory 240192 kb
Host smart-b1a15e6d-4da0-45f6-a353-af9ae5b32483
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2948774525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2948774525
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.62908615
Short name T348
Test name
Test status
Simulation time 32050180 ps
CPU time 5.19 seconds
Started Mar 31 12:29:42 PM PDT 24
Finished Mar 31 12:29:47 PM PDT 24
Peak memory 241392 kb
Host smart-c19ed461-5219-474a-b5bc-340397a9e110
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62908615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.alert_handler_csr_mem_rw_with_rand_reset.62908615
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3130410245
Short name T185
Test name
Test status
Simulation time 69426194 ps
CPU time 5.46 seconds
Started Mar 31 12:29:45 PM PDT 24
Finished Mar 31 12:29:50 PM PDT 24
Peak memory 236528 kb
Host smart-d37b701f-6f99-4a5e-8965-ab42d1e4817c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3130410245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3130410245
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.536758045
Short name T339
Test name
Test status
Simulation time 10614458 ps
CPU time 1.35 seconds
Started Mar 31 12:29:43 PM PDT 24
Finished Mar 31 12:29:44 PM PDT 24
Peak memory 235812 kb
Host smart-8e721163-4eff-4fb6-b4d6-d58db7ac469e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=536758045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.536758045
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1470056194
Short name T792
Test name
Test status
Simulation time 701542315 ps
CPU time 40.97 seconds
Started Mar 31 12:29:43 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 244756 kb
Host smart-be6fbec9-0cdf-4e67-b90a-ff064ba0f91f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1470056194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1470056194
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1924792431
Short name T139
Test name
Test status
Simulation time 4559008521 ps
CPU time 262.32 seconds
Started Mar 31 12:29:37 PM PDT 24
Finished Mar 31 12:34:00 PM PDT 24
Peak memory 265032 kb
Host smart-e57b5bd1-37d0-4ab4-9305-036b49e725a8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924792431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1924792431
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1455934852
Short name T807
Test name
Test status
Simulation time 345099734 ps
CPU time 10.67 seconds
Started Mar 31 12:30:01 PM PDT 24
Finished Mar 31 12:30:12 PM PDT 24
Peak memory 248404 kb
Host smart-a5652cba-406e-4387-842b-674af5629c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1455934852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1455934852
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3544417149
Short name T784
Test name
Test status
Simulation time 6776239 ps
CPU time 1.41 seconds
Started Mar 31 12:29:58 PM PDT 24
Finished Mar 31 12:30:00 PM PDT 24
Peak memory 236608 kb
Host smart-aa55c6f6-9562-4aae-84d8-299d7fa7784a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3544417149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3544417149
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.896847094
Short name T769
Test name
Test status
Simulation time 7575754 ps
CPU time 1.42 seconds
Started Mar 31 12:30:14 PM PDT 24
Finished Mar 31 12:30:16 PM PDT 24
Peak memory 236616 kb
Host smart-4500e7b2-c82d-4a3f-bf46-57c05d251bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=896847094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.896847094
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.500793031
Short name T342
Test name
Test status
Simulation time 8260805 ps
CPU time 1.42 seconds
Started Mar 31 12:30:03 PM PDT 24
Finished Mar 31 12:30:04 PM PDT 24
Peak memory 236624 kb
Host smart-6acf1843-fd75-43d1-8f4c-69c695b1929e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=500793031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.500793031
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3301765201
Short name T819
Test name
Test status
Simulation time 12057828 ps
CPU time 1.26 seconds
Started Mar 31 12:29:59 PM PDT 24
Finished Mar 31 12:30:00 PM PDT 24
Peak memory 235816 kb
Host smart-784adfd6-8373-4d7c-923f-7c44bf257431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3301765201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3301765201
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3066295478
Short name T777
Test name
Test status
Simulation time 11895140 ps
CPU time 1.48 seconds
Started Mar 31 12:30:03 PM PDT 24
Finished Mar 31 12:30:05 PM PDT 24
Peak memory 236624 kb
Host smart-23ab7aee-9ba8-45c4-b26f-c606c8d8b4dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3066295478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3066295478
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2562147705
Short name T824
Test name
Test status
Simulation time 18993933 ps
CPU time 1.4 seconds
Started Mar 31 12:31:23 PM PDT 24
Finished Mar 31 12:31:24 PM PDT 24
Peak memory 235608 kb
Host smart-8cb2d947-e545-4599-88c0-e5b7733f9d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2562147705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2562147705
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.906016661
Short name T818
Test name
Test status
Simulation time 10631367 ps
CPU time 1.55 seconds
Started Mar 31 12:30:11 PM PDT 24
Finished Mar 31 12:30:13 PM PDT 24
Peak memory 236704 kb
Host smart-767426f7-77d8-4e52-b8fd-875d8a41becc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=906016661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.906016661
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1878515223
Short name T750
Test name
Test status
Simulation time 7394104 ps
CPU time 1.47 seconds
Started Mar 31 12:30:10 PM PDT 24
Finished Mar 31 12:30:11 PM PDT 24
Peak memory 236564 kb
Host smart-27680d16-95e4-4db3-8e42-5a89c0b8e412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1878515223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1878515223
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.680283006
Short name T737
Test name
Test status
Simulation time 10295351 ps
CPU time 1.61 seconds
Started Mar 31 12:30:07 PM PDT 24
Finished Mar 31 12:30:09 PM PDT 24
Peak memory 236708 kb
Host smart-cba17177-142c-44d3-b6aa-ba065d0123bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=680283006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.680283006
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1281331084
Short name T825
Test name
Test status
Simulation time 11640249 ps
CPU time 1.26 seconds
Started Mar 31 12:30:17 PM PDT 24
Finished Mar 31 12:30:18 PM PDT 24
Peak memory 236712 kb
Host smart-8b569cb3-7e9c-432d-aba1-b69f1e349558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1281331084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1281331084
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3645346715
Short name T823
Test name
Test status
Simulation time 32029122 ps
CPU time 5.38 seconds
Started Mar 31 12:29:45 PM PDT 24
Finished Mar 31 12:29:50 PM PDT 24
Peak memory 241140 kb
Host smart-3d3efc9a-f594-48bf-87b2-4bdc65b850bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645346715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3645346715
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3003581432
Short name T720
Test name
Test status
Simulation time 362459847 ps
CPU time 7.29 seconds
Started Mar 31 12:29:48 PM PDT 24
Finished Mar 31 12:29:56 PM PDT 24
Peak memory 235740 kb
Host smart-9c3e4e1d-17fa-4ce8-8c36-c60a18d489ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3003581432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3003581432
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4136515003
Short name T733
Test name
Test status
Simulation time 710254960 ps
CPU time 23.1 seconds
Started Mar 31 12:29:37 PM PDT 24
Finished Mar 31 12:30:00 PM PDT 24
Peak memory 244764 kb
Host smart-88e9c6f9-37cb-4be8-98d3-d9814a056efd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4136515003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.4136515003
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3856219662
Short name T145
Test name
Test status
Simulation time 9231854252 ps
CPU time 141.27 seconds
Started Mar 31 12:29:41 PM PDT 24
Finished Mar 31 12:32:02 PM PDT 24
Peak memory 265100 kb
Host smart-58e7e28c-3f68-45bf-b22d-22e5530c5dd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3856219662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3856219662
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1879702063
Short name T164
Test name
Test status
Simulation time 81957474191 ps
CPU time 893.94 seconds
Started Mar 31 12:29:39 PM PDT 24
Finished Mar 31 12:44:33 PM PDT 24
Peak memory 272528 kb
Host smart-25f6b162-ad5e-447c-9e9a-d2053405da06
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879702063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1879702063
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2509840560
Short name T712
Test name
Test status
Simulation time 730291926 ps
CPU time 12.17 seconds
Started Mar 31 12:29:41 PM PDT 24
Finished Mar 31 12:29:54 PM PDT 24
Peak memory 248552 kb
Host smart-310b37de-a6b9-4639-890c-b8b2d2b9889e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2509840560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2509840560
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1777993085
Short name T779
Test name
Test status
Simulation time 162824738 ps
CPU time 5.65 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:29:45 PM PDT 24
Peak memory 256612 kb
Host smart-816234ac-6532-4a4a-9541-9d63164209f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777993085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1777993085
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2894433362
Short name T768
Test name
Test status
Simulation time 266015798 ps
CPU time 4.59 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:29:48 PM PDT 24
Peak memory 235696 kb
Host smart-869b1e3b-cfe3-4467-a620-f8ab2dd62de0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2894433362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2894433362
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1749027656
Short name T831
Test name
Test status
Simulation time 8023825 ps
CPU time 1.28 seconds
Started Mar 31 12:29:46 PM PDT 24
Finished Mar 31 12:29:48 PM PDT 24
Peak memory 234816 kb
Host smart-483ba8cb-08ea-4e5c-a589-ee872ea16873
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1749027656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1749027656
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3015105778
Short name T817
Test name
Test status
Simulation time 248227057 ps
CPU time 12.99 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:29:53 PM PDT 24
Peak memory 244756 kb
Host smart-25f3f690-9486-497d-8ee9-d81244d04922
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3015105778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3015105778
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2200342015
Short name T782
Test name
Test status
Simulation time 441962881 ps
CPU time 12.83 seconds
Started Mar 31 12:29:53 PM PDT 24
Finished Mar 31 12:30:06 PM PDT 24
Peak memory 248504 kb
Host smart-dcb80d6c-cb2d-46eb-bcac-19dc587c4957
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2200342015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2200342015
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2299178931
Short name T747
Test name
Test status
Simulation time 287412719 ps
CPU time 7.12 seconds
Started Mar 31 12:29:39 PM PDT 24
Finished Mar 31 12:29:46 PM PDT 24
Peak memory 240248 kb
Host smart-dea0accb-8fff-467f-919f-d2b27a27ac79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299178931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2299178931
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.273207218
Short name T729
Test name
Test status
Simulation time 127977118 ps
CPU time 8.9 seconds
Started Mar 31 12:29:45 PM PDT 24
Finished Mar 31 12:29:54 PM PDT 24
Peak memory 236580 kb
Host smart-3b95bc5d-61f2-4ae9-b118-bf1879971b41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=273207218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.273207218
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2715009951
Short name T755
Test name
Test status
Simulation time 8056995 ps
CPU time 1.3 seconds
Started Mar 31 12:29:45 PM PDT 24
Finished Mar 31 12:29:46 PM PDT 24
Peak memory 234700 kb
Host smart-a2b19b18-35ff-400b-8b5b-3fb479b136b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2715009951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2715009951
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2606077788
Short name T822
Test name
Test status
Simulation time 2444348706 ps
CPU time 32.76 seconds
Started Mar 31 12:31:09 PM PDT 24
Finished Mar 31 12:31:42 PM PDT 24
Peak memory 248404 kb
Host smart-d6024e48-1422-4556-b282-2ae836931dc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2606077788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2606077788
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2221955062
Short name T135
Test name
Test status
Simulation time 18037188522 ps
CPU time 272.87 seconds
Started Mar 31 12:29:51 PM PDT 24
Finished Mar 31 12:34:24 PM PDT 24
Peak memory 272820 kb
Host smart-31bda86d-0a4e-4216-8575-f670c1b66107
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2221955062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2221955062
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2922004949
Short name T132
Test name
Test status
Simulation time 12135494533 ps
CPU time 477.99 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:37:38 PM PDT 24
Peak memory 267524 kb
Host smart-dbb4e035-00e3-4520-aa8d-d5a53d5e9e5d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922004949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2922004949
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2842650718
Short name T713
Test name
Test status
Simulation time 481824190 ps
CPU time 19.73 seconds
Started Mar 31 12:30:05 PM PDT 24
Finished Mar 31 12:30:25 PM PDT 24
Peak memory 248548 kb
Host smart-02668eea-8395-4498-8973-1e8be96160b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2842650718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2842650718
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3173900544
Short name T743
Test name
Test status
Simulation time 355015209 ps
CPU time 4.92 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:29:49 PM PDT 24
Peak memory 244080 kb
Host smart-6de6a386-9cd7-43bb-b815-e82ca63d5357
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173900544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3173900544
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.615952093
Short name T745
Test name
Test status
Simulation time 222235342 ps
CPU time 7.97 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:29:48 PM PDT 24
Peak memory 235592 kb
Host smart-3ee8bcff-52a6-48bf-a397-97563281bf0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=615952093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.615952093
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3603357153
Short name T721
Test name
Test status
Simulation time 9995684 ps
CPU time 1.59 seconds
Started Mar 31 12:29:47 PM PDT 24
Finished Mar 31 12:29:49 PM PDT 24
Peak memory 236552 kb
Host smart-354eb2fe-4a87-46e0-b9db-e87b2a14205b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3603357153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3603357153
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4112574711
Short name T795
Test name
Test status
Simulation time 353940578 ps
CPU time 12.19 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:29:56 PM PDT 24
Peak memory 244736 kb
Host smart-aed9112b-2c0d-4e04-8a9d-99c068fa2c83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4112574711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.4112574711
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3243984698
Short name T141
Test name
Test status
Simulation time 3538234685 ps
CPU time 262.56 seconds
Started Mar 31 12:29:43 PM PDT 24
Finished Mar 31 12:34:10 PM PDT 24
Peak memory 265200 kb
Host smart-64f11902-574c-4f9f-96f8-0c19e79f56e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3243984698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3243984698
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2511803454
Short name T163
Test name
Test status
Simulation time 56869736210 ps
CPU time 523.02 seconds
Started Mar 31 12:30:19 PM PDT 24
Finished Mar 31 12:39:02 PM PDT 24
Peak memory 265172 kb
Host smart-336ea264-5ef5-4733-9796-0e5a5f482556
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511803454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2511803454
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.145220542
Short name T754
Test name
Test status
Simulation time 97101842 ps
CPU time 6.87 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:29:51 PM PDT 24
Peak memory 248248 kb
Host smart-a44b43c1-7117-438d-9791-f245469df4bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=145220542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.145220542
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1307841567
Short name T181
Test name
Test status
Simulation time 2424517261 ps
CPU time 20.64 seconds
Started Mar 31 12:29:43 PM PDT 24
Finished Mar 31 12:30:04 PM PDT 24
Peak memory 239432 kb
Host smart-03ee466b-bb58-4593-92e5-155b77b97b7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1307841567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1307841567
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.837926731
Short name T781
Test name
Test status
Simulation time 581410984 ps
CPU time 9.5 seconds
Started Mar 31 12:29:40 PM PDT 24
Finished Mar 31 12:29:50 PM PDT 24
Peak memory 240332 kb
Host smart-cfe8202f-aa79-4792-8cdf-f9e9eb449159
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837926731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.837926731
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3092716529
Short name T234
Test name
Test status
Simulation time 243650330 ps
CPU time 5.06 seconds
Started Mar 31 12:29:51 PM PDT 24
Finished Mar 31 12:29:56 PM PDT 24
Peak memory 240144 kb
Host smart-7f9fb04f-c59b-4012-8301-dd9d71691066
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3092716529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3092716529
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3694794891
Short name T799
Test name
Test status
Simulation time 10222459 ps
CPU time 1.27 seconds
Started Mar 31 12:30:17 PM PDT 24
Finished Mar 31 12:30:18 PM PDT 24
Peak memory 236560 kb
Host smart-37e721d5-e0d1-426c-a38b-72755ff0cedf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3694794891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3694794891
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2037403097
Short name T195
Test name
Test status
Simulation time 256415478 ps
CPU time 20.27 seconds
Started Mar 31 12:30:10 PM PDT 24
Finished Mar 31 12:30:31 PM PDT 24
Peak memory 248572 kb
Host smart-ca3eda85-23d7-44e6-8f2d-4e28600cdfb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2037403097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2037403097
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3907899945
Short name T133
Test name
Test status
Simulation time 6419915871 ps
CPU time 135.1 seconds
Started Mar 31 12:29:38 PM PDT 24
Finished Mar 31 12:31:53 PM PDT 24
Peak memory 256800 kb
Host smart-ddd29476-aafa-4493-8049-b3f7936eb06e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3907899945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3907899945
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.611146202
Short name T760
Test name
Test status
Simulation time 109559420 ps
CPU time 4.51 seconds
Started Mar 31 12:30:18 PM PDT 24
Finished Mar 31 12:30:23 PM PDT 24
Peak memory 249624 kb
Host smart-b6b13d6f-7276-4ea2-8c98-740e99f5d172
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=611146202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.611146202
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1143397356
Short name T660
Test name
Test status
Simulation time 125971305213 ps
CPU time 1559.84 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 01:14:22 PM PDT 24
Peak memory 282560 kb
Host smart-5bd6ae7d-b16a-4c79-8898-5f2003a89eb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143397356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1143397356
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2616193593
Short name T549
Test name
Test status
Simulation time 534748941 ps
CPU time 14.45 seconds
Started Mar 31 12:48:13 PM PDT 24
Finished Mar 31 12:48:27 PM PDT 24
Peak memory 248872 kb
Host smart-f6f4c507-3c33-41b6-bab6-260a4c50d118
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2616193593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2616193593
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3235690073
Short name T449
Test name
Test status
Simulation time 3319316008 ps
CPU time 190.88 seconds
Started Mar 31 12:48:13 PM PDT 24
Finished Mar 31 12:51:24 PM PDT 24
Peak memory 256756 kb
Host smart-cd56a2b8-f1ca-456c-ba78-0722126a1d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32356
90073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3235690073
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2484305594
Short name T649
Test name
Test status
Simulation time 38113353549 ps
CPU time 818.22 seconds
Started Mar 31 12:48:14 PM PDT 24
Finished Mar 31 01:01:53 PM PDT 24
Peak memory 265372 kb
Host smart-a0a4f27b-1bfd-41e8-833d-e4574d4f1eac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484305594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2484305594
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3672681155
Short name T674
Test name
Test status
Simulation time 42394427170 ps
CPU time 2691.44 seconds
Started Mar 31 12:48:16 PM PDT 24
Finished Mar 31 01:33:08 PM PDT 24
Peak memory 289128 kb
Host smart-9ce30d68-5ad1-48c8-bb28-89df4708ee06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672681155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3672681155
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.705066142
Short name T671
Test name
Test status
Simulation time 217854016189 ps
CPU time 463.2 seconds
Started Mar 31 12:48:16 PM PDT 24
Finished Mar 31 12:55:59 PM PDT 24
Peak memory 247960 kb
Host smart-20e143cf-e65b-4b79-a82c-1822d3cd25ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705066142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.705066142
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1986999862
Short name T523
Test name
Test status
Simulation time 306434186 ps
CPU time 22.45 seconds
Started Mar 31 12:48:16 PM PDT 24
Finished Mar 31 12:48:38 PM PDT 24
Peak memory 248844 kb
Host smart-a4fac82d-d8bf-4e61-a331-83f618b7e224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19869
99862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1986999862
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2169925966
Short name T481
Test name
Test status
Simulation time 39884610 ps
CPU time 5.62 seconds
Started Mar 31 12:48:13 PM PDT 24
Finished Mar 31 12:48:18 PM PDT 24
Peak memory 247280 kb
Host smart-5f54d3c2-4ed8-44d3-a311-943790a2b8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21699
25966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2169925966
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1041846675
Short name T257
Test name
Test status
Simulation time 740011426 ps
CPU time 38.31 seconds
Started Mar 31 12:48:16 PM PDT 24
Finished Mar 31 12:48:54 PM PDT 24
Peak memory 248884 kb
Host smart-8305db30-bb71-4da7-ab02-bcba8e87ee95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10418
46675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1041846675
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2803311864
Short name T680
Test name
Test status
Simulation time 1043160213 ps
CPU time 55.98 seconds
Started Mar 31 12:48:13 PM PDT 24
Finished Mar 31 12:49:09 PM PDT 24
Peak memory 248896 kb
Host smart-cf949a41-5a2b-4dcb-842a-4373e76f47b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28033
11864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2803311864
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2881410612
Short name T458
Test name
Test status
Simulation time 30196646293 ps
CPU time 1702.55 seconds
Started Mar 31 12:48:16 PM PDT 24
Finished Mar 31 01:16:39 PM PDT 24
Peak memory 289136 kb
Host smart-d662584b-9c9c-4df4-a0eb-1b2762f95f84
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881410612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2881410612
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3187845142
Short name T58
Test name
Test status
Simulation time 21742506353 ps
CPU time 1981.71 seconds
Started Mar 31 12:48:16 PM PDT 24
Finished Mar 31 01:21:18 PM PDT 24
Peak memory 289052 kb
Host smart-7227e14b-04a0-4738-bee1-f44fe30c8f3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187845142 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3187845142
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3239845131
Short name T580
Test name
Test status
Simulation time 42617175751 ps
CPU time 1233.02 seconds
Started Mar 31 12:48:24 PM PDT 24
Finished Mar 31 01:08:57 PM PDT 24
Peak memory 289452 kb
Host smart-deb5bc0c-7a95-4400-b002-f8a6eb167104
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239845131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3239845131
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3644120395
Short name T653
Test name
Test status
Simulation time 4398437773 ps
CPU time 67.03 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 12:49:29 PM PDT 24
Peak memory 257012 kb
Host smart-04380a18-486b-4420-9a3e-6592b1ed8a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36441
20395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3644120395
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2388096904
Short name T490
Test name
Test status
Simulation time 1059196996 ps
CPU time 31.77 seconds
Started Mar 31 12:48:20 PM PDT 24
Finished Mar 31 12:48:52 PM PDT 24
Peak memory 248904 kb
Host smart-315b930a-946e-49b3-9db7-150626729ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23880
96904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2388096904
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1794335276
Short name T438
Test name
Test status
Simulation time 15948832415 ps
CPU time 1628.74 seconds
Started Mar 31 12:48:19 PM PDT 24
Finished Mar 31 01:15:28 PM PDT 24
Peak memory 289544 kb
Host smart-f418c831-9056-468d-b443-f17956777f59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794335276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1794335276
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3179577321
Short name T301
Test name
Test status
Simulation time 7596188999 ps
CPU time 316.54 seconds
Started Mar 31 12:48:20 PM PDT 24
Finished Mar 31 12:53:37 PM PDT 24
Peak memory 248244 kb
Host smart-af1874d6-9ef0-4a73-802b-e61cf9a09028
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179577321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3179577321
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3979109205
Short name T363
Test name
Test status
Simulation time 970210918 ps
CPU time 25.33 seconds
Started Mar 31 12:48:23 PM PDT 24
Finished Mar 31 12:48:48 PM PDT 24
Peak memory 248840 kb
Host smart-7051cc6d-382c-4cc6-b60b-406a78091101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39791
09205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3979109205
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.89485740
Short name T32
Test name
Test status
Simulation time 1622626754 ps
CPU time 40.24 seconds
Started Mar 31 12:48:20 PM PDT 24
Finished Mar 31 12:49:00 PM PDT 24
Peak memory 247448 kb
Host smart-d6ef61d3-85e6-48db-afde-8b99e1ea9786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89485
740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.89485740
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3805126785
Short name T574
Test name
Test status
Simulation time 3911133452 ps
CPU time 60.74 seconds
Started Mar 31 12:48:24 PM PDT 24
Finished Mar 31 12:49:25 PM PDT 24
Peak memory 248068 kb
Host smart-a2cf74fd-9554-4285-ad47-baac26480a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38051
26785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3805126785
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.755115352
Short name T356
Test name
Test status
Simulation time 229772528 ps
CPU time 12.87 seconds
Started Mar 31 12:48:23 PM PDT 24
Finished Mar 31 12:48:36 PM PDT 24
Peak memory 248800 kb
Host smart-ccf706ec-f2ed-4deb-b245-4091fa5bbb77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75511
5352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.755115352
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.683501030
Short name T126
Test name
Test status
Simulation time 54436831 ps
CPU time 2.52 seconds
Started Mar 31 12:48:47 PM PDT 24
Finished Mar 31 12:48:50 PM PDT 24
Peak memory 249068 kb
Host smart-42da9865-fe56-45d4-baaf-de6b6f0600fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=683501030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.683501030
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3376589859
Short name T538
Test name
Test status
Simulation time 27290147976 ps
CPU time 1716.87 seconds
Started Mar 31 12:48:52 PM PDT 24
Finished Mar 31 01:17:30 PM PDT 24
Peak memory 273516 kb
Host smart-1d05ae9d-9dfa-419e-984a-722abca11ff8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376589859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3376589859
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.689537043
Short name T504
Test name
Test status
Simulation time 1479864416 ps
CPU time 19.27 seconds
Started Mar 31 12:48:46 PM PDT 24
Finished Mar 31 12:49:06 PM PDT 24
Peak memory 248876 kb
Host smart-515dd95a-e874-495e-87ea-19803ecf527f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=689537043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.689537043
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.374331641
Short name T350
Test name
Test status
Simulation time 1922336928 ps
CPU time 148.96 seconds
Started Mar 31 12:48:51 PM PDT 24
Finished Mar 31 12:51:20 PM PDT 24
Peak memory 256988 kb
Host smart-bec79610-4b93-4fb3-b932-a59b4941093c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37433
1641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.374331641
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3077599707
Short name T96
Test name
Test status
Simulation time 4984017144 ps
CPU time 55.38 seconds
Started Mar 31 12:48:52 PM PDT 24
Finished Mar 31 12:49:48 PM PDT 24
Peak memory 249016 kb
Host smart-5778acc8-7060-4987-9b59-657dc3eaed67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30775
99707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3077599707
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3818541425
Short name T683
Test name
Test status
Simulation time 23375669459 ps
CPU time 1331.02 seconds
Started Mar 31 12:48:46 PM PDT 24
Finished Mar 31 01:10:57 PM PDT 24
Peak memory 273496 kb
Host smart-7662b642-df7b-4a95-8ae1-fece42bc0d93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818541425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3818541425
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1053695830
Short name T621
Test name
Test status
Simulation time 40757105990 ps
CPU time 440.18 seconds
Started Mar 31 12:48:49 PM PDT 24
Finished Mar 31 12:56:09 PM PDT 24
Peak memory 247016 kb
Host smart-c9332b31-9f82-46a0-9bc9-64c662ca176d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053695830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1053695830
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.950369398
Short name T395
Test name
Test status
Simulation time 279112141 ps
CPU time 16.94 seconds
Started Mar 31 12:48:46 PM PDT 24
Finished Mar 31 12:49:03 PM PDT 24
Peak memory 248868 kb
Host smart-619b10ad-d879-494a-869b-d581b081e68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95036
9398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.950369398
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2915397079
Short name T53
Test name
Test status
Simulation time 908962575 ps
CPU time 13.4 seconds
Started Mar 31 12:48:45 PM PDT 24
Finished Mar 31 12:48:58 PM PDT 24
Peak memory 252968 kb
Host smart-f1a4997b-27e3-4ffd-b419-8fcf7bada6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29153
97079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2915397079
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.4128190345
Short name T529
Test name
Test status
Simulation time 275380883 ps
CPU time 28.29 seconds
Started Mar 31 12:48:45 PM PDT 24
Finished Mar 31 12:49:14 PM PDT 24
Peak memory 247344 kb
Host smart-9113b38b-abcb-4159-afa8-3e9010f99895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41281
90345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4128190345
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.562418605
Short name T263
Test name
Test status
Simulation time 217206651 ps
CPU time 11.13 seconds
Started Mar 31 12:48:46 PM PDT 24
Finished Mar 31 12:48:57 PM PDT 24
Peak memory 248828 kb
Host smart-0f894c85-4bfe-478a-b721-4ea73c852f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56241
8605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.562418605
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1125834369
Short name T632
Test name
Test status
Simulation time 15348820754 ps
CPU time 1452.5 seconds
Started Mar 31 12:48:45 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 287936 kb
Host smart-8022ae24-8372-4a6b-bb0d-129f7cd953d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125834369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1125834369
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1024110881
Short name T491
Test name
Test status
Simulation time 1203685985 ps
CPU time 48.78 seconds
Started Mar 31 12:48:51 PM PDT 24
Finished Mar 31 12:49:40 PM PDT 24
Peak memory 240628 kb
Host smart-9200f0b4-7971-48c2-ab89-50a2ddfa3ad0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1024110881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1024110881
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2797448838
Short name T411
Test name
Test status
Simulation time 8449158013 ps
CPU time 313.38 seconds
Started Mar 31 12:48:45 PM PDT 24
Finished Mar 31 12:53:59 PM PDT 24
Peak memory 256804 kb
Host smart-e25b0196-7064-4580-bb5c-3c8dd4742997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27974
48838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2797448838
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1547248836
Short name T392
Test name
Test status
Simulation time 176183775 ps
CPU time 18.01 seconds
Started Mar 31 12:48:50 PM PDT 24
Finished Mar 31 12:49:08 PM PDT 24
Peak memory 255460 kb
Host smart-43d93f80-831b-4199-b36a-510b764508e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15472
48836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1547248836
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1794517165
Short name T322
Test name
Test status
Simulation time 23548553993 ps
CPU time 1622.31 seconds
Started Mar 31 12:48:47 PM PDT 24
Finished Mar 31 01:15:50 PM PDT 24
Peak memory 270536 kb
Host smart-96ba389c-bfd0-455b-8d68-f40834fd9fb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794517165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1794517165
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1469265960
Short name T445
Test name
Test status
Simulation time 50713366001 ps
CPU time 1730.53 seconds
Started Mar 31 12:48:45 PM PDT 24
Finished Mar 31 01:17:36 PM PDT 24
Peak memory 288848 kb
Host smart-47b79734-caa7-43af-8ee7-5be9929e6c01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469265960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1469265960
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2150573073
Short name T297
Test name
Test status
Simulation time 7069348023 ps
CPU time 302.47 seconds
Started Mar 31 12:48:48 PM PDT 24
Finished Mar 31 12:53:50 PM PDT 24
Peak memory 247920 kb
Host smart-924eb6b0-987a-4598-a93a-ca7f1b5b4a27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150573073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2150573073
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1432865204
Short name T496
Test name
Test status
Simulation time 721871208 ps
CPU time 27.71 seconds
Started Mar 31 12:48:46 PM PDT 24
Finished Mar 31 12:49:14 PM PDT 24
Peak memory 248892 kb
Host smart-e5eeba5f-d2f6-4adc-aa4b-4eace3e22a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14328
65204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1432865204
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3769104434
Short name T631
Test name
Test status
Simulation time 485098849 ps
CPU time 24.22 seconds
Started Mar 31 12:48:50 PM PDT 24
Finished Mar 31 12:49:15 PM PDT 24
Peak memory 249284 kb
Host smart-90485879-1e65-40bb-8d9c-4353e0aee008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37691
04434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3769104434
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3630030843
Short name T85
Test name
Test status
Simulation time 891350646 ps
CPU time 13.19 seconds
Started Mar 31 12:48:46 PM PDT 24
Finished Mar 31 12:48:59 PM PDT 24
Peak memory 247332 kb
Host smart-35960aed-e0d6-4d6c-935d-59ec00f1061b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36300
30843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3630030843
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.4069707453
Short name T93
Test name
Test status
Simulation time 565431973 ps
CPU time 28.65 seconds
Started Mar 31 12:48:46 PM PDT 24
Finished Mar 31 12:49:15 PM PDT 24
Peak memory 248796 kb
Host smart-03047bce-8b68-4baa-b9b4-606bbc764d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40697
07453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.4069707453
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2189586317
Short name T439
Test name
Test status
Simulation time 15891929332 ps
CPU time 1449.22 seconds
Started Mar 31 12:48:49 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 289716 kb
Host smart-f9f81d3c-dbf8-4d19-867d-2be611a25d3e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189586317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2189586317
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3897144615
Short name T335
Test name
Test status
Simulation time 26396589793 ps
CPU time 1516.93 seconds
Started Mar 31 12:48:54 PM PDT 24
Finished Mar 31 01:14:11 PM PDT 24
Peak memory 273508 kb
Host smart-97ecc1dc-f97f-4fde-b448-b2f948ee8b2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897144615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3897144615
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1706135312
Short name T562
Test name
Test status
Simulation time 1775438968 ps
CPU time 21.89 seconds
Started Mar 31 12:48:56 PM PDT 24
Finished Mar 31 12:49:18 PM PDT 24
Peak memory 251664 kb
Host smart-2350a56c-9d2d-4270-a7ec-9b248f592af1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1706135312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1706135312
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3973848699
Short name T472
Test name
Test status
Simulation time 2621354891 ps
CPU time 137.68 seconds
Started Mar 31 12:48:53 PM PDT 24
Finished Mar 31 12:51:12 PM PDT 24
Peak memory 256488 kb
Host smart-762669aa-4499-4f91-85de-a520b0c9e47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39738
48699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3973848699
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4040728356
Short name T552
Test name
Test status
Simulation time 240731037 ps
CPU time 5.25 seconds
Started Mar 31 12:48:57 PM PDT 24
Finished Mar 31 12:49:02 PM PDT 24
Peak memory 240668 kb
Host smart-5636c962-113c-48e0-9e4b-ce52eb8e75bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40407
28356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4040728356
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3812093686
Short name T222
Test name
Test status
Simulation time 994643132838 ps
CPU time 2859.68 seconds
Started Mar 31 12:48:53 PM PDT 24
Finished Mar 31 01:36:33 PM PDT 24
Peak memory 289224 kb
Host smart-d5d907da-e475-477b-a1d9-a85078601492
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812093686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3812093686
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3700311915
Short name T502
Test name
Test status
Simulation time 8395755725 ps
CPU time 895.01 seconds
Started Mar 31 12:48:54 PM PDT 24
Finished Mar 31 01:03:49 PM PDT 24
Peak memory 273540 kb
Host smart-b4273ba2-8c5c-4354-b3fb-b4ebe539cac2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700311915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3700311915
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3071584003
Short name T229
Test name
Test status
Simulation time 4205378579 ps
CPU time 170.92 seconds
Started Mar 31 12:48:56 PM PDT 24
Finished Mar 31 12:51:47 PM PDT 24
Peak memory 248004 kb
Host smart-1396face-8ec1-462a-8929-498df7e2894e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071584003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3071584003
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3546165819
Short name T648
Test name
Test status
Simulation time 441055986 ps
CPU time 12.08 seconds
Started Mar 31 12:48:53 PM PDT 24
Finished Mar 31 12:49:05 PM PDT 24
Peak memory 248888 kb
Host smart-77d8507f-5868-45ee-a06c-243c9c292fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35461
65819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3546165819
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1281848410
Short name T508
Test name
Test status
Simulation time 5830178519 ps
CPU time 61.24 seconds
Started Mar 31 12:48:58 PM PDT 24
Finished Mar 31 12:50:00 PM PDT 24
Peak memory 249380 kb
Host smart-0fba066c-d014-4d36-be4c-dd14508f292e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12818
48410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1281848410
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3960713633
Short name T474
Test name
Test status
Simulation time 5225266466 ps
CPU time 50.24 seconds
Started Mar 31 12:48:53 PM PDT 24
Finished Mar 31 12:49:44 PM PDT 24
Peak memory 255620 kb
Host smart-23b23bf1-f373-4153-bf84-c2557c312c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39607
13633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3960713633
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.4165089331
Short name T517
Test name
Test status
Simulation time 341947701 ps
CPU time 16.76 seconds
Started Mar 31 12:48:54 PM PDT 24
Finished Mar 31 12:49:11 PM PDT 24
Peak memory 253060 kb
Host smart-b0e68261-da2b-4384-a8ac-b8c0c042ef72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41650
89331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.4165089331
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1750831287
Short name T38
Test name
Test status
Simulation time 146539745 ps
CPU time 3.24 seconds
Started Mar 31 12:48:53 PM PDT 24
Finished Mar 31 12:48:56 PM PDT 24
Peak memory 249140 kb
Host smart-96269b12-abb2-4605-9cf2-a5ed9ffb59f8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1750831287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1750831287
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3611590177
Short name T577
Test name
Test status
Simulation time 15282331694 ps
CPU time 1171.23 seconds
Started Mar 31 12:48:57 PM PDT 24
Finished Mar 31 01:08:28 PM PDT 24
Peak memory 281784 kb
Host smart-907a9fc5-9db9-4024-8863-4a372900f2fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611590177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3611590177
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.451495208
Short name T691
Test name
Test status
Simulation time 149822824 ps
CPU time 9.32 seconds
Started Mar 31 12:48:53 PM PDT 24
Finished Mar 31 12:49:03 PM PDT 24
Peak memory 248800 kb
Host smart-6e9bd6bf-d1ce-4b0b-9d2f-4860685c6e11
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=451495208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.451495208
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2101112829
Short name T430
Test name
Test status
Simulation time 2245729102 ps
CPU time 66 seconds
Started Mar 31 12:48:54 PM PDT 24
Finished Mar 31 12:50:00 PM PDT 24
Peak memory 256620 kb
Host smart-f1bb1613-101a-4910-9c74-cdaaad8e5a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21011
12829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2101112829
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3417701047
Short name T478
Test name
Test status
Simulation time 3345957507 ps
CPU time 48.11 seconds
Started Mar 31 12:48:53 PM PDT 24
Finished Mar 31 12:49:42 PM PDT 24
Peak memory 256016 kb
Host smart-214848bf-9d57-4df4-8c94-de9f1399a8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34177
01047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3417701047
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3871036829
Short name T118
Test name
Test status
Simulation time 66165738773 ps
CPU time 2064.02 seconds
Started Mar 31 12:48:55 PM PDT 24
Finished Mar 31 01:23:19 PM PDT 24
Peak memory 284636 kb
Host smart-27636e27-f011-4e15-ad49-e9fcf8dfba28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871036829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3871036829
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2741946926
Short name T387
Test name
Test status
Simulation time 190177599754 ps
CPU time 2700.44 seconds
Started Mar 31 12:48:54 PM PDT 24
Finished Mar 31 01:33:55 PM PDT 24
Peak memory 281764 kb
Host smart-e4b56811-f40b-44b3-8c34-71173909189c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741946926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2741946926
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1866101665
Short name T403
Test name
Test status
Simulation time 546908342 ps
CPU time 27.78 seconds
Started Mar 31 12:48:55 PM PDT 24
Finished Mar 31 12:49:23 PM PDT 24
Peak memory 248880 kb
Host smart-afe555d0-5ea9-40e3-afd0-65787b85fcc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18661
01665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1866101665
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3851291888
Short name T56
Test name
Test status
Simulation time 1948368642 ps
CPU time 37.3 seconds
Started Mar 31 12:48:54 PM PDT 24
Finished Mar 31 12:49:32 PM PDT 24
Peak memory 255548 kb
Host smart-2ad604f9-4693-4f4e-9d29-7eeb5edf3209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38512
91888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3851291888
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.4270059501
Short name T468
Test name
Test status
Simulation time 220835954 ps
CPU time 7.47 seconds
Started Mar 31 12:48:54 PM PDT 24
Finished Mar 31 12:49:02 PM PDT 24
Peak memory 240896 kb
Host smart-5f5653b9-f85e-4352-98a4-fd290281dfea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42700
59501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4270059501
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3187122972
Short name T370
Test name
Test status
Simulation time 304590901 ps
CPU time 34.69 seconds
Started Mar 31 12:48:55 PM PDT 24
Finished Mar 31 12:49:30 PM PDT 24
Peak memory 248844 kb
Host smart-d0938cbb-444d-421c-a512-8f8e7d04b751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31871
22972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3187122972
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2684234565
Short name T265
Test name
Test status
Simulation time 117818452303 ps
CPU time 3342.03 seconds
Started Mar 31 12:48:52 PM PDT 24
Finished Mar 31 01:44:35 PM PDT 24
Peak memory 288988 kb
Host smart-a02bfb57-aadd-4006-b075-7cf2b9ff4fb3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684234565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2684234565
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1700745367
Short name T201
Test name
Test status
Simulation time 29534470 ps
CPU time 2.9 seconds
Started Mar 31 12:49:01 PM PDT 24
Finished Mar 31 12:49:04 PM PDT 24
Peak memory 249136 kb
Host smart-c3afbc73-05a1-45d8-be3f-96ed1a45ab35
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1700745367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1700745367
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.4150589549
Short name T696
Test name
Test status
Simulation time 30985671948 ps
CPU time 1119.87 seconds
Started Mar 31 12:49:04 PM PDT 24
Finished Mar 31 01:07:45 PM PDT 24
Peak memory 272812 kb
Host smart-62b792ce-5489-4aa6-86e2-1bf711a32fe4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150589549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.4150589549
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1621184758
Short name T433
Test name
Test status
Simulation time 133096995 ps
CPU time 8.02 seconds
Started Mar 31 12:49:03 PM PDT 24
Finished Mar 31 12:49:11 PM PDT 24
Peak memory 240644 kb
Host smart-51001ca2-8b90-4cfb-bd6a-9fa293a76708
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1621184758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1621184758
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1939769937
Short name T603
Test name
Test status
Simulation time 16421443843 ps
CPU time 152.01 seconds
Started Mar 31 12:49:01 PM PDT 24
Finished Mar 31 12:51:34 PM PDT 24
Peak memory 248596 kb
Host smart-7b950004-7095-40dd-933a-406eb1e88933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19397
69937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1939769937
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3668646176
Short name T708
Test name
Test status
Simulation time 161248305 ps
CPU time 5.16 seconds
Started Mar 31 12:49:01 PM PDT 24
Finished Mar 31 12:49:06 PM PDT 24
Peak memory 250984 kb
Host smart-a9a2f2eb-8c8c-4215-afd0-14c37dccd0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36686
46176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3668646176
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.4161035614
Short name T223
Test name
Test status
Simulation time 16502284800 ps
CPU time 1489.19 seconds
Started Mar 31 12:49:02 PM PDT 24
Finished Mar 31 01:13:51 PM PDT 24
Peak memory 288624 kb
Host smart-fb608d00-3b24-429b-91a1-5d858b16fc21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161035614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.4161035614
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2851019007
Short name T444
Test name
Test status
Simulation time 79968414466 ps
CPU time 2149.43 seconds
Started Mar 31 12:49:03 PM PDT 24
Finished Mar 31 01:24:54 PM PDT 24
Peak memory 273572 kb
Host smart-f0393b09-a9b1-4000-b468-f26736a42cfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851019007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2851019007
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.190170341
Short name T692
Test name
Test status
Simulation time 254427835 ps
CPU time 16.41 seconds
Started Mar 31 12:48:54 PM PDT 24
Finished Mar 31 12:49:10 PM PDT 24
Peak memory 248836 kb
Host smart-58c263c4-0f0c-42b4-9676-2049c5297585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19017
0341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.190170341
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1878917331
Short name T397
Test name
Test status
Simulation time 7971845877 ps
CPU time 52.87 seconds
Started Mar 31 12:48:55 PM PDT 24
Finished Mar 31 12:49:48 PM PDT 24
Peak memory 257168 kb
Host smart-3e5abe50-0b4d-4c66-93d8-27a13807eadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18789
17331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1878917331
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3299423916
Short name T546
Test name
Test status
Simulation time 314274803 ps
CPU time 4.13 seconds
Started Mar 31 12:49:02 PM PDT 24
Finished Mar 31 12:49:06 PM PDT 24
Peak memory 239252 kb
Host smart-72435817-05e4-4003-afb4-f8bb7351736d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32994
23916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3299423916
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.989823935
Short name T412
Test name
Test status
Simulation time 1569127528 ps
CPU time 23.07 seconds
Started Mar 31 12:48:55 PM PDT 24
Finished Mar 31 12:49:19 PM PDT 24
Peak memory 248832 kb
Host smart-9e5c0a4f-1d92-405d-8c79-ed51240cbc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98982
3935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.989823935
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3518007817
Short name T54
Test name
Test status
Simulation time 121376135668 ps
CPU time 1897.44 seconds
Started Mar 31 12:49:02 PM PDT 24
Finished Mar 31 01:20:40 PM PDT 24
Peak memory 285572 kb
Host smart-5eb58c85-817a-4719-9a5b-b45560d344f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518007817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3518007817
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.531874260
Short name T52
Test name
Test status
Simulation time 178948990740 ps
CPU time 3996.53 seconds
Started Mar 31 12:49:02 PM PDT 24
Finished Mar 31 01:55:40 PM PDT 24
Peak memory 330404 kb
Host smart-b39a7d6f-89cc-403c-962d-a210939f11c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531874260 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.531874260
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1046849570
Short name T200
Test name
Test status
Simulation time 32048947 ps
CPU time 3.42 seconds
Started Mar 31 12:49:13 PM PDT 24
Finished Mar 31 12:49:16 PM PDT 24
Peak memory 249128 kb
Host smart-f075dfae-1b9b-42d3-b9b5-d26ccae5d7fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1046849570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1046849570
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3590390442
Short name T366
Test name
Test status
Simulation time 83186750998 ps
CPU time 1512.97 seconds
Started Mar 31 12:49:04 PM PDT 24
Finished Mar 31 01:14:17 PM PDT 24
Peak memory 273528 kb
Host smart-67056d8e-f813-4b8c-95b2-fbb34f273673
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590390442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3590390442
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3084242481
Short name T399
Test name
Test status
Simulation time 242433910 ps
CPU time 12.04 seconds
Started Mar 31 12:49:02 PM PDT 24
Finished Mar 31 12:49:14 PM PDT 24
Peak memory 240600 kb
Host smart-88c9db9f-a647-4fdc-b603-7cb0170efda4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3084242481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3084242481
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1739255996
Short name T485
Test name
Test status
Simulation time 5881304004 ps
CPU time 266.63 seconds
Started Mar 31 12:49:05 PM PDT 24
Finished Mar 31 12:53:32 PM PDT 24
Peak memory 251508 kb
Host smart-8067ec3e-e22c-4da1-bd9e-fd8e5a85cf7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17392
55996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1739255996
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2022587741
Short name T373
Test name
Test status
Simulation time 3199176183 ps
CPU time 54.35 seconds
Started Mar 31 12:49:04 PM PDT 24
Finished Mar 31 12:49:59 PM PDT 24
Peak memory 254964 kb
Host smart-f8e59fe4-960b-42fe-be3d-9a61bc495fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20225
87741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2022587741
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.608995669
Short name T317
Test name
Test status
Simulation time 180115877657 ps
CPU time 2537.75 seconds
Started Mar 31 12:49:01 PM PDT 24
Finished Mar 31 01:31:19 PM PDT 24
Peak memory 281776 kb
Host smart-c3a55690-6cd1-47ba-9cbe-69d1f37e9ed5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608995669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.608995669
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3574054434
Short name T513
Test name
Test status
Simulation time 140705504610 ps
CPU time 2642.85 seconds
Started Mar 31 12:49:06 PM PDT 24
Finished Mar 31 01:33:10 PM PDT 24
Peak memory 286996 kb
Host smart-bbe2d60c-8aaf-4f07-98c7-162f1ace0a94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574054434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3574054434
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.187296935
Short name T669
Test name
Test status
Simulation time 7135124808 ps
CPU time 299.12 seconds
Started Mar 31 12:49:03 PM PDT 24
Finished Mar 31 12:54:02 PM PDT 24
Peak memory 254648 kb
Host smart-68a7ec43-4474-4978-885d-8169b9a9fb54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187296935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.187296935
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3657528654
Short name T15
Test name
Test status
Simulation time 1175324764 ps
CPU time 28.55 seconds
Started Mar 31 12:49:06 PM PDT 24
Finished Mar 31 12:49:35 PM PDT 24
Peak memory 255972 kb
Host smart-70b0396b-6380-4307-9e03-f0e74db17617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36575
28654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3657528654
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1701285995
Short name T353
Test name
Test status
Simulation time 744989709 ps
CPU time 24.78 seconds
Started Mar 31 12:49:03 PM PDT 24
Finished Mar 31 12:49:29 PM PDT 24
Peak memory 254844 kb
Host smart-1b279ba4-d666-4b27-b370-dd8e1dcd6ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17012
85995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1701285995
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3519214572
Short name T124
Test name
Test status
Simulation time 1786481632 ps
CPU time 50.46 seconds
Started Mar 31 12:49:03 PM PDT 24
Finished Mar 31 12:49:53 PM PDT 24
Peak memory 248888 kb
Host smart-00ea9d76-ee00-46e0-b176-c098deb51995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35192
14572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3519214572
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3037539287
Short name T466
Test name
Test status
Simulation time 1022144795 ps
CPU time 19.4 seconds
Started Mar 31 12:49:04 PM PDT 24
Finished Mar 31 12:49:24 PM PDT 24
Peak memory 248660 kb
Host smart-ba3286c0-2acc-4c97-9134-7188fa92e126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30375
39287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3037539287
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3487504191
Short name T103
Test name
Test status
Simulation time 128108799702 ps
CPU time 1794.89 seconds
Started Mar 31 12:49:14 PM PDT 24
Finished Mar 31 01:19:09 PM PDT 24
Peak memory 289756 kb
Host smart-03cc2b4f-e1bb-4633-be31-3345b318d571
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487504191 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3487504191
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1194820880
Short name T204
Test name
Test status
Simulation time 43405986 ps
CPU time 3.06 seconds
Started Mar 31 12:49:14 PM PDT 24
Finished Mar 31 12:49:17 PM PDT 24
Peak memory 249020 kb
Host smart-a1c02a62-5c5b-44ee-b4ae-22361fad19ba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1194820880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1194820880
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.702905276
Short name T575
Test name
Test status
Simulation time 29571398374 ps
CPU time 756.14 seconds
Started Mar 31 12:49:14 PM PDT 24
Finished Mar 31 01:01:50 PM PDT 24
Peak memory 273580 kb
Host smart-b9fa5f8b-8db5-44fe-8ce7-0e05a306851a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702905276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.702905276
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3073274154
Short name T573
Test name
Test status
Simulation time 367676590 ps
CPU time 7.2 seconds
Started Mar 31 12:49:14 PM PDT 24
Finished Mar 31 12:49:21 PM PDT 24
Peak memory 240644 kb
Host smart-1587182d-d252-4346-bfaf-1e1f730bce47
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3073274154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3073274154
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2533906022
Short name T623
Test name
Test status
Simulation time 14189605283 ps
CPU time 139.94 seconds
Started Mar 31 12:49:16 PM PDT 24
Finished Mar 31 12:51:37 PM PDT 24
Peak memory 256460 kb
Host smart-90e6c25a-03e7-4b30-9d5b-ffbeb823229d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25339
06022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2533906022
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3842452955
Short name T383
Test name
Test status
Simulation time 5556859880 ps
CPU time 34.09 seconds
Started Mar 31 12:49:18 PM PDT 24
Finished Mar 31 12:49:52 PM PDT 24
Peak memory 249116 kb
Host smart-885609bd-1b42-4df1-8fda-ede95080e13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38424
52955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3842452955
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.689625137
Short name T334
Test name
Test status
Simulation time 29532358138 ps
CPU time 1917.45 seconds
Started Mar 31 12:49:14 PM PDT 24
Finished Mar 31 01:21:11 PM PDT 24
Peak memory 270700 kb
Host smart-062c31bc-907b-48c1-aff4-77494622f9ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689625137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.689625137
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.596440257
Short name T443
Test name
Test status
Simulation time 78724210104 ps
CPU time 1961.49 seconds
Started Mar 31 12:49:19 PM PDT 24
Finished Mar 31 01:22:01 PM PDT 24
Peak memory 273560 kb
Host smart-c80cf286-3014-4006-9603-9442682e7674
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596440257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.596440257
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3918896124
Short name T289
Test name
Test status
Simulation time 7026159443 ps
CPU time 301.81 seconds
Started Mar 31 12:49:15 PM PDT 24
Finished Mar 31 12:54:17 PM PDT 24
Peak memory 248140 kb
Host smart-c66b5af6-c7c8-4e4a-84ab-063e60980bea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918896124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3918896124
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3971870413
Short name T521
Test name
Test status
Simulation time 1064667145 ps
CPU time 60.61 seconds
Started Mar 31 12:49:15 PM PDT 24
Finished Mar 31 12:50:16 PM PDT 24
Peak memory 248908 kb
Host smart-33cf8ff3-5882-4ea7-8172-cf23d6c4f53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39718
70413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3971870413
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1430948442
Short name T385
Test name
Test status
Simulation time 1026700548 ps
CPU time 31.04 seconds
Started Mar 31 12:49:14 PM PDT 24
Finished Mar 31 12:49:45 PM PDT 24
Peak memory 255552 kb
Host smart-8e55d701-30a7-457c-b3f2-f7bd4a14bcc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14309
48442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1430948442
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1000161408
Short name T393
Test name
Test status
Simulation time 3938332333 ps
CPU time 55.59 seconds
Started Mar 31 12:49:17 PM PDT 24
Finished Mar 31 12:50:13 PM PDT 24
Peak memory 255448 kb
Host smart-755e190b-d91e-4bdc-9a0c-140ebe62c029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10001
61408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1000161408
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3207349437
Short name T544
Test name
Test status
Simulation time 353918255 ps
CPU time 25.86 seconds
Started Mar 31 12:49:16 PM PDT 24
Finished Mar 31 12:49:42 PM PDT 24
Peak memory 255848 kb
Host smart-02cfc1ea-9e85-435c-a507-03ed7c4bd3f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32073
49437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3207349437
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2046285239
Short name T615
Test name
Test status
Simulation time 50303250608 ps
CPU time 2752.23 seconds
Started Mar 31 12:49:13 PM PDT 24
Finished Mar 31 01:35:06 PM PDT 24
Peak memory 289304 kb
Host smart-c1b5a83f-bfed-4ca9-a61e-d7d1e195742f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046285239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2046285239
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2244018575
Short name T197
Test name
Test status
Simulation time 17534417 ps
CPU time 2.52 seconds
Started Mar 31 12:49:24 PM PDT 24
Finished Mar 31 12:49:27 PM PDT 24
Peak memory 249076 kb
Host smart-1f2ab12f-9041-4247-b5fb-3779f5d41b39
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2244018575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2244018575
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.4054046851
Short name T42
Test name
Test status
Simulation time 9619762710 ps
CPU time 544.03 seconds
Started Mar 31 12:49:22 PM PDT 24
Finished Mar 31 12:58:26 PM PDT 24
Peak memory 272220 kb
Host smart-365401f3-0a40-43b1-831b-32cfa56d54fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054046851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.4054046851
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.882648164
Short name T672
Test name
Test status
Simulation time 153792855 ps
CPU time 8.86 seconds
Started Mar 31 12:49:23 PM PDT 24
Finished Mar 31 12:49:33 PM PDT 24
Peak memory 248876 kb
Host smart-2471cf8b-aec9-4c23-9c9d-402e9912f984
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=882648164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.882648164
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.877371427
Short name T667
Test name
Test status
Simulation time 5133575414 ps
CPU time 114.7 seconds
Started Mar 31 12:49:26 PM PDT 24
Finished Mar 31 12:51:21 PM PDT 24
Peak memory 257000 kb
Host smart-c50b0463-7596-4806-81a0-21005ad3667d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87737
1427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.877371427
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2124130237
Short name T601
Test name
Test status
Simulation time 672767627 ps
CPU time 13.19 seconds
Started Mar 31 12:49:26 PM PDT 24
Finished Mar 31 12:49:39 PM PDT 24
Peak memory 252112 kb
Host smart-57c86d86-75fd-4648-a95f-f21eea5dcc6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21241
30237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2124130237
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.4029824732
Short name T647
Test name
Test status
Simulation time 31986374103 ps
CPU time 2035.57 seconds
Started Mar 31 12:49:23 PM PDT 24
Finished Mar 31 01:23:20 PM PDT 24
Peak memory 272704 kb
Host smart-7d67fe8c-8b73-4dd3-8f80-1683b7339635
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029824732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.4029824732
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2651911799
Short name T700
Test name
Test status
Simulation time 91508640329 ps
CPU time 2402.55 seconds
Started Mar 31 12:49:24 PM PDT 24
Finished Mar 31 01:29:27 PM PDT 24
Peak memory 289048 kb
Host smart-1de2fcc4-a144-443e-977a-9a39df254e0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651911799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2651911799
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3996292934
Short name T272
Test name
Test status
Simulation time 3149259209 ps
CPU time 44.32 seconds
Started Mar 31 12:49:16 PM PDT 24
Finished Mar 31 12:50:00 PM PDT 24
Peak memory 255684 kb
Host smart-4221bab3-ca29-418c-b364-2bca18a0eaf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39962
92934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3996292934
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.4093240764
Short name T684
Test name
Test status
Simulation time 459452640 ps
CPU time 25.23 seconds
Started Mar 31 12:49:25 PM PDT 24
Finished Mar 31 12:49:50 PM PDT 24
Peak memory 248148 kb
Host smart-b3de3bea-0b34-41bd-8e64-ba3002c14597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40932
40764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.4093240764
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1009018440
Short name T441
Test name
Test status
Simulation time 650264985 ps
CPU time 11.76 seconds
Started Mar 31 12:49:24 PM PDT 24
Finished Mar 31 12:49:36 PM PDT 24
Peak memory 248860 kb
Host smart-4ec3a377-fd15-4359-9782-66aefa3c2fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10090
18440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1009018440
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1505477031
Short name T446
Test name
Test status
Simulation time 1332416623 ps
CPU time 20.34 seconds
Started Mar 31 12:49:13 PM PDT 24
Finished Mar 31 12:49:33 PM PDT 24
Peak memory 248840 kb
Host smart-40710dd7-280f-4a72-8f5f-6ed6db10084b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15054
77031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1505477031
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3579616101
Short name T212
Test name
Test status
Simulation time 55616729 ps
CPU time 4 seconds
Started Mar 31 12:49:22 PM PDT 24
Finished Mar 31 12:49:27 PM PDT 24
Peak memory 249088 kb
Host smart-450c2da8-2d15-4a36-803c-04bc3f6b94e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3579616101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3579616101
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3393591755
Short name T592
Test name
Test status
Simulation time 79363805240 ps
CPU time 1293.7 seconds
Started Mar 31 12:49:25 PM PDT 24
Finished Mar 31 01:10:59 PM PDT 24
Peak memory 272832 kb
Host smart-3f773a2c-b3a0-4b8f-8bb5-00d9e8d72507
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393591755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3393591755
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3956107058
Short name T495
Test name
Test status
Simulation time 396481675 ps
CPU time 6.73 seconds
Started Mar 31 12:49:25 PM PDT 24
Finished Mar 31 12:49:32 PM PDT 24
Peak memory 240632 kb
Host smart-3c01de58-471c-45b0-8b8a-596bbf536538
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3956107058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3956107058
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3779597127
Short name T34
Test name
Test status
Simulation time 3018041410 ps
CPU time 82.02 seconds
Started Mar 31 12:49:24 PM PDT 24
Finished Mar 31 12:50:47 PM PDT 24
Peak memory 248824 kb
Host smart-19e35364-fe75-40cb-bb28-3a387c4f967b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37795
97127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3779597127
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2220023312
Short name T462
Test name
Test status
Simulation time 657707152 ps
CPU time 38.48 seconds
Started Mar 31 12:49:26 PM PDT 24
Finished Mar 31 12:50:04 PM PDT 24
Peak memory 254792 kb
Host smart-b323ea46-fe86-4c75-8cd7-182b6d54d9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22200
23312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2220023312
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1833226862
Short name T320
Test name
Test status
Simulation time 32571418004 ps
CPU time 1914.38 seconds
Started Mar 31 12:49:26 PM PDT 24
Finished Mar 31 01:21:21 PM PDT 24
Peak memory 272536 kb
Host smart-039b15ce-4e43-4d32-9615-30d0f8b15b8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833226862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1833226862
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.637136578
Short name T583
Test name
Test status
Simulation time 9421819386 ps
CPU time 922.73 seconds
Started Mar 31 12:49:23 PM PDT 24
Finished Mar 31 01:04:47 PM PDT 24
Peak memory 270708 kb
Host smart-aa09b6c7-62fe-4f51-9fd9-46a18cc9b951
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637136578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.637136578
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2451832676
Short name T307
Test name
Test status
Simulation time 12179472928 ps
CPU time 478.26 seconds
Started Mar 31 12:49:25 PM PDT 24
Finished Mar 31 12:57:24 PM PDT 24
Peak memory 248248 kb
Host smart-2b16226f-8014-45a6-9b18-1b2f8f540373
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451832676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2451832676
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.4127003594
Short name T381
Test name
Test status
Simulation time 2905645265 ps
CPU time 39.07 seconds
Started Mar 31 12:49:24 PM PDT 24
Finished Mar 31 12:50:04 PM PDT 24
Peak memory 248884 kb
Host smart-d01ba9d1-16e6-4672-a994-13bd993be85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41270
03594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.4127003594
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2652443298
Short name T422
Test name
Test status
Simulation time 1091326120 ps
CPU time 59.81 seconds
Started Mar 31 12:49:27 PM PDT 24
Finished Mar 31 12:50:27 PM PDT 24
Peak memory 254804 kb
Host smart-3e173f45-cf25-4fbf-bd1a-cf77741c129d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26524
43298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2652443298
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2736532477
Short name T657
Test name
Test status
Simulation time 55072209 ps
CPU time 4.3 seconds
Started Mar 31 12:49:24 PM PDT 24
Finished Mar 31 12:49:29 PM PDT 24
Peak memory 240632 kb
Host smart-30909ed2-c6c4-4226-af0d-73b6aaeb2a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27365
32477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2736532477
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3852860170
Short name T25
Test name
Test status
Simulation time 70022644378 ps
CPU time 2307.54 seconds
Started Mar 31 12:49:25 PM PDT 24
Finished Mar 31 01:27:53 PM PDT 24
Peak memory 288664 kb
Host smart-38c66618-35de-4e0f-a555-dbc60da7e20a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852860170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3852860170
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3726116078
Short name T211
Test name
Test status
Simulation time 34896451 ps
CPU time 3.07 seconds
Started Mar 31 12:49:31 PM PDT 24
Finished Mar 31 12:49:34 PM PDT 24
Peak memory 249104 kb
Host smart-79085daf-7944-44b5-9f9a-2f91e93167f6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3726116078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3726116078
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2910297852
Short name T460
Test name
Test status
Simulation time 75506286718 ps
CPU time 1687.6 seconds
Started Mar 31 12:49:30 PM PDT 24
Finished Mar 31 01:17:37 PM PDT 24
Peak memory 273584 kb
Host smart-e13ef265-66f6-4577-991a-69cdf16bc920
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910297852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2910297852
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.978759377
Short name T590
Test name
Test status
Simulation time 3561286808 ps
CPU time 19.26 seconds
Started Mar 31 12:49:29 PM PDT 24
Finished Mar 31 12:49:49 PM PDT 24
Peak memory 240724 kb
Host smart-80b3554c-2934-4fe9-813d-d3355a002516
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=978759377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.978759377
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1272523076
Short name T622
Test name
Test status
Simulation time 7394870013 ps
CPU time 128.86 seconds
Started Mar 31 12:49:25 PM PDT 24
Finished Mar 31 12:51:35 PM PDT 24
Peak memory 257208 kb
Host smart-b6e552d4-035c-41c5-b776-f2c05d44323c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12725
23076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1272523076
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.689428275
Short name T230
Test name
Test status
Simulation time 2032990374 ps
CPU time 15.54 seconds
Started Mar 31 12:49:24 PM PDT 24
Finished Mar 31 12:49:40 PM PDT 24
Peak memory 255060 kb
Host smart-5df89ba4-f551-4f43-bc3f-9eeb7d4f2f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68942
8275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.689428275
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1628314442
Short name T311
Test name
Test status
Simulation time 343677687319 ps
CPU time 2855.62 seconds
Started Mar 31 12:49:31 PM PDT 24
Finished Mar 31 01:37:07 PM PDT 24
Peak memory 281712 kb
Host smart-030d93e0-e397-4eec-a55d-d167311e50c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628314442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1628314442
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3640935963
Short name T12
Test name
Test status
Simulation time 9541764725 ps
CPU time 395.3 seconds
Started Mar 31 12:49:33 PM PDT 24
Finished Mar 31 12:56:08 PM PDT 24
Peak memory 255312 kb
Host smart-4d7f68bc-f5e1-4ba8-ad81-e3997b2fcd37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640935963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3640935963
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3454351559
Short name T689
Test name
Test status
Simulation time 68169771 ps
CPU time 7.72 seconds
Started Mar 31 12:49:26 PM PDT 24
Finished Mar 31 12:49:34 PM PDT 24
Peak memory 248652 kb
Host smart-86baf33c-f6bc-4571-8673-f7f708e01ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34543
51559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3454351559
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.93443425
Short name T534
Test name
Test status
Simulation time 1140907383 ps
CPU time 27.8 seconds
Started Mar 31 12:49:23 PM PDT 24
Finished Mar 31 12:49:51 PM PDT 24
Peak memory 254716 kb
Host smart-8329c319-452d-4f7d-9d22-6db9dcbdab0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93443
425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.93443425
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.4256172397
Short name T652
Test name
Test status
Simulation time 1968316979 ps
CPU time 35.31 seconds
Started Mar 31 12:49:25 PM PDT 24
Finished Mar 31 12:50:01 PM PDT 24
Peak memory 256708 kb
Host smart-3478b3ca-6bb1-4c41-b38a-b00edeb8353b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42561
72397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.4256172397
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2036179226
Short name T616
Test name
Test status
Simulation time 399843883 ps
CPU time 24.72 seconds
Started Mar 31 12:49:27 PM PDT 24
Finished Mar 31 12:49:51 PM PDT 24
Peak memory 255368 kb
Host smart-2746ab6e-28bb-4b88-a6c2-d644b511e2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20361
79226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2036179226
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2088568558
Short name T500
Test name
Test status
Simulation time 87875490489 ps
CPU time 2663.56 seconds
Started Mar 31 12:49:31 PM PDT 24
Finished Mar 31 01:33:55 PM PDT 24
Peak memory 289568 kb
Host smart-5ffebf89-edcb-4d76-a3b8-9536b59f29f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088568558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2088568558
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1557949091
Short name T241
Test name
Test status
Simulation time 145766498310 ps
CPU time 1619.1 seconds
Started Mar 31 12:49:32 PM PDT 24
Finished Mar 31 01:16:32 PM PDT 24
Peak memory 289672 kb
Host smart-cfe43927-6339-4ad4-ac65-36d1063836d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557949091 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1557949091
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.287444801
Short name T209
Test name
Test status
Simulation time 109995682 ps
CPU time 3.07 seconds
Started Mar 31 12:48:23 PM PDT 24
Finished Mar 31 12:48:26 PM PDT 24
Peak memory 249108 kb
Host smart-19612a68-a3a0-4cc5-8e21-e5c90b84da6d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=287444801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.287444801
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3336501053
Short name T429
Test name
Test status
Simulation time 52777830995 ps
CPU time 1619.28 seconds
Started Mar 31 12:48:18 PM PDT 24
Finished Mar 31 01:15:17 PM PDT 24
Peak memory 282560 kb
Host smart-f8655639-6864-4cf4-9928-c1568b393780
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336501053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3336501053
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2773759578
Short name T701
Test name
Test status
Simulation time 2472272909 ps
CPU time 26.92 seconds
Started Mar 31 12:48:21 PM PDT 24
Finished Mar 31 12:48:48 PM PDT 24
Peak memory 240664 kb
Host smart-0aa28dac-72f2-4b26-9e44-ace7a75d4956
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2773759578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2773759578
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1171559257
Short name T41
Test name
Test status
Simulation time 451628416 ps
CPU time 35.51 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 12:48:57 PM PDT 24
Peak memory 256524 kb
Host smart-7d7098b5-e48c-4ba9-84ec-891dab17ab94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11715
59257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1171559257
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.748858060
Short name T498
Test name
Test status
Simulation time 2664470605 ps
CPU time 41.8 seconds
Started Mar 31 12:48:20 PM PDT 24
Finished Mar 31 12:49:02 PM PDT 24
Peak memory 255652 kb
Host smart-27b8bea6-caae-4a71-83da-2a2958ae1493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74885
8060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.748858060
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3026522009
Short name T690
Test name
Test status
Simulation time 185343095220 ps
CPU time 2564.47 seconds
Started Mar 31 12:48:19 PM PDT 24
Finished Mar 31 01:31:04 PM PDT 24
Peak memory 273412 kb
Host smart-85959acc-7ef6-4bd0-a318-df2fc22e499b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026522009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3026522009
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1165832446
Short name T503
Test name
Test status
Simulation time 110784684317 ps
CPU time 1752.1 seconds
Started Mar 31 12:48:23 PM PDT 24
Finished Mar 31 01:17:36 PM PDT 24
Peak memory 272852 kb
Host smart-c403f111-9581-4d3b-9aa8-8ac83fcf27c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165832446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1165832446
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.4137158977
Short name T539
Test name
Test status
Simulation time 7716614435 ps
CPU time 158.29 seconds
Started Mar 31 12:48:23 PM PDT 24
Finished Mar 31 12:51:01 PM PDT 24
Peak memory 248132 kb
Host smart-44c814ca-2e77-4fb2-9867-0afa7cc9b9f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137158977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4137158977
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.69713885
Short name T448
Test name
Test status
Simulation time 975946769 ps
CPU time 59.74 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 12:49:22 PM PDT 24
Peak memory 249204 kb
Host smart-728d2c4c-2271-44fc-832d-8061a373cda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69713
885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.69713885
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1936569467
Short name T106
Test name
Test status
Simulation time 172289424 ps
CPU time 14.59 seconds
Started Mar 31 12:48:21 PM PDT 24
Finished Mar 31 12:48:35 PM PDT 24
Peak memory 255408 kb
Host smart-7fafb478-298b-4c92-9a20-605c696865fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19365
69467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1936569467
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.302244216
Short name T28
Test name
Test status
Simulation time 749893344 ps
CPU time 11.13 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 12:48:33 PM PDT 24
Peak memory 273492 kb
Host smart-d372d400-920e-457c-8cc0-32f759973e97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=302244216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.302244216
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1875066569
Short name T244
Test name
Test status
Simulation time 333274847 ps
CPU time 21.29 seconds
Started Mar 31 12:48:23 PM PDT 24
Finished Mar 31 12:48:44 PM PDT 24
Peak memory 255972 kb
Host smart-e675f447-ce97-439c-a7eb-3ff454edc8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18750
66569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1875066569
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1826368371
Short name T372
Test name
Test status
Simulation time 4996183304 ps
CPU time 41.09 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 12:49:03 PM PDT 24
Peak memory 249332 kb
Host smart-2d83ec62-9e5b-41ab-a124-8be153b016c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18263
68371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1826368371
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1976015750
Short name T447
Test name
Test status
Simulation time 835647720 ps
CPU time 57.78 seconds
Started Mar 31 12:48:20 PM PDT 24
Finished Mar 31 12:49:18 PM PDT 24
Peak memory 255408 kb
Host smart-f9dc76f5-3c62-4283-be50-d8280a0326b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976015750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1976015750
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.776796258
Short name T288
Test name
Test status
Simulation time 44625488395 ps
CPU time 2710.64 seconds
Started Mar 31 12:49:30 PM PDT 24
Finished Mar 31 01:34:41 PM PDT 24
Peak memory 289136 kb
Host smart-e1f197c3-1746-49d7-9ee4-cb8c0598505e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776796258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.776796258
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1273098001
Short name T465
Test name
Test status
Simulation time 6804404993 ps
CPU time 108.42 seconds
Started Mar 31 12:49:30 PM PDT 24
Finished Mar 31 12:51:18 PM PDT 24
Peak memory 256756 kb
Host smart-a9a206fd-52ac-4b2a-b442-89030c15c2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12730
98001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1273098001
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.476117557
Short name T80
Test name
Test status
Simulation time 492155082 ps
CPU time 31.31 seconds
Started Mar 31 12:49:31 PM PDT 24
Finished Mar 31 12:50:02 PM PDT 24
Peak memory 255892 kb
Host smart-1dbf34a2-7af6-4651-9021-e054a30740c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47611
7557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.476117557
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3307683132
Short name T324
Test name
Test status
Simulation time 11062572041 ps
CPU time 923.58 seconds
Started Mar 31 12:49:29 PM PDT 24
Finished Mar 31 01:04:53 PM PDT 24
Peak memory 269472 kb
Host smart-fb29dacc-975e-41e6-a54d-54c3c68a6d1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307683132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3307683132
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1395857651
Short name T450
Test name
Test status
Simulation time 97539627864 ps
CPU time 2114.76 seconds
Started Mar 31 12:49:34 PM PDT 24
Finished Mar 31 01:24:49 PM PDT 24
Peak memory 273532 kb
Host smart-63e81d99-13a5-43a4-bf3a-d5dac6598813
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395857651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1395857651
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1913769674
Short name T309
Test name
Test status
Simulation time 31302585963 ps
CPU time 362.26 seconds
Started Mar 31 12:49:33 PM PDT 24
Finished Mar 31 12:55:35 PM PDT 24
Peak memory 247900 kb
Host smart-3129d1fe-1975-48f9-ba54-b440a46b89bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913769674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1913769674
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1009518142
Short name T20
Test name
Test status
Simulation time 495882399 ps
CPU time 13.15 seconds
Started Mar 31 12:49:30 PM PDT 24
Finished Mar 31 12:49:43 PM PDT 24
Peak memory 248884 kb
Host smart-556e72e9-0519-4b03-a6b2-341091fdf15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10095
18142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1009518142
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1015304129
Short name T396
Test name
Test status
Simulation time 2827718453 ps
CPU time 40.91 seconds
Started Mar 31 12:49:30 PM PDT 24
Finished Mar 31 12:50:11 PM PDT 24
Peak memory 256124 kb
Host smart-b0741e4a-da99-4c17-b2ea-9bcae9bfb5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10153
04129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1015304129
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1307620401
Short name T687
Test name
Test status
Simulation time 305991650 ps
CPU time 16.29 seconds
Started Mar 31 12:49:29 PM PDT 24
Finished Mar 31 12:49:46 PM PDT 24
Peak memory 254600 kb
Host smart-a02b91ab-aab6-4d39-a743-0e08d60320e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13076
20401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1307620401
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3386045430
Short name T66
Test name
Test status
Simulation time 129056235 ps
CPU time 10.63 seconds
Started Mar 31 12:49:34 PM PDT 24
Finished Mar 31 12:49:45 PM PDT 24
Peak memory 255444 kb
Host smart-d433f194-5b45-4f54-81bd-c4fbff478c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33860
45430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3386045430
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.695682276
Short name T61
Test name
Test status
Simulation time 35338774185 ps
CPU time 2259.33 seconds
Started Mar 31 12:49:30 PM PDT 24
Finished Mar 31 01:27:09 PM PDT 24
Peak memory 281764 kb
Host smart-1e36fbec-55dc-4933-8f6f-f20fd2408aa7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695682276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.695682276
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3593242213
Short name T75
Test name
Test status
Simulation time 228260290954 ps
CPU time 4873.2 seconds
Started Mar 31 12:49:32 PM PDT 24
Finished Mar 31 02:10:46 PM PDT 24
Peak memory 322656 kb
Host smart-8d3de3d1-f1b7-41a9-bde8-b88fcd7650ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593242213 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3593242213
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.4270751827
Short name T501
Test name
Test status
Simulation time 21811511896 ps
CPU time 1162.07 seconds
Started Mar 31 12:49:38 PM PDT 24
Finished Mar 31 01:09:00 PM PDT 24
Peak memory 272844 kb
Host smart-87a48c83-70e1-4224-9ff1-92bee4546fa0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270751827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.4270751827
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.644420527
Short name T351
Test name
Test status
Simulation time 18500083135 ps
CPU time 280.23 seconds
Started Mar 31 12:49:30 PM PDT 24
Finished Mar 31 12:54:10 PM PDT 24
Peak memory 257164 kb
Host smart-a908eeff-546d-4930-a5a2-fbb2b6571668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64442
0527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.644420527
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.148613928
Short name T537
Test name
Test status
Simulation time 261650961 ps
CPU time 26.48 seconds
Started Mar 31 12:49:30 PM PDT 24
Finished Mar 31 12:49:56 PM PDT 24
Peak memory 255564 kb
Host smart-80957988-e92e-4e49-90de-9c67c452ca1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14861
3928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.148613928
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3414748043
Short name T284
Test name
Test status
Simulation time 114770442350 ps
CPU time 1926.18 seconds
Started Mar 31 12:49:41 PM PDT 24
Finished Mar 31 01:21:47 PM PDT 24
Peak memory 282480 kb
Host smart-8302484e-5489-4508-8ab4-9cbdcf0ee786
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414748043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3414748043
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.232571267
Short name T480
Test name
Test status
Simulation time 208882025274 ps
CPU time 2785.92 seconds
Started Mar 31 12:49:44 PM PDT 24
Finished Mar 31 01:36:11 PM PDT 24
Peak memory 288784 kb
Host smart-6633615f-c3cd-4760-9780-c1387686c0e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232571267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.232571267
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2210361032
Short name T129
Test name
Test status
Simulation time 34180213366 ps
CPU time 402 seconds
Started Mar 31 12:49:41 PM PDT 24
Finished Mar 31 12:56:24 PM PDT 24
Peak memory 247836 kb
Host smart-7ff1ce86-5049-401a-89fe-930284194c00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210361032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2210361032
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1443984764
Short name T661
Test name
Test status
Simulation time 20832654 ps
CPU time 3.58 seconds
Started Mar 31 12:49:31 PM PDT 24
Finished Mar 31 12:49:35 PM PDT 24
Peak memory 240684 kb
Host smart-49d97f91-1d7c-4d1e-922e-29d9ed023491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14439
84764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1443984764
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3176469021
Short name T408
Test name
Test status
Simulation time 912157187 ps
CPU time 25.57 seconds
Started Mar 31 12:49:34 PM PDT 24
Finished Mar 31 12:50:00 PM PDT 24
Peak memory 255520 kb
Host smart-77351489-481b-462d-b5ed-fd06bfe61b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31764
69021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3176469021
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3586150263
Short name T442
Test name
Test status
Simulation time 199147141 ps
CPU time 22.13 seconds
Started Mar 31 12:49:32 PM PDT 24
Finished Mar 31 12:49:54 PM PDT 24
Peak memory 254676 kb
Host smart-866198e2-4e05-4cac-b885-815ed3dc50ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35861
50263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3586150263
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.4090226720
Short name T518
Test name
Test status
Simulation time 217755567 ps
CPU time 13.41 seconds
Started Mar 31 12:49:30 PM PDT 24
Finished Mar 31 12:49:43 PM PDT 24
Peak memory 248852 kb
Host smart-886757d4-4ecb-40b9-b30a-299a50303e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40902
26720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.4090226720
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3524369281
Short name T110
Test name
Test status
Simulation time 54558661443 ps
CPU time 941.35 seconds
Started Mar 31 12:49:40 PM PDT 24
Finished Mar 31 01:05:22 PM PDT 24
Peak memory 272820 kb
Host smart-bc19ec95-56a4-43c1-9e4f-baf28f61ee3c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524369281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3524369281
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.620168668
Short name T79
Test name
Test status
Simulation time 54443170511 ps
CPU time 1457.82 seconds
Started Mar 31 12:49:39 PM PDT 24
Finished Mar 31 01:13:57 PM PDT 24
Peak memory 286836 kb
Host smart-bc2e060b-dc4d-4257-823d-1e4fa7c496f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620168668 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.620168668
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.407977487
Short name T377
Test name
Test status
Simulation time 62097009404 ps
CPU time 1897.89 seconds
Started Mar 31 12:49:40 PM PDT 24
Finished Mar 31 01:21:19 PM PDT 24
Peak memory 271528 kb
Host smart-16048ce1-fcc9-4866-b737-53b0785ee7af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407977487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.407977487
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1559835
Short name T18
Test name
Test status
Simulation time 1888223873 ps
CPU time 103.03 seconds
Started Mar 31 12:49:44 PM PDT 24
Finished Mar 31 12:51:28 PM PDT 24
Peak memory 251180 kb
Host smart-fa4f2cc7-cb91-40a6-ba54-b2bcb4a4779b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15598
35 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1559835
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3065581695
Short name T541
Test name
Test status
Simulation time 2002527326 ps
CPU time 29.15 seconds
Started Mar 31 12:49:38 PM PDT 24
Finished Mar 31 12:50:08 PM PDT 24
Peak memory 254708 kb
Host smart-39cb7439-aad7-4a08-9e96-8905c3d992dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30655
81695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3065581695
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1191839233
Short name T602
Test name
Test status
Simulation time 56685906284 ps
CPU time 2932.65 seconds
Started Mar 31 12:49:37 PM PDT 24
Finished Mar 31 01:38:30 PM PDT 24
Peak memory 289448 kb
Host smart-631f32d6-10bf-42e3-8dbe-5a85c94229f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191839233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1191839233
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2717918909
Short name T486
Test name
Test status
Simulation time 105848911844 ps
CPU time 1846.45 seconds
Started Mar 31 12:49:38 PM PDT 24
Finished Mar 31 01:20:25 PM PDT 24
Peak memory 283300 kb
Host smart-603b8211-fb6b-463f-8bfc-90c7919dff21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717918909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2717918909
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1292592657
Short name T295
Test name
Test status
Simulation time 14710280551 ps
CPU time 472.89 seconds
Started Mar 31 12:49:40 PM PDT 24
Finished Mar 31 12:57:33 PM PDT 24
Peak memory 247908 kb
Host smart-a0b2ad0e-c1e8-4dfa-a0a8-0b21154f3e43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292592657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1292592657
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3289210284
Short name T374
Test name
Test status
Simulation time 340662292 ps
CPU time 27.45 seconds
Started Mar 31 12:49:40 PM PDT 24
Finished Mar 31 12:50:08 PM PDT 24
Peak memory 255964 kb
Host smart-03003fd2-a409-40e7-a1e3-093a5ceb10dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32892
10284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3289210284
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1525046051
Short name T644
Test name
Test status
Simulation time 214070551 ps
CPU time 14.08 seconds
Started Mar 31 12:49:40 PM PDT 24
Finished Mar 31 12:49:55 PM PDT 24
Peak memory 248868 kb
Host smart-858e08de-30a1-448f-9a32-540e8ecd20da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15250
46051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1525046051
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3533305344
Short name T252
Test name
Test status
Simulation time 156508500 ps
CPU time 17.05 seconds
Started Mar 31 12:49:35 PM PDT 24
Finished Mar 31 12:49:53 PM PDT 24
Peak memory 247400 kb
Host smart-c359d652-7f18-4212-90aa-0a7b9cdc1690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35333
05344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3533305344
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2162416884
Short name T378
Test name
Test status
Simulation time 803503470 ps
CPU time 38.84 seconds
Started Mar 31 12:49:35 PM PDT 24
Finished Mar 31 12:50:15 PM PDT 24
Peak memory 256044 kb
Host smart-39eb83b4-8e53-4d13-ac2a-055522ed58e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21624
16884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2162416884
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2850011726
Short name T237
Test name
Test status
Simulation time 16683215837 ps
CPU time 1273.42 seconds
Started Mar 31 12:49:43 PM PDT 24
Finished Mar 31 01:10:57 PM PDT 24
Peak memory 286616 kb
Host smart-16ebc95b-41c1-4f32-9c33-525ef155873e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850011726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2850011726
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2476776656
Short name T107
Test name
Test status
Simulation time 141905029477 ps
CPU time 2114.56 seconds
Started Mar 31 12:49:38 PM PDT 24
Finished Mar 31 01:24:53 PM PDT 24
Peak memory 281776 kb
Host smart-88dc0bdb-1d93-4f06-b70f-956e3828ad27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476776656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2476776656
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1809927975
Short name T475
Test name
Test status
Simulation time 2912029242 ps
CPU time 36.55 seconds
Started Mar 31 12:49:37 PM PDT 24
Finished Mar 31 12:50:14 PM PDT 24
Peak memory 248712 kb
Host smart-3c41c473-91de-4111-a278-236b89ca0226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18099
27975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1809927975
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1650761873
Short name T484
Test name
Test status
Simulation time 828501094 ps
CPU time 33.76 seconds
Started Mar 31 12:49:37 PM PDT 24
Finished Mar 31 12:50:12 PM PDT 24
Peak memory 254872 kb
Host smart-19245246-982e-42ff-a0d9-5285b85115d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16507
61873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1650761873
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.881378285
Short name T640
Test name
Test status
Simulation time 8817179064 ps
CPU time 703.83 seconds
Started Mar 31 12:49:46 PM PDT 24
Finished Mar 31 01:01:30 PM PDT 24
Peak memory 273120 kb
Host smart-246d0294-c1fa-4995-91b9-c7868837303b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881378285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.881378285
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.759820308
Short name T269
Test name
Test status
Simulation time 92548021809 ps
CPU time 1348.04 seconds
Started Mar 31 12:49:46 PM PDT 24
Finished Mar 31 01:12:15 PM PDT 24
Peak memory 273344 kb
Host smart-412cf282-d017-4f7d-9193-cae8cd3a6ff4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759820308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.759820308
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2471478585
Short name T390
Test name
Test status
Simulation time 197387853 ps
CPU time 16 seconds
Started Mar 31 12:49:40 PM PDT 24
Finished Mar 31 12:49:56 PM PDT 24
Peak memory 255536 kb
Host smart-39636d0d-c4a4-451e-9b32-0c09cc4a307c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24714
78585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2471478585
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1223816851
Short name T706
Test name
Test status
Simulation time 2088296228 ps
CPU time 24.74 seconds
Started Mar 31 12:49:44 PM PDT 24
Finished Mar 31 12:50:10 PM PDT 24
Peak memory 255024 kb
Host smart-39eeab3a-3483-4fc8-b082-18b1b6f53dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12238
16851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1223816851
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.393538140
Short name T266
Test name
Test status
Simulation time 127315310 ps
CPU time 7.67 seconds
Started Mar 31 12:49:39 PM PDT 24
Finished Mar 31 12:49:47 PM PDT 24
Peak memory 248856 kb
Host smart-6d53501a-b7ec-41af-9491-be3ccebc8a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39353
8140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.393538140
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.4004387018
Short name T279
Test name
Test status
Simulation time 377253777 ps
CPU time 23.87 seconds
Started Mar 31 12:49:41 PM PDT 24
Finished Mar 31 12:50:05 PM PDT 24
Peak memory 248728 kb
Host smart-1b598237-50a2-4145-adf5-9d99303efb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40043
87018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.4004387018
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1915473051
Short name T662
Test name
Test status
Simulation time 76555021073 ps
CPU time 2300.37 seconds
Started Mar 31 12:49:45 PM PDT 24
Finished Mar 31 01:28:06 PM PDT 24
Peak memory 289880 kb
Host smart-2aba7856-c9ee-4466-a54e-a3ee902316d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915473051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1915473051
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.4092473426
Short name T189
Test name
Test status
Simulation time 1113019793217 ps
CPU time 6198.44 seconds
Started Mar 31 12:49:45 PM PDT 24
Finished Mar 31 02:33:04 PM PDT 24
Peak memory 303868 kb
Host smart-b4b85278-97fa-48dc-9e19-e2dd7d71f741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092473426 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.4092473426
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2894116523
Short name T43
Test name
Test status
Simulation time 55979871856 ps
CPU time 1860.75 seconds
Started Mar 31 12:49:44 PM PDT 24
Finished Mar 31 01:20:46 PM PDT 24
Peak memory 284532 kb
Host smart-8d077b0e-8e6f-4302-8c89-1fdf39ca2266
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894116523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2894116523
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1486037302
Short name T40
Test name
Test status
Simulation time 3160179701 ps
CPU time 94.36 seconds
Started Mar 31 12:49:44 PM PDT 24
Finished Mar 31 12:51:19 PM PDT 24
Peak memory 256760 kb
Host smart-b30e4665-9c9b-449a-8b92-66279f8edbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14860
37302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1486037302
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.610324295
Short name T247
Test name
Test status
Simulation time 980199543 ps
CPU time 51.96 seconds
Started Mar 31 12:49:45 PM PDT 24
Finished Mar 31 12:50:37 PM PDT 24
Peak memory 256124 kb
Host smart-9e1e77bc-d629-417b-9031-244a3dee5d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61032
4295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.610324295
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2399642281
Short name T519
Test name
Test status
Simulation time 71396113568 ps
CPU time 2050.38 seconds
Started Mar 31 12:49:46 PM PDT 24
Finished Mar 31 01:23:57 PM PDT 24
Peak memory 270452 kb
Host smart-dd7b3581-d39c-4a67-8620-dfd0f53597af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399642281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2399642281
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1544567793
Short name T425
Test name
Test status
Simulation time 19401831893 ps
CPU time 1394.71 seconds
Started Mar 31 12:49:44 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 273528 kb
Host smart-0c2826e9-d0c3-4d35-8414-8cbd3154b44a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544567793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1544567793
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1874933179
Short name T688
Test name
Test status
Simulation time 90414255812 ps
CPU time 455.6 seconds
Started Mar 31 12:49:44 PM PDT 24
Finished Mar 31 12:57:20 PM PDT 24
Peak memory 247128 kb
Host smart-21f40f50-42f9-44fb-8601-b7e6faa3ce0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874933179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1874933179
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2677924604
Short name T39
Test name
Test status
Simulation time 1362854243 ps
CPU time 32.67 seconds
Started Mar 31 12:49:47 PM PDT 24
Finished Mar 31 12:50:20 PM PDT 24
Peak memory 248908 kb
Host smart-c8145c52-b76c-4c69-9596-12ad3a9a2e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26779
24604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2677924604
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.795901621
Short name T99
Test name
Test status
Simulation time 549199012 ps
CPU time 38.05 seconds
Started Mar 31 12:49:44 PM PDT 24
Finished Mar 31 12:50:23 PM PDT 24
Peak memory 255884 kb
Host smart-908a0992-9c46-49ae-bbcb-edb705e93fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79590
1621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.795901621
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1111725767
Short name T258
Test name
Test status
Simulation time 2293556064 ps
CPU time 71.84 seconds
Started Mar 31 12:49:45 PM PDT 24
Finished Mar 31 12:50:57 PM PDT 24
Peak memory 254840 kb
Host smart-905b62f3-b9e9-45ea-a483-c11ee8f4141c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11117
25767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1111725767
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.40518456
Short name T380
Test name
Test status
Simulation time 1250095630 ps
CPU time 26.5 seconds
Started Mar 31 12:49:44 PM PDT 24
Finished Mar 31 12:50:11 PM PDT 24
Peak memory 248844 kb
Host smart-f34dee19-9696-4512-8feb-7034e23e8ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40518
456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.40518456
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3538812571
Short name T695
Test name
Test status
Simulation time 52181827381 ps
CPU time 2954.91 seconds
Started Mar 31 12:49:51 PM PDT 24
Finished Mar 31 01:39:06 PM PDT 24
Peak memory 281768 kb
Host smart-be13bdd2-5229-4097-876d-6dec3e2ce2d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538812571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3538812571
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1824548591
Short name T630
Test name
Test status
Simulation time 1944255620 ps
CPU time 26.69 seconds
Started Mar 31 12:49:51 PM PDT 24
Finished Mar 31 12:50:18 PM PDT 24
Peak memory 254968 kb
Host smart-089d1c18-c306-4eed-be68-1b7a2b8169a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18245
48591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1824548591
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1912196252
Short name T578
Test name
Test status
Simulation time 1156298827 ps
CPU time 31.5 seconds
Started Mar 31 12:49:53 PM PDT 24
Finished Mar 31 12:50:25 PM PDT 24
Peak memory 254884 kb
Host smart-df089596-93e6-4032-87e3-c3ce19b5476c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19121
96252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1912196252
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3748488163
Short name T556
Test name
Test status
Simulation time 169304030490 ps
CPU time 1286.11 seconds
Started Mar 31 12:49:53 PM PDT 24
Finished Mar 31 01:11:20 PM PDT 24
Peak memory 284236 kb
Host smart-807f77c5-d147-4b26-8129-fb9c432dc22b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748488163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3748488163
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1857714703
Short name T435
Test name
Test status
Simulation time 158220161665 ps
CPU time 2713.37 seconds
Started Mar 31 12:49:53 PM PDT 24
Finished Mar 31 01:35:07 PM PDT 24
Peak memory 289324 kb
Host smart-0b732e9b-36b7-4541-930f-e31fc04e8f3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857714703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1857714703
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1689636238
Short name T213
Test name
Test status
Simulation time 1336708201 ps
CPU time 43.75 seconds
Started Mar 31 12:49:51 PM PDT 24
Finished Mar 31 12:50:35 PM PDT 24
Peak memory 249108 kb
Host smart-f476a0ca-f87f-4f9d-b4a7-8ac438e50cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16896
36238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1689636238
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.4156773258
Short name T45
Test name
Test status
Simulation time 470821566 ps
CPU time 15.39 seconds
Started Mar 31 12:49:52 PM PDT 24
Finished Mar 31 12:50:08 PM PDT 24
Peak memory 247364 kb
Host smart-abd9a192-ccc2-465c-87c6-3dae7edbd075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41567
73258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4156773258
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3887389833
Short name T270
Test name
Test status
Simulation time 746445560 ps
CPU time 41.39 seconds
Started Mar 31 12:49:50 PM PDT 24
Finished Mar 31 12:50:32 PM PDT 24
Peak memory 256780 kb
Host smart-b926ec3c-9db5-4586-8f2d-5128d2d3e631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38873
89833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3887389833
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1923797171
Short name T421
Test name
Test status
Simulation time 1383916088 ps
CPU time 43.49 seconds
Started Mar 31 12:49:45 PM PDT 24
Finished Mar 31 12:50:29 PM PDT 24
Peak memory 257036 kb
Host smart-1f60551a-a5f8-41c4-ba08-aa216ff98aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19237
97171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1923797171
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2961156409
Short name T431
Test name
Test status
Simulation time 194519412824 ps
CPU time 1374.95 seconds
Started Mar 31 12:49:50 PM PDT 24
Finished Mar 31 01:12:45 PM PDT 24
Peak memory 288720 kb
Host smart-94e729f6-ce62-40f6-ad94-1543ce319c23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961156409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2961156409
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.246518513
Short name T365
Test name
Test status
Simulation time 1304821411 ps
CPU time 24.6 seconds
Started Mar 31 12:49:55 PM PDT 24
Finished Mar 31 12:50:20 PM PDT 24
Peak memory 255756 kb
Host smart-495e2e87-c77b-4813-bdb6-674db01bea3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24651
8513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.246518513
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2340720141
Short name T586
Test name
Test status
Simulation time 689867628 ps
CPU time 33.13 seconds
Started Mar 31 12:49:55 PM PDT 24
Finished Mar 31 12:50:28 PM PDT 24
Peak memory 255752 kb
Host smart-fd42daff-7e35-42aa-8bd8-b241dbc5d4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23407
20141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2340720141
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.815898497
Short name T5
Test name
Test status
Simulation time 4947804615 ps
CPU time 57.07 seconds
Started Mar 31 12:49:53 PM PDT 24
Finished Mar 31 12:50:51 PM PDT 24
Peak memory 247112 kb
Host smart-6378ed7a-1c36-486f-8560-1b05c219f48a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815898497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.815898497
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.639275726
Short name T31
Test name
Test status
Simulation time 246830780 ps
CPU time 7.18 seconds
Started Mar 31 12:49:50 PM PDT 24
Finished Mar 31 12:49:58 PM PDT 24
Peak memory 248700 kb
Host smart-ee8b035b-7c20-4e34-aaec-3554c14b7bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63927
5726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.639275726
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2847942156
Short name T682
Test name
Test status
Simulation time 4464693256 ps
CPU time 42.9 seconds
Started Mar 31 12:49:51 PM PDT 24
Finished Mar 31 12:50:34 PM PDT 24
Peak memory 256232 kb
Host smart-e9cf8ad7-011e-4b6a-950d-f0512953c52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28479
42156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2847942156
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2517923002
Short name T608
Test name
Test status
Simulation time 1677379604 ps
CPU time 24.28 seconds
Started Mar 31 12:49:53 PM PDT 24
Finished Mar 31 12:50:17 PM PDT 24
Peak memory 254660 kb
Host smart-8be927bb-ca8a-4934-ba1f-18aa7e79bc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25179
23002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2517923002
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.4008418178
Short name T588
Test name
Test status
Simulation time 65480555 ps
CPU time 7.17 seconds
Started Mar 31 12:49:52 PM PDT 24
Finished Mar 31 12:49:59 PM PDT 24
Peak memory 254220 kb
Host smart-6574e2d1-401a-44f8-b230-24f8c41be922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40084
18178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.4008418178
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2548494094
Short name T16
Test name
Test status
Simulation time 2595414233 ps
CPU time 37.08 seconds
Started Mar 31 12:49:58 PM PDT 24
Finished Mar 31 12:50:35 PM PDT 24
Peak memory 256412 kb
Host smart-07f038db-fd56-4ec5-83d8-7d35a98e4845
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548494094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2548494094
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2297519576
Short name T196
Test name
Test status
Simulation time 197780996610 ps
CPU time 4666.68 seconds
Started Mar 31 12:49:58 PM PDT 24
Finished Mar 31 02:07:45 PM PDT 24
Peak memory 338788 kb
Host smart-51552f16-7afe-442d-b6ca-34fa41c37531
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297519576 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2297519576
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3051867672
Short name T382
Test name
Test status
Simulation time 34324622512 ps
CPU time 1820.16 seconds
Started Mar 31 12:49:58 PM PDT 24
Finished Mar 31 01:20:19 PM PDT 24
Peak memory 282888 kb
Host smart-0d4fe7e5-3910-4452-b2d8-99faac722920
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051867672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3051867672
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.610718948
Short name T638
Test name
Test status
Simulation time 22822956708 ps
CPU time 149.7 seconds
Started Mar 31 12:50:00 PM PDT 24
Finished Mar 31 12:52:30 PM PDT 24
Peak memory 251492 kb
Host smart-42f692e0-7b0a-498f-9ffd-0c0e03a2b902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61071
8948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.610718948
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.116987127
Short name T705
Test name
Test status
Simulation time 2681950042 ps
CPU time 44.32 seconds
Started Mar 31 12:49:59 PM PDT 24
Finished Mar 31 12:50:43 PM PDT 24
Peak memory 248884 kb
Host smart-a2ee553e-9d03-4803-8968-b3438cd98b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11698
7127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.116987127
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1180943966
Short name T315
Test name
Test status
Simulation time 176869243190 ps
CPU time 2570.54 seconds
Started Mar 31 12:49:57 PM PDT 24
Finished Mar 31 01:32:48 PM PDT 24
Peak memory 289468 kb
Host smart-368fbbfb-84ad-4a03-9aa3-55248e8ff5d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180943966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1180943966
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.859148194
Short name T579
Test name
Test status
Simulation time 16556938063 ps
CPU time 1584.33 seconds
Started Mar 31 12:50:03 PM PDT 24
Finished Mar 31 01:16:28 PM PDT 24
Peak memory 289316 kb
Host smart-c98980be-a07d-4c93-a0de-c4a711054b97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859148194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.859148194
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3374160942
Short name T292
Test name
Test status
Simulation time 20657722636 ps
CPU time 226.63 seconds
Started Mar 31 12:49:59 PM PDT 24
Finished Mar 31 12:53:45 PM PDT 24
Peak memory 248176 kb
Host smart-5c0eb154-8b53-482b-aa9b-e38858bba664
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374160942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3374160942
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.396166894
Short name T487
Test name
Test status
Simulation time 3506331968 ps
CPU time 57.22 seconds
Started Mar 31 12:50:00 PM PDT 24
Finished Mar 31 12:50:57 PM PDT 24
Peak memory 248904 kb
Host smart-20971171-b8b9-444a-baca-a2c3fcf8e7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39616
6894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.396166894
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3526910892
Short name T35
Test name
Test status
Simulation time 676400384 ps
CPU time 36.56 seconds
Started Mar 31 12:49:57 PM PDT 24
Finished Mar 31 12:50:34 PM PDT 24
Peak memory 249128 kb
Host smart-e451b027-77ae-4352-a376-2c9a43b1813b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35269
10892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3526910892
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.580296113
Short name T676
Test name
Test status
Simulation time 588887537 ps
CPU time 33.99 seconds
Started Mar 31 12:49:59 PM PDT 24
Finished Mar 31 12:50:33 PM PDT 24
Peak memory 254480 kb
Host smart-e8398472-b565-4aff-a103-bd2d475ec1cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58029
6113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.580296113
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.596353935
Short name T666
Test name
Test status
Simulation time 1043009536 ps
CPU time 6.01 seconds
Started Mar 31 12:49:59 PM PDT 24
Finished Mar 31 12:50:05 PM PDT 24
Peak memory 248832 kb
Host smart-a38a0729-10c5-46f9-b8cc-f76e38cb14a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59635
3935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.596353935
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3534064860
Short name T86
Test name
Test status
Simulation time 56200236453 ps
CPU time 1526.48 seconds
Started Mar 31 12:50:05 PM PDT 24
Finished Mar 31 01:15:31 PM PDT 24
Peak memory 273148 kb
Host smart-bf10305f-7a01-4fce-8056-59e38209b38b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534064860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3534064860
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3419028492
Short name T643
Test name
Test status
Simulation time 68867615795 ps
CPU time 1471.24 seconds
Started Mar 31 12:50:07 PM PDT 24
Finished Mar 31 01:14:38 PM PDT 24
Peak memory 266400 kb
Host smart-62125ca7-1a4a-4e97-97de-6107e96e152e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419028492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3419028492
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1652337151
Short name T281
Test name
Test status
Simulation time 5221169969 ps
CPU time 266.67 seconds
Started Mar 31 12:50:04 PM PDT 24
Finished Mar 31 12:54:31 PM PDT 24
Peak memory 256916 kb
Host smart-0784ccd6-ab25-4725-9566-9bebe673c298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16523
37151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1652337151
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3833189032
Short name T482
Test name
Test status
Simulation time 401207951 ps
CPU time 8.42 seconds
Started Mar 31 12:50:03 PM PDT 24
Finished Mar 31 12:50:12 PM PDT 24
Peak memory 253172 kb
Host smart-9b1f8559-3f05-4274-bc63-430639487cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38331
89032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3833189032
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2270838473
Short name T428
Test name
Test status
Simulation time 20112365533 ps
CPU time 932.29 seconds
Started Mar 31 12:50:06 PM PDT 24
Finished Mar 31 01:05:39 PM PDT 24
Peak memory 273576 kb
Host smart-cac753b0-f6bf-4c89-9281-4236eb52a5ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270838473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2270838473
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2247779279
Short name T655
Test name
Test status
Simulation time 686732145 ps
CPU time 16.64 seconds
Started Mar 31 12:50:05 PM PDT 24
Finished Mar 31 12:50:22 PM PDT 24
Peak memory 255836 kb
Host smart-27f94bfa-9e08-47c2-b61c-752b4b1ed43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22477
79279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2247779279
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2036219804
Short name T645
Test name
Test status
Simulation time 1291119934 ps
CPU time 28.77 seconds
Started Mar 31 12:50:05 PM PDT 24
Finished Mar 31 12:50:34 PM PDT 24
Peak memory 247744 kb
Host smart-10755770-03e5-447b-98ef-ae80517d49a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20362
19804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2036219804
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1036168101
Short name T398
Test name
Test status
Simulation time 185431596 ps
CPU time 19.7 seconds
Started Mar 31 12:50:05 PM PDT 24
Finished Mar 31 12:50:25 PM PDT 24
Peak memory 248860 kb
Host smart-04fabdd6-faeb-4d7a-9b9f-663a2d0c5b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10361
68101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1036168101
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2583856759
Short name T83
Test name
Test status
Simulation time 725558842 ps
CPU time 24.22 seconds
Started Mar 31 12:50:04 PM PDT 24
Finished Mar 31 12:50:29 PM PDT 24
Peak memory 256124 kb
Host smart-15b3c6cf-0f23-44ab-b0ee-95208e80f062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25838
56759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2583856759
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2619021999
Short name T47
Test name
Test status
Simulation time 49053768745 ps
CPU time 2619.91 seconds
Started Mar 31 12:50:05 PM PDT 24
Finished Mar 31 01:33:45 PM PDT 24
Peak memory 289820 kb
Host smart-b94f8625-5da0-4661-91cd-8683b2d1bd83
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619021999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2619021999
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3986449356
Short name T514
Test name
Test status
Simulation time 193423216874 ps
CPU time 2369.2 seconds
Started Mar 31 12:50:11 PM PDT 24
Finished Mar 31 01:29:40 PM PDT 24
Peak memory 289660 kb
Host smart-2f2558dc-425a-4f85-ad4e-0b60dd7dd6ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986449356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3986449356
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1898575442
Short name T467
Test name
Test status
Simulation time 49243267 ps
CPU time 5.91 seconds
Started Mar 31 12:50:11 PM PDT 24
Finished Mar 31 12:50:17 PM PDT 24
Peak memory 250980 kb
Host smart-01a11d20-cd2a-4750-b97f-0b2f2a88d9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18985
75442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1898575442
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1726114177
Short name T531
Test name
Test status
Simulation time 749840453 ps
CPU time 27.3 seconds
Started Mar 31 12:50:11 PM PDT 24
Finished Mar 31 12:50:38 PM PDT 24
Peak memory 255620 kb
Host smart-637d08a0-3207-408d-ba4d-431f1d9a6194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17261
14177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1726114177
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.600911979
Short name T321
Test name
Test status
Simulation time 32603224044 ps
CPU time 1966.67 seconds
Started Mar 31 12:50:15 PM PDT 24
Finished Mar 31 01:23:02 PM PDT 24
Peak memory 281696 kb
Host smart-f1f5f966-4f07-407a-aa3d-a08c45416198
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600911979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.600911979
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1590629274
Short name T114
Test name
Test status
Simulation time 23322094631 ps
CPU time 1396.43 seconds
Started Mar 31 12:50:12 PM PDT 24
Finished Mar 31 01:13:28 PM PDT 24
Peak memory 272332 kb
Host smart-97eb9e90-5bfc-4f65-9163-9a2579b6e0fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590629274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1590629274
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.4174555109
Short name T298
Test name
Test status
Simulation time 6323237388 ps
CPU time 269.5 seconds
Started Mar 31 12:50:13 PM PDT 24
Finished Mar 31 12:54:43 PM PDT 24
Peak memory 247868 kb
Host smart-9ee698c8-194c-46ff-a2c6-84583e63424a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174555109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.4174555109
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1612046091
Short name T555
Test name
Test status
Simulation time 777120667 ps
CPU time 23.58 seconds
Started Mar 31 12:50:05 PM PDT 24
Finished Mar 31 12:50:29 PM PDT 24
Peak memory 256052 kb
Host smart-117eb2de-ac25-4466-9820-2a6c4a69ecf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16120
46091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1612046091
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.185133469
Short name T361
Test name
Test status
Simulation time 588858259 ps
CPU time 7.91 seconds
Started Mar 31 12:50:04 PM PDT 24
Finished Mar 31 12:50:12 PM PDT 24
Peak memory 247364 kb
Host smart-d3b34870-6849-446a-8f2a-55ae9f699b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18513
3469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.185133469
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2848970796
Short name T582
Test name
Test status
Simulation time 474821160 ps
CPU time 31.71 seconds
Started Mar 31 12:50:11 PM PDT 24
Finished Mar 31 12:50:43 PM PDT 24
Peak memory 255172 kb
Host smart-580e9d5d-f1c4-422c-920e-e915d1509926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28489
70796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2848970796
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.738491751
Short name T423
Test name
Test status
Simulation time 3755114570 ps
CPU time 54.43 seconds
Started Mar 31 12:50:06 PM PDT 24
Finished Mar 31 12:51:01 PM PDT 24
Peak memory 248796 kb
Host smart-eee9c8af-eb96-4c04-bc70-e088c4d68cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73849
1751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.738491751
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3004429211
Short name T78
Test name
Test status
Simulation time 63353670490 ps
CPU time 3464.96 seconds
Started Mar 31 12:50:13 PM PDT 24
Finished Mar 31 01:47:58 PM PDT 24
Peak memory 305044 kb
Host smart-f810db5e-5724-46d0-bbd2-3cdda2526016
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004429211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3004429211
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.280042661
Short name T208
Test name
Test status
Simulation time 117686587 ps
CPU time 3.01 seconds
Started Mar 31 12:48:20 PM PDT 24
Finished Mar 31 12:48:23 PM PDT 24
Peak memory 249000 kb
Host smart-ac860d9b-e076-4be2-9f7c-e62bc31486d8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=280042661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.280042661
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1786805795
Short name T493
Test name
Test status
Simulation time 1678684571 ps
CPU time 12.5 seconds
Started Mar 31 12:48:23 PM PDT 24
Finished Mar 31 12:48:35 PM PDT 24
Peak memory 248892 kb
Host smart-4621d3ba-0738-4326-9f47-012e8fdfd4e3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1786805795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1786805795
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.4266650545
Short name T384
Test name
Test status
Simulation time 3051415643 ps
CPU time 45.65 seconds
Started Mar 31 12:48:21 PM PDT 24
Finished Mar 31 12:49:07 PM PDT 24
Peak memory 249068 kb
Host smart-49f276ca-b6d9-46d0-98d9-931fa8648884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42666
50545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.4266650545
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1636814054
Short name T572
Test name
Test status
Simulation time 75604750212 ps
CPU time 1228.21 seconds
Started Mar 31 12:48:19 PM PDT 24
Finished Mar 31 01:08:48 PM PDT 24
Peak memory 273572 kb
Host smart-edd600cc-7a38-4112-86b5-fffeb8f6cce4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636814054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1636814054
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3269551588
Short name T73
Test name
Test status
Simulation time 9362708776 ps
CPU time 340.27 seconds
Started Mar 31 12:48:20 PM PDT 24
Finished Mar 31 12:54:01 PM PDT 24
Peak memory 247300 kb
Host smart-be3dd2e2-a86b-4689-972a-87eab67177ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269551588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3269551588
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2712235357
Short name T463
Test name
Test status
Simulation time 796111684 ps
CPU time 18.1 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 12:48:41 PM PDT 24
Peak memory 248828 kb
Host smart-c9bfbb60-421e-41ec-80f6-a518680376ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27122
35357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2712235357
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3224915931
Short name T268
Test name
Test status
Simulation time 805346170 ps
CPU time 22.2 seconds
Started Mar 31 12:48:22 PM PDT 24
Finished Mar 31 12:48:44 PM PDT 24
Peak memory 254828 kb
Host smart-2ec86e06-9e7b-46e0-970d-fd47d25b461e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32249
15931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3224915931
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3946542096
Short name T8
Test name
Test status
Simulation time 573292624 ps
CPU time 12.88 seconds
Started Mar 31 12:48:28 PM PDT 24
Finished Mar 31 12:48:41 PM PDT 24
Peak memory 277648 kb
Host smart-41f87149-91ca-4c52-9cd8-55c1a4cea9ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3946542096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3946542096
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3136135313
Short name T379
Test name
Test status
Simulation time 422843062 ps
CPU time 12.19 seconds
Started Mar 31 12:48:21 PM PDT 24
Finished Mar 31 12:48:33 PM PDT 24
Peak memory 255720 kb
Host smart-0ff94130-3167-44bb-af59-b97deb40f446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31361
35313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3136135313
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2816254034
Short name T89
Test name
Test status
Simulation time 1380244112 ps
CPU time 64.47 seconds
Started Mar 31 12:48:20 PM PDT 24
Finished Mar 31 12:49:25 PM PDT 24
Peak memory 255976 kb
Host smart-cc93cbff-3156-458e-9e2e-e6cd8c972034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28162
54034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2816254034
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3054636063
Short name T613
Test name
Test status
Simulation time 5552728169 ps
CPU time 251.83 seconds
Started Mar 31 12:48:21 PM PDT 24
Finished Mar 31 12:52:33 PM PDT 24
Peak memory 257196 kb
Host smart-dcdadfb8-1796-47f5-9fad-c420d847d24e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054636063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3054636063
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2415019401
Short name T686
Test name
Test status
Simulation time 35295528455 ps
CPU time 2232.77 seconds
Started Mar 31 12:50:19 PM PDT 24
Finished Mar 31 01:27:32 PM PDT 24
Peak memory 289660 kb
Host smart-8c79f2e5-2e43-4c35-8c75-f17c0eef8712
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415019401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2415019401
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.944052161
Short name T349
Test name
Test status
Simulation time 2444274802 ps
CPU time 158.96 seconds
Started Mar 31 12:50:10 PM PDT 24
Finished Mar 31 12:52:49 PM PDT 24
Peak memory 257108 kb
Host smart-2d8f34af-738a-4f53-a501-dfd187abf47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94405
2161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.944052161
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3981919384
Short name T479
Test name
Test status
Simulation time 157773935 ps
CPU time 6.57 seconds
Started Mar 31 12:50:11 PM PDT 24
Finished Mar 31 12:50:18 PM PDT 24
Peak memory 248856 kb
Host smart-8f3990a6-9917-4e8d-9734-c5a7e24247e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39819
19384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3981919384
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3624059521
Short name T330
Test name
Test status
Simulation time 183850555581 ps
CPU time 2558.27 seconds
Started Mar 31 12:50:22 PM PDT 24
Finished Mar 31 01:33:01 PM PDT 24
Peak memory 289144 kb
Host smart-9831fd91-26bf-4335-876a-dfab41709ff5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624059521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3624059521
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2723779984
Short name T477
Test name
Test status
Simulation time 13181400518 ps
CPU time 1056.36 seconds
Started Mar 31 12:50:21 PM PDT 24
Finished Mar 31 01:07:58 PM PDT 24
Peak memory 273532 kb
Host smart-3bcc2488-ca0c-4c33-8296-65fc9ec852bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723779984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2723779984
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2380405846
Short name T312
Test name
Test status
Simulation time 6440189244 ps
CPU time 276.05 seconds
Started Mar 31 12:50:22 PM PDT 24
Finished Mar 31 12:54:58 PM PDT 24
Peak memory 247896 kb
Host smart-1ca9a4b8-c397-4e97-9712-4b767fd3305a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380405846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2380405846
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2785314359
Short name T456
Test name
Test status
Simulation time 1661147750 ps
CPU time 23.78 seconds
Started Mar 31 12:50:11 PM PDT 24
Finished Mar 31 12:50:35 PM PDT 24
Peak memory 254964 kb
Host smart-c2a1620e-a8f0-484b-a0d8-36aec2f8cc0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27853
14359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2785314359
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.293443494
Short name T424
Test name
Test status
Simulation time 678935046 ps
CPU time 26.74 seconds
Started Mar 31 12:50:11 PM PDT 24
Finished Mar 31 12:50:38 PM PDT 24
Peak memory 249196 kb
Host smart-76e5037a-669e-4ac8-b3f0-01c8a71564ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29344
3494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.293443494
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.347451449
Short name T388
Test name
Test status
Simulation time 61023278 ps
CPU time 3.19 seconds
Started Mar 31 12:50:10 PM PDT 24
Finished Mar 31 12:50:14 PM PDT 24
Peak memory 239228 kb
Host smart-04a9cd00-98c3-4b1c-89aa-899f07b497da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34745
1449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.347451449
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.103371268
Short name T618
Test name
Test status
Simulation time 1097318223 ps
CPU time 62.48 seconds
Started Mar 31 12:50:12 PM PDT 24
Finished Mar 31 12:51:14 PM PDT 24
Peak memory 248788 kb
Host smart-c1a9744e-6533-47dc-821d-c50dde10bef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10337
1268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.103371268
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2366509783
Short name T120
Test name
Test status
Simulation time 27636995392 ps
CPU time 1464.28 seconds
Started Mar 31 12:50:21 PM PDT 24
Finished Mar 31 01:14:46 PM PDT 24
Peak memory 272684 kb
Host smart-cad0844a-c146-4fa9-8ae3-6fc218c13aaa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366509783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2366509783
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.511778449
Short name T119
Test name
Test status
Simulation time 49097477423 ps
CPU time 3084.25 seconds
Started Mar 31 12:50:17 PM PDT 24
Finished Mar 31 01:41:42 PM PDT 24
Peak memory 297940 kb
Host smart-745c9516-a2b5-48d1-90fe-737266f19288
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511778449 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.511778449
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3713987417
Short name T221
Test name
Test status
Simulation time 9708329660 ps
CPU time 1175.74 seconds
Started Mar 31 12:50:20 PM PDT 24
Finished Mar 31 01:09:56 PM PDT 24
Peak memory 289320 kb
Host smart-67a4e7b1-2d4a-4759-a736-486b09981dc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713987417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3713987417
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.781250822
Short name T277
Test name
Test status
Simulation time 1003336160 ps
CPU time 40.69 seconds
Started Mar 31 12:50:20 PM PDT 24
Finished Mar 31 12:51:01 PM PDT 24
Peak memory 256784 kb
Host smart-61b2eb89-5256-425e-9a86-fee9f004a195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78125
0822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.781250822
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.41033438
Short name T694
Test name
Test status
Simulation time 1294048359 ps
CPU time 30.85 seconds
Started Mar 31 12:50:16 PM PDT 24
Finished Mar 31 12:50:47 PM PDT 24
Peak memory 248884 kb
Host smart-9b53828b-a834-438e-81b3-56bb11a8e70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41033
438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.41033438
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3305174633
Short name T332
Test name
Test status
Simulation time 10636932848 ps
CPU time 861.11 seconds
Started Mar 31 12:50:20 PM PDT 24
Finished Mar 31 01:04:42 PM PDT 24
Peak memory 272588 kb
Host smart-c239eac6-3f3b-406e-b061-9b66f158865f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305174633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3305174633
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2833128660
Short name T571
Test name
Test status
Simulation time 50538271327 ps
CPU time 926.15 seconds
Started Mar 31 12:50:23 PM PDT 24
Finished Mar 31 01:05:50 PM PDT 24
Peak memory 272940 kb
Host smart-e8ea37f0-fd44-4c49-b9d5-ad296a04097d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833128660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2833128660
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2430469011
Short name T294
Test name
Test status
Simulation time 108338161693 ps
CPU time 284.92 seconds
Started Mar 31 12:50:19 PM PDT 24
Finished Mar 31 12:55:04 PM PDT 24
Peak memory 247928 kb
Host smart-920c3fb6-9273-471c-bbc3-039b2c89ea83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430469011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2430469011
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2214421458
Short name T591
Test name
Test status
Simulation time 962628417 ps
CPU time 12.37 seconds
Started Mar 31 12:50:20 PM PDT 24
Finished Mar 31 12:50:32 PM PDT 24
Peak memory 254300 kb
Host smart-9a9558df-3f00-4814-9cde-e8547984d80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22144
21458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2214421458
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3952628670
Short name T36
Test name
Test status
Simulation time 1137241690 ps
CPU time 11.95 seconds
Started Mar 31 12:50:18 PM PDT 24
Finished Mar 31 12:50:30 PM PDT 24
Peak memory 252700 kb
Host smart-e7b2626e-1ab1-4cfc-a8ba-210ce30f1f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39526
28670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3952628670
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1763823878
Short name T256
Test name
Test status
Simulation time 3472794858 ps
CPU time 48.05 seconds
Started Mar 31 12:50:19 PM PDT 24
Finished Mar 31 12:51:07 PM PDT 24
Peak memory 247784 kb
Host smart-58e9e7ca-843c-4dc9-9a1a-a347d6942a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17638
23878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1763823878
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.386851804
Short name T26
Test name
Test status
Simulation time 871178404 ps
CPU time 49.72 seconds
Started Mar 31 12:50:16 PM PDT 24
Finished Mar 31 12:51:05 PM PDT 24
Peak memory 249132 kb
Host smart-b99f8612-4833-46fd-a7b9-c2fa902ee82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38685
1804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.386851804
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3393444680
Short name T243
Test name
Test status
Simulation time 194550371158 ps
CPU time 3265.16 seconds
Started Mar 31 12:50:24 PM PDT 24
Finished Mar 31 01:44:49 PM PDT 24
Peak memory 300968 kb
Host smart-95307836-343b-48d6-ab5b-0f3e56c84d73
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393444680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3393444680
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.983695318
Short name T568
Test name
Test status
Simulation time 140488624623 ps
CPU time 2192.91 seconds
Started Mar 31 12:50:23 PM PDT 24
Finished Mar 31 01:26:57 PM PDT 24
Peak memory 284012 kb
Host smart-44aa375d-01a1-4699-8956-87a8b3e347b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983695318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.983695318
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.992662526
Short name T511
Test name
Test status
Simulation time 14017701090 ps
CPU time 243.18 seconds
Started Mar 31 12:50:27 PM PDT 24
Finished Mar 31 12:54:30 PM PDT 24
Peak memory 257132 kb
Host smart-24358780-8f4d-4c36-a84e-d2ff36964d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99266
2526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.992662526
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.962946873
Short name T434
Test name
Test status
Simulation time 50921820 ps
CPU time 3.99 seconds
Started Mar 31 12:50:26 PM PDT 24
Finished Mar 31 12:50:31 PM PDT 24
Peak memory 240628 kb
Host smart-cb079635-a8f8-4396-8fd6-d3718d89c984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96294
6873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.962946873
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3011826699
Short name T276
Test name
Test status
Simulation time 99159803250 ps
CPU time 2757.09 seconds
Started Mar 31 12:50:24 PM PDT 24
Finished Mar 31 01:36:22 PM PDT 24
Peak memory 281748 kb
Host smart-e1b3ee9e-994b-47ce-b5a7-4a0def24ab9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011826699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3011826699
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1512572933
Short name T94
Test name
Test status
Simulation time 32264199456 ps
CPU time 1261.06 seconds
Started Mar 31 12:50:26 PM PDT 24
Finished Mar 31 01:11:27 PM PDT 24
Peak memory 281712 kb
Host smart-74f7bccf-d0b1-41d6-a093-f8543b9b633a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512572933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1512572933
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.671737304
Short name T293
Test name
Test status
Simulation time 33533470308 ps
CPU time 353.74 seconds
Started Mar 31 12:50:23 PM PDT 24
Finished Mar 31 12:56:17 PM PDT 24
Peak memory 248276 kb
Host smart-ed7792eb-983d-4eb3-95e4-78ae3904c3b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671737304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.671737304
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2539199099
Short name T391
Test name
Test status
Simulation time 445425874 ps
CPU time 35.7 seconds
Started Mar 31 12:50:23 PM PDT 24
Finished Mar 31 12:50:58 PM PDT 24
Peak memory 248876 kb
Host smart-6bfe512e-1331-4c02-841b-0431b826b6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25391
99099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2539199099
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2051143964
Short name T527
Test name
Test status
Simulation time 400896640 ps
CPU time 23.56 seconds
Started Mar 31 12:50:22 PM PDT 24
Finished Mar 31 12:50:46 PM PDT 24
Peak memory 255600 kb
Host smart-0a1956db-30ea-4a2e-9924-b3db9c4bc877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20511
43964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2051143964
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3462921603
Short name T610
Test name
Test status
Simulation time 339468736 ps
CPU time 21.12 seconds
Started Mar 31 12:50:27 PM PDT 24
Finished Mar 31 12:50:48 PM PDT 24
Peak memory 254872 kb
Host smart-7db797b2-3401-4467-a157-8950dbb534e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34629
21603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3462921603
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.235553687
Short name T432
Test name
Test status
Simulation time 624569968 ps
CPU time 36.92 seconds
Started Mar 31 12:50:25 PM PDT 24
Finished Mar 31 12:51:03 PM PDT 24
Peak memory 256016 kb
Host smart-b9f059d9-06f5-47b0-aeab-fc80a8a5dab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23555
3687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.235553687
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.938749685
Short name T46
Test name
Test status
Simulation time 124701438719 ps
CPU time 3392.24 seconds
Started Mar 31 12:50:32 PM PDT 24
Finished Mar 31 01:47:04 PM PDT 24
Peak memory 289540 kb
Host smart-ff1e2ef8-5687-4c01-b6a8-9567292e6385
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938749685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.938749685
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3879099852
Short name T109
Test name
Test status
Simulation time 16779717801 ps
CPU time 1262.4 seconds
Started Mar 31 12:50:34 PM PDT 24
Finished Mar 31 01:11:36 PM PDT 24
Peak memory 289828 kb
Host smart-5c80fb40-24a3-4456-8e16-326670e04a10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879099852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3879099852
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1431099170
Short name T565
Test name
Test status
Simulation time 5312855903 ps
CPU time 162.65 seconds
Started Mar 31 12:50:34 PM PDT 24
Finished Mar 31 12:53:17 PM PDT 24
Peak memory 249956 kb
Host smart-e87ec483-2a15-4033-841f-002881d7124c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14310
99170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1431099170
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1416645708
Short name T510
Test name
Test status
Simulation time 217265413 ps
CPU time 4.62 seconds
Started Mar 31 12:50:32 PM PDT 24
Finished Mar 31 12:50:37 PM PDT 24
Peak memory 240624 kb
Host smart-f20d51ce-8cae-4a03-b98f-dfed62d11427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14166
45708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1416645708
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.4076015674
Short name T285
Test name
Test status
Simulation time 69315262410 ps
CPU time 2135.63 seconds
Started Mar 31 12:50:30 PM PDT 24
Finished Mar 31 01:26:07 PM PDT 24
Peak memory 288984 kb
Host smart-e34cf260-3137-48bc-a102-5d033e4a04e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076015674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.4076015674
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1305323160
Short name T273
Test name
Test status
Simulation time 56778277783 ps
CPU time 3355.02 seconds
Started Mar 31 12:50:32 PM PDT 24
Finished Mar 31 01:46:28 PM PDT 24
Peak memory 289272 kb
Host smart-03fd4a84-c9c8-4c0b-b4ac-941dca817636
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305323160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1305323160
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1271526547
Short name T436
Test name
Test status
Simulation time 869007830 ps
CPU time 14.47 seconds
Started Mar 31 12:50:34 PM PDT 24
Finished Mar 31 12:50:48 PM PDT 24
Peak memory 248788 kb
Host smart-f10c7304-8369-4e40-b145-240c7e3506fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12715
26547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1271526547
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1783983295
Short name T663
Test name
Test status
Simulation time 1639875463 ps
CPU time 21.3 seconds
Started Mar 31 12:50:31 PM PDT 24
Finished Mar 31 12:50:52 PM PDT 24
Peak memory 256268 kb
Host smart-77a532d2-e89d-4f5d-a0f6-76f1985848db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17839
83295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1783983295
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4233541285
Short name T471
Test name
Test status
Simulation time 236491301 ps
CPU time 4.56 seconds
Started Mar 31 12:50:37 PM PDT 24
Finished Mar 31 12:50:42 PM PDT 24
Peak memory 240672 kb
Host smart-95992b2d-9ebc-4818-aa0a-e6aab62bac6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42335
41285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4233541285
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.776096365
Short name T454
Test name
Test status
Simulation time 11585973269 ps
CPU time 1199.37 seconds
Started Mar 31 12:50:30 PM PDT 24
Finished Mar 31 01:10:30 PM PDT 24
Peak memory 282780 kb
Host smart-f16acfe8-66f9-46c1-83d6-c091cdebecd9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776096365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.776096365
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2502147310
Short name T656
Test name
Test status
Simulation time 196620596616 ps
CPU time 2742.35 seconds
Started Mar 31 12:50:43 PM PDT 24
Finished Mar 31 01:36:25 PM PDT 24
Peak memory 289344 kb
Host smart-03996f26-c482-4391-b66c-94bd9f255e03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502147310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2502147310
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2004331622
Short name T560
Test name
Test status
Simulation time 2629749053 ps
CPU time 79.56 seconds
Started Mar 31 12:50:35 PM PDT 24
Finished Mar 31 12:51:55 PM PDT 24
Peak memory 256516 kb
Host smart-ccb9c8f7-e022-4eff-9bc9-bb1384a619c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20043
31622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2004331622
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2847032340
Short name T596
Test name
Test status
Simulation time 387400141 ps
CPU time 32.44 seconds
Started Mar 31 12:50:32 PM PDT 24
Finished Mar 31 12:51:05 PM PDT 24
Peak memory 248820 kb
Host smart-e3457b92-ffb4-483d-8e1e-572228dcb183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28470
32340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2847032340
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.4273487244
Short name T216
Test name
Test status
Simulation time 22489329919 ps
CPU time 1424.26 seconds
Started Mar 31 12:50:41 PM PDT 24
Finished Mar 31 01:14:26 PM PDT 24
Peak memory 269452 kb
Host smart-2c1dc276-b65e-41bc-875e-5b1b7a637faa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273487244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.4273487244
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1893140706
Short name T707
Test name
Test status
Simulation time 63364894936 ps
CPU time 1551.63 seconds
Started Mar 31 12:50:38 PM PDT 24
Finished Mar 31 01:16:30 PM PDT 24
Peak memory 286848 kb
Host smart-72e38809-29a8-4cc9-8b93-ee5557d94366
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893140706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1893140706
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3963731981
Short name T308
Test name
Test status
Simulation time 8115797318 ps
CPU time 345.62 seconds
Started Mar 31 12:50:40 PM PDT 24
Finished Mar 31 12:56:26 PM PDT 24
Peak memory 248908 kb
Host smart-94192b3c-3475-4284-848e-76576948776b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963731981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3963731981
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.4041914829
Short name T95
Test name
Test status
Simulation time 6285012550 ps
CPU time 23.79 seconds
Started Mar 31 12:50:32 PM PDT 24
Finished Mar 31 12:50:56 PM PDT 24
Peak memory 248932 kb
Host smart-f3591913-f6c1-40c0-9091-322c8da94bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40419
14829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.4041914829
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1517059204
Short name T81
Test name
Test status
Simulation time 2274671686 ps
CPU time 46.35 seconds
Started Mar 31 12:50:31 PM PDT 24
Finished Mar 31 12:51:17 PM PDT 24
Peak memory 255860 kb
Host smart-568d3dbf-ac9f-436a-8df6-1c479241feb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15170
59204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1517059204
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.172462757
Short name T127
Test name
Test status
Simulation time 144894385 ps
CPU time 9.28 seconds
Started Mar 31 12:50:38 PM PDT 24
Finished Mar 31 12:50:48 PM PDT 24
Peak memory 247388 kb
Host smart-15309732-c410-4fbf-85a4-d5fa79194447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17246
2757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.172462757
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2064952030
Short name T65
Test name
Test status
Simulation time 427823769 ps
CPU time 10.04 seconds
Started Mar 31 12:50:31 PM PDT 24
Finished Mar 31 12:50:42 PM PDT 24
Peak memory 248828 kb
Host smart-dadffe55-52fb-4050-a2c0-b94cf1348a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20649
52030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2064952030
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2039656122
Short name T76
Test name
Test status
Simulation time 143985322176 ps
CPU time 2232.84 seconds
Started Mar 31 12:50:42 PM PDT 24
Finished Mar 31 01:27:56 PM PDT 24
Peak memory 289752 kb
Host smart-e66a7955-4353-477c-99c2-13c2bbda56fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039656122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2039656122
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.4281572307
Short name T507
Test name
Test status
Simulation time 40728141736 ps
CPU time 2243.95 seconds
Started Mar 31 12:50:39 PM PDT 24
Finished Mar 31 01:28:03 PM PDT 24
Peak memory 281756 kb
Host smart-0c1a3732-ba20-48d3-976c-3e58c38ff449
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281572307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4281572307
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1709386284
Short name T675
Test name
Test status
Simulation time 1623815642 ps
CPU time 98.34 seconds
Started Mar 31 12:50:40 PM PDT 24
Finished Mar 31 12:52:18 PM PDT 24
Peak memory 248372 kb
Host smart-4fbe94b5-8488-463b-b4fa-b35cd04d19c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17093
86284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1709386284
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2460013774
Short name T17
Test name
Test status
Simulation time 166364524 ps
CPU time 20.89 seconds
Started Mar 31 12:50:38 PM PDT 24
Finished Mar 31 12:51:00 PM PDT 24
Peak memory 248668 kb
Host smart-053588d7-349b-4979-977e-1d678afcf978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24600
13774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2460013774
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1888763805
Short name T329
Test name
Test status
Simulation time 155798782936 ps
CPU time 2449.24 seconds
Started Mar 31 12:50:40 PM PDT 24
Finished Mar 31 01:31:30 PM PDT 24
Peak memory 271528 kb
Host smart-ec7bcc9f-5334-4bc4-9b9a-b298887e7736
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888763805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1888763805
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.4122672018
Short name T362
Test name
Test status
Simulation time 18243130681 ps
CPU time 877.86 seconds
Started Mar 31 12:50:42 PM PDT 24
Finished Mar 31 01:05:20 PM PDT 24
Peak memory 281768 kb
Host smart-52b260b3-aef0-4647-9911-b36e30b9d74b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122672018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.4122672018
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.714296373
Short name T639
Test name
Test status
Simulation time 8558871926 ps
CPU time 92.68 seconds
Started Mar 31 12:50:40 PM PDT 24
Finished Mar 31 12:52:13 PM PDT 24
Peak memory 247920 kb
Host smart-594abfdf-fe53-48b4-b598-92b3e4a8bf00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714296373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.714296373
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1545735064
Short name T548
Test name
Test status
Simulation time 737892046 ps
CPU time 18.99 seconds
Started Mar 31 12:50:40 PM PDT 24
Finished Mar 31 12:51:00 PM PDT 24
Peak memory 248800 kb
Host smart-8f0a2edc-93ba-44c1-ab02-ee27e16e5b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15457
35064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1545735064
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.158923568
Short name T464
Test name
Test status
Simulation time 28711833 ps
CPU time 4.19 seconds
Started Mar 31 12:50:41 PM PDT 24
Finished Mar 31 12:50:45 PM PDT 24
Peak memory 240448 kb
Host smart-46707c7a-1e3d-433e-b861-c8d680e73df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15892
3568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.158923568
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.10560026
Short name T545
Test name
Test status
Simulation time 1628383668 ps
CPU time 31.85 seconds
Started Mar 31 12:50:40 PM PDT 24
Finished Mar 31 12:51:12 PM PDT 24
Peak memory 255812 kb
Host smart-d572e176-942e-4ce1-b549-e76ad5faf4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10560
026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.10560026
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2191714542
Short name T122
Test name
Test status
Simulation time 226435491121 ps
CPU time 2400.78 seconds
Started Mar 31 12:50:40 PM PDT 24
Finished Mar 31 01:30:41 PM PDT 24
Peak memory 282464 kb
Host smart-4365e65c-70f6-4cd6-b846-4d28bb87adaa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191714542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2191714542
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3762487262
Short name T254
Test name
Test status
Simulation time 125502436228 ps
CPU time 4463.59 seconds
Started Mar 31 12:50:40 PM PDT 24
Finished Mar 31 02:05:04 PM PDT 24
Peak memory 316992 kb
Host smart-e779774c-32f8-4d67-ac55-a692a1cea77b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762487262 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3762487262
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2892789253
Short name T10
Test name
Test status
Simulation time 23149524661 ps
CPU time 1100.62 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 01:09:09 PM PDT 24
Peak memory 271032 kb
Host smart-19f5fd57-ce56-4cba-9a7d-f0365000f482
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892789253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2892789253
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1655284229
Short name T494
Test name
Test status
Simulation time 6655132950 ps
CPU time 146.28 seconds
Started Mar 31 12:50:47 PM PDT 24
Finished Mar 31 12:53:14 PM PDT 24
Peak memory 256888 kb
Host smart-ac254cbb-a861-47f5-9675-c005ddbb96f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16552
84229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1655284229
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1120169853
Short name T612
Test name
Test status
Simulation time 261952855 ps
CPU time 8.56 seconds
Started Mar 31 12:50:49 PM PDT 24
Finished Mar 31 12:50:57 PM PDT 24
Peak memory 248600 kb
Host smart-9aa6e5a8-34c0-4435-9cd8-f18fef0ea28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11201
69853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1120169853
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.4197922431
Short name T218
Test name
Test status
Simulation time 54338740741 ps
CPU time 1657.96 seconds
Started Mar 31 12:50:45 PM PDT 24
Finished Mar 31 01:18:23 PM PDT 24
Peak memory 265316 kb
Host smart-d1c2a75f-6f7a-4a94-812f-d3148d783368
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197922431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4197922431
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3473810429
Short name T401
Test name
Test status
Simulation time 51847114310 ps
CPU time 3284.05 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 01:45:33 PM PDT 24
Peak memory 281772 kb
Host smart-c441417f-f960-4eef-9fd5-d848069b28a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473810429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3473810429
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2762158644
Short name T306
Test name
Test status
Simulation time 37919289353 ps
CPU time 384.84 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 12:57:13 PM PDT 24
Peak memory 247856 kb
Host smart-434aa2d4-78f7-4ebd-b4e6-1fb23db7e28d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762158644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2762158644
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3573414084
Short name T606
Test name
Test status
Simulation time 2085302611 ps
CPU time 30.24 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 12:51:19 PM PDT 24
Peak memory 248900 kb
Host smart-f873f5f0-525a-4724-b5ae-cf01fae0a17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35734
14084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3573414084
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1019464521
Short name T679
Test name
Test status
Simulation time 121295418 ps
CPU time 6.36 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 12:50:54 PM PDT 24
Peak memory 248868 kb
Host smart-06c16141-28e4-4843-bcea-9fd10bad1119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10194
64521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1019464521
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.286322574
Short name T553
Test name
Test status
Simulation time 1067075707 ps
CPU time 28.98 seconds
Started Mar 31 12:50:46 PM PDT 24
Finished Mar 31 12:51:16 PM PDT 24
Peak memory 255580 kb
Host smart-ef1b5cfa-077c-4811-8643-df48b6832cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28632
2574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.286322574
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.4034574455
Short name T540
Test name
Test status
Simulation time 270742305 ps
CPU time 19.47 seconds
Started Mar 31 12:50:49 PM PDT 24
Finished Mar 31 12:51:08 PM PDT 24
Peak memory 255996 kb
Host smart-801f0ffa-9656-4052-bbc6-b702d569addf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40345
74455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.4034574455
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.778406876
Short name T614
Test name
Test status
Simulation time 8977483558 ps
CPU time 1225.95 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 01:11:15 PM PDT 24
Peak memory 286972 kb
Host smart-e9aab862-66a1-4715-947f-757910db6f0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778406876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.778406876
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3666359240
Short name T121
Test name
Test status
Simulation time 27471221566 ps
CPU time 2079.62 seconds
Started Mar 31 12:50:49 PM PDT 24
Finished Mar 31 01:25:29 PM PDT 24
Peak memory 289948 kb
Host smart-17f0fc31-3ed5-411f-8edd-8f4a42db1a2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666359240 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3666359240
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.4075859714
Short name T51
Test name
Test status
Simulation time 47359855454 ps
CPU time 1056.79 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 01:08:25 PM PDT 24
Peak memory 273544 kb
Host smart-d668d309-069f-4697-a067-ef5098611469
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075859714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.4075859714
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1753204082
Short name T459
Test name
Test status
Simulation time 2451964411 ps
CPU time 141.48 seconds
Started Mar 31 12:50:49 PM PDT 24
Finished Mar 31 12:53:10 PM PDT 24
Peak memory 257084 kb
Host smart-8831a646-aefc-4a77-871e-6912dcf9a2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17532
04082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1753204082
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.832678287
Short name T437
Test name
Test status
Simulation time 771228657 ps
CPU time 47.77 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 12:51:36 PM PDT 24
Peak memory 248656 kb
Host smart-9f07868f-4e6e-4645-b50e-257367525a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83267
8287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.832678287
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3328000847
Short name T326
Test name
Test status
Simulation time 26099888534 ps
CPU time 1101.59 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 01:09:10 PM PDT 24
Peak memory 281760 kb
Host smart-e9a39d14-8dd2-4318-ad48-67816884ca8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328000847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3328000847
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3179066393
Short name T368
Test name
Test status
Simulation time 52084498564 ps
CPU time 2994.43 seconds
Started Mar 31 12:50:56 PM PDT 24
Finished Mar 31 01:40:51 PM PDT 24
Peak memory 289500 kb
Host smart-8398c1aa-1175-4823-bf99-d17f7af8fb9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179066393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3179066393
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.494852246
Short name T624
Test name
Test status
Simulation time 9917324044 ps
CPU time 405.58 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 12:57:34 PM PDT 24
Peak memory 247104 kb
Host smart-5671b22e-f97c-4dd9-917c-b46a177c695f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494852246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.494852246
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.4043431029
Short name T678
Test name
Test status
Simulation time 839134927 ps
CPU time 18.73 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 12:51:06 PM PDT 24
Peak memory 248836 kb
Host smart-450bca75-5b5d-4ab1-88d8-ddffff783e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40434
31029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.4043431029
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2197999596
Short name T476
Test name
Test status
Simulation time 165676871 ps
CPU time 15.49 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 12:51:04 PM PDT 24
Peak memory 248572 kb
Host smart-9010b620-d29b-4945-9369-acbaad88c107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21979
99596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2197999596
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1733259955
Short name T55
Test name
Test status
Simulation time 669836985 ps
CPU time 36.43 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 12:51:25 PM PDT 24
Peak memory 255340 kb
Host smart-e25b843c-9508-4cfb-9702-795a79dad7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17332
59955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1733259955
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2213157177
Short name T629
Test name
Test status
Simulation time 432965877 ps
CPU time 25.16 seconds
Started Mar 31 12:50:48 PM PDT 24
Finished Mar 31 12:51:14 PM PDT 24
Peak memory 249000 kb
Host smart-4e5def38-6712-4337-94b2-2441a1467c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22131
57177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2213157177
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3800499389
Short name T497
Test name
Test status
Simulation time 55624304846 ps
CPU time 1836.29 seconds
Started Mar 31 12:50:57 PM PDT 24
Finished Mar 31 01:21:34 PM PDT 24
Peak memory 299544 kb
Host smart-80d9377c-d3cf-4c74-b586-0094dd0975ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800499389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3800499389
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.339709914
Short name T251
Test name
Test status
Simulation time 127827984056 ps
CPU time 1189.89 seconds
Started Mar 31 12:50:57 PM PDT 24
Finished Mar 31 01:10:48 PM PDT 24
Peak memory 284248 kb
Host smart-d06b53d5-d69e-4243-8db6-8da087b66bab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339709914 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.339709914
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.759047806
Short name T451
Test name
Test status
Simulation time 59136609319 ps
CPU time 1199.6 seconds
Started Mar 31 12:50:58 PM PDT 24
Finished Mar 31 01:10:59 PM PDT 24
Peak memory 283732 kb
Host smart-423b6a3e-e76b-4a28-aeb9-21746e8eb254
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759047806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.759047806
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3062878931
Short name T457
Test name
Test status
Simulation time 921941901 ps
CPU time 54.7 seconds
Started Mar 31 12:50:55 PM PDT 24
Finished Mar 31 12:51:50 PM PDT 24
Peak memory 256104 kb
Host smart-5b831ece-998f-4760-ab74-f5d46762c29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30628
78931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3062878931
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.369383452
Short name T634
Test name
Test status
Simulation time 642801438 ps
CPU time 17.93 seconds
Started Mar 31 12:50:55 PM PDT 24
Finished Mar 31 12:51:13 PM PDT 24
Peak memory 253084 kb
Host smart-b540a456-28ca-489f-bb47-d29bf73f92b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36938
3452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.369383452
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.4118734115
Short name T328
Test name
Test status
Simulation time 12714994216 ps
CPU time 748.45 seconds
Started Mar 31 12:50:57 PM PDT 24
Finished Mar 31 01:03:26 PM PDT 24
Peak memory 265396 kb
Host smart-3f9fa057-72f3-47d8-bafc-ea60d5584b18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118734115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.4118734115
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2071721
Short name T410
Test name
Test status
Simulation time 26170153494 ps
CPU time 637 seconds
Started Mar 31 12:50:54 PM PDT 24
Finished Mar 31 01:01:31 PM PDT 24
Peak memory 272064 kb
Host smart-47e00a94-7943-4ac7-be88-519937dcf9da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2071721
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3347875019
Short name T72
Test name
Test status
Simulation time 20325398797 ps
CPU time 212.04 seconds
Started Mar 31 12:50:56 PM PDT 24
Finished Mar 31 12:54:29 PM PDT 24
Peak memory 248140 kb
Host smart-993d3f6b-490d-413d-8603-958ef0c3261c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347875019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3347875019
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.487652114
Short name T364
Test name
Test status
Simulation time 1110030659 ps
CPU time 24.25 seconds
Started Mar 31 12:50:55 PM PDT 24
Finished Mar 31 12:51:19 PM PDT 24
Peak memory 248976 kb
Host smart-75e4ef63-84bf-40de-8778-0b3175aaf76f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48765
2114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.487652114
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.486069700
Short name T525
Test name
Test status
Simulation time 3933962096 ps
CPU time 71.24 seconds
Started Mar 31 12:50:56 PM PDT 24
Finished Mar 31 12:52:08 PM PDT 24
Peak memory 255576 kb
Host smart-0acb708a-9ff3-4baa-9ae5-ebe824c09174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48606
9700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.486069700
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.4014400631
Short name T246
Test name
Test status
Simulation time 283496866 ps
CPU time 18.52 seconds
Started Mar 31 12:50:58 PM PDT 24
Finished Mar 31 12:51:17 PM PDT 24
Peak memory 253572 kb
Host smart-fcb9c2ab-27b6-487c-9f02-41c69e25da19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40144
00631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.4014400631
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.374665985
Short name T352
Test name
Test status
Simulation time 372070975 ps
CPU time 9.83 seconds
Started Mar 31 12:50:55 PM PDT 24
Finished Mar 31 12:51:05 PM PDT 24
Peak memory 248908 kb
Host smart-ccc94521-47b1-41e0-be7d-cd67aa3bf93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37466
5985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.374665985
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.931110652
Short name T698
Test name
Test status
Simulation time 25998412892 ps
CPU time 1556.16 seconds
Started Mar 31 12:51:00 PM PDT 24
Finished Mar 31 01:16:57 PM PDT 24
Peak memory 273544 kb
Host smart-446fd339-9770-4b95-b798-1f8289d71691
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931110652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.931110652
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3393571139
Short name T543
Test name
Test status
Simulation time 86562954428 ps
CPU time 1530.57 seconds
Started Mar 31 12:51:05 PM PDT 24
Finished Mar 31 01:16:36 PM PDT 24
Peak memory 268664 kb
Host smart-0e39a03f-e0c7-451f-a1ef-4e0be7c05ec2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393571139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3393571139
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2069086779
Short name T414
Test name
Test status
Simulation time 8099538970 ps
CPU time 133.45 seconds
Started Mar 31 12:51:01 PM PDT 24
Finished Mar 31 12:53:15 PM PDT 24
Peak memory 251080 kb
Host smart-7359eb3a-aecb-46db-9c12-537b273d72d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20690
86779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2069086779
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.752677200
Short name T82
Test name
Test status
Simulation time 1726809625 ps
CPU time 42.62 seconds
Started Mar 31 12:51:03 PM PDT 24
Finished Mar 31 12:51:45 PM PDT 24
Peak memory 255808 kb
Host smart-f0761d2c-8599-4804-a9e7-5a94b7e14f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75267
7200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.752677200
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1585404532
Short name T589
Test name
Test status
Simulation time 36093256537 ps
CPU time 1832.29 seconds
Started Mar 31 12:51:10 PM PDT 24
Finished Mar 31 01:21:44 PM PDT 24
Peak memory 273392 kb
Host smart-fa7cd301-7d27-49cc-ae43-1c4bff153d8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585404532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1585404532
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.311637616
Short name T492
Test name
Test status
Simulation time 10693039802 ps
CPU time 960.68 seconds
Started Mar 31 12:51:09 PM PDT 24
Finished Mar 31 01:07:11 PM PDT 24
Peak memory 273176 kb
Host smart-1a913d1d-93ca-47ab-a3f6-faa8e6b76644
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311637616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.311637616
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.374758272
Short name T303
Test name
Test status
Simulation time 7972241992 ps
CPU time 169.87 seconds
Started Mar 31 12:51:02 PM PDT 24
Finished Mar 31 12:53:52 PM PDT 24
Peak memory 247988 kb
Host smart-8af6c558-8400-4dff-81ab-e073b26d7466
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374758272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.374758272
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.599847781
Short name T359
Test name
Test status
Simulation time 252885314 ps
CPU time 26.51 seconds
Started Mar 31 12:51:01 PM PDT 24
Finished Mar 31 12:51:28 PM PDT 24
Peak memory 248856 kb
Host smart-2b19c937-245b-4db9-9dd5-6818f8eacc3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59984
7781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.599847781
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2740139029
Short name T419
Test name
Test status
Simulation time 780402672 ps
CPU time 47.7 seconds
Started Mar 31 12:51:01 PM PDT 24
Finished Mar 31 12:51:49 PM PDT 24
Peak memory 248720 kb
Host smart-31cfbd01-7160-4d41-b7d6-c9ffe7cd3668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27401
39029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2740139029
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2408010707
Short name T664
Test name
Test status
Simulation time 467128985 ps
CPU time 18.9 seconds
Started Mar 31 12:51:01 PM PDT 24
Finished Mar 31 12:51:20 PM PDT 24
Peak memory 248820 kb
Host smart-5ae43e7f-5394-4e26-b07d-211cc8f9f0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24080
10707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2408010707
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.963923108
Short name T358
Test name
Test status
Simulation time 105288318 ps
CPU time 11.95 seconds
Started Mar 31 12:51:02 PM PDT 24
Finished Mar 31 12:51:14 PM PDT 24
Peak memory 254956 kb
Host smart-33fca2d3-fd54-4882-8617-54d7232dec9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96392
3108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.963923108
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.3502603163
Short name T225
Test name
Test status
Simulation time 68308627783 ps
CPU time 1107.32 seconds
Started Mar 31 12:51:08 PM PDT 24
Finished Mar 31 01:09:36 PM PDT 24
Peak memory 281796 kb
Host smart-9e46c3ab-d29a-4f22-9991-ddc46cb157ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502603163 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.3502603163
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1152477604
Short name T210
Test name
Test status
Simulation time 103848954 ps
CPU time 2.94 seconds
Started Mar 31 12:48:26 PM PDT 24
Finished Mar 31 12:48:29 PM PDT 24
Peak memory 249036 kb
Host smart-7c9b3f09-5bf4-4a61-a378-fc1df013be7e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1152477604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1152477604
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2989085379
Short name T635
Test name
Test status
Simulation time 12367529043 ps
CPU time 969.73 seconds
Started Mar 31 12:48:28 PM PDT 24
Finished Mar 31 01:04:38 PM PDT 24
Peak memory 272896 kb
Host smart-9a2b4b9b-45ec-4c2c-b62b-7e29edb76284
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989085379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2989085379
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2025637136
Short name T214
Test name
Test status
Simulation time 179653278 ps
CPU time 10.35 seconds
Started Mar 31 12:48:28 PM PDT 24
Finished Mar 31 12:48:38 PM PDT 24
Peak memory 248872 kb
Host smart-b0f57921-7e84-4f07-81e0-9f140217a278
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2025637136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2025637136
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.4151456697
Short name T92
Test name
Test status
Simulation time 2000527855 ps
CPU time 155.06 seconds
Started Mar 31 12:48:28 PM PDT 24
Finished Mar 31 12:51:03 PM PDT 24
Peak memory 250772 kb
Host smart-8bc69b73-9ba4-4cca-a912-4941b42a9b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41514
56697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.4151456697
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3000941627
Short name T566
Test name
Test status
Simulation time 1847115059 ps
CPU time 47.73 seconds
Started Mar 31 12:48:27 PM PDT 24
Finished Mar 31 12:49:14 PM PDT 24
Peak memory 255380 kb
Host smart-40b11168-3a99-43b0-b16c-141ac637f9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30009
41627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3000941627
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2807858381
Short name T69
Test name
Test status
Simulation time 127529098854 ps
CPU time 927.53 seconds
Started Mar 31 12:48:28 PM PDT 24
Finished Mar 31 01:03:56 PM PDT 24
Peak memory 270484 kb
Host smart-a8864f0a-c297-41c9-9a63-6595678593fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807858381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2807858381
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2398571107
Short name T300
Test name
Test status
Simulation time 34759071037 ps
CPU time 369.66 seconds
Started Mar 31 12:48:26 PM PDT 24
Finished Mar 31 12:54:36 PM PDT 24
Peak memory 247108 kb
Host smart-1e8fc3e2-6343-4c94-ad4f-3b12cc07432f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398571107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2398571107
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3190737605
Short name T693
Test name
Test status
Simulation time 4000480469 ps
CPU time 57.81 seconds
Started Mar 31 12:48:29 PM PDT 24
Finished Mar 31 12:49:26 PM PDT 24
Peak memory 256184 kb
Host smart-db35356a-d4d3-4097-9866-f7c3dac31529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31907
37605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3190737605
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.333166473
Short name T217
Test name
Test status
Simulation time 586755750 ps
CPU time 31.3 seconds
Started Mar 31 12:48:28 PM PDT 24
Finished Mar 31 12:49:00 PM PDT 24
Peak memory 255736 kb
Host smart-fe2406f9-9c05-4a7f-994c-5e8aa1398230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33316
6473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.333166473
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1665363999
Short name T9
Test name
Test status
Simulation time 213341327 ps
CPU time 11.7 seconds
Started Mar 31 12:48:26 PM PDT 24
Finished Mar 31 12:48:38 PM PDT 24
Peak memory 273980 kb
Host smart-049c0ecf-1f24-4901-bfe1-2fa9d60620e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1665363999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1665363999
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3490612989
Short name T88
Test name
Test status
Simulation time 114368928 ps
CPU time 13.4 seconds
Started Mar 31 12:48:29 PM PDT 24
Finished Mar 31 12:48:42 PM PDT 24
Peak memory 255796 kb
Host smart-382ae4bc-8017-4cd6-878f-d022eaa49a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34906
12989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3490612989
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.676666161
Short name T581
Test name
Test status
Simulation time 93843236 ps
CPU time 10.94 seconds
Started Mar 31 12:48:30 PM PDT 24
Finished Mar 31 12:48:41 PM PDT 24
Peak memory 257044 kb
Host smart-a0b73d8c-09b2-4716-9141-6556f3b7c135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67666
6161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.676666161
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.81022996
Short name T245
Test name
Test status
Simulation time 33828283189 ps
CPU time 588.96 seconds
Started Mar 31 12:48:28 PM PDT 24
Finished Mar 31 12:58:17 PM PDT 24
Peak memory 282428 kb
Host smart-ade41d99-71b2-4f09-aea1-2af4b57651a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81022996 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.81022996
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3153767075
Short name T557
Test name
Test status
Simulation time 331584117782 ps
CPU time 1662.69 seconds
Started Mar 31 12:51:08 PM PDT 24
Finished Mar 31 01:18:51 PM PDT 24
Peak memory 268484 kb
Host smart-b2e9c153-27d8-44c4-93fd-1dfb64a01491
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153767075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3153767075
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1369652644
Short name T394
Test name
Test status
Simulation time 3080087949 ps
CPU time 76.94 seconds
Started Mar 31 12:51:08 PM PDT 24
Finished Mar 31 12:52:26 PM PDT 24
Peak memory 248720 kb
Host smart-d9d8402d-677e-4113-aed9-0456bd56ef6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13696
52644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1369652644
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2346076368
Short name T651
Test name
Test status
Simulation time 339259099 ps
CPU time 25.15 seconds
Started Mar 31 12:51:09 PM PDT 24
Finished Mar 31 12:51:35 PM PDT 24
Peak memory 248872 kb
Host smart-d261c156-ff3d-4f78-ab7a-057aa9259309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23460
76368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2346076368
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3844595738
Short name T650
Test name
Test status
Simulation time 55232458189 ps
CPU time 756.19 seconds
Started Mar 31 12:51:08 PM PDT 24
Finished Mar 31 01:03:44 PM PDT 24
Peak memory 266340 kb
Host smart-c35da3fb-0b9f-4d81-8c0a-854d71ae573b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844595738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3844595738
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1308831239
Short name T406
Test name
Test status
Simulation time 29327989449 ps
CPU time 1536.8 seconds
Started Mar 31 12:51:09 PM PDT 24
Finished Mar 31 01:16:47 PM PDT 24
Peak memory 272816 kb
Host smart-e6c5eb2f-a33a-4054-9fc8-b2ee1d945726
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308831239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1308831239
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.890776779
Short name T542
Test name
Test status
Simulation time 74518197207 ps
CPU time 276.44 seconds
Started Mar 31 12:51:12 PM PDT 24
Finished Mar 31 12:55:50 PM PDT 24
Peak memory 247208 kb
Host smart-e24d746a-5ab4-4b4e-8de7-a2bafaa0dbbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890776779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.890776779
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2952077110
Short name T532
Test name
Test status
Simulation time 338717374 ps
CPU time 22.14 seconds
Started Mar 31 12:51:11 PM PDT 24
Finished Mar 31 12:51:34 PM PDT 24
Peak memory 256164 kb
Host smart-1c85e9ac-a371-4572-8eae-36e11004319c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29520
77110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2952077110
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.4257468649
Short name T402
Test name
Test status
Simulation time 482907127 ps
CPU time 16.03 seconds
Started Mar 31 12:51:11 PM PDT 24
Finished Mar 31 12:51:28 PM PDT 24
Peak memory 252940 kb
Host smart-a3e1caa6-bb03-43bf-89da-07500bf658c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42574
68649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.4257468649
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2446308709
Short name T620
Test name
Test status
Simulation time 66170932 ps
CPU time 9.08 seconds
Started Mar 31 12:51:11 PM PDT 24
Finished Mar 31 12:51:21 PM PDT 24
Peak memory 247408 kb
Host smart-6b9867de-3289-45b6-9274-061a56a149b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24463
08709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2446308709
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3551873374
Short name T426
Test name
Test status
Simulation time 7334829227 ps
CPU time 33.35 seconds
Started Mar 31 12:51:08 PM PDT 24
Finished Mar 31 12:51:42 PM PDT 24
Peak memory 256176 kb
Host smart-377b7e79-fd16-4574-b2e3-2be1cbe5721c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35518
73374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3551873374
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.801737826
Short name T249
Test name
Test status
Simulation time 113186917566 ps
CPU time 2730.39 seconds
Started Mar 31 12:51:20 PM PDT 24
Finished Mar 31 01:36:51 PM PDT 24
Peak memory 286852 kb
Host smart-f7ecff95-4814-426e-8e38-5bdb123f29bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801737826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.801737826
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2778465055
Short name T702
Test name
Test status
Simulation time 24382904553 ps
CPU time 1052.38 seconds
Started Mar 31 12:51:21 PM PDT 24
Finished Mar 31 01:08:53 PM PDT 24
Peak memory 281768 kb
Host smart-60620090-386f-4b5f-b853-780544388761
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778465055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2778465055
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2543817659
Short name T400
Test name
Test status
Simulation time 4402843774 ps
CPU time 91.83 seconds
Started Mar 31 12:51:19 PM PDT 24
Finished Mar 31 12:52:51 PM PDT 24
Peak memory 257184 kb
Host smart-82ae863c-4d56-4883-82d7-5f15b36ac7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25438
17659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2543817659
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2669118332
Short name T659
Test name
Test status
Simulation time 345914414 ps
CPU time 22.04 seconds
Started Mar 31 12:51:20 PM PDT 24
Finished Mar 31 12:51:42 PM PDT 24
Peak memory 248728 kb
Host smart-cb56f91f-ef31-4a5b-81f9-6de8fefea202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26691
18332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2669118332
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3525930279
Short name T1
Test name
Test status
Simulation time 85277979629 ps
CPU time 1679.54 seconds
Started Mar 31 12:51:27 PM PDT 24
Finished Mar 31 01:19:27 PM PDT 24
Peak memory 273340 kb
Host smart-3fee30e7-1d93-4d9e-b8dd-1654208cafb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525930279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3525930279
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3429195270
Short name T593
Test name
Test status
Simulation time 95220143306 ps
CPU time 1747.45 seconds
Started Mar 31 12:51:27 PM PDT 24
Finished Mar 31 01:20:35 PM PDT 24
Peak memory 273556 kb
Host smart-fa52dee2-e46c-4cc0-b9e6-062d1774ed1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429195270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3429195270
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2433688386
Short name T642
Test name
Test status
Simulation time 1253937611 ps
CPU time 46.05 seconds
Started Mar 31 12:51:19 PM PDT 24
Finished Mar 31 12:52:05 PM PDT 24
Peak memory 248820 kb
Host smart-686795a5-0f3e-4019-9f95-5c528953b9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24336
88386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2433688386
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.744739413
Short name T63
Test name
Test status
Simulation time 455106523 ps
CPU time 34.7 seconds
Started Mar 31 12:51:19 PM PDT 24
Finished Mar 31 12:51:53 PM PDT 24
Peak memory 248884 kb
Host smart-050043f8-1c14-4483-864b-73f6f9fbde70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74473
9413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.744739413
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2704516681
Short name T533
Test name
Test status
Simulation time 568052155 ps
CPU time 17.67 seconds
Started Mar 31 12:51:19 PM PDT 24
Finished Mar 31 12:51:37 PM PDT 24
Peak memory 248472 kb
Host smart-c47ef3ed-fb32-4f97-a6f2-53b07e746c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27045
16681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2704516681
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2230128198
Short name T587
Test name
Test status
Simulation time 1133306435 ps
CPU time 32.52 seconds
Started Mar 31 12:51:19 PM PDT 24
Finished Mar 31 12:51:51 PM PDT 24
Peak memory 256052 kb
Host smart-57f6f59d-553d-4bde-9a86-b7d0b57bce24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22301
28198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2230128198
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1970664365
Short name T117
Test name
Test status
Simulation time 161981921016 ps
CPU time 4459.11 seconds
Started Mar 31 12:51:28 PM PDT 24
Finished Mar 31 02:05:48 PM PDT 24
Peak memory 305576 kb
Host smart-8ca7b395-c6df-45fc-9873-f4a8f105dd03
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970664365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1970664365
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.159609191
Short name T125
Test name
Test status
Simulation time 18703641291 ps
CPU time 1203.66 seconds
Started Mar 31 12:51:30 PM PDT 24
Finished Mar 31 01:11:34 PM PDT 24
Peak memory 265500 kb
Host smart-434ab246-51ec-4550-942c-f9f7a654c26e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159609191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.159609191
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1989790913
Short name T665
Test name
Test status
Simulation time 2623150252 ps
CPU time 66.6 seconds
Started Mar 31 12:51:27 PM PDT 24
Finished Mar 31 12:52:34 PM PDT 24
Peak memory 256784 kb
Host smart-38dd4d8b-434e-4891-9df8-3a1d25d29203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19897
90913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1989790913
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3728835691
Short name T483
Test name
Test status
Simulation time 204901798 ps
CPU time 12.89 seconds
Started Mar 31 12:51:28 PM PDT 24
Finished Mar 31 12:51:41 PM PDT 24
Peak memory 255496 kb
Host smart-4f5a4fe3-d845-4e5a-a43d-1aafed67154b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37288
35691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3728835691
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2349897212
Short name T389
Test name
Test status
Simulation time 8793620681 ps
CPU time 760.79 seconds
Started Mar 31 12:51:38 PM PDT 24
Finished Mar 31 01:04:19 PM PDT 24
Peak memory 273100 kb
Host smart-567a995a-60ed-478b-968f-ab2c9ea751c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349897212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2349897212
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3006502963
Short name T310
Test name
Test status
Simulation time 59329127447 ps
CPU time 340.27 seconds
Started Mar 31 12:51:29 PM PDT 24
Finished Mar 31 12:57:09 PM PDT 24
Peak memory 248012 kb
Host smart-b1f85235-7780-433f-93e0-1e299d56030b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006502963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3006502963
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3525464669
Short name T654
Test name
Test status
Simulation time 1795330110 ps
CPU time 66.91 seconds
Started Mar 31 12:51:27 PM PDT 24
Finished Mar 31 12:52:34 PM PDT 24
Peak memory 256016 kb
Host smart-049ec4b0-e3ec-40b4-ac90-3cfec613f64a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35254
64669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3525464669
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2706761623
Short name T703
Test name
Test status
Simulation time 3267470539 ps
CPU time 42.83 seconds
Started Mar 31 12:51:28 PM PDT 24
Finished Mar 31 12:52:11 PM PDT 24
Peak memory 248908 kb
Host smart-502ed07f-b6a1-43b1-8ab1-d2bc022e6659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27067
61623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2706761623
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1497402205
Short name T516
Test name
Test status
Simulation time 509488862 ps
CPU time 27.65 seconds
Started Mar 31 12:51:26 PM PDT 24
Finished Mar 31 12:51:54 PM PDT 24
Peak memory 247424 kb
Host smart-4235f63c-127a-4a9f-b2d4-db8808ebac21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14974
02205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1497402205
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1056832156
Short name T512
Test name
Test status
Simulation time 37968768 ps
CPU time 4.66 seconds
Started Mar 31 12:51:27 PM PDT 24
Finished Mar 31 12:51:32 PM PDT 24
Peak memory 240664 kb
Host smart-91f42487-1999-48db-a659-00e59c08e191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10568
32156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1056832156
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.946657857
Short name T520
Test name
Test status
Simulation time 3769759685 ps
CPU time 312.37 seconds
Started Mar 31 12:51:37 PM PDT 24
Finished Mar 31 12:56:50 PM PDT 24
Peak memory 257088 kb
Host smart-f71d085c-23eb-4ae2-8878-fcc8f2f2ddd4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946657857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.946657857
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1212209285
Short name T367
Test name
Test status
Simulation time 35756137420 ps
CPU time 864.25 seconds
Started Mar 31 12:51:37 PM PDT 24
Finished Mar 31 01:06:01 PM PDT 24
Peak memory 281768 kb
Host smart-6cad2d53-fae0-443e-a448-065f2589e21d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212209285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1212209285
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2977622426
Short name T473
Test name
Test status
Simulation time 6083133937 ps
CPU time 82.52 seconds
Started Mar 31 12:51:37 PM PDT 24
Finished Mar 31 12:53:00 PM PDT 24
Peak memory 256724 kb
Host smart-bbad2f10-08e5-45a6-82a9-b07f9e9c94e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29776
22426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2977622426
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2391308738
Short name T219
Test name
Test status
Simulation time 1229686027 ps
CPU time 39.17 seconds
Started Mar 31 12:51:34 PM PDT 24
Finished Mar 31 12:52:13 PM PDT 24
Peak memory 255556 kb
Host smart-64bcf71a-a099-443e-86ed-20126672a5d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23913
08738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2391308738
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1412706104
Short name T636
Test name
Test status
Simulation time 65644350505 ps
CPU time 780.49 seconds
Started Mar 31 12:51:38 PM PDT 24
Finished Mar 31 01:04:39 PM PDT 24
Peak memory 268444 kb
Host smart-66c2483a-4613-44bb-8f29-705bf92e3135
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412706104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1412706104
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1496020160
Short name T594
Test name
Test status
Simulation time 50857882437 ps
CPU time 609.42 seconds
Started Mar 31 12:51:37 PM PDT 24
Finished Mar 31 01:01:46 PM PDT 24
Peak memory 255808 kb
Host smart-76e6cb51-06a5-451d-ae8a-8de1446cdc68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496020160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1496020160
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1037168274
Short name T128
Test name
Test status
Simulation time 485051393 ps
CPU time 14.54 seconds
Started Mar 31 12:51:36 PM PDT 24
Finished Mar 31 12:51:51 PM PDT 24
Peak memory 252948 kb
Host smart-ba824676-acb9-4cd7-8955-7be3e46663e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10371
68274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1037168274
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2952280005
Short name T505
Test name
Test status
Simulation time 2338894998 ps
CPU time 36.41 seconds
Started Mar 31 12:51:36 PM PDT 24
Finished Mar 31 12:52:13 PM PDT 24
Peak memory 256088 kb
Host smart-e5d660bb-26a6-4a13-a0c7-d8beb39cead2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29522
80005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2952280005
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.4016690015
Short name T626
Test name
Test status
Simulation time 2030148108 ps
CPU time 64.32 seconds
Started Mar 31 12:51:37 PM PDT 24
Finished Mar 31 12:52:42 PM PDT 24
Peak memory 248892 kb
Host smart-a0b65436-6ed9-4c02-882b-19190a637679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40166
90015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.4016690015
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3672924196
Short name T427
Test name
Test status
Simulation time 766284548 ps
CPU time 54.02 seconds
Started Mar 31 12:51:37 PM PDT 24
Finished Mar 31 12:52:31 PM PDT 24
Peak memory 255916 kb
Host smart-3f1cee24-aea8-4915-9a78-e6f9c8b0d4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36729
24196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3672924196
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.673267070
Short name T11
Test name
Test status
Simulation time 382407205848 ps
CPU time 7416.74 seconds
Started Mar 31 12:51:42 PM PDT 24
Finished Mar 31 02:55:20 PM PDT 24
Peak memory 370660 kb
Host smart-01e1b0e3-6630-409b-8834-3be7c72c329f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673267070 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.673267070
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1104897601
Short name T74
Test name
Test status
Simulation time 15611783693 ps
CPU time 1439.04 seconds
Started Mar 31 12:51:45 PM PDT 24
Finished Mar 31 01:15:45 PM PDT 24
Peak memory 289896 kb
Host smart-e61caa47-3933-438c-b693-6ba5bc8a92d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104897601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1104897601
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3331683972
Short name T220
Test name
Test status
Simulation time 874597695 ps
CPU time 87.57 seconds
Started Mar 31 12:51:43 PM PDT 24
Finished Mar 31 12:53:11 PM PDT 24
Peak memory 256684 kb
Host smart-3fd7df40-4dd1-4e21-be78-8ccd323ca8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33316
83972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3331683972
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1492362323
Short name T84
Test name
Test status
Simulation time 936935362 ps
CPU time 33.96 seconds
Started Mar 31 12:51:45 PM PDT 24
Finished Mar 31 12:52:19 PM PDT 24
Peak memory 255440 kb
Host smart-e94313e3-6083-4495-811f-9d900b141f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14923
62323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1492362323
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2346528665
Short name T585
Test name
Test status
Simulation time 198510429887 ps
CPU time 2513.31 seconds
Started Mar 31 12:51:44 PM PDT 24
Finished Mar 31 01:33:38 PM PDT 24
Peak memory 287436 kb
Host smart-c954e7d9-2943-4f4e-8b54-62f7cd47f475
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346528665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2346528665
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2607554575
Short name T404
Test name
Test status
Simulation time 12071669821 ps
CPU time 1013.61 seconds
Started Mar 31 12:51:44 PM PDT 24
Finished Mar 31 01:08:37 PM PDT 24
Peak memory 286332 kb
Host smart-843c6140-58e8-420f-9f96-0804ac7cc3bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607554575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2607554575
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3330688097
Short name T633
Test name
Test status
Simulation time 33251983894 ps
CPU time 513.79 seconds
Started Mar 31 12:51:42 PM PDT 24
Finished Mar 31 01:00:15 PM PDT 24
Peak memory 249004 kb
Host smart-33006039-e0d9-4c2e-9c6b-1e3c73bd1bb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330688097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3330688097
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.4232417247
Short name T417
Test name
Test status
Simulation time 414466567 ps
CPU time 20.84 seconds
Started Mar 31 12:51:43 PM PDT 24
Finished Mar 31 12:52:04 PM PDT 24
Peak memory 255760 kb
Host smart-88cbbe54-4cc9-4ff8-ae79-e2307ac9f931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42324
17247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.4232417247
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.559258314
Short name T452
Test name
Test status
Simulation time 53852828 ps
CPU time 5.36 seconds
Started Mar 31 12:51:43 PM PDT 24
Finished Mar 31 12:51:48 PM PDT 24
Peak memory 239056 kb
Host smart-27ab8ad2-b851-4d3a-b8fe-08ef26023a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55925
8314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.559258314
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1137637314
Short name T68
Test name
Test status
Simulation time 304401044 ps
CPU time 18.93 seconds
Started Mar 31 12:51:44 PM PDT 24
Finished Mar 31 12:52:03 PM PDT 24
Peak memory 247400 kb
Host smart-3720d534-8e59-43a5-9a19-ea27f461aa7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11376
37314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1137637314
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.360793316
Short name T681
Test name
Test status
Simulation time 3095305269 ps
CPU time 35.41 seconds
Started Mar 31 12:51:45 PM PDT 24
Finished Mar 31 12:52:21 PM PDT 24
Peak memory 249088 kb
Host smart-6595418c-aa24-4431-9d80-6c1b2c567375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36079
3316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.360793316
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.719450528
Short name T522
Test name
Test status
Simulation time 994284724210 ps
CPU time 4122.56 seconds
Started Mar 31 12:51:45 PM PDT 24
Finished Mar 31 02:00:28 PM PDT 24
Peak memory 304260 kb
Host smart-3c173bec-ee90-4448-a52b-dd438e16bad4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719450528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.719450528
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3193291899
Short name T97
Test name
Test status
Simulation time 47459186483 ps
CPU time 1076.88 seconds
Started Mar 31 12:51:44 PM PDT 24
Finished Mar 31 01:09:41 PM PDT 24
Peak memory 273200 kb
Host smart-86c2ffbe-5cd7-491a-9a7b-330f454db229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193291899 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3193291899
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.4043570489
Short name T371
Test name
Test status
Simulation time 21766605136 ps
CPU time 616.54 seconds
Started Mar 31 12:51:49 PM PDT 24
Finished Mar 31 01:02:06 PM PDT 24
Peak memory 272908 kb
Host smart-c9778273-a192-4d87-90cd-80e1238e3394
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043570489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.4043570489
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2330387136
Short name T282
Test name
Test status
Simulation time 9960615272 ps
CPU time 193.51 seconds
Started Mar 31 12:51:48 PM PDT 24
Finished Mar 31 12:55:01 PM PDT 24
Peak memory 257172 kb
Host smart-7516507d-9a21-4be6-9fcb-a83d4ced077d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303
87136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2330387136
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2678418502
Short name T236
Test name
Test status
Simulation time 338898132 ps
CPU time 33.56 seconds
Started Mar 31 12:51:44 PM PDT 24
Finished Mar 31 12:52:18 PM PDT 24
Peak memory 254684 kb
Host smart-13976452-7450-4b0c-b936-f6dc76fd0ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26784
18502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2678418502
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3284553154
Short name T470
Test name
Test status
Simulation time 11076487123 ps
CPU time 845.51 seconds
Started Mar 31 12:51:52 PM PDT 24
Finished Mar 31 01:05:58 PM PDT 24
Peak memory 273420 kb
Host smart-6ba844ae-ae60-4a4d-a299-a327da72353a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284553154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3284553154
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2716170461
Short name T547
Test name
Test status
Simulation time 52660121893 ps
CPU time 1827.41 seconds
Started Mar 31 12:51:51 PM PDT 24
Finished Mar 31 01:22:19 PM PDT 24
Peak memory 271532 kb
Host smart-b8a73680-595a-4654-920d-f92f9322e172
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716170461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2716170461
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1187726721
Short name T314
Test name
Test status
Simulation time 18995234791 ps
CPU time 404.78 seconds
Started Mar 31 12:51:48 PM PDT 24
Finished Mar 31 12:58:33 PM PDT 24
Peak memory 248188 kb
Host smart-4b159e28-73b7-4471-9327-1b951e41ae75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187726721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1187726721
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1225316522
Short name T354
Test name
Test status
Simulation time 218495471 ps
CPU time 18.72 seconds
Started Mar 31 12:51:45 PM PDT 24
Finished Mar 31 12:52:04 PM PDT 24
Peak memory 255732 kb
Host smart-fdf400f4-167d-41bb-8060-3c0e7bdb9975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12253
16522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1225316522
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3788487505
Short name T524
Test name
Test status
Simulation time 704261766 ps
CPU time 18.83 seconds
Started Mar 31 12:51:43 PM PDT 24
Finished Mar 31 12:52:02 PM PDT 24
Peak memory 255688 kb
Host smart-573ff097-4290-427a-90eb-5942fd5f1285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37884
87505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3788487505
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1886733718
Short name T685
Test name
Test status
Simulation time 375924514 ps
CPU time 10.05 seconds
Started Mar 31 12:51:50 PM PDT 24
Finished Mar 31 12:52:00 PM PDT 24
Peak memory 248808 kb
Host smart-b129655b-6603-442c-b9c8-c2e62e18c65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18867
33718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1886733718
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1417549552
Short name T71
Test name
Test status
Simulation time 2835659588 ps
CPU time 42.51 seconds
Started Mar 31 12:51:43 PM PDT 24
Finished Mar 31 12:52:25 PM PDT 24
Peak memory 256164 kb
Host smart-484a8705-70e2-4cc5-9dc0-08baba4bb44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14175
49552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1417549552
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.925565300
Short name T625
Test name
Test status
Simulation time 296523874927 ps
CPU time 2621.83 seconds
Started Mar 31 12:51:52 PM PDT 24
Finished Mar 31 01:35:35 PM PDT 24
Peak memory 289948 kb
Host smart-20223eaf-e18f-41ca-93d2-fa9bf297a7de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925565300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.925565300
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2718187915
Short name T499
Test name
Test status
Simulation time 41340480535 ps
CPU time 1348.58 seconds
Started Mar 31 12:51:59 PM PDT 24
Finished Mar 31 01:14:28 PM PDT 24
Peak memory 287888 kb
Host smart-1f3fe43b-da77-4187-a000-d62baf0a10db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718187915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2718187915
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3296247777
Short name T704
Test name
Test status
Simulation time 526371632 ps
CPU time 8.98 seconds
Started Mar 31 12:51:55 PM PDT 24
Finished Mar 31 12:52:05 PM PDT 24
Peak memory 253032 kb
Host smart-3c5975dd-8458-499a-8381-63651c2c9312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32962
47777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3296247777
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2328627910
Short name T611
Test name
Test status
Simulation time 4267332561 ps
CPU time 50.4 seconds
Started Mar 31 12:51:49 PM PDT 24
Finished Mar 31 12:52:39 PM PDT 24
Peak memory 255112 kb
Host smart-66194112-83cb-4c2a-9c25-7e7cae6db963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23286
27910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2328627910
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1290273401
Short name T576
Test name
Test status
Simulation time 14241405527 ps
CPU time 1118.91 seconds
Started Mar 31 12:51:56 PM PDT 24
Finished Mar 31 01:10:35 PM PDT 24
Peak memory 273560 kb
Host smart-3cbc471e-d42f-4b6e-9273-dcdc362928a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290273401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1290273401
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2453925913
Short name T275
Test name
Test status
Simulation time 160401549895 ps
CPU time 1866.88 seconds
Started Mar 31 12:51:56 PM PDT 24
Finished Mar 31 01:23:03 PM PDT 24
Peak memory 268560 kb
Host smart-eb3a0b16-1a3e-48f4-9b4a-ad3539eb1f83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453925913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2453925913
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3990763799
Short name T619
Test name
Test status
Simulation time 27750766292 ps
CPU time 563.49 seconds
Started Mar 31 12:51:59 PM PDT 24
Finished Mar 31 01:01:22 PM PDT 24
Peak memory 248208 kb
Host smart-b0e09eea-fb90-444c-b14e-766b8f6c2585
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990763799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3990763799
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.4185437977
Short name T440
Test name
Test status
Simulation time 7744181235 ps
CPU time 58.29 seconds
Started Mar 31 12:51:49 PM PDT 24
Finished Mar 31 12:52:47 PM PDT 24
Peak memory 248948 kb
Host smart-e26a2eab-b7ae-4da0-b9d2-71301d66d886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41854
37977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.4185437977
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.932725466
Short name T597
Test name
Test status
Simulation time 395062488 ps
CPU time 23.65 seconds
Started Mar 31 12:51:49 PM PDT 24
Finished Mar 31 12:52:13 PM PDT 24
Peak memory 255364 kb
Host smart-42f7261c-b69c-40a1-bffc-4d5892e40a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93272
5466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.932725466
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3792539803
Short name T415
Test name
Test status
Simulation time 1050392514 ps
CPU time 11.8 seconds
Started Mar 31 12:51:57 PM PDT 24
Finished Mar 31 12:52:09 PM PDT 24
Peak memory 247424 kb
Host smart-c2d88e86-cacd-4849-bd6a-e5e59ab02ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37925
39803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3792539803
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.4017937689
Short name T563
Test name
Test status
Simulation time 547636100 ps
CPU time 33.58 seconds
Started Mar 31 12:51:50 PM PDT 24
Finished Mar 31 12:52:24 PM PDT 24
Peak memory 249104 kb
Host smart-dabded32-68ba-42d4-ac4f-e9f1015f754d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40179
37689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.4017937689
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1159401676
Short name T274
Test name
Test status
Simulation time 298498577851 ps
CPU time 4404.66 seconds
Started Mar 31 12:51:59 PM PDT 24
Finished Mar 31 02:05:24 PM PDT 24
Peak memory 298168 kb
Host smart-ccd7fff8-e8ad-4856-95b5-22a5506e6260
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159401676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1159401676
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2959248868
Short name T628
Test name
Test status
Simulation time 11740985252 ps
CPU time 170.69 seconds
Started Mar 31 12:52:04 PM PDT 24
Finished Mar 31 12:54:55 PM PDT 24
Peak memory 249972 kb
Host smart-848525e3-c3e1-44ca-92db-b51724e53e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29592
48868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2959248868
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3517011248
Short name T564
Test name
Test status
Simulation time 1850517708 ps
CPU time 16.21 seconds
Started Mar 31 12:51:57 PM PDT 24
Finished Mar 31 12:52:13 PM PDT 24
Peak memory 253556 kb
Host smart-3d2e5ead-97ed-4593-a3dd-6b5d4227b945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35170
11248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3517011248
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3328861675
Short name T333
Test name
Test status
Simulation time 626369677422 ps
CPU time 2660.7 seconds
Started Mar 31 12:52:04 PM PDT 24
Finished Mar 31 01:36:25 PM PDT 24
Peak memory 288924 kb
Host smart-25521a8f-7318-429e-98b4-45b984487b82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328861675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3328861675
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.546825001
Short name T232
Test name
Test status
Simulation time 112124068098 ps
CPU time 3408.8 seconds
Started Mar 31 12:52:03 PM PDT 24
Finished Mar 31 01:48:53 PM PDT 24
Peak memory 289456 kb
Host smart-91f73ac8-797e-494b-8646-3e3b1bdd5802
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546825001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.546825001
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.37840827
Short name T305
Test name
Test status
Simulation time 3888228496 ps
CPU time 158.03 seconds
Started Mar 31 12:52:04 PM PDT 24
Finished Mar 31 12:54:43 PM PDT 24
Peak memory 247956 kb
Host smart-2d0e31f5-4181-413e-a0ab-d78c516ce13c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37840827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.37840827
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2859401343
Short name T375
Test name
Test status
Simulation time 462910783 ps
CPU time 27.42 seconds
Started Mar 31 12:51:56 PM PDT 24
Finished Mar 31 12:52:24 PM PDT 24
Peak memory 255988 kb
Host smart-c79d0063-407f-461b-b7ac-2275e07959ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28594
01343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2859401343
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1693590482
Short name T102
Test name
Test status
Simulation time 3252475380 ps
CPU time 45.87 seconds
Started Mar 31 12:51:57 PM PDT 24
Finished Mar 31 12:52:43 PM PDT 24
Peak memory 255540 kb
Host smart-db501f8f-592d-402b-b809-9371abe0939b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16935
90482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1693590482
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2503112043
Short name T550
Test name
Test status
Simulation time 189640428 ps
CPU time 7.55 seconds
Started Mar 31 12:52:04 PM PDT 24
Finished Mar 31 12:52:11 PM PDT 24
Peak memory 247324 kb
Host smart-12746f43-5d36-4a4b-87c5-6984d2c98ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25031
12043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2503112043
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3499065152
Short name T469
Test name
Test status
Simulation time 208237885 ps
CPU time 4.46 seconds
Started Mar 31 12:51:56 PM PDT 24
Finished Mar 31 12:52:01 PM PDT 24
Peak memory 240684 kb
Host smart-cfaf2135-2fce-4c0a-a43f-9f3583648144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34990
65152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3499065152
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1068364320
Short name T570
Test name
Test status
Simulation time 42833534511 ps
CPU time 2718.21 seconds
Started Mar 31 12:52:07 PM PDT 24
Finished Mar 31 01:37:26 PM PDT 24
Peak memory 289356 kb
Host smart-b1129801-f6e1-4ad4-a2e5-f44c01bb642b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068364320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1068364320
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1733593209
Short name T104
Test name
Test status
Simulation time 44410222041 ps
CPU time 3081.39 seconds
Started Mar 31 12:52:04 PM PDT 24
Finished Mar 31 01:43:26 PM PDT 24
Peak memory 298320 kb
Host smart-b4e681f7-72b0-4e38-91fd-a2b5f489e7a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733593209 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1733593209
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1002430729
Short name T116
Test name
Test status
Simulation time 35767592077 ps
CPU time 862.01 seconds
Started Mar 31 12:52:14 PM PDT 24
Finished Mar 31 01:06:36 PM PDT 24
Peak memory 269352 kb
Host smart-62bc4f48-414f-42aa-bfca-b9a7574efdae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002430729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1002430729
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.88767940
Short name T600
Test name
Test status
Simulation time 11040716783 ps
CPU time 153.24 seconds
Started Mar 31 12:52:14 PM PDT 24
Finished Mar 31 12:54:48 PM PDT 24
Peak memory 256720 kb
Host smart-945fc54e-9d58-488d-ab31-8a1a5903374c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88767
940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.88767940
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2681927886
Short name T697
Test name
Test status
Simulation time 801617388 ps
CPU time 13.04 seconds
Started Mar 31 12:52:12 PM PDT 24
Finished Mar 31 12:52:25 PM PDT 24
Peak memory 251624 kb
Host smart-79a5c8e6-1ba2-4848-8a39-703046eaefb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26819
27886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2681927886
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.128342782
Short name T604
Test name
Test status
Simulation time 26224658467 ps
CPU time 1251.67 seconds
Started Mar 31 12:52:12 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 283208 kb
Host smart-754e24c8-b8fd-4442-b4ce-d9662be704c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128342782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.128342782
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3849345860
Short name T2
Test name
Test status
Simulation time 86452391657 ps
CPU time 1506.8 seconds
Started Mar 31 12:52:11 PM PDT 24
Finished Mar 31 01:17:18 PM PDT 24
Peak memory 288944 kb
Host smart-dab18ab3-d344-4692-bdf1-6a8ff2eb5173
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849345860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3849345860
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.4080014969
Short name T290
Test name
Test status
Simulation time 30916436639 ps
CPU time 442.25 seconds
Started Mar 31 12:52:10 PM PDT 24
Finished Mar 31 12:59:32 PM PDT 24
Peak memory 248168 kb
Host smart-197c1059-61bf-493d-8de1-b3b182acfa9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080014969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.4080014969
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.507054772
Short name T60
Test name
Test status
Simulation time 1025272933 ps
CPU time 54.18 seconds
Started Mar 31 12:52:03 PM PDT 24
Finished Mar 31 12:52:57 PM PDT 24
Peak memory 255992 kb
Host smart-abc52063-0f2e-4932-bcd2-9de40390bfc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50705
4772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.507054772
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.712577107
Short name T231
Test name
Test status
Simulation time 263876100 ps
CPU time 24.12 seconds
Started Mar 31 12:52:15 PM PDT 24
Finished Mar 31 12:52:39 PM PDT 24
Peak memory 255432 kb
Host smart-062b9c91-eee8-4fe7-a730-730f5c4c64a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71257
7107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.712577107
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1996835026
Short name T605
Test name
Test status
Simulation time 1583180575 ps
CPU time 10.45 seconds
Started Mar 31 12:52:10 PM PDT 24
Finished Mar 31 12:52:21 PM PDT 24
Peak memory 248884 kb
Host smart-9a9cefaf-3ea4-4756-b482-7dc329e015cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19968
35026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1996835026
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3454943260
Short name T30
Test name
Test status
Simulation time 165735339 ps
CPU time 15.68 seconds
Started Mar 31 12:52:04 PM PDT 24
Finished Mar 31 12:52:20 PM PDT 24
Peak memory 256052 kb
Host smart-fd882c11-4c68-4fc4-b4a6-d4c653a9bc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34549
43260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3454943260
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.889530038
Short name T455
Test name
Test status
Simulation time 1088926632 ps
CPU time 63.66 seconds
Started Mar 31 12:52:19 PM PDT 24
Finished Mar 31 12:53:22 PM PDT 24
Peak memory 256156 kb
Host smart-c1da98e6-64f0-43bd-a3c1-d219f743e7de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889530038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.889530038
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1302905935
Short name T418
Test name
Test status
Simulation time 253201664157 ps
CPU time 2506.21 seconds
Started Mar 31 12:52:27 PM PDT 24
Finished Mar 31 01:34:13 PM PDT 24
Peak memory 281624 kb
Host smart-19c94e66-49c9-48e5-bbc6-ff0d485fd7b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302905935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1302905935
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2314131290
Short name T90
Test name
Test status
Simulation time 9949456563 ps
CPU time 163.83 seconds
Started Mar 31 12:52:29 PM PDT 24
Finished Mar 31 12:55:14 PM PDT 24
Peak memory 256692 kb
Host smart-2b24a0ce-1976-4c65-a988-a17d73b2dbbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23141
31290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2314131290
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3582618137
Short name T599
Test name
Test status
Simulation time 1154968589 ps
CPU time 40.7 seconds
Started Mar 31 12:52:28 PM PDT 24
Finished Mar 31 12:53:08 PM PDT 24
Peak memory 255032 kb
Host smart-52a8510b-85e1-4750-903d-970e380bb96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35826
18137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3582618137
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2418114917
Short name T551
Test name
Test status
Simulation time 12866077631 ps
CPU time 865.78 seconds
Started Mar 31 12:52:23 PM PDT 24
Finished Mar 31 01:06:49 PM PDT 24
Peak memory 272700 kb
Host smart-0d6e36a8-8c14-4a48-939f-e1923fe70ec1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418114917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2418114917
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.197192238
Short name T554
Test name
Test status
Simulation time 46494369387 ps
CPU time 1870.94 seconds
Started Mar 31 12:52:26 PM PDT 24
Finished Mar 31 01:23:37 PM PDT 24
Peak memory 273548 kb
Host smart-7a4d112d-5e38-4b77-93f3-6969c39f9af0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197192238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.197192238
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3248258599
Short name T567
Test name
Test status
Simulation time 5077104675 ps
CPU time 204.57 seconds
Started Mar 31 12:52:25 PM PDT 24
Finished Mar 31 12:55:50 PM PDT 24
Peak memory 254652 kb
Host smart-2ab991af-6c62-4b05-8ba5-0ad81addf2c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248258599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3248258599
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1916169548
Short name T569
Test name
Test status
Simulation time 708499145 ps
CPU time 38.31 seconds
Started Mar 31 12:52:19 PM PDT 24
Finished Mar 31 12:52:57 PM PDT 24
Peak memory 255524 kb
Host smart-ecdd01b3-770f-42db-8583-385a9300c275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19161
69548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1916169548
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2108182762
Short name T407
Test name
Test status
Simulation time 175687599 ps
CPU time 16.8 seconds
Started Mar 31 12:52:17 PM PDT 24
Finished Mar 31 12:52:34 PM PDT 24
Peak memory 247752 kb
Host smart-4d014da7-ce1a-473c-b2ff-e91a96402abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21081
82762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2108182762
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1828050104
Short name T112
Test name
Test status
Simulation time 1182335602 ps
CPU time 26.06 seconds
Started Mar 31 12:52:28 PM PDT 24
Finished Mar 31 12:52:55 PM PDT 24
Peak memory 247564 kb
Host smart-01297600-166a-413f-9d63-8e2197924773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18280
50104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1828050104
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.258561886
Short name T215
Test name
Test status
Simulation time 553580999 ps
CPU time 25.08 seconds
Started Mar 31 12:52:18 PM PDT 24
Finished Mar 31 12:52:44 PM PDT 24
Peak memory 248864 kb
Host smart-3786055b-c75d-4d39-886c-6c60718ca1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25856
1886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.258561886
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2515369049
Short name T111
Test name
Test status
Simulation time 121588806152 ps
CPU time 2214.01 seconds
Started Mar 31 12:52:35 PM PDT 24
Finished Mar 31 01:29:29 PM PDT 24
Peak memory 290028 kb
Host smart-50b09ce3-e7b9-44dd-9906-8daf7bf8114f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515369049 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2515369049
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2071279611
Short name T199
Test name
Test status
Simulation time 17881156 ps
CPU time 2.6 seconds
Started Mar 31 12:48:34 PM PDT 24
Finished Mar 31 12:48:37 PM PDT 24
Peak memory 249128 kb
Host smart-bcae1def-e3c8-455e-8543-736b77483cee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2071279611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2071279611
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3000557955
Short name T558
Test name
Test status
Simulation time 43495420977 ps
CPU time 2575.41 seconds
Started Mar 31 12:48:32 PM PDT 24
Finished Mar 31 01:31:28 PM PDT 24
Peak memory 289848 kb
Host smart-e23dd168-de56-441d-8d45-213026e431b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000557955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3000557955
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.650087096
Short name T409
Test name
Test status
Simulation time 871932352 ps
CPU time 12.07 seconds
Started Mar 31 12:48:34 PM PDT 24
Finished Mar 31 12:48:46 PM PDT 24
Peak memory 240684 kb
Host smart-15f32eef-85b1-460b-936b-871b138cfa4c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=650087096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.650087096
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.4157433165
Short name T670
Test name
Test status
Simulation time 35233674 ps
CPU time 2.72 seconds
Started Mar 31 12:48:28 PM PDT 24
Finished Mar 31 12:48:30 PM PDT 24
Peak memory 239200 kb
Host smart-0a6a940c-8fbc-45b2-99e1-a10cef5f3905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41574
33165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.4157433165
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2654435314
Short name T255
Test name
Test status
Simulation time 3852768076 ps
CPU time 58.93 seconds
Started Mar 31 12:48:27 PM PDT 24
Finished Mar 31 12:49:27 PM PDT 24
Peak memory 248636 kb
Host smart-b57a8057-ddf8-4e1f-a12c-7f3381faf560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26544
35314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2654435314
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3681528782
Short name T325
Test name
Test status
Simulation time 16659926561 ps
CPU time 1203.1 seconds
Started Mar 31 12:48:33 PM PDT 24
Finished Mar 31 01:08:37 PM PDT 24
Peak memory 281792 kb
Host smart-317f0460-cbc0-4160-be95-4da4e79af076
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681528782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3681528782
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3782552048
Short name T658
Test name
Test status
Simulation time 77074300149 ps
CPU time 1258.16 seconds
Started Mar 31 12:48:34 PM PDT 24
Finished Mar 31 01:09:33 PM PDT 24
Peak memory 273552 kb
Host smart-430ec97c-1c9f-43e8-ae4a-2f4a0e6aa03f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782552048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3782552048
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2625707530
Short name T304
Test name
Test status
Simulation time 18907671586 ps
CPU time 390.05 seconds
Started Mar 31 12:48:35 PM PDT 24
Finished Mar 31 12:55:05 PM PDT 24
Peak memory 247896 kb
Host smart-cee04300-6330-44d6-ae70-f556e4d6ece5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625707530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2625707530
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.967887614
Short name T526
Test name
Test status
Simulation time 2205452850 ps
CPU time 66.37 seconds
Started Mar 31 12:48:29 PM PDT 24
Finished Mar 31 12:49:35 PM PDT 24
Peak memory 256068 kb
Host smart-4f2cdf81-b4e3-429f-9c67-6f619277f3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96788
7614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.967887614
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1764393491
Short name T461
Test name
Test status
Simulation time 1736629281 ps
CPU time 30.93 seconds
Started Mar 31 12:48:29 PM PDT 24
Finished Mar 31 12:49:00 PM PDT 24
Peak memory 248508 kb
Host smart-75ac8681-181b-44aa-8d80-cecd9655d74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17643
93491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1764393491
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.305345980
Short name T609
Test name
Test status
Simulation time 278232938 ps
CPU time 15.57 seconds
Started Mar 31 12:48:29 PM PDT 24
Finished Mar 31 12:48:44 PM PDT 24
Peak memory 253088 kb
Host smart-328becab-79cb-4996-9021-9a9242320550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30534
5980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.305345980
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3030384700
Short name T355
Test name
Test status
Simulation time 2817381845 ps
CPU time 31.03 seconds
Started Mar 31 12:48:31 PM PDT 24
Finished Mar 31 12:49:02 PM PDT 24
Peak memory 248924 kb
Host smart-863d154c-bdcb-4eb1-8643-c17ef5cf6935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30303
84700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3030384700
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3360366032
Short name T405
Test name
Test status
Simulation time 15669565745 ps
CPU time 230.85 seconds
Started Mar 31 12:48:33 PM PDT 24
Finished Mar 31 12:52:24 PM PDT 24
Peak memory 256692 kb
Host smart-48daefca-aa05-4798-8fb1-dac73121a3ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360366032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3360366032
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.742191405
Short name T198
Test name
Test status
Simulation time 60541109 ps
CPU time 3.08 seconds
Started Mar 31 12:48:40 PM PDT 24
Finished Mar 31 12:48:44 PM PDT 24
Peak memory 249104 kb
Host smart-0dd9d099-4eb9-437c-a7b1-b271ee57b661
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=742191405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.742191405
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2847799672
Short name T646
Test name
Test status
Simulation time 95180035618 ps
CPU time 1403.85 seconds
Started Mar 31 12:48:38 PM PDT 24
Finished Mar 31 01:12:02 PM PDT 24
Peak memory 289676 kb
Host smart-5e91f8a9-33eb-4c20-bea3-e69de7c2e9d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847799672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2847799672
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1701857158
Short name T561
Test name
Test status
Simulation time 565851783 ps
CPU time 24.56 seconds
Started Mar 31 12:48:37 PM PDT 24
Finished Mar 31 12:49:02 PM PDT 24
Peak memory 252204 kb
Host smart-8bbd202f-4138-4a48-8b78-1e56c195c6bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1701857158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1701857158
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3909807042
Short name T67
Test name
Test status
Simulation time 410883696 ps
CPU time 24.89 seconds
Started Mar 31 12:48:35 PM PDT 24
Finished Mar 31 12:49:00 PM PDT 24
Peak memory 256220 kb
Host smart-6ec316b9-14bb-43f7-84e0-234e7c0a5564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39098
07042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3909807042
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3374454344
Short name T21
Test name
Test status
Simulation time 2385486454 ps
CPU time 19.81 seconds
Started Mar 31 12:48:35 PM PDT 24
Finished Mar 31 12:48:54 PM PDT 24
Peak memory 255004 kb
Host smart-e27f8fab-e9f2-4758-bbbe-ca456677f665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33744
54344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3374454344
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.426126211
Short name T489
Test name
Test status
Simulation time 25602200541 ps
CPU time 1247.03 seconds
Started Mar 31 12:48:32 PM PDT 24
Finished Mar 31 01:09:19 PM PDT 24
Peak memory 289000 kb
Host smart-7c0c2044-27b5-4784-bb8c-8efa4e1106f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426126211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.426126211
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.308361326
Short name T413
Test name
Test status
Simulation time 275161468889 ps
CPU time 2690.47 seconds
Started Mar 31 12:48:33 PM PDT 24
Finished Mar 31 01:33:24 PM PDT 24
Peak memory 281728 kb
Host smart-27edce2e-6018-462d-a1d7-b9da2cb114bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308361326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.308361326
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.4189820780
Short name T641
Test name
Test status
Simulation time 10115757868 ps
CPU time 422.2 seconds
Started Mar 31 12:48:37 PM PDT 24
Finished Mar 31 12:55:39 PM PDT 24
Peak memory 248064 kb
Host smart-c04e7331-1792-47be-9f19-6623f2ccd4e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189820780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.4189820780
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2009997491
Short name T453
Test name
Test status
Simulation time 714845913 ps
CPU time 32.06 seconds
Started Mar 31 12:48:33 PM PDT 24
Finished Mar 31 12:49:05 PM PDT 24
Peak memory 248856 kb
Host smart-e96248b2-cab5-4e44-b57f-9f16a230ccac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20099
97491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2009997491
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.221381283
Short name T420
Test name
Test status
Simulation time 1655924425 ps
CPU time 29.2 seconds
Started Mar 31 12:48:37 PM PDT 24
Finished Mar 31 12:49:07 PM PDT 24
Peak memory 254400 kb
Host smart-9e15e738-3999-4fbb-b658-1064b030676d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22138
1283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.221381283
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3300484280
Short name T250
Test name
Test status
Simulation time 1553670003 ps
CPU time 27.61 seconds
Started Mar 31 12:48:32 PM PDT 24
Finished Mar 31 12:49:00 PM PDT 24
Peak memory 255468 kb
Host smart-b4ae559e-3d0c-4d6d-9174-0532dcd53f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33004
84280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3300484280
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2935725748
Short name T559
Test name
Test status
Simulation time 291442396 ps
CPU time 9.96 seconds
Started Mar 31 12:48:37 PM PDT 24
Finished Mar 31 12:48:47 PM PDT 24
Peak memory 248868 kb
Host smart-56b66d13-ca9f-4002-949f-97c12240133f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29357
25748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2935725748
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1164391415
Short name T49
Test name
Test status
Simulation time 5378571377 ps
CPU time 345.91 seconds
Started Mar 31 12:48:33 PM PDT 24
Finished Mar 31 12:54:19 PM PDT 24
Peak memory 257052 kb
Host smart-27968e7f-3053-43e1-a8e0-b28dfda71989
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164391415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1164391415
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1785285055
Short name T535
Test name
Test status
Simulation time 535240618778 ps
CPU time 10540.1 seconds
Started Mar 31 12:48:41 PM PDT 24
Finished Mar 31 03:44:22 PM PDT 24
Peak memory 338448 kb
Host smart-aeccf12b-fcec-4958-8592-bfe42e408262
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785285055 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1785285055
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3397516834
Short name T202
Test name
Test status
Simulation time 33654936 ps
CPU time 3.26 seconds
Started Mar 31 12:48:43 PM PDT 24
Finished Mar 31 12:48:47 PM PDT 24
Peak memory 249072 kb
Host smart-8380d4c0-be18-4024-9548-d7bd3e18b6d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3397516834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3397516834
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2487840682
Short name T57
Test name
Test status
Simulation time 46571936668 ps
CPU time 2371.04 seconds
Started Mar 31 12:48:40 PM PDT 24
Finished Mar 31 01:28:11 PM PDT 24
Peak memory 281752 kb
Host smart-9ed203de-c501-412d-b196-d5f6039ac1fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487840682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2487840682
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.696283657
Short name T416
Test name
Test status
Simulation time 5109114653 ps
CPU time 41.16 seconds
Started Mar 31 12:48:41 PM PDT 24
Finished Mar 31 12:49:22 PM PDT 24
Peak memory 240776 kb
Host smart-95f7aeb9-1b4a-4806-ba5c-3e4bba847d4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=696283657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.696283657
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.446797759
Short name T386
Test name
Test status
Simulation time 2372442194 ps
CPU time 144.55 seconds
Started Mar 31 12:48:42 PM PDT 24
Finished Mar 31 12:51:07 PM PDT 24
Peak memory 248896 kb
Host smart-5fbe9a67-eae5-4dd7-aa42-aa4695d22f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44679
7759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.446797759
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2553851247
Short name T357
Test name
Test status
Simulation time 665742532 ps
CPU time 15.83 seconds
Started Mar 31 12:48:42 PM PDT 24
Finished Mar 31 12:48:58 PM PDT 24
Peak memory 248880 kb
Host smart-fe9afc14-25e4-4255-9cdf-329205f44e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25538
51247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2553851247
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4265531646
Short name T318
Test name
Test status
Simulation time 198499973377 ps
CPU time 2030.22 seconds
Started Mar 31 12:48:42 PM PDT 24
Finished Mar 31 01:22:33 PM PDT 24
Peak memory 289356 kb
Host smart-31f5f9f5-d365-4736-aab3-94c50dcee436
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265531646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4265531646
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2857572258
Short name T101
Test name
Test status
Simulation time 42474915709 ps
CPU time 990.69 seconds
Started Mar 31 12:48:44 PM PDT 24
Finished Mar 31 01:05:15 PM PDT 24
Peak memory 273112 kb
Host smart-2eab7f04-e623-4f5c-82cd-dbbf800de04d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857572258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2857572258
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1805411679
Short name T506
Test name
Test status
Simulation time 1920744307 ps
CPU time 9.31 seconds
Started Mar 31 12:48:40 PM PDT 24
Finished Mar 31 12:48:49 PM PDT 24
Peak memory 248900 kb
Host smart-c1c3b938-ac32-4de7-9b94-6e2652883690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18054
11679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1805411679
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2932972105
Short name T515
Test name
Test status
Simulation time 865750855 ps
CPU time 24.19 seconds
Started Mar 31 12:48:42 PM PDT 24
Finished Mar 31 12:49:07 PM PDT 24
Peak memory 254912 kb
Host smart-ad789fd6-6496-4923-8f4f-35d00567f4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29329
72105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2932972105
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.323417200
Short name T528
Test name
Test status
Simulation time 1010972221 ps
CPU time 15.24 seconds
Started Mar 31 12:48:42 PM PDT 24
Finished Mar 31 12:48:57 PM PDT 24
Peak memory 248812 kb
Host smart-4f529c05-c0bf-4c01-a882-18b781ba8ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32341
7200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.323417200
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2791409460
Short name T673
Test name
Test status
Simulation time 1258047658 ps
CPU time 39.67 seconds
Started Mar 31 12:48:40 PM PDT 24
Finished Mar 31 12:49:20 PM PDT 24
Peak memory 257060 kb
Host smart-a48015b3-6f48-4f0c-9b85-b56487de11c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27914
09460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2791409460
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3371223810
Short name T509
Test name
Test status
Simulation time 119593908014 ps
CPU time 1894.85 seconds
Started Mar 31 12:48:42 PM PDT 24
Finished Mar 31 01:20:17 PM PDT 24
Peak memory 281784 kb
Host smart-24c0e1a7-58db-4d0e-8b11-9261dddc2ad5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371223810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3371223810
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2805522534
Short name T37
Test name
Test status
Simulation time 158977322 ps
CPU time 3.58 seconds
Started Mar 31 12:48:42 PM PDT 24
Finished Mar 31 12:48:46 PM PDT 24
Peak memory 249040 kb
Host smart-1cc654d3-097a-43fb-9b67-7e749029d2e5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2805522534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2805522534
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3653633833
Short name T113
Test name
Test status
Simulation time 17152324282 ps
CPU time 1440.39 seconds
Started Mar 31 12:48:40 PM PDT 24
Finished Mar 31 01:12:40 PM PDT 24
Peak memory 288676 kb
Host smart-eb0ed6ff-2e27-4dae-ab99-44b434ece05e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653633833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3653633833
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1087027472
Short name T224
Test name
Test status
Simulation time 864371305 ps
CPU time 8.93 seconds
Started Mar 31 12:48:40 PM PDT 24
Finished Mar 31 12:48:49 PM PDT 24
Peak memory 240680 kb
Host smart-c3700d06-e428-4091-8b96-7fcde03e2e02
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1087027472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1087027472
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1308405699
Short name T264
Test name
Test status
Simulation time 5363479864 ps
CPU time 108.57 seconds
Started Mar 31 12:48:44 PM PDT 24
Finished Mar 31 12:50:32 PM PDT 24
Peak memory 256868 kb
Host smart-c3c4cecd-e449-4c4e-b048-f31548494ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13084
05699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1308405699
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.866931160
Short name T87
Test name
Test status
Simulation time 38252617 ps
CPU time 5.14 seconds
Started Mar 31 12:48:41 PM PDT 24
Finished Mar 31 12:48:47 PM PDT 24
Peak memory 251580 kb
Host smart-44ed5e6e-3c16-4015-a6e5-ad1f7905cb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86693
1160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.866931160
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.4244853335
Short name T584
Test name
Test status
Simulation time 7126843058 ps
CPU time 287.22 seconds
Started Mar 31 12:48:43 PM PDT 24
Finished Mar 31 12:53:31 PM PDT 24
Peak memory 247916 kb
Host smart-50cf5322-4dac-47a0-a888-5a4b71253e31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244853335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.4244853335
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.843737105
Short name T637
Test name
Test status
Simulation time 285029814 ps
CPU time 25.24 seconds
Started Mar 31 12:48:42 PM PDT 24
Finished Mar 31 12:49:08 PM PDT 24
Peak memory 248840 kb
Host smart-42d41a94-201a-45ee-9689-354bf814f89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84373
7105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.843737105
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1759573684
Short name T271
Test name
Test status
Simulation time 664243112 ps
CPU time 19.51 seconds
Started Mar 31 12:48:43 PM PDT 24
Finished Mar 31 12:49:03 PM PDT 24
Peak memory 255096 kb
Host smart-b0aaf618-d849-4b1a-87c6-94f2376ca90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17595
73684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1759573684
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3767757574
Short name T677
Test name
Test status
Simulation time 1652219533 ps
CPU time 46.08 seconds
Started Mar 31 12:48:43 PM PDT 24
Finished Mar 31 12:49:29 PM PDT 24
Peak memory 255568 kb
Host smart-0ed576cb-bf4d-4084-8ac1-2ed68e874784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37677
57574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3767757574
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.548713086
Short name T530
Test name
Test status
Simulation time 185235937 ps
CPU time 14.29 seconds
Started Mar 31 12:48:42 PM PDT 24
Finished Mar 31 12:48:56 PM PDT 24
Peak memory 248820 kb
Host smart-7074364f-596c-4a19-9231-abb1c383eb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54871
3086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.548713086
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1184605659
Short name T536
Test name
Test status
Simulation time 4627655480 ps
CPU time 295.41 seconds
Started Mar 31 12:48:43 PM PDT 24
Finished Mar 31 12:53:39 PM PDT 24
Peak memory 257156 kb
Host smart-687d11e6-26cd-4408-973b-d494964b1dcb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184605659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1184605659
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2715993167
Short name T259
Test name
Test status
Simulation time 35633526394 ps
CPU time 2618.94 seconds
Started Mar 31 12:48:42 PM PDT 24
Finished Mar 31 01:32:21 PM PDT 24
Peak memory 289188 kb
Host smart-dfabea02-6060-4455-b252-e5b3af61744d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715993167 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2715993167
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1393257948
Short name T205
Test name
Test status
Simulation time 37778061 ps
CPU time 3.75 seconds
Started Mar 31 12:48:51 PM PDT 24
Finished Mar 31 12:48:55 PM PDT 24
Peak memory 249052 kb
Host smart-844972a8-6a3d-4978-a3c7-2cc9d982c68b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1393257948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1393257948
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1956360948
Short name T62
Test name
Test status
Simulation time 21813302675 ps
CPU time 1380.97 seconds
Started Mar 31 12:48:47 PM PDT 24
Finished Mar 31 01:11:49 PM PDT 24
Peak memory 265376 kb
Host smart-0e48e8c2-1b58-4331-a49e-36195d90ebfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956360948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1956360948
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3839789939
Short name T595
Test name
Test status
Simulation time 654965870 ps
CPU time 16.58 seconds
Started Mar 31 12:48:51 PM PDT 24
Finished Mar 31 12:49:08 PM PDT 24
Peak memory 252596 kb
Host smart-0e34f86d-1d87-4d47-9eb2-9ad6389305ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3839789939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3839789939
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3870950972
Short name T360
Test name
Test status
Simulation time 1101449074 ps
CPU time 76.64 seconds
Started Mar 31 12:48:41 PM PDT 24
Finished Mar 31 12:49:58 PM PDT 24
Peak memory 256804 kb
Host smart-5fa82101-d03f-4725-a11b-107fa91a1ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38709
50972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3870950972
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.589277221
Short name T627
Test name
Test status
Simulation time 320420230 ps
CPU time 32.13 seconds
Started Mar 31 12:48:41 PM PDT 24
Finished Mar 31 12:49:13 PM PDT 24
Peak memory 254836 kb
Host smart-2bdb5296-4f0f-490d-b01a-df8e81707ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58927
7221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.589277221
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1510492823
Short name T699
Test name
Test status
Simulation time 15816811485 ps
CPU time 643.01 seconds
Started Mar 31 12:48:46 PM PDT 24
Finished Mar 31 12:59:29 PM PDT 24
Peak memory 265320 kb
Host smart-8640c2a7-3533-4b79-9541-5315c7f22230
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510492823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1510492823
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2267438545
Short name T278
Test name
Test status
Simulation time 62751121033 ps
CPU time 3496.8 seconds
Started Mar 31 12:48:45 PM PDT 24
Finished Mar 31 01:47:03 PM PDT 24
Peak memory 289500 kb
Host smart-dac0923e-902b-4b0f-8f50-3f5987e3e126
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267438545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2267438545
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3154866399
Short name T376
Test name
Test status
Simulation time 2249376395 ps
CPU time 37.4 seconds
Started Mar 31 12:48:43 PM PDT 24
Finished Mar 31 12:49:21 PM PDT 24
Peak memory 256080 kb
Host smart-c9922b94-0fbf-4013-9e81-aae31031f2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31548
66399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3154866399
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1817906293
Short name T488
Test name
Test status
Simulation time 372467332 ps
CPU time 31.87 seconds
Started Mar 31 12:48:41 PM PDT 24
Finished Mar 31 12:49:14 PM PDT 24
Peak memory 255572 kb
Host smart-cb37a284-c7a1-4cfa-a776-1bc7387c0df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18179
06293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1817906293
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2759984722
Short name T607
Test name
Test status
Simulation time 1998097702 ps
CPU time 34.86 seconds
Started Mar 31 12:48:42 PM PDT 24
Finished Mar 31 12:49:17 PM PDT 24
Peak memory 254596 kb
Host smart-3db75f57-7770-4810-907f-a15cd9ebaa52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27599
84722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2759984722
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2434136563
Short name T369
Test name
Test status
Simulation time 1054655176 ps
CPU time 56.05 seconds
Started Mar 31 12:48:43 PM PDT 24
Finished Mar 31 12:49:39 PM PDT 24
Peak memory 248868 kb
Host smart-6be48493-575b-411c-93d5-dac5591a1537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24341
36563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2434136563
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.110321852
Short name T48
Test name
Test status
Simulation time 15948139748 ps
CPU time 1094.07 seconds
Started Mar 31 12:48:46 PM PDT 24
Finished Mar 31 01:07:01 PM PDT 24
Peak memory 265316 kb
Host smart-6d9f8bae-f563-48bb-a013-d47b384be9c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110321852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.110321852
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.720827459
Short name T123
Test name
Test status
Simulation time 1425144488307 ps
CPU time 4565.11 seconds
Started Mar 31 12:48:45 PM PDT 24
Finished Mar 31 02:04:51 PM PDT 24
Peak memory 314624 kb
Host smart-77b627fe-a128-4234-b252-9e201ab8447c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720827459 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.720827459
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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