Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T205,T206
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13318	0	0
DisabledNoTrigBkwd_A	2147483647	871555	0	0
DisabledNoTrigFwd_A	2147483647	1434729245	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13318	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	460	0	0
T25	39830	0	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0
T35	297455	0	0	0
T49	589533	0	0	0
T100	701670	0	0	0
T101	185022	0	0	0
T205	0	1119	0	0
T206	0	566	0	0
T207	1093	333	0	0
T208	0	378	0	0
T209	0	1002	0	0
T210	0	591	0	0
T211	1293	334	0	0
T212	0	941	0	0
T213	0	331	0	0
T214	0	530	0	0
T215	0	382	0	0
T216	0	754	0	0
T217	0	659	0	0
T218	0	1575	0	0
T219	0	421	0	0
T220	0	671	0	0
T221	0	1462	0	0
T222	0	399	0	0
T223	0	410	0	0
T224	10767	0	0	0
T225	409006	0	0	0
T226	12817	0	0	0
T227	17723	0	0	0
T228	27481	0	0	0
T229	28948	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	871555	0	0
T1	617411	5	0	0
T2	52694	78	0	0
T3	202476	64	0	0
T4	1070112	1486	0	0
T5	1573972	3724	0	0
T6	735196	433	0	0
T7	3517752	3746	0	0
T8	44874	0	0	0
T9	0	37	0	0
T14	0	191	0	0
T15	0	462	0	0
T16	0	2334	0	0
T17	49196	11	0	0
T18	38784	11	0	0
T19	109720	0	0	0
T22	0	7	0	0
T23	84176	1	0	0
T25	0	14	0	0
T31	0	41	0	0
T32	0	5	0	0
T35	0	38	0	0
T36	0	38	0	0
T37	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1434729245	0	0
T1	2469644	1070857	0	0
T2	105388	79711	0	0
T3	202476	66158	0	0
T4	1070112	812921	0	0
T5	1573972	812907	0	0
T6	735196	394818	0	0
T7	3517752	1759864	0	0
T17	49196	36539	0	0
T18	38784	13807	0	0
T19	109720	56731	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T205,T208
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	693182191	3290	0	0
DisabledNoTrigBkwd_A	693182191	255563	0	0
DisabledNoTrigFwd_A	693182191	340626196	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	3290	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	460	0	0
T25	39830	0	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0
T35	297455	0	0	0
T205	0	1119	0	0
T208	0	378	0	0
T209	0	1002	0	0
T213	0	331	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	255563	0	0
T2	26347	78	0	0
T3	50619	16	0	0
T4	267528	0	0	0
T5	393493	2	0	0
T6	183799	2	0	0
T7	879438	1749	0	0
T8	14958	0	0	0
T17	12299	11	0	0
T18	9696	3	0	0
T19	27430	0	0	0
T22	0	7	0	0
T23	0	1	0	0
T31	0	41	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	340626196	0	0
T1	617411	1971	0	0
T2	26347	901	0	0
T3	50619	18554	0	0
T4	267528	266931	0	0
T5	393493	392799	0	0
T6	183799	2066	0	0
T7	879438	2032	0	0
T17	12299	2061	0	0
T18	9696	2780	0	0
T19	27430	20105	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T211,T212,T216
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	693182191	3121	0	0
DisabledNoTrigBkwd_A	693182191	239887	0	0
DisabledNoTrigFwd_A	693182191	340968598	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	3121	0	0
T49	589533	0	0	0
T100	701670	0	0	0
T101	185022	0	0	0
T211	1293	334	0	0
T212	0	941	0	0
T216	0	754	0	0
T219	0	421	0	0
T220	0	671	0	0
T224	10767	0	0	0
T225	409006	0	0	0
T226	12817	0	0	0
T227	17723	0	0	0
T228	27481	0	0	0
T229	28948	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	239887	0	0
T3	50619	1	0	0
T4	267528	1481	0	0
T5	393493	88	0	0
T6	183799	431	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	0	28	0	0
T15	0	173	0	0
T16	0	1392	0	0
T17	12299	0	0	0
T18	9696	6	0	0
T19	27430	0	0	0
T23	42088	0	0	0
T35	0	38	0	0
T37	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	340968598	0	0
T1	617411	481247	0	0
T2	26347	26270	0	0
T3	50619	35200	0	0
T4	267528	11940	0	0
T5	393493	391096	0	0
T6	183799	25168	0	0
T7	879438	877949	0	0
T17	12299	12202	0	0
T18	9696	1715	0	0
T19	27430	27343	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207,T215,T218
1	1	Covered	T1,T3,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	693182191	3752	0	0
DisabledNoTrigBkwd_A	693182191	185854	0	0
DisabledNoTrigFwd_A	693182191	366318172	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	3752	0	0
T109	598449	0	0	0
T207	1093	333	0	0
T208	1168	0	0	0
T215	0	382	0	0
T218	0	1575	0	0
T221	0	1462	0	0
T230	323710	0	0	0
T231	899983	0	0	0
T232	38236	0	0	0
T233	11338	0	0	0
T234	437327	0	0	0
T235	27248	0	0	0
T236	2692	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	185854	0	0
T3	50619	29	0	0
T4	267528	0	0	0
T5	393493	1629	0	0
T6	183799	0	0	0
T7	879438	2	0	0
T8	14958	0	0	0
T9	0	9	0	0
T14	0	190	0	0
T15	0	187	0	0
T16	0	20	0	0
T17	12299	0	0	0
T18	9696	0	0	0
T19	27430	0	0	0
T23	42088	0	0	0
T25	0	8	0	0
T32	0	5	0	0
T36	0	38	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	366318172	0	0
T1	617411	585623	0	0
T2	26347	26270	0	0
T3	50619	6196	0	0
T4	267528	267523	0	0
T5	393493	9933	0	0
T6	183799	183792	0	0
T7	879438	877949	0	0
T17	12299	10074	0	0
T18	9696	5391	0	0
T19	27430	2332	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T210,T214
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	693182191	3155	0	0
DisabledNoTrigBkwd_A	693182191	190251	0	0
DisabledNoTrigFwd_A	693182191	386816279	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	3155	0	0
T44	185398	0	0	0
T45	132889	0	0	0
T67	12223	0	0	0
T68	78013	0	0	0
T69	48130	0	0	0
T70	34788	0	0	0
T99	220681	0	0	0
T206	4108	566	0	0
T210	0	591	0	0
T214	0	530	0	0
T217	0	659	0	0
T222	0	399	0	0
T223	0	410	0	0
T237	114297	0	0	0
T238	945517	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	190251	0	0
T1	617411	5	0	0
T2	26347	0	0	0
T3	50619	18	0	0
T4	267528	5	0	0
T5	393493	2005	0	0
T6	183799	0	0	0
T7	879438	1995	0	0
T14	0	1	0	0
T15	0	102	0	0
T16	0	922	0	0
T17	12299	0	0	0
T18	9696	2	0	0
T19	27430	0	0	0
T25	0	6	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	386816279	0	0
T1	617411	2016	0	0
T2	26347	26270	0	0
T3	50619	6208	0	0
T4	267528	266527	0	0
T5	393493	19079	0	0
T6	183799	183792	0	0
T7	879438	1934	0	0
T17	12299	12202	0	0
T18	9696	3921	0	0
T19	27430	6951	0	0