Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T17

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T17,T4
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T3,T4,T5

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T19,T15,T20
1	0	Covered	T3,T4,T16

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T16

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T21
1	1	Covered	T19,T15,T20

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T4
1	Covered	T2,T3,T22

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T17,T6

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T7,T23

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T17,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T17

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T3,T4,T5

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T2,T3,T17
IdleSt->TimeoutSt	154	Covered	T3,T4,T5
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T4,T16,T24
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T25,T26,T24
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T4,T27,T28
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T4,T16,T26
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T3,T17,T4
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T4,T5,T18
TimeoutSt->Phase0St	167	Covered	T3,T4,T19

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T16,T24
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T26,T24
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T27,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T16,T26
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T17,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1195	0	0
CheckAccumTrig0_A	2147483647	2394	0	0
CheckAccumTrig1_A	2147483647	120	0	0
CheckClr_A	2147483647	1103	0	0
CheckEn_A	2147483647	1121512634	0	0
CheckPhase0_A	2147483647	2728	0	0
CheckPhase1_A	2147483647	2672	0	0
CheckPhase2_A	2147483647	2623	0	0
CheckPhase3_A	2147483647	2574	0	0
CheckTimeout0_A	2147483647	7707	0	0
CheckTimeoutSt1_A	2147483647	776059	0	0
CheckTimeoutSt2_A	2147483647	7312	0	0
CheckTimeoutStTrig_A	2147483647	266	0	0
ErrorStAllEscAsserted_A	2147483647	5710	0	0
ErrorStIsTerminal_A	2147483647	4750	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1195	0	0
T11	202840	278	0	0
T12	0	339	0	0
T13	0	295	0	0
T15	2213812	0	0	0
T16	1566536	0	0	0
T20	109932	0	0	0
T22	11948	0	0	0
T25	159320	0	0	0
T29	0	142	0	0
T30	0	141	0	0
T31	167336	0	0	0
T32	572640	0	0	0
T33	20988	0	0	0
T34	214244	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2394	0	0
T1	617411	0	0	0
T2	52694	1	0	0
T3	151857	3	0	0
T4	1070112	14	0	0
T5	1573972	4	0	0
T6	735196	2	0	0
T7	3517752	2	0	0
T8	44874	0	0	0
T9	104523	2	0	0
T14	719401	1	0	0
T15	0	5	0	0
T16	0	13	0	0
T17	36897	2	0	0
T18	38784	4	0	0
T19	109720	0	0	0
T22	0	1	0	0
T23	84176	1	0	0
T25	0	1	0	0
T31	0	4	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	120	0	0
T3	50619	1	0	0
T4	267528	2	0	0
T5	393493	0	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T16	391634	3	0	0
T17	12299	0	0	0
T18	9696	0	0	0
T19	27430	0	0	0
T23	42088	0	0	0
T24	0	5	0	0
T25	39830	0	0	0
T28	0	1	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0
T35	297455	0	0	0
T39	0	1	0	0
T40	108466	1	0	0
T41	0	3	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	4	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	124378	0	0	0
T56	28087	0	0	0
T57	28494	0	0	0
T58	99157	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1103	0	0
T3	50619	1	0	0
T4	1070112	15	0	0
T5	1573972	2	0	0
T6	735196	0	0	0
T7	3517752	1	0	0
T8	59832	0	0	0
T9	209046	0	0	0
T14	2158203	0	0	0
T15	0	3	0	0
T16	0	14	0	0
T17	24598	1	0	0
T18	38784	2	0	0
T19	109720	3	0	0
T23	168352	0	0	0
T24	0	8	0	0
T25	0	2	0	0
T28	0	4	0	0
T31	0	3	0	0
T32	0	1	0	0
T34	0	1	0	0
T41	0	6	0	0
T56	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1121512634	0	0
T1	2469644	1070855	0	0
T2	105388	79708	0	0
T3	202476	25671	0	0
T4	1070112	812921	0	0
T5	1573972	419716	0	0
T6	735196	394818	0	0
T7	3517752	1759862	0	0
T17	49196	36537	0	0
T18	38784	12677	0	0
T19	109720	56729	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2728	0	0
T1	617411	1	0	0
T2	52694	1	0	0
T3	202476	5	0	0
T4	1070112	17	0	0
T5	1573972	5	0	0
T6	735196	2	0	0
T7	3517752	5	0	0
T8	44874	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T15	0	14	0	0
T16	0	18	0	0
T17	49196	2	0	0
T18	38784	5	0	0
T19	109720	4	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	84176	1	0	0
T25	0	2	0	0
T31	0	4	0	0
T32	0	1	0	0
T35	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2672	0	0
T1	617411	1	0	0
T2	52694	1	0	0
T3	202476	5	0	0
T4	1070112	17	0	0
T5	1573972	5	0	0
T6	735196	2	0	0
T7	3517752	3	0	0
T8	44874	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T15	0	14	0	0
T16	0	18	0	0
T17	49196	2	0	0
T18	38784	5	0	0
T19	109720	4	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	84176	1	0	0
T25	0	2	0	0
T31	0	4	0	0
T32	0	1	0	0
T35	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2623	0	0
T1	617411	1	0	0
T2	52694	1	0	0
T3	202476	5	0	0
T4	1070112	16	0	0
T5	1573972	5	0	0
T6	735196	2	0	0
T7	3517752	3	0	0
T8	44874	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T15	0	14	0	0
T16	0	18	0	0
T17	49196	2	0	0
T18	38784	5	0	0
T19	109720	4	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	84176	1	0	0
T25	0	2	0	0
T31	0	4	0	0
T32	0	1	0	0
T35	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2574	0	0
T1	617411	1	0	0
T2	52694	1	0	0
T3	202476	5	0	0
T4	1070112	15	0	0
T5	1573972	5	0	0
T6	735196	2	0	0
T7	3517752	3	0	0
T8	44874	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T15	0	14	0	0
T16	0	18	0	0
T17	49196	2	0	0
T18	38784	5	0	0
T19	109720	4	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	84176	1	0	0
T25	0	2	0	0
T31	0	4	0	0
T32	0	1	0	0
T35	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7707	0	0
T3	50619	1	0	0
T4	535056	5	0	0
T5	1180479	1	0	0
T6	551397	0	0	0
T7	3517752	0	0	0
T8	59832	0	0	0
T9	313569	0	0	0
T11	101420	0	0	0
T14	2158203	0	0	0
T15	0	24	0	0
T16	0	10	0	0
T17	12299	0	0	0
T18	38784	2	0	0
T19	109720	5	0	0
T20	0	6	0	0
T22	2987	0	0	0
T23	168352	0	0	0
T24	0	1060	0	0
T27	0	2	0	0
T31	41834	0	0	0
T32	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T55	0	12	0	0
T59	0	3	0	0
T60	0	1	0	0
T62	0	367	0	0
T63	0	27	0	0
T64	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	776059	0	0
T3	50619	1	0	0
T4	535056	463	0	0
T5	1180479	86	0	0
T6	551397	0	0	0
T7	3517752	0	0	0
T8	59832	0	0	0
T9	313569	0	0	0
T11	101420	0	0	0
T14	2158203	0	0	0
T15	0	3263	0	0
T16	0	2365	0	0
T17	12299	0	0	0
T18	38784	69	0	0
T19	109720	600	0	0
T20	0	907	0	0
T22	2987	0	0	0
T23	168352	0	0	0
T24	0	84707	0	0
T27	0	113	0	0
T31	41834	0	0	0
T32	0	83	0	0
T39	0	41	0	0
T40	0	117	0	0
T55	0	2724	0	0
T59	0	532	0	0
T60	0	16	0	0
T62	0	17922	0	0
T63	0	5813	0	0
T64	0	566	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7312	0	0
T4	535056	3	0	0
T5	1180479	1	0	0
T6	551397	0	0	0
T7	3517752	0	0	0
T8	59832	0	0	0
T9	418092	0	0	0
T11	101420	0	0	0
T14	2877604	0	0	0
T15	0	18	0	0
T16	0	3	0	0
T18	38784	2	0	0
T19	109720	0	0	0
T20	0	5	0	0
T22	2987	0	0	0
T23	168352	0	0	0
T24	0	1048	0	0
T27	0	2	0	0
T28	0	2	0	0
T31	41834	0	0	0
T32	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	9	0	0
T43	0	6	0	0
T55	0	10	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	364	0	0
T63	0	22	0	0
T65	0	1	0	0
T66	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	266	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T11	50710	0	0	0
T14	719401	0	0	0
T15	1106906	3	0	0
T16	783268	3	0	0
T19	27430	4	0	0
T20	27483	1	0	0
T22	2987	0	0	0
T23	42088	0	0	0
T24	0	5	0	0
T25	79660	0	0	0
T31	41834	0	0	0
T32	286320	0	0	0
T33	10494	0	0	0
T34	107122	0	0	0
T35	594910	0	0	0
T41	0	3	0	0
T43	0	5	0	0
T45	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T55	248756	1	0	0
T56	56174	0	0	0
T57	28494	0	0	0
T58	99157	0	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5710	0	0
T11	202840	1420	0	0
T12	0	1417	0	0
T13	0	1453	0	0
T15	2213812	0	0	0
T16	1566536	0	0	0
T20	109932	0	0	0
T22	11948	0	0	0
T25	159320	0	0	0
T29	0	708	0	0
T30	0	712	0	0
T31	167336	0	0	0
T32	572640	0	0	0
T33	20988	0	0	0
T34	214244	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4750	0	0
T11	202840	1180	0	0
T12	0	1177	0	0
T13	0	1213	0	0
T15	2213812	0	0	0
T16	1566536	0	0	0
T20	109932	0	0	0
T22	11948	0	0	0
T25	159320	0	0	0
T29	0	588	0	0
T30	0	592	0	0
T31	167336	0	0	0
T32	572640	0	0	0
T33	20988	0	0	0
T34	214244	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2469644	2469312	0	0
T2	105388	105080	0	0
T3	202476	202128	0	0
T4	1070112	1070092	0	0
T5	1573972	1573944	0	0
T6	735196	735168	0	0
T7	3517752	3517516	0	0
T17	49196	48808	0	0
T18	38784	38444	0	0
T19	109720	109372	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T17
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T17

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T17

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T4,T5
1	0	1	Covered	T7,T22,T15
1	1	0	Covered	T4,T5,T19
1	1	1	Covered	T4,T18,T15

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T18,T15
0	1	Covered	T16,T24,T63
1	0	Covered	T16,T24,T39

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T18,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T24,T39

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T15
1	0	Not Covered
1	1	Covered	T16,T24,T63

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T5,T6
1	Covered	T2,T3,T22

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T5,T6,T18

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T17,T18,T16

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T23,T15,T16

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T6,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T18,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T17,T6,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T17
Phase1St	193	Covered	T2,T3,T17
Phase2St	210	Covered	T2,T3,T17
Phase3St	228	Covered	T2,T3,T17
TerminalSt	244	Covered	T2,T3,T17
TimeoutSt	154	Covered	T4,T18,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T2,T3,T17
IdleSt->TimeoutSt	154	Covered	T4,T18,T15
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T16,T51,T73
Phase0St->Phase1St	193	Covered	T2,T3,T17
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T25,T26,T45
Phase1St->Phase2St	210	Covered	T2,T3,T17
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T41,T43,T44
Phase2St->Phase3St	228	Covered	T2,T3,T17
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T16,T74,T75
Phase3St->TerminalSt	244	Covered	T2,T3,T17
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T17,T5,T18
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T4,T18,T15
TimeoutSt->Phase0St	167	Covered	T16,T24,T63

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T18,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T24,T63
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T18,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T18,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T16,T76,T77
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T26,T45
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T41,T43,T44
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T74,T75
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T5,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	693182191	305	0	0
CheckAccumTrig0_A	693182191	834	0	0
CheckAccumTrig1_A	693182191	50	0	0
CheckClr_A	693182191	424	0	0
CheckEn_A	692943015	279603260	0	0
CheckPhase0_A	693182191	941	0	0
CheckPhase1_A	693182191	924	0	0
CheckPhase2_A	693182191	905	0	0
CheckPhase3_A	693182191	881	0	0
CheckTimeout0_A	693182191	1714	0	0
CheckTimeoutSt1_A	693182191	171243	0	0
CheckTimeoutSt2_A	693182191	1585	0	0
CheckTimeoutStTrig_A	693182191	75	0	0
ErrorStAllEscAsserted_A	693182191	1394	0	0
ErrorStIsTerminal_A	693182191	1154	0	0
u_state_regs_A	693182191	693007367	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	305	0	0
T11	50710	72	0	0
T12	0	69	0	0
T13	0	94	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	0	0	0
T25	39830	0	0	0
T29	0	39	0	0
T30	0	31	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	834	0	0
T2	26347	1	0	0
T3	50619	1	0	0
T4	267528	0	0	0
T5	393493	1	0	0
T6	183799	1	0	0
T7	879438	1	0	0
T8	14958	0	0	0
T17	12299	2	0	0
T18	9696	2	0	0
T19	27430	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T31	0	4	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	50	0	0
T16	391634	3	0	0
T24	0	1	0	0
T25	39830	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0
T35	297455	0	0	0
T39	0	1	0	0
T42	0	3	0	0
T44	0	1	0	0
T45	0	4	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	124378	0	0	0
T56	28087	0	0	0
T57	28494	0	0	0
T58	99157	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	424	0	0
T4	267528	0	0	0
T5	393493	1	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T14	719401	0	0	0
T15	0	1	0	0
T16	0	7	0	0
T17	12299	1	0	0
T18	9696	1	0	0
T19	27430	0	0	0
T23	42088	0	0	0
T25	0	2	0	0
T31	0	3	0	0
T34	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692943015	279603260	0	0
T1	617411	1971	0	0
T2	26347	901	0	0
T3	50619	6171	0	0
T4	267528	266931	0	0
T5	393493	392799	0	0
T6	183799	2066	0	0
T7	879438	2032	0	0
T17	12299	2061	0	0
T18	9696	2780	0	0
T19	27430	20104	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	941	0	0
T2	26347	1	0	0
T3	50619	1	0	0
T4	267528	0	0	0
T5	393493	1	0	0
T6	183799	1	0	0
T7	879438	1	0	0
T8	14958	0	0	0
T17	12299	2	0	0
T18	9696	2	0	0
T19	27430	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T31	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	924	0	0
T2	26347	1	0	0
T3	50619	1	0	0
T4	267528	0	0	0
T5	393493	1	0	0
T6	183799	1	0	0
T7	879438	1	0	0
T8	14958	0	0	0
T17	12299	2	0	0
T18	9696	2	0	0
T19	27430	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T31	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	905	0	0
T2	26347	1	0	0
T3	50619	1	0	0
T4	267528	0	0	0
T5	393493	1	0	0
T6	183799	1	0	0
T7	879438	1	0	0
T8	14958	0	0	0
T17	12299	2	0	0
T18	9696	2	0	0
T19	27430	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T31	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	881	0	0
T2	26347	1	0	0
T3	50619	1	0	0
T4	267528	0	0	0
T5	393493	1	0	0
T6	183799	1	0	0
T7	879438	1	0	0
T8	14958	0	0	0
T17	12299	2	0	0
T18	9696	2	0	0
T19	27430	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T31	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1714	0	0
T4	267528	1	0	0
T5	393493	0	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T14	719401	0	0	0
T15	0	5	0	0
T16	0	5	0	0
T18	9696	1	0	0
T19	27430	0	0	0
T20	0	5	0	0
T23	42088	0	0	0
T24	0	557	0	0
T32	0	1	0	0
T39	0	2	0	0
T62	0	280	0	0
T63	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	171243	0	0
T4	267528	111	0	0
T5	393493	0	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T14	719401	0	0	0
T15	0	866	0	0
T16	0	1430	0	0
T18	9696	34	0	0
T19	27430	0	0	0
T20	0	743	0	0
T23	42088	0	0	0
T24	0	46408	0	0
T32	0	83	0	0
T39	0	41	0	0
T62	0	13629	0	0
T63	0	483	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1585	0	0
T4	267528	1	0	0
T5	393493	0	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T14	719401	0	0	0
T15	0	5	0	0
T18	9696	1	0	0
T19	27430	0	0	0
T20	0	5	0	0
T23	42088	0	0	0
T24	0	554	0	0
T32	0	1	0	0
T39	0	1	0	0
T62	0	280	0	0
T63	0	2	0	0
T65	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	75	0	0
T16	391634	2	0	0
T24	0	2	0	0
T25	39830	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0
T35	297455	0	0	0
T43	0	5	0	0
T45	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T55	124378	0	0	0
T56	28087	0	0	0
T57	28494	0	0	0
T58	99157	0	0	0
T63	0	1	0	0
T67	0	1	0	0
T69	0	1	0	0
T72	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1394	0	0
T11	50710	340	0	0
T12	0	316	0	0
T13	0	398	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	0	0	0
T25	39830	0	0	0
T29	0	168	0	0
T30	0	172	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1154	0	0
T11	50710	280	0	0
T12	0	256	0	0
T13	0	338	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	0	0	0
T25	39830	0	0	0
T29	0	138	0	0
T30	0	142	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	693007367	0	0
T1	617411	617328	0	0
T2	26347	26270	0	0
T3	50619	50532	0	0
T4	267528	267523	0	0
T5	393493	393486	0	0
T6	183799	183792	0	0
T7	879438	879379	0	0
T17	12299	12202	0	0
T18	9696	9611	0	0
T19	27430	27343	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T3,T19,T15
1	1	1	Covered	T3,T4,T15

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T15
0	1	Covered	T15,T20,T16
1	0	Covered	T3,T4,T24

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T24

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T15
1	0	Not Covered
1	1	Covered	T15,T20,T16

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T15,T20

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T9
1	Covered	T4,T5,T18

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T6,T9,T15

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T15,T16,T37

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T18,T20

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T18,T9

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T15,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T4,T5
Phase1St	193	Covered	T3,T4,T5
Phase2St	210	Covered	T3,T4,T5
Phase3St	228	Covered	T3,T4,T5
TerminalSt	244	Covered	T3,T4,T5
TimeoutSt	154	Covered	T3,T4,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T4,T5,T6
IdleSt->TimeoutSt	154	Covered	T3,T4,T15
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T4,T16,T24
Phase0St->Phase1St	193	Covered	T3,T4,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T24,T41,T42
Phase1St->Phase2St	210	Covered	T3,T4,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T4,T28,T73
Phase2St->Phase3St	228	Covered	T3,T4,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T4,T28,T70
Phase3St->TerminalSt	244	Covered	T3,T4,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T18,T15
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T4,T15,T16
TimeoutSt->Phase0St	167	Covered	T3,T4,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T15,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T16,T24
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T41,T42
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T28,T73
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T28,T70
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T18,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	693182191	291	0	0
CheckAccumTrig0_A	693182191	522	0	0
CheckAccumTrig1_A	693182191	29	0	0
CheckClr_A	693182191	220	0	0
CheckEn_A	692943015	267243911	0	0
CheckPhase0_A	693182191	581	0	0
CheckPhase1_A	693182191	567	0	0
CheckPhase2_A	693182191	561	0	0
CheckPhase3_A	693182191	553	0	0
CheckTimeout0_A	693182191	2687	0	0
CheckTimeoutSt1_A	693182191	282037	0	0
CheckTimeoutSt2_A	693182191	2604	0	0
CheckTimeoutStTrig_A	693182191	51	0	0
ErrorStAllEscAsserted_A	693182191	1461	0	0
ErrorStIsTerminal_A	693182191	1221	0	0
u_state_regs_A	693182191	693007367	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	291	0	0
T11	50710	70	0	0
T12	0	83	0	0
T13	0	63	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	0	0	0
T25	39830	0	0	0
T29	0	38	0	0
T30	0	37	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	522	0	0
T4	267528	14	0	0
T5	393493	1	0	0
T6	183799	1	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	1	0	0
T14	719401	0	0	0
T15	0	3	0	0
T16	0	12	0	0
T18	9696	2	0	0
T19	27430	0	0	0
T23	42088	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	29	0	0
T3	50619	1	0	0
T4	267528	2	0	0
T5	393493	0	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T17	12299	0	0	0
T18	9696	0	0	0
T19	27430	0	0	0
T23	42088	0	0	0
T24	0	4	0	0
T28	0	1	0	0
T41	0	2	0	0
T43	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	220	0	0
T4	267528	15	0	0
T5	393493	0	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T14	719401	0	0	0
T15	0	1	0	0
T16	0	7	0	0
T18	9696	1	0	0
T19	27430	0	0	0
T23	42088	0	0	0
T24	0	6	0	0
T28	0	4	0	0
T41	0	6	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692943015	267243911	0	0
T1	617411	481246	0	0
T2	26347	26269	0	0
T3	50619	7096	0	0
T4	267528	11940	0	0
T5	393493	3057	0	0
T6	183799	25168	0	0
T7	879438	877948	0	0
T17	12299	12201	0	0
T18	9696	586	0	0
T19	27430	27342	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	581	0	0
T3	50619	1	0	0
T4	267528	15	0	0
T5	393493	1	0	0
T6	183799	1	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	0	1	0	0
T15	0	4	0	0
T16	0	9	0	0
T17	12299	0	0	0
T18	9696	2	0	0
T19	27430	0	0	0
T20	0	1	0	0
T23	42088	0	0	0
T35	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	567	0	0
T3	50619	1	0	0
T4	267528	15	0	0
T5	393493	1	0	0
T6	183799	1	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	0	1	0	0
T15	0	4	0	0
T16	0	9	0	0
T17	12299	0	0	0
T18	9696	2	0	0
T19	27430	0	0	0
T20	0	1	0	0
T23	42088	0	0	0
T35	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	561	0	0
T3	50619	1	0	0
T4	267528	14	0	0
T5	393493	1	0	0
T6	183799	1	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	0	1	0	0
T15	0	4	0	0
T16	0	9	0	0
T17	12299	0	0	0
T18	9696	2	0	0
T19	27430	0	0	0
T20	0	1	0	0
T23	42088	0	0	0
T35	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	553	0	0
T3	50619	1	0	0
T4	267528	13	0	0
T5	393493	1	0	0
T6	183799	1	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	0	1	0	0
T15	0	4	0	0
T16	0	9	0	0
T17	12299	0	0	0
T18	9696	2	0	0
T19	27430	0	0	0
T20	0	1	0	0
T23	42088	0	0	0
T35	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	2687	0	0
T3	50619	1	0	0
T4	267528	4	0	0
T5	393493	0	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T15	0	2	0	0
T16	0	4	0	0
T17	12299	0	0	0
T18	9696	0	0	0
T19	27430	0	0	0
T20	0	1	0	0
T23	42088	0	0	0
T24	0	498	0	0
T55	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	0	19	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	282037	0	0
T3	50619	1	0	0
T4	267528	352	0	0
T5	393493	0	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T15	0	61	0	0
T16	0	931	0	0
T17	12299	0	0	0
T18	9696	0	0	0
T19	27430	0	0	0
T20	0	164	0	0
T23	42088	0	0	0
T24	0	37603	0	0
T55	0	13	0	0
T59	0	11	0	0
T62	0	91	0	0
T63	0	4205	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	2604	0	0
T4	267528	2	0	0
T5	393493	0	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T14	719401	0	0	0
T15	0	1	0	0
T16	0	3	0	0
T18	9696	0	0	0
T19	27430	0	0	0
T23	42088	0	0	0
T24	0	493	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	18	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	51	0	0
T15	553453	1	0	0
T16	391634	1	0	0
T20	27483	1	0	0
T24	0	1	0	0
T25	39830	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0
T35	297455	0	0	0
T41	0	3	0	0
T55	124378	1	0	0
T56	28087	0	0	0
T63	0	1	0	0
T68	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1461	0	0
T11	50710	373	0	0
T12	0	346	0	0
T13	0	365	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	0	0	0
T25	39830	0	0	0
T29	0	185	0	0
T30	0	192	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1221	0	0
T11	50710	313	0	0
T12	0	286	0	0
T13	0	305	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	0	0	0
T25	39830	0	0	0
T29	0	155	0	0
T30	0	162	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	693007367	0	0
T1	617411	617328	0	0
T2	26347	26270	0	0
T3	50619	50532	0	0
T4	267528	267523	0	0
T5	393493	393486	0	0
T6	183799	183792	0	0
T7	879438	879379	0	0
T17	12299	12202	0	0
T18	9696	9611	0	0
T19	27430	27343	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T18
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T18

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T7

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T5,T18
1	0	1	Covered	T1,T7,T14
1	1	0	Covered	T4,T18,T15
1	1	1	Covered	T18,T19,T15

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T15
0	1	Covered	T19,T15,T62
1	0	Covered	T40,T41,T50

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T18,T19,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T40,T41,T50

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T15
1	0	Not Covered
1	1	Covered	T19,T15,T62

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T19
1	Covered	T16,T25,T32

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T19,T7
1	Covered	T5,T14,T15

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T19,T7
1	Covered	T3,T9,T15

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T14
1	Covered	T19,T7,T15

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T14,T9

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T5,T19
Phase1St	193	Covered	T3,T5,T19
Phase2St	210	Covered	T3,T5,T19
Phase3St	228	Covered	T3,T5,T19
TerminalSt	244	Covered	T3,T5,T19
TimeoutSt	154	Covered	T18,T19,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T3,T5,T7
IdleSt->TimeoutSt	154	Covered	T18,T19,T15
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T78,T79,T80
Phase0St->Phase1St	193	Covered	T3,T5,T19
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T27,T42,T45
Phase1St->Phase2St	210	Covered	T3,T5,T19
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T27,T41,T81
Phase2St->Phase3St	228	Covered	T3,T5,T19
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T26,T27,T82
Phase3St->TerminalSt	244	Covered	T3,T5,T19
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T3,T5,T19
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T18,T15,T55
TimeoutSt->Phase0St	167	Covered	T19,T15,T62

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T15,T62
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T18,T15,T55
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T78,T79
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T5,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T5,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T42,T45
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T5,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T5,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T41,T81
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T5,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T5,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T27,T82
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T5,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T5,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T5,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T5,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	693182191	304	0	0
CheckAccumTrig0_A	693182191	511	0	0
CheckAccumTrig1_A	693182191	17	0	0
CheckClr_A	693182191	232	0	0
CheckEn_A	692943015	298348003	0	0
CheckPhase0_A	693182191	595	0	0
CheckPhase1_A	693182191	583	0	0
CheckPhase2_A	693182191	570	0	0
CheckPhase3_A	693182191	560	0	0
CheckTimeout0_A	693182191	1394	0	0
CheckTimeoutSt1_A	693182191	136428	0	0
CheckTimeoutSt2_A	693182191	1305	0	0
CheckTimeoutStTrig_A	693182191	72	0	0
ErrorStAllEscAsserted_A	693182191	1409	0	0
ErrorStIsTerminal_A	693182191	1169	0	0
u_state_regs_A	693182191	693007367	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	304	0	0
T11	50710	71	0	0
T12	0	96	0	0
T13	0	58	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	0	0	0
T25	39830	0	0	0
T29	0	42	0	0
T30	0	37	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	511	0	0
T3	50619	2	0	0
T4	267528	0	0	0
T5	393493	2	0	0
T6	183799	0	0	0
T7	879438	1	0	0
T8	14958	0	0	0
T9	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	12299	0	0	0
T18	9696	0	0	0
T19	27430	0	0	0
T23	42088	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T36	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	17	0	0
T27	165718	0	0	0
T28	117392	0	0	0
T40	108466	1	0	0
T41	0	1	0	0
T50	0	2	0	0
T52	0	1	0	0
T61	19317	0	0	0
T64	69119	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	119788	0	0	0
T90	444983	0	0	0
T91	85290	0	0	0
T92	234911	0	0	0
T93	333241	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	232	0	0
T3	50619	1	0	0
T4	267528	0	0	0
T5	393493	1	0	0
T6	183799	0	0	0
T7	879438	1	0	0
T8	14958	0	0	0
T15	0	1	0	0
T17	12299	0	0	0
T18	9696	0	0	0
T19	27430	3	0	0
T23	42088	0	0	0
T24	0	2	0	0
T26	0	2	0	0
T32	0	1	0	0
T89	0	1	0	0
T94	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692943015	298348003	0	0
T1	617411	585622	0	0
T2	26347	26269	0	0
T3	50619	6196	0	0
T4	267528	267523	0	0
T5	393493	9933	0	0
T6	183799	183792	0	0
T7	879438	877948	0	0
T17	12299	10074	0	0
T18	9696	5390	0	0
T19	27430	2332	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	595	0	0
T3	50619	2	0	0
T4	267528	0	0	0
T5	393493	2	0	0
T6	183799	0	0	0
T7	879438	1	0	0
T8	14958	0	0	0
T9	0	1	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	12299	0	0	0
T18	9696	0	0	0
T19	27430	4	0	0
T23	42088	0	0	0
T25	0	1	0	0
T32	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	583	0	0
T3	50619	2	0	0
T4	267528	0	0	0
T5	393493	2	0	0
T6	183799	0	0	0
T7	879438	1	0	0
T8	14958	0	0	0
T9	0	1	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	12299	0	0	0
T18	9696	0	0	0
T19	27430	4	0	0
T23	42088	0	0	0
T25	0	1	0	0
T32	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	570	0	0
T3	50619	2	0	0
T4	267528	0	0	0
T5	393493	2	0	0
T6	183799	0	0	0
T7	879438	1	0	0
T8	14958	0	0	0
T9	0	1	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	12299	0	0	0
T18	9696	0	0	0
T19	27430	4	0	0
T23	42088	0	0	0
T25	0	1	0	0
T32	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	560	0	0
T3	50619	2	0	0
T4	267528	0	0	0
T5	393493	2	0	0
T6	183799	0	0	0
T7	879438	1	0	0
T8	14958	0	0	0
T9	0	1	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	12299	0	0	0
T18	9696	0	0	0
T19	27430	4	0	0
T23	42088	0	0	0
T25	0	1	0	0
T32	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1394	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T11	50710	0	0	0
T14	719401	0	0	0
T15	0	4	0	0
T18	9696	1	0	0
T19	27430	4	0	0
T22	2987	0	0	0
T23	42088	0	0	0
T24	0	2	0	0
T27	0	2	0	0
T31	41834	0	0	0
T40	0	2	0	0
T55	0	10	0	0
T59	0	1	0	0
T62	0	79	0	0
T64	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	136428	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T11	50710	0	0	0
T14	719401	0	0	0
T15	0	388	0	0
T18	9696	35	0	0
T19	27430	476	0	0
T22	2987	0	0	0
T23	42088	0	0	0
T24	0	553	0	0
T27	0	113	0	0
T31	41834	0	0	0
T40	0	117	0	0
T55	0	2436	0	0
T59	0	209	0	0
T62	0	3698	0	0
T64	0	566	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1305	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T11	50710	0	0	0
T14	719401	0	0	0
T15	0	2	0	0
T18	9696	1	0	0
T19	27430	0	0	0
T22	2987	0	0	0
T23	42088	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T31	41834	0	0	0
T40	0	1	0	0
T41	0	6	0	0
T43	0	3	0	0
T55	0	10	0	0
T62	0	78	0	0
T66	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	72	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T11	50710	0	0	0
T14	719401	0	0	0
T15	553453	2	0	0
T19	27430	4	0	0
T22	2987	0	0	0
T23	42088	0	0	0
T24	0	2	0	0
T31	41834	0	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T82	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1409	0	0
T11	50710	377	0	0
T12	0	374	0	0
T13	0	320	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	0	0	0
T25	39830	0	0	0
T29	0	172	0	0
T30	0	166	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1169	0	0
T11	50710	317	0	0
T12	0	314	0	0
T13	0	260	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	0	0	0
T25	39830	0	0	0
T29	0	142	0	0
T30	0	136	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	693007367	0	0
T1	617411	617328	0	0
T2	26347	26270	0	0
T3	50619	50532	0	0
T4	267528	267523	0	0
T5	393493	393486	0	0
T6	183799	183792	0	0
T7	879438	879379	0	0
T17	12299	12202	0	0
T18	9696	9611	0	0
T19	27430	27343	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T18
1	0	1	Covered	T3,T14,T9
1	1	0	Covered	T4,T18,T19
1	1	1	Covered	T5,T19,T15

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T19,T15
0	1	Covered	T15,T55,T62
1	0	Covered	T15,T16,T24

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T19,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T24

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T15
1	0	Covered	T21
1	1	Covered	T15,T55,T62

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T15,T16

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T5,T7,T15

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T14,T15

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T4,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T4
Phase1St	193	Covered	T1,T3,T4
Phase2St	210	Covered	T1,T3,T4
Phase3St	228	Covered	T1,T3,T4
TerminalSt	244	Covered	T1,T3,T4
TimeoutSt	154	Covered	T5,T19,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T1,T3,T4
IdleSt->TimeoutSt	154	Covered	T5,T19,T15
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T48,T97,T98
Phase0St->Phase1St	193	Covered	T1,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T7,T24,T99
Phase1St->Phase2St	210	Covered	T1,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T100,T75,T83
Phase2St->Phase3St	228	Covered	T1,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T42,T101,T102
Phase3St->TerminalSt	244	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T15,T16
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T5,T19,T15
TimeoutSt->Phase0St	167	Covered	T15,T16,T55

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T19,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T55
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T19,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T19,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T48,T103,T104
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T24,T99
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T100,T75,T83
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T42,T101,T102
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T15,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	693182191	295	0	0
CheckAccumTrig0_A	693182191	527	0	0
CheckAccumTrig1_A	693182191	24	0	0
CheckClr_A	693182191	227	0	0
CheckEn_A	692943015	276317460	0	0
CheckPhase0_A	693182191	611	0	0
CheckPhase1_A	693182191	598	0	0
CheckPhase2_A	693182191	587	0	0
CheckPhase3_A	693182191	580	0	0
CheckTimeout0_A	693182191	1912	0	0
CheckTimeoutSt1_A	693182191	186351	0	0
CheckTimeoutSt2_A	693182191	1818	0	0
CheckTimeoutStTrig_A	693182191	68	0	0
ErrorStAllEscAsserted_A	693182191	1446	0	0
ErrorStIsTerminal_A	693182191	1206	0	0
u_state_regs_A	693182191	693007367	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	295	0	0
T11	50710	65	0	0
T12	0	91	0	0
T13	0	80	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	0	0	0
T25	39830	0	0	0
T29	0	23	0	0
T30	0	36	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	527	0	0
T1	617411	1	0	0
T2	26347	0	0	0
T3	50619	1	0	0
T4	267528	2	0	0
T5	393493	1	0	0
T6	183799	0	0	0
T7	879438	3	0	0
T14	0	1	0	0
T15	0	3	0	0
T16	0	7	0	0
T17	12299	0	0	0
T18	9696	1	0	0
T19	27430	0	0	0
T25	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	24	0	0
T15	553453	1	0	0
T16	391634	1	0	0
T20	27483	0	0	0
T24	0	1	0	0
T25	39830	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0
T35	297455	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	0	1	0	0
T55	124378	0	0	0
T56	28087	0	0	0
T60	0	1	0	0
T75	0	3	0	0
T105	0	1	0	0
T106	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	227	0	0
T4	267528	2	0	0
T5	393493	0	0	0
T6	183799	0	0	0
T7	879438	2	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T14	719401	0	0	0
T15	0	3	0	0
T16	0	4	0	0
T18	9696	0	0	0
T19	27430	0	0	0
T23	42088	0	0	0
T24	0	4	0	0
T26	0	1	0	0
T32	0	1	0	0
T59	0	1	0	0
T63	0	1	0	0
T107	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692943015	276317460	0	0
T1	617411	2016	0	0
T2	26347	26269	0	0
T3	50619	6208	0	0
T4	267528	266527	0	0
T5	393493	13927	0	0
T6	183799	183792	0	0
T7	879438	1934	0	0
T17	12299	12201	0	0
T18	9696	3921	0	0
T19	27430	6951	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	611	0	0
T1	617411	1	0	0
T2	26347	0	0	0
T3	50619	1	0	0
T4	267528	2	0	0
T5	393493	1	0	0
T6	183799	0	0	0
T7	879438	3	0	0
T14	0	1	0	0
T15	0	6	0	0
T16	0	8	0	0
T17	12299	0	0	0
T18	9696	1	0	0
T19	27430	0	0	0
T25	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	598	0	0
T1	617411	1	0	0
T2	26347	0	0	0
T3	50619	1	0	0
T4	267528	2	0	0
T5	393493	1	0	0
T6	183799	0	0	0
T7	879438	1	0	0
T14	0	1	0	0
T15	0	6	0	0
T16	0	8	0	0
T17	12299	0	0	0
T18	9696	1	0	0
T19	27430	0	0	0
T25	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	587	0	0
T1	617411	1	0	0
T2	26347	0	0	0
T3	50619	1	0	0
T4	267528	2	0	0
T5	393493	1	0	0
T6	183799	0	0	0
T7	879438	1	0	0
T14	0	1	0	0
T15	0	6	0	0
T16	0	8	0	0
T17	12299	0	0	0
T18	9696	1	0	0
T19	27430	0	0	0
T25	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	580	0	0
T1	617411	1	0	0
T2	26347	0	0	0
T3	50619	1	0	0
T4	267528	2	0	0
T5	393493	1	0	0
T6	183799	0	0	0
T7	879438	1	0	0
T14	0	1	0	0
T15	0	6	0	0
T16	0	8	0	0
T17	12299	0	0	0
T18	9696	1	0	0
T19	27430	0	0	0
T25	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1912	0	0
T5	393493	1	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T11	50710	0	0	0
T14	719401	0	0	0
T15	0	13	0	0
T16	0	1	0	0
T18	9696	0	0	0
T19	27430	1	0	0
T23	42088	0	0	0
T24	0	3	0	0
T55	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	7	0	0
T63	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	186351	0	0
T5	393493	86	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T11	50710	0	0	0
T14	719401	0	0	0
T15	0	1948	0	0
T16	0	4	0	0
T18	9696	0	0	0
T19	27430	124	0	0
T23	42088	0	0	0
T24	0	143	0	0
T55	0	275	0	0
T59	0	312	0	0
T60	0	16	0	0
T62	0	504	0	0
T63	0	1125	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1818	0	0
T5	393493	1	0	0
T6	183799	0	0	0
T7	879438	0	0	0
T8	14958	0	0	0
T9	104523	0	0	0
T11	50710	0	0	0
T14	719401	0	0	0
T15	0	10	0	0
T18	9696	0	0	0
T19	27430	1	0	0
T23	42088	0	0	0
T24	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T62	0	5	0	0
T63	0	2	0	0
T66	0	1	0	0
T95	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	68	0	0
T15	553453	2	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T24	0	1	0	0
T25	39830	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0
T35	297455	0	0	0
T42	0	1	0	0
T55	124378	1	0	0
T56	28087	0	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	0	3	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1446	0	0
T11	50710	330	0	0
T12	0	381	0	0
T13	0	370	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	0	0	0
T25	39830	0	0	0
T29	0	183	0	0
T30	0	182	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	1206	0	0
T11	50710	270	0	0
T12	0	321	0	0
T13	0	310	0	0
T15	553453	0	0	0
T16	391634	0	0	0
T20	27483	0	0	0
T22	2987	0	0	0
T25	39830	0	0	0
T29	0	153	0	0
T30	0	152	0	0
T31	41834	0	0	0
T32	143160	0	0	0
T33	5247	0	0	0
T34	53561	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693182191	693007367	0	0
T1	617411	617328	0	0
T2	26347	26270	0	0
T3	50619	50532	0	0
T4	267528	267523	0	0
T5	393493	393486	0	0
T6	183799	183792	0	0
T7	879438	879379	0	0
T17	12299	12202	0	0
T18	9696	9611	0	0
T19	27430	27343	0	0