Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	71413	1			T1	584		T2	4200		T4	1
class_i[0x1]	56287	1			T4	5		T5	2		T7	9
class_i[0x2]	57151	1			T4	13		T7	15		T11	16
class_i[0x3]	62711	1			T2	78		T7	7		T11	19

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	62533	1			T1	546		T2	1074		T4	7
alert[0x1]	64681	1			T1	13		T2	1114		T4	2
alert[0x2]	61033	1			T1	11		T2	1119		T4	7
alert[0x3]	59315	1			T1	14		T2	971		T4	3

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

247305

1

T1

584

T2

4278

T4

13

esc_ping_fail

257

1

T4

6

T12

10

T14

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	62455	1			T1	546		T2	1074		T4	5
esc_integrity_fail	alert[0x1]	64615	1			T1	13		T2	1114		T4	1
esc_integrity_fail	alert[0x2]	60979	1			T1	11		T2	1119		T4	5
esc_integrity_fail	alert[0x3]	59256	1			T1	14		T2	971		T4	2
esc_ping_fail	alert[0x0]	78	1			T4	2		T12	4		T14	2
esc_ping_fail	alert[0x1]	66	1			T4	1		T12	2		T14	2
esc_ping_fail	alert[0x2]	54	1			T4	2		T12	1		T14	1
esc_ping_fail	alert[0x3]	59	1			T4	1		T12	3		T14	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	71377	1			T1	584		T2	4200		T5	4
esc_integrity_fail	class_i[0x1]	56186	1			T5	2		T7	9		T11	20
esc_integrity_fail	class_i[0x2]	57098	1			T4	13		T7	15		T11	16
esc_integrity_fail	class_i[0x3]	62644	1			T2	78		T7	7		T11	19
esc_ping_fail	class_i[0x0]	36	1			T4	1		T12	9		T42	1
esc_ping_fail	class_i[0x1]	101	1			T4	5		T12	1		T14	6
esc_ping_fail	class_i[0x2]	53	1			T326	1		T42	2		T92	1
esc_ping_fail	class_i[0x3]	67	1			T326	1		T42	2		T225	7