Assertions
dashboard | hierarchy | modlist | groups | tests | asserts

Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A 0069885711600624
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A 00698857116000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AckPKnownO_A 0069885711669870195700
tb.dut.CheckAccuCntDw 0062462400
tb.dut.CheckEscCntDw 0062462400
tb.dut.CheckNAlerts 0062462400
tb.dut.CheckNClasses 0062462400
tb.dut.CheckNEscSev 0062462400
tb.dut.CrashdumpKnownO_A 0069885711669870195700
tb.dut.EdnKnownO_A 0069885711669870195700
tb.dut.EscPKnownO_A 0069885711669870195700
tb.dut.FpvSecCmPingTimerCnterCheck_A 006988571167000
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A 006988571167000
tb.dut.FpvSecCmPingTimerEscCnterCheck_A 006988571167000
tb.dut.FpvSecCmPingTimerFsmCheck_A 006988571167000
tb.dut.FpvSecCmRegWeOnehotCheck_A 006988571167000
tb.dut.IrqAKnownO_A 0069885711669870195700
tb.dut.IrqBKnownO_A 0069885711669870195700
tb.dut.IrqCKnownO_A 0069885711669870195700
tb.dut.IrqDKnownO_A 0069885711669870195700
tb.dut.TlAReadyKnownO_A 0069885711669870195700
tb.dut.TlDValidKnownO_A 0069885711669870195700
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A 00725602874270914900
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A 007256028741724200
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A 007256028741818700
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A 007256028741618800
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A 007256028741729000
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A 007256028741611100
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A 007256028741613800
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A 007256028741611100
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A 007256028741603900
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A 007256028741594300
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A 007256028741731600
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A 007256028741715100
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A 007256028741612700
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A 007256028741602500
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A 007256028741712800
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A 007256028741843400
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A 007256028741629500
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A 007256028741737000
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A 007256028741844100
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A 007256028741587900
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A 007256028741736900
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A 007256028741817200
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A 007256028741572300
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A 007256028741728200
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A 007256028741603600
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A 007256028741794400
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A 007256028741659000
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A 007256028741830100
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A 007256028741745200
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A 007256028741702200
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A 007256028741617800
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A 007256028741715400
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A 007256028741632400
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A 007256028741708000
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A 007256028741597300
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A 007256028741611200
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A 007256028741718300
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A 007256028741620700
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A 007256028741846000
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A 007256028741593800
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A 007256028741699300
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A 007256028741599700
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A 007256028741629800
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A 007256028741618500
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A 007256028741610200
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A 007256028741604900
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A 007256028741879300
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A 007256028741718500
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A 007256028741691000
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A 007256028741583600
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A 007256028741717500
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A 007256028741594400
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A 007256028741735500
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A 007256028741579600
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A 007256028741631000
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A 007256028741590500
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A 007256028741586400
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A 007256028741594900
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A 007256028741576200
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A 007256028741862000
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A 007256028741852000
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A 007256028741737600
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A 007256028741607200
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A 007256028741730200
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A 007256028741606100
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A 007256028741718800
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A 007256028741579000
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A 007256028741752800
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A 007256028741584600
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A 007256028741590900
tb.dut.alert_handler_csr_assert.intr_enable_rd_A 007256028743117400
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A 007256028741597700
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A 007256028741635800
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A 007256028741647100
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A 007256028741587600
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A 007256028741630800
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A 007256028741859400
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A 007256028741726900
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A 007256028741595900
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A 006988571167000
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A 006988571167000
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A 006988571167000
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A 00698857116335500
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A 0069885711624426200
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A 0069885711630874895100
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A 0069885711629600
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A 0069885711682400
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A 006988571163800
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A 0069885711642100
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A 0069871448823627823000
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A 0069885711692700
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A 0069885711691500
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A 0069885711689700
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A 0069885711687500
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A 00698857116107200
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A 0069885711612027000
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A 0069885711695200
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A 006988571168100
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A 00698857116128000
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A 00698857116107000
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A 0062462400
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A 0069885711669870195700
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A 006988571167000
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A 006988571167000
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A 006988571167000
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A 00698857116310800
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A 0069885711618579500
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A 0069885711638818244500
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A 0069885711626000
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A 0069885711647400
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A 006988571162600
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A 0069885711623100
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A 0069871448829591249300
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A 0069885711655700
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A 0069885711654000
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A 0069885711653100
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A 0069885711651900
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A 0069885711692300
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A 0069885711610372800
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A 0069885711683000
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A 006988571166300
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A 00698857116134700
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A 00698857116113700
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A 0062462400
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A 0069885711669870195700
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A 006988571167000
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A 006988571167000
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A 006988571167000
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A 00698857116548000
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A 0069885711620367500
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A 0069885711634638098000
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A 0069885711619200
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A 0069885711653700
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A 006988571162600
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A 0069885711626000
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A 0069871448828126934100
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A 0069885711661600
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A 0069885711660300
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A 0069885711659200
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A 0069885711657900
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A 00698857116100200
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A 0069885711610426500
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A 0069885711691500
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A 006988571166100
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A 00698857116127600
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A 00698857116106600
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A 0062462400
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A 0069885711669870195700
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A 006988571167000
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A 006988571167000
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A 006988571167000
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A 00698857116262400
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A 0069885711621059000
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A 0069885711638114204900
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A 0069885711625500
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A 0069885711650900
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A 006988571162000
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A 0069885711624700
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A 0069871448830208669200
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A 0069885711658100
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A 0069885711657000
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A 0069885711655500
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A 0069885711654900
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A 00698857116104400
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A 006988571169851100
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A 0069885711695500
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A 006988571166800
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A 00698857116121800
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A 00698857116100800
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A 0062462400
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A 0069885711669870195700
tb.dut.tlul_assert_device.aKnown_A 0072560287412487002200
tb.dut.tlul_assert_device.aKnown_AKnownEnable 0072560287472492883800
tb.dut.tlul_assert_device.aReadyKnown_A 0072560287472492883800
tb.dut.tlul_assert_device.dKnown_A 0072560287420443846600
tb.dut.tlul_assert_device.dKnown_AKnownEnable 0072560287472492883800
tb.dut.tlul_assert_device.dReadyKnown_A 0072560287472492883800
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A 0082982900
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A 0082982900
Go next page
Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1275010
Category 01275010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1275010
Severity 01275010


Summary for Assertions
NUMBERPERCENT
Total Number1275100.00
Uncovered20.16
Success127399.84
Failure00.00
Incomplete493.84
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered660.00
All Matches440.00
First Matches440.00
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%