Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	185	1			T2	1		T5	1		T7	2
index[0x1]	189	1			T5	2		T21	1		T11	1
index[0x2]	170	1			T23	1		T18	3		T31	7
index[0x3]	165	1			T6	1		T7	1		T18	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	217	1			T2	1		T23	1		T11	1
lens_less_than_1000[1]	135	1			T5	2		T6	1		T21	1
lens_less_than_1000[2]	111	1			T5	1		T11	1		T8	1
lens_less_than_1000[3]	85	1			T28	1		T45	1		T46	1
lens_less_than_1000[4]	46	1			T31	1		T75	1		T46	1
lens_less_than_1000[5]	43	1			T7	3		T61	1		T233	1
lens_less_than_1000[6]	24	1			T18	3		T45	1		T49	1
lens_less_than_1000[7]	18	1			T47	1		T280	1		T113	1
lens_less_than_1000[8]	11	1			T45	1		T76	1		T49	1
lens_less_than_1000[9]	8	1			T68	1		T47	1		T236	1
len_2	11	1			T65	1		T259	2		T281	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	48	1			T2	1		T11	1		T26	1
index[0x0]	lens_less_than_1000[1]	42	1			T11	7		T47	2		T81	1
index[0x0]	lens_less_than_1000[2]	39	1			T5	1		T28	1		T45	1
index[0x0]	lens_less_than_1000[3]	19	1			T59	1		T282	1		T108	1
index[0x0]	lens_less_than_1000[4]	8	1			T85	1		T283	1		T284	1
index[0x0]	lens_less_than_1000[5]	14	1			T7	2		T45	2		T83	1
index[0x0]	lens_less_than_1000[6]	5	1			T49	1		T88	1		T83	1
index[0x0]	lens_less_than_1000[7]	5	1			T285	1		T271	1		T236	2
index[0x0]	lens_less_than_1000[8]	2	1			T91	1		T269	1		-	-
index[0x0]	len_2	3	1			T259	2		T281	1		-	-
index[0x1]	lens_less_than_1000[0]	63	1			T18	1		T28	1		T66	2
index[0x1]	lens_less_than_1000[1]	35	1			T5	2		T21	1		T61	2
index[0x1]	lens_less_than_1000[2]	28	1			T11	1		T8	1		T286	1
index[0x1]	lens_less_than_1000[3]	26	1			T46	1		T47	1		T39	1
index[0x1]	lens_less_than_1000[4]	11	1			T46	1		T287	1		T288	3
index[0x1]	lens_less_than_1000[5]	11	1			T46	1		T89	1		T113	1
index[0x1]	lens_less_than_1000[6]	3	1			T45	1		T53	1		T273	1
index[0x1]	lens_less_than_1000[7]	6	1			T280	1		T113	1		T289	1
index[0x1]	lens_less_than_1000[8]	3	1			T76	1		T290	1		T279	1
index[0x1]	lens_less_than_1000[9]	2	1			T236	1		T255	1		-	-
index[0x1]	len_2	1	1			T291	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	48	1			T23	1		T10	1		T66	4
index[0x2]	lens_less_than_1000[1]	33	1			T31	6		T10	4		T45	1
index[0x2]	lens_less_than_1000[2]	24	1			T19	1		T64	1		T101	4
index[0x2]	lens_less_than_1000[3]	20	1			T292	1		T293	1		T294	1
index[0x2]	lens_less_than_1000[4]	10	1			T31	1		T47	1		T88	1
index[0x2]	lens_less_than_1000[5]	10	1			T61	1		T233	1		T45	1
index[0x2]	lens_less_than_1000[6]	13	1			T18	3		T58	1		T272	1
index[0x2]	lens_less_than_1000[7]	6	1			T47	1		T278	1		T235	1
index[0x2]	lens_less_than_1000[8]	2	1			T49	1		T268	1		-	-
index[0x2]	lens_less_than_1000[9]	2	1			T250	1		T253	1		-	-
index[0x2]	len_2	2	1			T65	1		T252	1		-	-
index[0x3]	lens_less_than_1000[0]	58	1			T18	1		T29	1		T86	1
index[0x3]	lens_less_than_1000[1]	25	1			T6	1		T295	1		T296	2
index[0x3]	lens_less_than_1000[2]	20	1			T9	1		T28	1		T71	1
index[0x3]	lens_less_than_1000[3]	20	1			T28	1		T45	1		T297	1
index[0x3]	lens_less_than_1000[4]	17	1			T75	1		T96	1		T298	1
index[0x3]	lens_less_than_1000[5]	8	1			T7	1		T76	1		T97	1
index[0x3]	lens_less_than_1000[6]	3	1			T299	1		T266	2		-	-
index[0x3]	lens_less_than_1000[7]	1	1			T282	1		-	-		-	-
index[0x3]	lens_less_than_1000[8]	4	1			T45	1		T52	1		T300	1
index[0x3]	lens_less_than_1000[9]	4	1			T68	1		T47	1		T301	2
index[0x3]	len_2	5	1			T92	4		T253	1		-	-