Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	81	1			T18	4		T71	2		T74	1
class_index[0x1]	63	1			T71	1		T45	3		T73	1
class_index[0x2]	61	1			T1	1		T11	2		T18	3
class_index[0x3]	68	1			T1	1		T18	1		T73	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	92	1			T1	1		T11	1		T71	3
intr_timeout_cnt[1]	59	1			T11	1		T18	1		T45	2
intr_timeout_cnt[2]	35	1			T18	4		T46	2		T41	2
intr_timeout_cnt[3]	20	1			T45	1		T83	1		T84	2
intr_timeout_cnt[4]	19	1			T73	1		T46	1		T256	1
intr_timeout_cnt[5]	16	1			T1	1		T18	1		T44	1
intr_timeout_cnt[6]	6	1			T18	2		T257	1		T108	1
intr_timeout_cnt[7]	9	1			T108	1		T258	1		T235	1
intr_timeout_cnt[8]	8	1			T259	1		T84	2		T85	1
intr_timeout_cnt[9]	9	1			T83	1		T260	1		T114	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	29	1			T71	2		T74	1		T46	1
class_index[0x0]	intr_timeout_cnt[1]	24	1			T73	1		T77	2		T81	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T18	4		T261	1		T262	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T263	1		T264	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	6	1			T256	1		T106	1		T265	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T256	1		T266	1		T238	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T108	1		T267	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T108	1		T235	1		T268	1
class_index[0x0]	intr_timeout_cnt[8]	3	1			T259	1		T84	2		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T114	1		T253	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	9	1			T71	1		T85	1		T269	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T45	2		T77	2		T270	2
class_index[0x1]	intr_timeout_cnt[2]	14	1			T41	1		T82	1		T52	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T45	1		T83	1		T260	3
class_index[0x1]	intr_timeout_cnt[4]	7	1			T73	1		T84	3		T271	1
class_index[0x1]	intr_timeout_cnt[5]	7	1			T55	2		T114	3		T250	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T257	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	3	1			T258	1		T268	1		T181	1
class_index[0x1]	intr_timeout_cnt[8]	2	1			T272	1		T250	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T83	1		T260	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	23	1			T11	1		T37	1		T38	1
class_index[0x2]	intr_timeout_cnt[1]	10	1			T11	1		T79	1		T99	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T46	1		T83	1		T256	1
class_index[0x2]	intr_timeout_cnt[3]	7	1			T84	2		T257	1		T224	1
class_index[0x2]	intr_timeout_cnt[4]	4	1			T46	1		T266	1		T238	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T1	1		T18	1		T44	1
class_index[0x2]	intr_timeout_cnt[6]	2	1			T18	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T273	1		T274	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	3	1			T264	1		T181	2		-	-
class_index[0x3]	intr_timeout_cnt[0]	31	1			T1	1		T38	3		T84	5
class_index[0x3]	intr_timeout_cnt[1]	12	1			T18	1		T52	1		T275	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T46	1		T41	1		T276	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T257	1		T224	1		T277	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T273	1		T265	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	3	1			T73	2		T82	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T278	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	3	1			T250	1		T267	1		T279	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T85	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T98	1		T238	1		-	-