Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	336559	1			T1	8		T2	1795		T3	201
all_values[1]	336559	1			T1	8		T2	1795		T3	201
all_values[2]	336559	1			T1	8		T2	1795		T3	201
all_values[3]	336559	1			T1	8		T2	1795		T3	201

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

670304

1

T1

20

T2

3561

T3

368

auto[1]

675932

1

T1

12

T2

3619

T3

436

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

806588

1

T1

4

T2

6032

T3

424

auto[1]

539648

1

T1

28

T2

1148

T3

380

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97668	1			T2	462		T3	48		T5	448
all_values[0]	auto[0]	auto[1]	69934	1			T1	4		T2	425		T3	41
all_values[0]	auto[1]	auto[0]	98819	1			T1	1		T2	479		T3	59
all_values[0]	auto[1]	auto[1]	70138	1			T1	3		T2	429		T3	53
all_values[1]	auto[0]	auto[0]	101407	1			T1	1		T2	893		T3	48
all_values[1]	auto[0]	auto[1]	66553	1			T1	4		T2	56		T3	40
all_values[1]	auto[1]	auto[0]	102200	1			T2	807		T3	65		T4	38
all_values[1]	auto[1]	auto[1]	66399	1			T1	3		T2	39		T3	48
all_values[2]	auto[0]	auto[0]	100173	1			T1	1		T2	823		T3	47
all_values[2]	auto[0]	auto[1]	67504	1			T1	4		T2	47		T3	46
all_values[2]	auto[1]	auto[0]	101498	1			T2	873		T3	54		T4	37
all_values[2]	auto[1]	auto[1]	67384	1			T1	3		T2	52		T3	54
all_values[3]	auto[0]	auto[0]	101419	1			T1	1		T2	812		T3	50
all_values[3]	auto[0]	auto[1]	65646	1			T1	5		T2	43		T3	48
all_values[3]	auto[1]	auto[0]	103404	1			T2	883		T3	53		T4	42
all_values[3]	auto[1]	auto[1]	66090	1			T1	2		T2	57		T3	50