Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	336559	1			T1	8		T2	1795		T3	201
all_pins[1]	336559	1			T1	8		T2	1795		T3	201
all_pins[2]	336559	1			T1	8		T2	1795		T3	201
all_pins[3]	336559	1			T1	8		T2	1795		T3	201

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1076225	1			T1	21		T2	6603		T3	599
values[0x1]	270011	1			T1	11		T2	577		T3	205
transitions[0x0=>0x1]	179215	1			T1	6		T2	506		T3	129
transitions[0x1=>0x0]	179468	1			T1	6		T2	506		T3	129

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	266421	1			T1	5		T2	1366		T3	148
all_pins[0]	values[0x1]	70138	1			T1	3		T2	429		T3	53
all_pins[0]	transitions[0x0=>0x1]	69510	1			T1	3		T2	429		T3	53
all_pins[0]	transitions[0x1=>0x0]	65715	1			T1	2		T2	57		T3	50
all_pins[1]	values[0x0]	270160	1			T1	5		T2	1756		T3	153
all_pins[1]	values[0x1]	66399	1			T1	3		T2	39		T3	48
all_pins[1]	transitions[0x0=>0x1]	36489	1			T1	3		T2	19		T3	25
all_pins[1]	transitions[0x1=>0x0]	40228	1			T1	3		T2	409		T3	30
all_pins[2]	values[0x0]	269175	1			T1	5		T2	1743		T3	147
all_pins[2]	values[0x1]	67384	1			T1	3		T2	52		T3	54
all_pins[2]	transitions[0x0=>0x1]	37398	1			T2	31		T3	30		T4	1
all_pins[2]	transitions[0x1=>0x0]	36413	1			T2	18		T3	24		T5	208
all_pins[3]	values[0x0]	270469	1			T1	6		T2	1738		T3	151
all_pins[3]	values[0x1]	66090	1			T1	2		T2	57		T3	50
all_pins[3]	transitions[0x0=>0x1]	35818	1			T2	27		T3	21		T4	1
all_pins[3]	transitions[0x1=>0x0]	37112	1			T1	1		T2	22		T3	25