Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	98877	1			T2	197		T5	682		T7	1025
accum_cnt_1000	231710	1			T1	1		T2	178		T3	84
accum_cnt_100	26134	1			T2	11		T3	56		T5	22
accum_cnt_50	59198	1			T1	10		T2	18		T3	41
accum_cnt_10	170622	1			T1	24		T2	129		T3	204
accum_cnt_0	366438	1			T1	9		T2	3954		T3	15

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	249436	1			T1	11		T2	1312		T3	100
class_index[0x1]	249436	1			T1	11		T2	1312		T3	100
class_index[0x2]	249436	1			T1	11		T2	1312		T3	100
class_index[0x3]	249436	1			T1	11		T2	1312		T3	100

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	28576	1			T2	197		T7	346		T9	211
class_index[0x0]	accum_cnt_1000	61885	1			T1	1		T2	178		T7	591
class_index[0x0]	accum_cnt_100	7911	1			T2	9		T7	28		T11	536
class_index[0x0]	accum_cnt_50	14998	1			T1	3		T2	15		T6	3
class_index[0x0]	accum_cnt_10	44600	1			T1	5		T2	126		T3	94
class_index[0x0]	accum_cnt_0	77878	1			T1	2		T2	26		T3	6
class_index[0x1]	accum_cnt_2000	22608	1			T7	188		T8	602		T10	430
class_index[0x1]	accum_cnt_1000	54619	1			T3	17		T21	56		T7	729
class_index[0x1]	accum_cnt_100	7013	1			T3	40		T21	18		T7	48
class_index[0x1]	accum_cnt_50	19591	1			T1	7		T3	30		T21	16
class_index[0x1]	accum_cnt_10	42520	1			T1	2		T2	3		T3	9
class_index[0x1]	accum_cnt_0	94173	1			T1	2		T2	1309		T3	4
class_index[0x2]	accum_cnt_2000	23213	1			T5	682		T66	76		T68	290
class_index[0x2]	accum_cnt_1000	60493	1			T3	67		T5	679		T21	38
class_index[0x2]	accum_cnt_100	5789	1			T3	16		T5	22		T21	30
class_index[0x2]	accum_cnt_50	13389	1			T3	11		T21	20		T22	1
class_index[0x2]	accum_cnt_10	39858	1			T1	11		T3	5		T4	26
class_index[0x2]	accum_cnt_0	96025	1			T2	1312		T3	1		T4	7
class_index[0x3]	accum_cnt_2000	24480	1			T7	491		T11	134		T18	78
class_index[0x3]	accum_cnt_1000	54713	1			T21	52		T7	468		T11	686
class_index[0x3]	accum_cnt_100	5421	1			T2	2		T21	19		T7	21
class_index[0x3]	accum_cnt_50	11220	1			T2	3		T21	17		T7	21
class_index[0x3]	accum_cnt_10	43644	1			T1	6		T3	96		T4	32
class_index[0x3]	accum_cnt_0	98362	1			T1	5		T2	1307		T3	4