Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3014	1			T5	7		T11	29		T44	4
alert[0x1]	5118	1			T4	1		T12	2		T73	1
alert[0x2]	3712	1			T11	18		T69	189		T112	1
alert[0x3]	2832	1			T1	23		T11	72		T69	159
alert[0x4]	4659	1			T5	80		T86	9		T46	1
alert[0x5]	7665	1			T5	87		T11	21		T18	8
alert[0x6]	6473	1			T11	8		T18	532		T44	3
alert[0x7]	4977	1			T5	772		T83	8		T85	1
alert[0x8]	1624	1			T5	33		T11	20		T87	1
alert[0x9]	8117	1			T5	5040		T69	356		T86	6
alert[0xa]	5784	1			T5	36		T11	34		T69	6
alert[0xb]	5861	1			T5	12		T67	53		T45	32
alert[0xc]	8060	1			T5	142		T11	12		T18	331
alert[0xd]	4911	1			T1	6		T11	93		T18	40
alert[0xe]	3210	1			T1	3		T18	109		T69	65
alert[0xf]	4227	1			T4	1		T18	729		T12	2
alert[0x10]	11369	1			T5	115		T11	8		T69	2165
alert[0x11]	4585	1			T18	29		T69	35		T45	45
alert[0x12]	5939	1			T4	1		T11	1149		T14	1
alert[0x13]	4542	1			T4	1		T5	17		T12	1
alert[0x14]	8341	1			T2	4		T14	1		T45	44
alert[0x15]	2987	1			T4	1		T18	23		T14	1
alert[0x16]	5743	1			T1	1		T18	247		T44	2
alert[0x17]	4371	1			T47	3		T307	1		T55	4
alert[0x18]	5012	1			T11	64		T12	1		T69	625
alert[0x19]	3746	1			T4	1		T5	207		T11	202
alert[0x1a]	7181	1			T4	1		T69	389		T14	1
alert[0x1b]	3214	1			T18	1		T12	3		T44	9
alert[0x1c]	5206	1			T18	3		T69	291		T45	520
alert[0x1d]	3965	1			T18	13		T87	1		T46	1
alert[0x1e]	2634	1			T11	16		T18	70		T76	1
alert[0x1f]	5878	1			T4	1		T12	1		T44	1
alert[0x20]	4555	1			T5	6		T11	27		T44	8
alert[0x21]	2707	1			T28	1		T45	271		T83	38
alert[0x22]	4683	1			T5	175		T18	1273		T69	276
alert[0x23]	4956	1			T4	1		T5	1131		T308	1
alert[0x24]	9021	1			T5	193		T14	1		T46	1
alert[0x25]	2731	1			T69	59		T67	2		T14	1
alert[0x26]	9167	1			T1	1		T5	232		T18	269
alert[0x27]	6182	1			T44	16		T69	2131		T35	37
alert[0x28]	9764	1			T4	1		T18	2328		T86	1
alert[0x29]	14146	1			T5	23		T12	1		T45	44
alert[0x2a]	8590	1			T11	94		T18	100		T12	1
alert[0x2b]	3865	1			T4	1		T18	16		T12	1
alert[0x2c]	11377	1			T5	75		T11	9		T69	21
alert[0x2d]	9691	1			T4	2		T5	4987		T18	134
alert[0x2e]	2464	1			T44	32		T65	1		T83	57
alert[0x2f]	10231	1			T5	1425		T11	43		T67	3
alert[0x30]	9777	1			T5	3		T11	3725		T18	1087
alert[0x31]	2221	1			T18	19		T45	5		T87	2
alert[0x32]	14640	1			T5	3154		T11	416		T18	389
alert[0x33]	9150	1			T5	198		T18	139		T69	68
alert[0x34]	7168	1			T11	23		T65	1		T67	2
alert[0x35]	5338	1			T69	1607		T47	2		T35	5
alert[0x36]	5002	1			T2	2		T4	1		T5	211
alert[0x37]	5165	1			T5	192		T11	53		T18	1
alert[0x38]	1792	1			T86	1		T47	3		T42	1
alert[0x39]	3647	1			T11	33		T42	1		T95	1
alert[0x3a]	4965	1			T11	21		T69	179		T14	2
alert[0x3b]	4624	1			T5	336		T18	13		T44	1
alert[0x3c]	3308	1			T69	488		T67	12		T45	86
alert[0x3d]	5830	1			T18	125		T14	2		T45	274
alert[0x3e]	6453	1			T11	163		T18	191		T112	1
alert[0x3f]	4089	1			T11	5		T44	2		T67	44
alert[0x40]	3243	1			T2	2		T4	1		T11	185

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	115252	1			T4	14		T5	2		T11	2752
class_i[0x1]	96661	1			T1	34		T44	124		T69	12899
class_i[0x2]	72837	1			T5	137		T11	4		T12	18
class_i[0x3]	90749	1			T2	8		T4	1		T5	18750

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

374791

1

T1

34

T2

8

T5

18889

alert_ping_fail

708

1

T4

15

T12

19

T13

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3002	1			T5	7		T11	29		T44	4
alert_integrity_fail	alert[0x1]	5107	1			T73	1		T259	2		T256	1
alert_integrity_fail	alert[0x2]	3703	1			T11	18		T69	189		T46	9
alert_integrity_fail	alert[0x3]	2823	1			T1	23		T11	72		T69	159
alert_integrity_fail	alert[0x4]	4653	1			T5	80		T86	9		T46	1
alert_integrity_fail	alert[0x5]	7649	1			T5	87		T11	21		T18	8
alert_integrity_fail	alert[0x6]	6463	1			T11	8		T18	532		T44	3
alert_integrity_fail	alert[0x7]	4963	1			T5	772		T83	8		T85	1
alert_integrity_fail	alert[0x8]	1608	1			T5	33		T11	20		T259	6
alert_integrity_fail	alert[0x9]	8102	1			T5	5040		T69	356		T86	6
alert_integrity_fail	alert[0xa]	5775	1			T5	36		T11	34		T69	6
alert_integrity_fail	alert[0xb]	5853	1			T5	12		T67	53		T45	32
alert_integrity_fail	alert[0xc]	8053	1			T5	142		T11	12		T18	331
alert_integrity_fail	alert[0xd]	4900	1			T1	6		T11	93		T18	40
alert_integrity_fail	alert[0xe]	3202	1			T1	3		T18	109		T69	65
alert_integrity_fail	alert[0xf]	4213	1			T18	729		T45	66		T73	2
alert_integrity_fail	alert[0x10]	11354	1			T5	115		T11	8		T69	2165
alert_integrity_fail	alert[0x11]	4576	1			T18	29		T69	35		T45	45
alert_integrity_fail	alert[0x12]	5927	1			T11	1149		T45	143		T46	100
alert_integrity_fail	alert[0x13]	4528	1			T5	17		T67	13		T47	1
alert_integrity_fail	alert[0x14]	8320	1			T2	4		T45	44		T76	4
alert_integrity_fail	alert[0x15]	2969	1			T18	23		T95	7		T52	70
alert_integrity_fail	alert[0x16]	5729	1			T1	1		T18	247		T44	2
alert_integrity_fail	alert[0x17]	4366	1			T47	3		T55	4		T89	3
alert_integrity_fail	alert[0x18]	5003	1			T11	64		T69	625		T46	1
alert_integrity_fail	alert[0x19]	3738	1			T5	207		T11	202		T35	16
alert_integrity_fail	alert[0x1a]	7166	1			T69	389		T46	4		T35	1
alert_integrity_fail	alert[0x1b]	3199	1			T18	1		T44	9		T45	27
alert_integrity_fail	alert[0x1c]	5197	1			T18	3		T69	291		T45	520
alert_integrity_fail	alert[0x1d]	3948	1			T18	13		T46	1		T83	49
alert_integrity_fail	alert[0x1e]	2627	1			T11	16		T18	70		T76	1
alert_integrity_fail	alert[0x1f]	5858	1			T44	1		T69	2		T86	1
alert_integrity_fail	alert[0x20]	4546	1			T5	6		T11	27		T44	8
alert_integrity_fail	alert[0x21]	2692	1			T28	1		T45	271		T83	38
alert_integrity_fail	alert[0x22]	4666	1			T5	175		T18	1273		T69	276
alert_integrity_fail	alert[0x23]	4940	1			T5	1131		T83	26		T261	1
alert_integrity_fail	alert[0x24]	9011	1			T5	193		T46	1		T259	2
alert_integrity_fail	alert[0x25]	2720	1			T69	59		T67	2		T45	119
alert_integrity_fail	alert[0x26]	9161	1			T1	1		T5	232		T18	269
alert_integrity_fail	alert[0x27]	6175	1			T44	16		T69	2131		T35	37
alert_integrity_fail	alert[0x28]	9751	1			T18	2328		T86	1		T45	7
alert_integrity_fail	alert[0x29]	14140	1			T5	23		T45	44		T91	6
alert_integrity_fail	alert[0x2a]	8572	1			T11	94		T18	100		T69	274
alert_integrity_fail	alert[0x2b]	3855	1			T18	16		T86	4		T82	7
alert_integrity_fail	alert[0x2c]	11369	1			T5	75		T11	9		T69	21
alert_integrity_fail	alert[0x2d]	9678	1			T5	4987		T18	134		T69	1478
alert_integrity_fail	alert[0x2e]	2453	1			T44	32		T65	1		T83	57
alert_integrity_fail	alert[0x2f]	10220	1			T5	1425		T11	43		T67	3
alert_integrity_fail	alert[0x30]	9763	1			T5	3		T11	3725		T18	1087
alert_integrity_fail	alert[0x31]	2213	1			T18	19		T45	5		T81	5
alert_integrity_fail	alert[0x32]	14634	1			T5	3154		T11	416		T18	389
alert_integrity_fail	alert[0x33]	9145	1			T5	198		T18	139		T69	68
alert_integrity_fail	alert[0x34]	7160	1			T11	23		T65	1		T67	2
alert_integrity_fail	alert[0x35]	5329	1			T69	1607		T47	2		T35	5
alert_integrity_fail	alert[0x36]	4996	1			T2	2		T5	211		T69	1356
alert_integrity_fail	alert[0x37]	5150	1			T5	192		T11	53		T18	1
alert_integrity_fail	alert[0x38]	1783	1			T86	1		T47	3		T84	5
alert_integrity_fail	alert[0x39]	3642	1			T11	33		T95	1		T52	416
alert_integrity_fail	alert[0x3a]	4955	1			T11	21		T69	179		T45	91
alert_integrity_fail	alert[0x3b]	4613	1			T5	336		T18	13		T44	1
alert_integrity_fail	alert[0x3c]	3299	1			T69	488		T67	12		T45	86
alert_integrity_fail	alert[0x3d]	5825	1			T18	125		T45	274		T73	1
alert_integrity_fail	alert[0x3e]	6441	1			T11	163		T18	191		T46	1
alert_integrity_fail	alert[0x3f]	4082	1			T11	5		T44	2		T67	44
alert_integrity_fail	alert[0x40]	3238	1			T2	2		T11	185		T45	31
alert_ping_fail	alert[0x0]	12	1			T308	1		T309	1		T310	2
alert_ping_fail	alert[0x1]	11	1			T4	1		T12	2		T42	1
alert_ping_fail	alert[0x2]	9	1			T112	1		T311	1		T312	1
alert_ping_fail	alert[0x3]	9	1			T14	1		T42	1		T313	1
alert_ping_fail	alert[0x4]	6	1			T314	1		T315	1		T316	1
alert_ping_fail	alert[0x5]	16	1			T42	1		T317	2		T318	1
alert_ping_fail	alert[0x6]	10	1			T319	2		T320	1		T318	1
alert_ping_fail	alert[0x7]	14	1			T313	2		T321	1		T310	1
alert_ping_fail	alert[0x8]	16	1			T87	1		T40	1		T319	1
alert_ping_fail	alert[0x9]	15	1			T307	1		T225	1		T318	1
alert_ping_fail	alert[0xa]	9	1			T319	1		T321	1		T322	1
alert_ping_fail	alert[0xb]	8	1			T323	1		T324	1		T315	1
alert_ping_fail	alert[0xc]	7	1			T87	1		T225	1		T325	1
alert_ping_fail	alert[0xd]	11	1			T12	1		T308	1		T309	1
alert_ping_fail	alert[0xe]	8	1			T326	1		T308	1		T307	1
alert_ping_fail	alert[0xf]	14	1			T4	1		T12	2		T87	1
alert_ping_fail	alert[0x10]	15	1			T14	1		T308	2		T318	1
alert_ping_fail	alert[0x11]	9	1			T225	1		T309	1		T324	1
alert_ping_fail	alert[0x12]	12	1			T4	1		T14	1		T312	1
alert_ping_fail	alert[0x13]	14	1			T4	1		T12	1		T13	1
alert_ping_fail	alert[0x14]	21	1			T14	1		T327	2		T307	2
alert_ping_fail	alert[0x15]	18	1			T4	1		T14	1		T328	2
alert_ping_fail	alert[0x16]	14	1			T232	2		T87	1		T326	1
alert_ping_fail	alert[0x17]	5	1			T307	1		T225	1		T316	1
alert_ping_fail	alert[0x18]	9	1			T12	1		T307	1		T313	1
alert_ping_fail	alert[0x19]	8	1			T4	1		T12	1		T112	1
alert_ping_fail	alert[0x1a]	15	1			T4	1		T14	1		T313	1
alert_ping_fail	alert[0x1b]	15	1			T12	3		T42	1		T225	1
alert_ping_fail	alert[0x1c]	9	1			T305	1		T280	3		T310	1
alert_ping_fail	alert[0x1d]	17	1			T87	1		T42	1		T308	1
alert_ping_fail	alert[0x1e]	7	1			T307	1		T313	1		T225	1
alert_ping_fail	alert[0x1f]	20	1			T4	1		T12	1		T233	2
alert_ping_fail	alert[0x20]	9	1			T308	1		T314	1		T317	1
alert_ping_fail	alert[0x21]	15	1			T313	1		T329	1		T309	1
alert_ping_fail	alert[0x22]	17	1			T87	1		T304	1		T313	1
alert_ping_fail	alert[0x23]	16	1			T4	1		T308	1		T318	1
alert_ping_fail	alert[0x24]	10	1			T14	1		T307	1		T225	1
alert_ping_fail	alert[0x25]	11	1			T14	1		T314	1		T309	1
alert_ping_fail	alert[0x26]	6	1			T14	1		T112	1		T308	1
alert_ping_fail	alert[0x27]	7	1			T313	1		T310	2		T330	1
alert_ping_fail	alert[0x28]	13	1			T4	1		T308	2		T313	1
alert_ping_fail	alert[0x29]	6	1			T12	1		T330	1		T331	1
alert_ping_fail	alert[0x2a]	18	1			T12	1		T332	1		T333	1
alert_ping_fail	alert[0x2b]	10	1			T4	1		T12	1		T334	1
alert_ping_fail	alert[0x2c]	8	1			T304	1		T307	1		T328	1
alert_ping_fail	alert[0x2d]	13	1			T4	2		T12	2		T232	1
alert_ping_fail	alert[0x2e]	11	1			T314	1		T313	1		T310	2
alert_ping_fail	alert[0x2f]	11	1			T14	1		T314	1		T335	1
alert_ping_fail	alert[0x30]	14	1			T14	1		T87	1		T314	1
alert_ping_fail	alert[0x31]	8	1			T87	2		T225	1		T324	1
alert_ping_fail	alert[0x32]	6	1			T308	1		T322	1		T330	1
alert_ping_fail	alert[0x33]	5	1			T307	1		T323	1		T336	1
alert_ping_fail	alert[0x34]	8	1			T14	1		T326	1		T308	1
alert_ping_fail	alert[0x35]	9	1			T312	2		T310	1		T337	2
alert_ping_fail	alert[0x36]	6	1			T4	1		T42	1		T312	1
alert_ping_fail	alert[0x37]	15	1			T12	2		T87	1		T326	1
alert_ping_fail	alert[0x38]	9	1			T42	1		T323	1		T315	1
alert_ping_fail	alert[0x39]	5	1			T42	1		T324	1		T338	1
alert_ping_fail	alert[0x3a]	10	1			T14	2		T42	1		T318	1
alert_ping_fail	alert[0x3b]	11	1			T112	1		T314	1		T225	2
alert_ping_fail	alert[0x3c]	9	1			T307	2		T310	1		T339	2
alert_ping_fail	alert[0x3d]	5	1			T14	2		T326	1		T323	1
alert_ping_fail	alert[0x3e]	12	1			T112	1		T42	1		T333	1
alert_ping_fail	alert[0x3f]	7	1			T308	1		T313	1		T225	1
alert_ping_fail	alert[0x40]	5	1			T4	1		T308	1		T311	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	115069	1			T5	2		T11	2752		T28	384
alert_integrity_fail	class_i[0x1]	96470	1			T1	34		T44	124		T69	12899
alert_integrity_fail	class_i[0x2]	72659	1			T5	137		T11	4		T86	17
alert_integrity_fail	class_i[0x3]	90593	1			T2	8		T5	18750		T11	3787
alert_ping_fail	class_i[0x0]	183	1			T4	14		T12	1		T14	14
alert_ping_fail	class_i[0x1]	191	1			T232	4		T14	2		T112	1
alert_ping_fail	class_i[0x2]	178	1			T12	18		T13	1		T233	2
alert_ping_fail	class_i[0x3]	156	1			T4	1		T87	10		T40	2