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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.69 99.99 98.74 100.00 100.00 100.00 99.38 99.72


Total test records in report: 829
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T140 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1430645016 Apr 04 04:05:52 PM PDT 24 Apr 04 04:22:33 PM PDT 24 50340329402 ps
T774 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1426838906 Apr 04 04:05:36 PM PDT 24 Apr 04 04:06:20 PM PDT 24 3341919408 ps
T148 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1113494944 Apr 04 04:05:05 PM PDT 24 Apr 04 04:24:33 PM PDT 24 15391518393 ps
T775 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1220962940 Apr 04 04:06:12 PM PDT 24 Apr 04 04:06:14 PM PDT 24 9064893 ps
T776 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.458253327 Apr 04 04:05:03 PM PDT 24 Apr 04 04:09:21 PM PDT 24 3335098762 ps
T777 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3701988365 Apr 04 04:05:39 PM PDT 24 Apr 04 04:05:41 PM PDT 24 6683133 ps
T144 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2642642467 Apr 04 04:05:39 PM PDT 24 Apr 04 04:20:59 PM PDT 24 46473301438 ps
T778 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1445332315 Apr 04 04:06:12 PM PDT 24 Apr 04 04:06:14 PM PDT 24 13251792 ps
T160 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.4207713330 Apr 04 04:05:36 PM PDT 24 Apr 04 04:05:41 PM PDT 24 115756701 ps
T779 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3084369287 Apr 04 04:05:37 PM PDT 24 Apr 04 04:06:20 PM PDT 24 6468864962 ps
T780 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2498871535 Apr 04 04:05:37 PM PDT 24 Apr 04 04:05:51 PM PDT 24 1095601849 ps
T781 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.946852250 Apr 04 04:05:18 PM PDT 24 Apr 04 04:05:54 PM PDT 24 1061921786 ps
T782 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3110325756 Apr 04 04:05:20 PM PDT 24 Apr 04 04:05:34 PM PDT 24 181313884 ps
T783 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3824170759 Apr 04 04:05:38 PM PDT 24 Apr 04 04:05:40 PM PDT 24 10783998 ps
T161 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2273809977 Apr 04 04:05:19 PM PDT 24 Apr 04 04:06:53 PM PDT 24 3584176719 ps
T784 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3613713341 Apr 04 04:05:51 PM PDT 24 Apr 04 04:06:07 PM PDT 24 85378212 ps
T785 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3828459760 Apr 04 04:04:51 PM PDT 24 Apr 04 04:05:00 PM PDT 24 263359569 ps
T143 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.690500473 Apr 04 04:05:03 PM PDT 24 Apr 04 04:07:04 PM PDT 24 846116226 ps
T786 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1483410862 Apr 04 04:06:26 PM PDT 24 Apr 04 04:06:28 PM PDT 24 9320396 ps
T787 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.853335027 Apr 04 04:06:13 PM PDT 24 Apr 04 04:06:22 PM PDT 24 780589050 ps
T166 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1592527007 Apr 04 04:05:05 PM PDT 24 Apr 04 04:06:24 PM PDT 24 5138332521 ps
T788 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2135004028 Apr 04 04:05:02 PM PDT 24 Apr 04 04:05:13 PM PDT 24 76668006 ps
T168 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1961666312 Apr 04 04:05:21 PM PDT 24 Apr 04 04:05:24 PM PDT 24 23616280 ps
T789 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.4145263747 Apr 04 04:06:13 PM PDT 24 Apr 04 04:06:14 PM PDT 24 11708978 ps
T790 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2381258144 Apr 04 04:05:23 PM PDT 24 Apr 04 04:05:24 PM PDT 24 7536394 ps
T176 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2825363512 Apr 04 04:05:23 PM PDT 24 Apr 04 04:05:44 PM PDT 24 313521573 ps
T791 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.170379779 Apr 04 04:05:20 PM PDT 24 Apr 04 04:05:47 PM PDT 24 668052580 ps
T792 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3777374235 Apr 04 04:04:51 PM PDT 24 Apr 04 04:04:59 PM PDT 24 95320893 ps
T138 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.280006947 Apr 04 04:05:51 PM PDT 24 Apr 04 04:09:28 PM PDT 24 6578997650 ps
T793 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1028090997 Apr 04 04:06:14 PM PDT 24 Apr 04 04:06:16 PM PDT 24 13875628 ps
T367 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1602455022 Apr 04 04:05:20 PM PDT 24 Apr 04 04:25:57 PM PDT 24 34106869432 ps
T794 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3656432906 Apr 04 04:05:39 PM PDT 24 Apr 04 04:06:20 PM PDT 24 2531511314 ps
T795 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2471612101 Apr 04 04:05:36 PM PDT 24 Apr 04 04:05:42 PM PDT 24 52039381 ps
T796 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2723615080 Apr 04 04:04:49 PM PDT 24 Apr 04 04:04:56 PM PDT 24 45606226 ps
T797 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1556509730 Apr 04 04:04:48 PM PDT 24 Apr 04 04:04:49 PM PDT 24 6355657 ps
T798 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.546226034 Apr 04 04:05:02 PM PDT 24 Apr 04 04:05:16 PM PDT 24 256400711 ps
T799 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2762111816 Apr 04 04:06:11 PM PDT 24 Apr 04 04:06:12 PM PDT 24 13050121 ps
T150 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1905301285 Apr 04 04:05:02 PM PDT 24 Apr 04 04:10:14 PM PDT 24 4707217640 ps
T800 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2161680837 Apr 04 04:05:37 PM PDT 24 Apr 04 04:05:58 PM PDT 24 1043866701 ps
T801 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3631855990 Apr 04 04:05:03 PM PDT 24 Apr 04 04:05:13 PM PDT 24 607674191 ps
T165 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.953103913 Apr 04 04:05:57 PM PDT 24 Apr 04 04:06:01 PM PDT 24 171579134 ps
T802 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2536237030 Apr 04 04:04:49 PM PDT 24 Apr 04 04:04:56 PM PDT 24 157160797 ps
T146 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3023916968 Apr 04 04:05:36 PM PDT 24 Apr 04 04:21:34 PM PDT 24 25219790759 ps
T803 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3155856058 Apr 04 04:05:37 PM PDT 24 Apr 04 04:05:44 PM PDT 24 360551660 ps
T804 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.559169054 Apr 04 04:05:05 PM PDT 24 Apr 04 04:05:12 PM PDT 24 1125334884 ps
T164 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3818002275 Apr 04 04:05:39 PM PDT 24 Apr 04 04:06:01 PM PDT 24 180621961 ps
T163 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.903850753 Apr 04 04:04:52 PM PDT 24 Apr 04 04:05:13 PM PDT 24 1040481068 ps
T805 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2979096275 Apr 04 04:04:49 PM PDT 24 Apr 04 04:07:41 PM PDT 24 1150723705 ps
T151 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1538119531 Apr 04 04:05:20 PM PDT 24 Apr 04 04:08:46 PM PDT 24 1775352915 ps
T806 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3210666272 Apr 04 04:05:22 PM PDT 24 Apr 04 04:05:32 PM PDT 24 128100567 ps
T807 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.4145703863 Apr 04 04:06:12 PM PDT 24 Apr 04 04:06:13 PM PDT 24 8843057 ps
T808 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1893191285 Apr 04 04:05:05 PM PDT 24 Apr 04 04:05:30 PM PDT 24 169555348 ps
T149 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1233156537 Apr 04 04:05:54 PM PDT 24 Apr 04 04:17:28 PM PDT 24 18801247460 ps
T809 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3081805164 Apr 04 04:04:49 PM PDT 24 Apr 04 04:04:59 PM PDT 24 104418368 ps
T175 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.968101429 Apr 04 04:05:36 PM PDT 24 Apr 04 04:05:38 PM PDT 24 58347098 ps
T810 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1801452072 Apr 04 04:05:21 PM PDT 24 Apr 04 04:05:30 PM PDT 24 580401531 ps
T147 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.679585559 Apr 04 04:05:37 PM PDT 24 Apr 04 04:09:14 PM PDT 24 3698930421 ps
T811 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.374496635 Apr 04 04:05:02 PM PDT 24 Apr 04 04:08:16 PM PDT 24 1672239498 ps
T812 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2192960929 Apr 04 04:06:13 PM PDT 24 Apr 04 04:06:14 PM PDT 24 11441357 ps
T813 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1901790668 Apr 04 04:05:19 PM PDT 24 Apr 04 04:05:25 PM PDT 24 386458116 ps
T814 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3827131932 Apr 04 04:05:37 PM PDT 24 Apr 04 04:05:46 PM PDT 24 366550292 ps
T366 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.867866148 Apr 04 04:05:06 PM PDT 24 Apr 04 04:26:04 PM PDT 24 86184806352 ps
T815 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3100946353 Apr 04 04:06:13 PM PDT 24 Apr 04 04:06:15 PM PDT 24 35597199 ps
T816 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1647207212 Apr 04 04:06:11 PM PDT 24 Apr 04 04:06:13 PM PDT 24 11734970 ps
T817 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.322584714 Apr 04 04:05:02 PM PDT 24 Apr 04 04:05:08 PM PDT 24 8215299 ps
T818 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.667004547 Apr 04 04:05:20 PM PDT 24 Apr 04 04:05:28 PM PDT 24 725979233 ps
T819 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2078586674 Apr 04 04:05:02 PM PDT 24 Apr 04 04:05:24 PM PDT 24 1771802459 ps
T162 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3381425230 Apr 04 04:04:51 PM PDT 24 Apr 04 04:05:31 PM PDT 24 1949381767 ps
T820 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2088597065 Apr 04 04:05:56 PM PDT 24 Apr 04 04:06:03 PM PDT 24 234760602 ps
T821 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.893056349 Apr 04 04:05:03 PM PDT 24 Apr 04 04:05:25 PM PDT 24 715668602 ps
T822 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1304213561 Apr 04 04:06:12 PM PDT 24 Apr 04 04:06:18 PM PDT 24 69789500 ps
T823 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.4004875615 Apr 04 04:05:56 PM PDT 24 Apr 04 04:06:51 PM PDT 24 8622133555 ps
T824 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1609367181 Apr 04 04:05:56 PM PDT 24 Apr 04 04:05:57 PM PDT 24 18086244 ps
T825 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.840944989 Apr 04 04:05:50 PM PDT 24 Apr 04 04:05:52 PM PDT 24 7426625 ps
T826 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2296192778 Apr 04 04:05:19 PM PDT 24 Apr 04 04:05:30 PM PDT 24 857947572 ps
T827 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2017199808 Apr 04 04:04:47 PM PDT 24 Apr 04 04:09:30 PM PDT 24 4460102027 ps
T828 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3767467350 Apr 04 04:05:01 PM PDT 24 Apr 04 04:05:06 PM PDT 24 233706496 ps
T829 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.444540281 Apr 04 04:05:52 PM PDT 24 Apr 04 04:06:14 PM PDT 24 2222342942 ps
T152 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4292710072 Apr 04 04:05:57 PM PDT 24 Apr 04 04:13:26 PM PDT 24 6485191007 ps

Test location /workspace/coverage/default/29.alert_handler_entropy.3424644558
Short name T7
Test name
Test status
Simulation time 9317939787 ps
CPU time 882.23 seconds
Started Apr 04 03:14:49 PM PDT 24
Finished Apr 04 03:29:32 PM PDT 24
Peak memory 273624 kb
Host smart-3eb0f0ed-a6a8-4744-86e8-7fdd307bbea4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424644558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3424644558
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.750477270
Short name T11
Test name
Test status
Simulation time 403554219784 ps
CPU time 5795.46 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 04:50:48 PM PDT 24
Peak memory 338940 kb
Host smart-e71b9aea-e099-40ea-85ac-b11296894003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750477270 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.750477270
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2630563972
Short name T16
Test name
Test status
Simulation time 1529765601 ps
CPU time 22.76 seconds
Started Apr 04 03:13:43 PM PDT 24
Finished Apr 04 03:14:06 PM PDT 24
Peak memory 273652 kb
Host smart-3f188712-cc09-462e-b406-885f1e5cbe69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2630563972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2630563972
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.4034418420
Short name T45
Test name
Test status
Simulation time 82382165314 ps
CPU time 5025.16 seconds
Started Apr 04 03:15:48 PM PDT 24
Finished Apr 04 04:39:34 PM PDT 24
Peak memory 338524 kb
Host smart-a94b4503-68d9-4c2c-9404-bfeb18eef816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034418420 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.4034418420
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.798547343
Short name T117
Test name
Test status
Simulation time 56877934990 ps
CPU time 981.78 seconds
Started Apr 04 04:05:19 PM PDT 24
Finished Apr 04 04:21:41 PM PDT 24
Peak memory 265008 kb
Host smart-794bdda3-76b3-4b03-9b85-b037f6b257f5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798547343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.798547343
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3758899092
Short name T18
Test name
Test status
Simulation time 71501065372 ps
CPU time 2173.57 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:50:06 PM PDT 24
Peak memory 273736 kb
Host smart-ff925b7b-425d-4afb-8b4f-0fdd609b8f0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758899092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3758899092
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1029351162
Short name T153
Test name
Test status
Simulation time 1368737937 ps
CPU time 39.87 seconds
Started Apr 04 04:05:38 PM PDT 24
Finished Apr 04 04:06:19 PM PDT 24
Peak memory 240012 kb
Host smart-ba2f093a-5c9a-4c8c-bc83-ac93089f7e41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1029351162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1029351162
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2680326628
Short name T471
Test name
Test status
Simulation time 50659513518 ps
CPU time 2692.68 seconds
Started Apr 04 03:15:05 PM PDT 24
Finished Apr 04 03:59:58 PM PDT 24
Peak memory 289464 kb
Host smart-164b8a9c-d915-40af-9704-cf2409a798c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680326628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2680326628
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3253678857
Short name T232
Test name
Test status
Simulation time 24015382856 ps
CPU time 1251.15 seconds
Started Apr 04 03:14:26 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 273252 kb
Host smart-4cda596d-ae9d-4bc1-9312-a6d265e99d67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253678857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3253678857
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3226061357
Short name T108
Test name
Test status
Simulation time 84676088275 ps
CPU time 2365.57 seconds
Started Apr 04 03:14:36 PM PDT 24
Finished Apr 04 03:54:01 PM PDT 24
Peak memory 289892 kb
Host smart-af35dca1-8253-49ef-9bfe-3e9098ee5006
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226061357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3226061357
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2158185264
Short name T121
Test name
Test status
Simulation time 1684058442 ps
CPU time 207.06 seconds
Started Apr 04 04:05:53 PM PDT 24
Finished Apr 04 04:09:20 PM PDT 24
Peak memory 264784 kb
Host smart-a895e0e0-25ae-45a0-a44b-cc8f19332d5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2158185264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2158185264
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2959081868
Short name T115
Test name
Test status
Simulation time 40645584512 ps
CPU time 2364.53 seconds
Started Apr 04 03:14:59 PM PDT 24
Finished Apr 04 03:54:25 PM PDT 24
Peak memory 284748 kb
Host smart-d5a409d2-e577-4ba0-ba23-61234f606da0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959081868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2959081868
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3736732389
Short name T4
Test name
Test status
Simulation time 64237568801 ps
CPU time 403.27 seconds
Started Apr 04 03:13:45 PM PDT 24
Finished Apr 04 03:20:29 PM PDT 24
Peak memory 248296 kb
Host smart-76693913-1d5e-4d58-9370-11eee6a4d526
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736732389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3736732389
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.491586927
Short name T127
Test name
Test status
Simulation time 17817412317 ps
CPU time 694.61 seconds
Started Apr 04 04:04:51 PM PDT 24
Finished Apr 04 04:16:26 PM PDT 24
Peak memory 265088 kb
Host smart-c4311696-c046-43fc-917c-91694af97c9a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491586927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.491586927
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2987799277
Short name T9
Test name
Test status
Simulation time 16606678705 ps
CPU time 1048.08 seconds
Started Apr 04 03:14:44 PM PDT 24
Finished Apr 04 03:32:12 PM PDT 24
Peak memory 265616 kb
Host smart-3e2329bc-40fc-45be-b522-2125bf67cf84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987799277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2987799277
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.4061427167
Short name T89
Test name
Test status
Simulation time 70752714734 ps
CPU time 6684.79 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 05:06:00 PM PDT 24
Peak memory 348340 kb
Host smart-56a567e7-6e28-4822-b0da-7518010c3123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061427167 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.4061427167
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2129574296
Short name T304
Test name
Test status
Simulation time 192398909481 ps
CPU time 2901.33 seconds
Started Apr 04 03:14:21 PM PDT 24
Finished Apr 04 04:02:43 PM PDT 24
Peak memory 286092 kb
Host smart-1b1ef2ba-f4bd-4a0d-9769-2c3304ecb25b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129574296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2129574296
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.659143523
Short name T120
Test name
Test status
Simulation time 39642489757 ps
CPU time 386.39 seconds
Started Apr 04 04:05:19 PM PDT 24
Finished Apr 04 04:11:46 PM PDT 24
Peak memory 265024 kb
Host smart-c74a209e-00e5-4917-8fa4-6a8a2c3e5694
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=659143523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.659143523
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1412989410
Short name T158
Test name
Test status
Simulation time 24400545 ps
CPU time 1.53 seconds
Started Apr 04 04:06:28 PM PDT 24
Finished Apr 04 04:06:30 PM PDT 24
Peak memory 235532 kb
Host smart-2e288ab5-e507-40a3-9725-2c9a4ef944aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1412989410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1412989410
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.280006947
Short name T138
Test name
Test status
Simulation time 6578997650 ps
CPU time 216.75 seconds
Started Apr 04 04:05:51 PM PDT 24
Finished Apr 04 04:09:28 PM PDT 24
Peak memory 265048 kb
Host smart-c399023e-7623-41d0-85e6-a7328d1f0948
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=280006947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.280006947
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2076191469
Short name T46
Test name
Test status
Simulation time 98087039942 ps
CPU time 1669.89 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 03:42:25 PM PDT 24
Peak memory 289292 kb
Host smart-88705b29-09e4-4d73-b771-7764dba07a33
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076191469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2076191469
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3577540590
Short name T320
Test name
Test status
Simulation time 68943360678 ps
CPU time 1870.99 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:45:46 PM PDT 24
Peak memory 273740 kb
Host smart-99609216-4b8d-418f-804a-443049411d7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577540590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3577540590
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2008601012
Short name T85
Test name
Test status
Simulation time 352120884507 ps
CPU time 2950.02 seconds
Started Apr 04 03:15:46 PM PDT 24
Finished Apr 04 04:04:57 PM PDT 24
Peak memory 289284 kb
Host smart-491a6743-9f8a-4cbc-b22a-a14e22e5da20
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008601012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2008601012
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1934410289
Short name T142
Test name
Test status
Simulation time 8673779510 ps
CPU time 316.86 seconds
Started Apr 04 04:05:40 PM PDT 24
Finished Apr 04 04:10:57 PM PDT 24
Peak memory 269220 kb
Host smart-a693f539-9806-4a80-bb01-7e9e5809526b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934410289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1934410289
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2545401938
Short name T324
Test name
Test status
Simulation time 41678895716 ps
CPU time 428.62 seconds
Started Apr 04 03:14:50 PM PDT 24
Finished Apr 04 03:21:58 PM PDT 24
Peak memory 248380 kb
Host smart-3eb3ac83-1b64-407d-9d7c-1c522483e523
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545401938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2545401938
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3023916968
Short name T146
Test name
Test status
Simulation time 25219790759 ps
CPU time 957.35 seconds
Started Apr 04 04:05:36 PM PDT 24
Finished Apr 04 04:21:34 PM PDT 24
Peak memory 265028 kb
Host smart-11e5330b-dbec-4eb2-a7dd-de9829568967
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023916968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3023916968
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3135563506
Short name T313
Test name
Test status
Simulation time 49193709355 ps
CPU time 525.11 seconds
Started Apr 04 03:14:51 PM PDT 24
Finished Apr 04 03:23:36 PM PDT 24
Peak memory 249140 kb
Host smart-965d9d58-6cd4-4c48-ab8e-6b7047ba8d58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135563506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3135563506
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.679585559
Short name T147
Test name
Test status
Simulation time 3698930421 ps
CPU time 217.36 seconds
Started Apr 04 04:05:37 PM PDT 24
Finished Apr 04 04:09:14 PM PDT 24
Peak memory 265016 kb
Host smart-bcaa5f12-0374-4a08-a8b8-2b5bea8c572b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=679585559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.679585559
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3579260299
Short name T319
Test name
Test status
Simulation time 187365413470 ps
CPU time 2133.24 seconds
Started Apr 04 03:13:46 PM PDT 24
Finished Apr 04 03:49:20 PM PDT 24
Peak memory 289124 kb
Host smart-5fe00ff5-86eb-4d2b-a214-cd080f449d59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579260299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3579260299
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3977367430
Short name T84
Test name
Test status
Simulation time 45223044064 ps
CPU time 1191.7 seconds
Started Apr 04 03:15:46 PM PDT 24
Finished Apr 04 03:35:38 PM PDT 24
Peak memory 289536 kb
Host smart-05dbd85a-5e4d-47c9-b424-5435a6b5dbb9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977367430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3977367430
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1211998231
Short name T132
Test name
Test status
Simulation time 60891781267 ps
CPU time 484.84 seconds
Started Apr 04 04:05:55 PM PDT 24
Finished Apr 04 04:14:00 PM PDT 24
Peak memory 265104 kb
Host smart-0563b523-80e4-4b15-835a-2c0bc2f72346
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211998231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1211998231
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1701888052
Short name T14
Test name
Test status
Simulation time 13926698366 ps
CPU time 563.05 seconds
Started Apr 04 03:14:28 PM PDT 24
Finished Apr 04 03:23:51 PM PDT 24
Peak memory 248304 kb
Host smart-276ecc85-9b57-4609-957a-0456c4740ef0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701888052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1701888052
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1894327782
Short name T119
Test name
Test status
Simulation time 1954092440 ps
CPU time 136.18 seconds
Started Apr 04 04:05:36 PM PDT 24
Finished Apr 04 04:07:52 PM PDT 24
Peak memory 256716 kb
Host smart-bacd6253-6033-44b6-98ad-b30436d23828
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1894327782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1894327782
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3353206025
Short name T47
Test name
Test status
Simulation time 39432301177 ps
CPU time 1052.7 seconds
Started Apr 04 03:14:24 PM PDT 24
Finished Apr 04 03:31:57 PM PDT 24
Peak memory 289740 kb
Host smart-3e1070aa-7adb-4f6b-9da6-656e3d3b93e0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353206025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3353206025
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.12554475
Short name T526
Test name
Test status
Simulation time 41512415024 ps
CPU time 2323.36 seconds
Started Apr 04 03:14:23 PM PDT 24
Finished Apr 04 03:53:07 PM PDT 24
Peak memory 289200 kb
Host smart-9c922a04-3f2d-4c52-a1bb-399c808dc4c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12554475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.12554475
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2805216424
Short name T65
Test name
Test status
Simulation time 32100693418 ps
CPU time 1043.16 seconds
Started Apr 04 03:14:10 PM PDT 24
Finished Apr 04 03:31:34 PM PDT 24
Peak memory 281680 kb
Host smart-ff179aca-0e64-4fa3-9e66-01cb90cf327d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805216424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2805216424
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.4202283816
Short name T181
Test name
Test status
Simulation time 52109760133 ps
CPU time 1012.72 seconds
Started Apr 04 03:14:09 PM PDT 24
Finished Apr 04 03:31:02 PM PDT 24
Peak memory 285772 kb
Host smart-148ebf0b-b755-4578-89f8-9d21e45a75c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202283816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.4202283816
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1052217495
Short name T307
Test name
Test status
Simulation time 85363986543 ps
CPU time 376.49 seconds
Started Apr 04 03:15:33 PM PDT 24
Finished Apr 04 03:21:50 PM PDT 24
Peak memory 247192 kb
Host smart-6684bcbd-e7d8-4052-82aa-257accacd940
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052217495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1052217495
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2267168678
Short name T156
Test name
Test status
Simulation time 18885298 ps
CPU time 2.01 seconds
Started Apr 04 04:04:51 PM PDT 24
Finished Apr 04 04:04:53 PM PDT 24
Peak memory 235556 kb
Host smart-d7b7e00a-af14-40e7-91ff-19d69da5d00c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2267168678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2267168678
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1540309747
Short name T343
Test name
Test status
Simulation time 214199621493 ps
CPU time 2838.24 seconds
Started Apr 04 03:14:29 PM PDT 24
Finished Apr 04 04:01:47 PM PDT 24
Peak memory 286812 kb
Host smart-74886549-c2fb-41cf-9c4d-0828e2699f1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540309747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1540309747
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2757085674
Short name T625
Test name
Test status
Simulation time 27525085976 ps
CPU time 1689.64 seconds
Started Apr 04 03:14:48 PM PDT 24
Finished Apr 04 03:42:58 PM PDT 24
Peak memory 273724 kb
Host smart-778113fa-ff3d-4a21-b87f-560a17ff188b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757085674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2757085674
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.4236736556
Short name T250
Test name
Test status
Simulation time 262588003876 ps
CPU time 3190.02 seconds
Started Apr 04 03:15:14 PM PDT 24
Finished Apr 04 04:08:24 PM PDT 24
Peak memory 289832 kb
Host smart-c98fb168-17d8-4b20-8a37-d2d2a14fb2b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236736556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.4236736556
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3036780896
Short name T129
Test name
Test status
Simulation time 28257184149 ps
CPU time 528.42 seconds
Started Apr 04 04:05:38 PM PDT 24
Finished Apr 04 04:14:26 PM PDT 24
Peak memory 265060 kb
Host smart-552a9788-f009-4b32-8e5d-9fe556688125
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036780896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3036780896
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1434733361
Short name T83
Test name
Test status
Simulation time 64352311023 ps
CPU time 1741.12 seconds
Started Apr 04 03:14:37 PM PDT 24
Finished Apr 04 03:43:38 PM PDT 24
Peak memory 306096 kb
Host smart-d881d67a-697c-466d-a50e-b1c8b7eb9434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434733361 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1434733361
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1278024268
Short name T349
Test name
Test status
Simulation time 52077992037 ps
CPU time 1468.2 seconds
Started Apr 04 03:15:00 PM PDT 24
Finished Apr 04 03:39:29 PM PDT 24
Peak memory 273180 kb
Host smart-6741b7e1-b490-443a-9caf-fac0c4b449e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278024268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1278024268
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3077359426
Short name T315
Test name
Test status
Simulation time 17478090220 ps
CPU time 350.93 seconds
Started Apr 04 03:13:52 PM PDT 24
Finished Apr 04 03:19:44 PM PDT 24
Peak memory 247416 kb
Host smart-98a994af-6d56-4f1a-a376-9cb5e56881a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077359426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3077359426
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2166401535
Short name T128
Test name
Test status
Simulation time 1596589095 ps
CPU time 208.26 seconds
Started Apr 04 04:05:01 PM PDT 24
Finished Apr 04 04:08:29 PM PDT 24
Peak memory 271000 kb
Host smart-59fd8e23-8d58-4e63-a8c2-e98d217a32a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2166401535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2166401535
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.867866148
Short name T366
Test name
Test status
Simulation time 86184806352 ps
CPU time 1256.85 seconds
Started Apr 04 04:05:06 PM PDT 24
Finished Apr 04 04:26:04 PM PDT 24
Peak memory 271568 kb
Host smart-0e87fe5a-7341-4c19-aef4-c0e18d49062b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867866148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.867866148
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3595837669
Short name T211
Test name
Test status
Simulation time 43613075 ps
CPU time 3.62 seconds
Started Apr 04 03:13:39 PM PDT 24
Finished Apr 04 03:13:43 PM PDT 24
Peak memory 249284 kb
Host smart-beed8f4a-1f52-4435-977c-fc3f1d75e060
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3595837669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3595837669
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.859360637
Short name T202
Test name
Test status
Simulation time 38322448 ps
CPU time 3.29 seconds
Started Apr 04 03:13:45 PM PDT 24
Finished Apr 04 03:13:49 PM PDT 24
Peak memory 249332 kb
Host smart-e99a6799-42d4-4f03-b49c-4f1e313271c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=859360637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.859360637
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4238682496
Short name T207
Test name
Test status
Simulation time 16193166 ps
CPU time 2.52 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:14 PM PDT 24
Peak memory 249340 kb
Host smart-3b6046b5-fdf1-442d-a070-93fc26d4fb42
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4238682496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4238682496
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3578775996
Short name T209
Test name
Test status
Simulation time 23699487 ps
CPU time 2.16 seconds
Started Apr 04 03:14:10 PM PDT 24
Finished Apr 04 03:14:13 PM PDT 24
Peak memory 249344 kb
Host smart-222cbfaa-a699-4e70-a16d-7a1c936a3f94
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3578775996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3578775996
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2063580226
Short name T743
Test name
Test status
Simulation time 7114481 ps
CPU time 1.49 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:05:41 PM PDT 24
Peak memory 236416 kb
Host smart-2f1275e5-226c-4457-8888-0c09c9370e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2063580226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2063580226
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.98526496
Short name T274
Test name
Test status
Simulation time 50096696111 ps
CPU time 1299.68 seconds
Started Apr 04 03:13:45 PM PDT 24
Finished Apr 04 03:35:25 PM PDT 24
Peak memory 299244 kb
Host smart-8b29d4e4-db27-4eaa-aaa5-7720d23c3545
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98526496 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.98526496
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.889723899
Short name T278
Test name
Test status
Simulation time 78285949843 ps
CPU time 2024.74 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:47:57 PM PDT 24
Peak memory 305952 kb
Host smart-5bd064fa-7139-4d50-99be-a618c8ab82bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889723899 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.889723899
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1614941697
Short name T317
Test name
Test status
Simulation time 38692569497 ps
CPU time 1517.9 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 03:39:53 PM PDT 24
Peak memory 266224 kb
Host smart-434b08d7-72c6-401a-a05c-ba5855086708
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614941697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1614941697
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.961047373
Short name T604
Test name
Test status
Simulation time 52431365308 ps
CPU time 502.23 seconds
Started Apr 04 03:14:45 PM PDT 24
Finished Apr 04 03:23:07 PM PDT 24
Peak memory 248044 kb
Host smart-3e7a7f8c-daad-4e3a-b182-9ec9291dc889
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961047373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.961047373
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.42474548
Short name T238
Test name
Test status
Simulation time 568155194203 ps
CPU time 3382.11 seconds
Started Apr 04 03:14:47 PM PDT 24
Finished Apr 04 04:11:10 PM PDT 24
Peak memory 298432 kb
Host smart-99a49e90-8171-42e6-af45-5f06e01732f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42474548 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.42474548
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3662143407
Short name T332
Test name
Test status
Simulation time 35770190235 ps
CPU time 2327.39 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:54:18 PM PDT 24
Peak memory 289352 kb
Host smart-9592c371-e8fc-4aad-a834-a4d1bf9de430
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662143407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3662143407
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2727170141
Short name T257
Test name
Test status
Simulation time 2841704287 ps
CPU time 64.26 seconds
Started Apr 04 03:15:31 PM PDT 24
Finished Apr 04 03:16:35 PM PDT 24
Peak memory 255832 kb
Host smart-5b20fa64-77b8-432e-8275-47bb8dff2a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27271
70141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2727170141
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2722504051
Short name T253
Test name
Test status
Simulation time 27698425238 ps
CPU time 1351.11 seconds
Started Apr 04 03:16:15 PM PDT 24
Finished Apr 04 03:38:46 PM PDT 24
Peak memory 290092 kb
Host smart-ce1a839d-1fbb-4cc0-aeec-230c3f5b386b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722504051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2722504051
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3736493708
Short name T159
Test name
Test status
Simulation time 236465673 ps
CPU time 3.97 seconds
Started Apr 04 04:05:01 PM PDT 24
Finished Apr 04 04:05:05 PM PDT 24
Peak memory 236336 kb
Host smart-637430bb-6cfc-47b2-b691-3089ab378ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3736493708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3736493708
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1172217720
Short name T135
Test name
Test status
Simulation time 7941942063 ps
CPU time 671 seconds
Started Apr 04 04:04:49 PM PDT 24
Finished Apr 04 04:16:01 PM PDT 24
Peak memory 265308 kb
Host smart-30016b61-1c14-4f34-9557-b017f0821e12
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172217720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1172217720
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3420646771
Short name T131
Test name
Test status
Simulation time 2480857271 ps
CPU time 171.17 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:08:30 PM PDT 24
Peak memory 264796 kb
Host smart-1677cfc5-2dbb-4528-a45e-c79ec039f3c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3420646771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3420646771
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1592527007
Short name T166
Test name
Test status
Simulation time 5138332521 ps
CPU time 77.63 seconds
Started Apr 04 04:05:05 PM PDT 24
Finished Apr 04 04:06:24 PM PDT 24
Peak memory 240072 kb
Host smart-01a22a77-a52d-4d74-9a2c-e558e548ea97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1592527007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1592527007
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.110688273
Short name T631
Test name
Test status
Simulation time 151080123712 ps
CPU time 315.92 seconds
Started Apr 04 03:13:56 PM PDT 24
Finished Apr 04 03:19:13 PM PDT 24
Peak memory 248032 kb
Host smart-bbabff79-e976-43c4-98e7-fec5bf26fa3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110688273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.110688273
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2177760044
Short name T255
Test name
Test status
Simulation time 2108176884 ps
CPU time 36.77 seconds
Started Apr 04 03:13:59 PM PDT 24
Finished Apr 04 03:14:36 PM PDT 24
Peak memory 247676 kb
Host smart-e2cc76df-5653-46f6-a8a0-0580fc49c450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21777
60044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2177760044
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3983200533
Short name T268
Test name
Test status
Simulation time 739441479 ps
CPU time 22.6 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 03:14:20 PM PDT 24
Peak memory 249080 kb
Host smart-cbd323ca-69ea-43f0-b3e5-44a03a06220c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39832
00533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3983200533
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.592345170
Short name T273
Test name
Test status
Simulation time 191082226929 ps
CPU time 2401.51 seconds
Started Apr 04 03:14:12 PM PDT 24
Finished Apr 04 03:54:14 PM PDT 24
Peak memory 285900 kb
Host smart-d42df2c6-6fa5-4c87-98c5-d0c7d34afbf6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592345170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.592345170
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.174286803
Short name T290
Test name
Test status
Simulation time 874177240 ps
CPU time 57.61 seconds
Started Apr 04 03:14:12 PM PDT 24
Finished Apr 04 03:15:10 PM PDT 24
Peak memory 254840 kb
Host smart-6ee62032-e44d-4a85-abad-e1dead8ef445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17428
6803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.174286803
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3809623945
Short name T269
Test name
Test status
Simulation time 189286905051 ps
CPU time 2306.62 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:52:38 PM PDT 24
Peak memory 281928 kb
Host smart-b458519f-09c1-4689-bcf9-61380ba65985
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809623945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3809623945
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1241081413
Short name T263
Test name
Test status
Simulation time 818841330 ps
CPU time 16.51 seconds
Started Apr 04 03:14:28 PM PDT 24
Finished Apr 04 03:14:44 PM PDT 24
Peak memory 255148 kb
Host smart-fcdae57b-347d-4ba4-8367-1b407e602971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12410
81413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1241081413
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.642491489
Short name T73
Test name
Test status
Simulation time 1605258915 ps
CPU time 60.54 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:14:52 PM PDT 24
Peak memory 248480 kb
Host smart-6931a1ee-a3fa-49d8-a52f-62977c46e1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64249
1489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.642491489
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.37892204
Short name T87
Test name
Test status
Simulation time 6328567897 ps
CPU time 258.59 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:18:44 PM PDT 24
Peak memory 247252 kb
Host smart-44ba4515-23d5-4e9e-9103-f01d7dcee2fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37892204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.37892204
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2330310888
Short name T281
Test name
Test status
Simulation time 156108637 ps
CPU time 9.55 seconds
Started Apr 04 03:14:28 PM PDT 24
Finished Apr 04 03:14:37 PM PDT 24
Peak memory 257244 kb
Host smart-9d2a1106-8cfb-435a-a2fa-5c8999ea11c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303
10888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2330310888
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3828639741
Short name T687
Test name
Test status
Simulation time 59097690906 ps
CPU time 1381.98 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 03:37:38 PM PDT 24
Peak memory 289364 kb
Host smart-9e58e647-4562-4107-a464-b2474fb0d9f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828639741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3828639741
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2473742155
Short name T291
Test name
Test status
Simulation time 1589608553 ps
CPU time 48.66 seconds
Started Apr 04 03:14:49 PM PDT 24
Finished Apr 04 03:15:37 PM PDT 24
Peak memory 256196 kb
Host smart-907510aa-cc02-4c10-b828-383dc7672bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24737
42155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2473742155
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.775290064
Short name T282
Test name
Test status
Simulation time 358165012 ps
CPU time 32.67 seconds
Started Apr 04 03:14:49 PM PDT 24
Finished Apr 04 03:15:21 PM PDT 24
Peak memory 249056 kb
Host smart-85476c83-22f6-4888-ba7d-6a10b4e97628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77529
0064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.775290064
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.298005620
Short name T266
Test name
Test status
Simulation time 39146276412 ps
CPU time 2489.87 seconds
Started Apr 04 03:15:01 PM PDT 24
Finished Apr 04 03:56:31 PM PDT 24
Peak memory 289904 kb
Host smart-de5fdef9-f7ab-47bc-8efd-29f5cca079c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298005620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.298005620
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.388646258
Short name T345
Test name
Test status
Simulation time 111489129562 ps
CPU time 1538.34 seconds
Started Apr 04 03:15:46 PM PDT 24
Finished Apr 04 03:41:24 PM PDT 24
Peak memory 268812 kb
Host smart-a8496547-eee5-44a2-ad9d-af4d79e67bd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388646258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.388646258
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2594772619
Short name T130
Test name
Test status
Simulation time 4538800749 ps
CPU time 172.66 seconds
Started Apr 04 04:04:49 PM PDT 24
Finished Apr 04 04:07:42 PM PDT 24
Peak memory 267280 kb
Host smart-2d5db12c-5e10-488b-8321-67bb6d2f6296
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2594772619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2594772619
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.4010847830
Short name T133
Test name
Test status
Simulation time 2329229761 ps
CPU time 143.14 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:08:02 PM PDT 24
Peak memory 256884 kb
Host smart-1bfdf298-1679-4168-871e-5ea9a347daf2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4010847830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.4010847830
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.4207713330
Short name T160
Test name
Test status
Simulation time 115756701 ps
CPU time 4.31 seconds
Started Apr 04 04:05:36 PM PDT 24
Finished Apr 04 04:05:41 PM PDT 24
Peak memory 236276 kb
Host smart-b0897a02-6d09-494c-b318-ed3bc6762c79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4207713330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.4207713330
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1233156537
Short name T149
Test name
Test status
Simulation time 18801247460 ps
CPU time 694.31 seconds
Started Apr 04 04:05:54 PM PDT 24
Finished Apr 04 04:17:28 PM PDT 24
Peak memory 265184 kb
Host smart-5481f6d8-d9fa-4738-a69d-cc531f09d7e5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233156537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1233156537
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2720496148
Short name T169
Test name
Test status
Simulation time 1296367703 ps
CPU time 42.35 seconds
Started Apr 04 04:05:03 PM PDT 24
Finished Apr 04 04:05:49 PM PDT 24
Peak memory 239180 kb
Host smart-cec3cd87-eaad-43a7-abb8-b1f98f4aec91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2720496148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2720496148
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1963836277
Short name T137
Test name
Test status
Simulation time 3679102834 ps
CPU time 265.27 seconds
Started Apr 04 04:05:20 PM PDT 24
Finished Apr 04 04:09:45 PM PDT 24
Peak memory 264804 kb
Host smart-0b791434-0e88-4c0e-ab72-e86291261eb0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1963836277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1963836277
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.4056901702
Short name T170
Test name
Test status
Simulation time 194453575 ps
CPU time 3.72 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:05:43 PM PDT 24
Peak memory 236960 kb
Host smart-7fe715a5-9d77-43c7-84f8-b4bba9e34dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4056901702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.4056901702
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2273809977
Short name T161
Test name
Test status
Simulation time 3584176719 ps
CPU time 93.25 seconds
Started Apr 04 04:05:19 PM PDT 24
Finished Apr 04 04:06:53 PM PDT 24
Peak memory 240204 kb
Host smart-aade6e4e-4224-415d-a799-4828c5941d02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2273809977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2273809977
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.903850753
Short name T163
Test name
Test status
Simulation time 1040481068 ps
CPU time 20.44 seconds
Started Apr 04 04:04:52 PM PDT 24
Finished Apr 04 04:05:13 PM PDT 24
Peak memory 240076 kb
Host smart-fb01e2f2-8cba-4c19-8100-36bd8a19b9d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=903850753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.903850753
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3696539134
Short name T167
Test name
Test status
Simulation time 109198075 ps
CPU time 3.15 seconds
Started Apr 04 04:05:41 PM PDT 24
Finished Apr 04 04:05:44 PM PDT 24
Peak memory 236372 kb
Host smart-8187c3a5-1769-4cf3-85d2-83ce7a783a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3696539134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3696539134
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.953103913
Short name T165
Test name
Test status
Simulation time 171579134 ps
CPU time 4.22 seconds
Started Apr 04 04:05:57 PM PDT 24
Finished Apr 04 04:06:01 PM PDT 24
Peak memory 237436 kb
Host smart-aa05b387-ee7e-4294-96f2-a6f06c49672b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=953103913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.953103913
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3381425230
Short name T162
Test name
Test status
Simulation time 1949381767 ps
CPU time 40.51 seconds
Started Apr 04 04:04:51 PM PDT 24
Finished Apr 04 04:05:31 PM PDT 24
Peak memory 240044 kb
Host smart-5a8cba2e-022e-424b-925f-d75ee78a95b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3381425230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3381425230
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1961666312
Short name T168
Test name
Test status
Simulation time 23616280 ps
CPU time 2.45 seconds
Started Apr 04 04:05:21 PM PDT 24
Finished Apr 04 04:05:24 PM PDT 24
Peak memory 236400 kb
Host smart-76a9a0d2-8ecc-42c0-b412-cf8bb86dfd65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1961666312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1961666312
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3818002275
Short name T164
Test name
Test status
Simulation time 180621961 ps
CPU time 21.52 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:06:01 PM PDT 24
Peak memory 240056 kb
Host smart-dee25987-bc2f-4902-8902-3510f1b81ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3818002275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3818002275
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1974356313
Short name T154
Test name
Test status
Simulation time 83088690 ps
CPU time 4.45 seconds
Started Apr 04 04:05:56 PM PDT 24
Finished Apr 04 04:06:00 PM PDT 24
Peak memory 237436 kb
Host smart-ae43c952-8c9b-4a97-a912-ef7cb83c7e19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1974356313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1974356313
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1643608040
Short name T155
Test name
Test status
Simulation time 3611363633 ps
CPU time 37.55 seconds
Started Apr 04 04:05:54 PM PDT 24
Finished Apr 04 04:06:32 PM PDT 24
Peak memory 236816 kb
Host smart-6b30c125-9d4b-4620-b150-ad24f275dbcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1643608040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1643608040
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3743335540
Short name T174
Test name
Test status
Simulation time 546373352 ps
CPU time 41.57 seconds
Started Apr 04 04:06:12 PM PDT 24
Finished Apr 04 04:06:53 PM PDT 24
Peak memory 240060 kb
Host smart-d95bf53b-36f5-4ab1-8581-f7f1d2b10105
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3743335540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3743335540
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2825363512
Short name T176
Test name
Test status
Simulation time 313521573 ps
CPU time 21.04 seconds
Started Apr 04 04:05:23 PM PDT 24
Finished Apr 04 04:05:44 PM PDT 24
Peak memory 240076 kb
Host smart-679013b8-3772-478a-9270-782fda1f6c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2825363512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2825363512
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.687868495
Short name T25
Test name
Test status
Simulation time 1298295612 ps
CPU time 70.62 seconds
Started Apr 04 03:14:22 PM PDT 24
Finished Apr 04 03:15:33 PM PDT 24
Peak memory 255752 kb
Host smart-2f5b0f02-99e0-4e2a-b161-00bacb7fbf62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68786
8495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.687868495
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3354527321
Short name T27
Test name
Test status
Simulation time 5454234067 ps
CPU time 36.69 seconds
Started Apr 04 03:14:52 PM PDT 24
Finished Apr 04 03:15:29 PM PDT 24
Peak memory 256240 kb
Host smart-c5563d31-51f0-40db-b271-bf5a0307e15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33545
27321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3354527321
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2979096275
Short name T805
Test name
Test status
Simulation time 1150723705 ps
CPU time 171.67 seconds
Started Apr 04 04:04:49 PM PDT 24
Finished Apr 04 04:07:41 PM PDT 24
Peak memory 240544 kb
Host smart-eceecfe2-4b9e-4349-b25d-95bb2b1f3436
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2979096275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2979096275
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1881093069
Short name T766
Test name
Test status
Simulation time 6803135153 ps
CPU time 218.25 seconds
Started Apr 04 04:04:49 PM PDT 24
Finished Apr 04 04:08:28 PM PDT 24
Peak memory 236480 kb
Host smart-608276e0-f220-41ab-843b-4b2419e7b823
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1881093069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1881093069
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2276968911
Short name T759
Test name
Test status
Simulation time 135879726 ps
CPU time 5.99 seconds
Started Apr 04 04:04:50 PM PDT 24
Finished Apr 04 04:04:56 PM PDT 24
Peak memory 240032 kb
Host smart-99b9408c-09e1-4c86-9201-65eebece984f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2276968911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2276968911
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2723615080
Short name T796
Test name
Test status
Simulation time 45606226 ps
CPU time 6.54 seconds
Started Apr 04 04:04:49 PM PDT 24
Finished Apr 04 04:04:56 PM PDT 24
Peak memory 241008 kb
Host smart-3dc33838-228e-4f2c-b45f-929975a8921e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723615080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2723615080
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4057918102
Short name T723
Test name
Test status
Simulation time 64456959 ps
CPU time 5.9 seconds
Started Apr 04 04:04:48 PM PDT 24
Finished Apr 04 04:04:54 PM PDT 24
Peak memory 236324 kb
Host smart-2ac5511a-8a18-4e63-94ed-e84b15e7881f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4057918102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.4057918102
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3001879168
Short name T722
Test name
Test status
Simulation time 23656594 ps
CPU time 1.33 seconds
Started Apr 04 04:04:47 PM PDT 24
Finished Apr 04 04:04:49 PM PDT 24
Peak memory 236404 kb
Host smart-79b7dbda-77ac-4cdf-8834-1514915a6ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3001879168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3001879168
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.945027228
Short name T758
Test name
Test status
Simulation time 2283153747 ps
CPU time 35.09 seconds
Started Apr 04 04:04:48 PM PDT 24
Finished Apr 04 04:05:23 PM PDT 24
Peak memory 243808 kb
Host smart-4ff2f107-023a-47ee-8ad4-8ce555a7145c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=945027228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.945027228
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.554068985
Short name T126
Test name
Test status
Simulation time 22006124146 ps
CPU time 367.91 seconds
Started Apr 04 04:04:48 PM PDT 24
Finished Apr 04 04:10:56 PM PDT 24
Peak memory 265048 kb
Host smart-33a2a346-d298-46bb-a40b-83e32c10c927
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=554068985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.554068985
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3828459760
Short name T785
Test name
Test status
Simulation time 263359569 ps
CPU time 8.24 seconds
Started Apr 04 04:04:51 PM PDT 24
Finished Apr 04 04:05:00 PM PDT 24
Peak memory 248080 kb
Host smart-1038d6e6-5cca-4e87-9215-61491056ebad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3828459760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3828459760
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1487255673
Short name T761
Test name
Test status
Simulation time 27350557 ps
CPU time 2.52 seconds
Started Apr 04 04:04:49 PM PDT 24
Finished Apr 04 04:04:52 PM PDT 24
Peak memory 236700 kb
Host smart-65bba9fa-5834-400e-be8b-9f2096e8792c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1487255673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1487255673
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4003643640
Short name T197
Test name
Test status
Simulation time 20814990758 ps
CPU time 258.5 seconds
Started Apr 04 04:04:48 PM PDT 24
Finished Apr 04 04:09:07 PM PDT 24
Peak memory 240196 kb
Host smart-d90f7bbe-bfb8-43f9-aa39-afc5b60f8ea4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4003643640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.4003643640
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2017199808
Short name T827
Test name
Test status
Simulation time 4460102027 ps
CPU time 281.86 seconds
Started Apr 04 04:04:47 PM PDT 24
Finished Apr 04 04:09:30 PM PDT 24
Peak memory 236508 kb
Host smart-6db77b08-655b-4731-b01a-cdae870aa4b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2017199808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2017199808
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2471523983
Short name T188
Test name
Test status
Simulation time 405585757 ps
CPU time 9.07 seconds
Started Apr 04 04:04:51 PM PDT 24
Finished Apr 04 04:05:00 PM PDT 24
Peak memory 240044 kb
Host smart-93737c58-bcee-4647-b056-ee59f44861d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2471523983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2471523983
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3081805164
Short name T809
Test name
Test status
Simulation time 104418368 ps
CPU time 9.45 seconds
Started Apr 04 04:04:49 PM PDT 24
Finished Apr 04 04:04:59 PM PDT 24
Peak memory 240112 kb
Host smart-2d46dd22-fd60-486f-9300-0adb73250e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081805164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3081805164
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3777374235
Short name T792
Test name
Test status
Simulation time 95320893 ps
CPU time 7.43 seconds
Started Apr 04 04:04:51 PM PDT 24
Finished Apr 04 04:04:59 PM PDT 24
Peak memory 235520 kb
Host smart-40f2d044-9947-49c9-bfd1-d6a178299b8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3777374235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3777374235
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.67515730
Short name T744
Test name
Test status
Simulation time 1336710524 ps
CPU time 47.21 seconds
Started Apr 04 04:04:50 PM PDT 24
Finished Apr 04 04:05:38 PM PDT 24
Peak memory 244604 kb
Host smart-0dc0a78d-91cc-4908-8481-4c9e2328c86a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=67515730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outst
anding.67515730
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2262756250
Short name T141
Test name
Test status
Simulation time 6230215820 ps
CPU time 305.09 seconds
Started Apr 04 04:04:52 PM PDT 24
Finished Apr 04 04:09:57 PM PDT 24
Peak memory 265100 kb
Host smart-6d58ea08-31a4-4e13-a79e-045a6a513fdf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262756250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2262756250
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2536237030
Short name T802
Test name
Test status
Simulation time 157160797 ps
CPU time 6.6 seconds
Started Apr 04 04:04:49 PM PDT 24
Finished Apr 04 04:04:56 PM PDT 24
Peak memory 247524 kb
Host smart-6968c0f1-0c9a-4f93-b680-00d270cad624
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2536237030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2536237030
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.280291561
Short name T364
Test name
Test status
Simulation time 1513635825 ps
CPU time 6.69 seconds
Started Apr 04 04:05:36 PM PDT 24
Finished Apr 04 04:05:44 PM PDT 24
Peak memory 239824 kb
Host smart-6de5cd7a-e732-4ecc-ad36-5da17d8ce3f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280291561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.280291561
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3355570340
Short name T369
Test name
Test status
Simulation time 243808341 ps
CPU time 10.12 seconds
Started Apr 04 04:05:38 PM PDT 24
Finished Apr 04 04:05:49 PM PDT 24
Peak memory 240068 kb
Host smart-210513a3-4d65-4e44-80de-087af2ea1c2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3355570340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3355570340
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2125529025
Short name T773
Test name
Test status
Simulation time 6032833 ps
CPU time 1.38 seconds
Started Apr 04 04:05:37 PM PDT 24
Finished Apr 04 04:05:39 PM PDT 24
Peak memory 234528 kb
Host smart-e3df147a-e012-4984-9c98-be5f82f3eb5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2125529025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2125529025
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3656432906
Short name T794
Test name
Test status
Simulation time 2531511314 ps
CPU time 40.55 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:06:20 PM PDT 24
Peak memory 248404 kb
Host smart-0f4548b4-af45-4c4b-861c-7fc1c05539fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3656432906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3656432906
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1186637608
Short name T760
Test name
Test status
Simulation time 3025547460 ps
CPU time 15.46 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:05:55 PM PDT 24
Peak memory 247720 kb
Host smart-770aee63-8249-4bb5-bdd2-6f1de2339f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1186637608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1186637608
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1794131998
Short name T768
Test name
Test status
Simulation time 159434427 ps
CPU time 24.77 seconds
Started Apr 04 04:05:38 PM PDT 24
Finished Apr 04 04:06:03 PM PDT 24
Peak memory 239168 kb
Host smart-433fbacb-12f8-4f6e-9fde-170ef9b79412
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1794131998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1794131998
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1761767505
Short name T724
Test name
Test status
Simulation time 81127444 ps
CPU time 6.85 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:05:46 PM PDT 24
Peak memory 240156 kb
Host smart-3e533eae-6388-4066-ae28-f8a6b292f791
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761767505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1761767505
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2837683961
Short name T189
Test name
Test status
Simulation time 591417541 ps
CPU time 10.45 seconds
Started Apr 04 04:05:34 PM PDT 24
Finished Apr 04 04:05:45 PM PDT 24
Peak memory 236324 kb
Host smart-a3add479-a164-4f3c-86dd-4b8761068469
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2837683961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2837683961
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3701988365
Short name T777
Test name
Test status
Simulation time 6683133 ps
CPU time 1.52 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:05:41 PM PDT 24
Peak memory 236328 kb
Host smart-d744d70b-780c-4c30-a474-12188b8558b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3701988365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3701988365
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3794348383
Short name T192
Test name
Test status
Simulation time 1868916119 ps
CPU time 38.88 seconds
Started Apr 04 04:05:37 PM PDT 24
Finished Apr 04 04:06:16 PM PDT 24
Peak memory 243728 kb
Host smart-561b50f9-281c-496c-85f4-d7c5b0bf9f5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3794348383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3794348383
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3182590291
Short name T739
Test name
Test status
Simulation time 1607801589 ps
CPU time 27.72 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:06:07 PM PDT 24
Peak memory 247140 kb
Host smart-39b23a28-a3ac-47ad-a4dc-365e6100b859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3182590291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3182590291
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3155856058
Short name T803
Test name
Test status
Simulation time 360551660 ps
CPU time 5.98 seconds
Started Apr 04 04:05:37 PM PDT 24
Finished Apr 04 04:05:44 PM PDT 24
Peak memory 240112 kb
Host smart-6ad4e527-7e82-405f-8e54-77714a081722
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155856058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3155856058
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1916156173
Short name T740
Test name
Test status
Simulation time 232314750 ps
CPU time 5.66 seconds
Started Apr 04 04:05:35 PM PDT 24
Finished Apr 04 04:05:41 PM PDT 24
Peak memory 236240 kb
Host smart-5c4c49e9-aeea-4894-ac11-5556189c92fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1916156173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1916156173
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1552290845
Short name T754
Test name
Test status
Simulation time 34446298 ps
CPU time 1.29 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:05:40 PM PDT 24
Peak memory 235548 kb
Host smart-30a714cc-a168-43cd-be45-73488a92e62a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1552290845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1552290845
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1426838906
Short name T774
Test name
Test status
Simulation time 3341919408 ps
CPU time 44.42 seconds
Started Apr 04 04:05:36 PM PDT 24
Finished Apr 04 04:06:20 PM PDT 24
Peak memory 244576 kb
Host smart-26c563e4-bcfd-4a3b-8e2a-ff22aa25b8a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1426838906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1426838906
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2129938291
Short name T145
Test name
Test status
Simulation time 50702125300 ps
CPU time 1081.59 seconds
Started Apr 04 04:05:36 PM PDT 24
Finished Apr 04 04:23:37 PM PDT 24
Peak memory 265172 kb
Host smart-e6230290-ca01-49ae-a2dc-5ba1c01d714e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129938291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2129938291
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4223003499
Short name T734
Test name
Test status
Simulation time 92557427 ps
CPU time 8.52 seconds
Started Apr 04 04:05:40 PM PDT 24
Finished Apr 04 04:05:48 PM PDT 24
Peak memory 248256 kb
Host smart-3caae425-73ea-4243-966f-2bd4aef2674d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4223003499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.4223003499
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2498871535
Short name T780
Test name
Test status
Simulation time 1095601849 ps
CPU time 14.21 seconds
Started Apr 04 04:05:37 PM PDT 24
Finished Apr 04 04:05:51 PM PDT 24
Peak memory 250484 kb
Host smart-728ddf32-ee84-4c79-9ac8-dee55964b524
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498871535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2498871535
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3827131932
Short name T814
Test name
Test status
Simulation time 366550292 ps
CPU time 8.55 seconds
Started Apr 04 04:05:37 PM PDT 24
Finished Apr 04 04:05:46 PM PDT 24
Peak memory 240036 kb
Host smart-66605fb2-4109-437b-b511-0382d2f1b5c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3827131932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3827131932
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3824170759
Short name T783
Test name
Test status
Simulation time 10783998 ps
CPU time 1.42 seconds
Started Apr 04 04:05:38 PM PDT 24
Finished Apr 04 04:05:40 PM PDT 24
Peak memory 235560 kb
Host smart-6374fb76-a573-4b56-b51f-ee88ef633021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3824170759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3824170759
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3084369287
Short name T779
Test name
Test status
Simulation time 6468864962 ps
CPU time 43.07 seconds
Started Apr 04 04:05:37 PM PDT 24
Finished Apr 04 04:06:20 PM PDT 24
Peak memory 248388 kb
Host smart-83b351d4-d19a-4f3e-af41-110c1ba4da57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3084369287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3084369287
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.4126570464
Short name T365
Test name
Test status
Simulation time 31917350203 ps
CPU time 506.41 seconds
Started Apr 04 04:05:38 PM PDT 24
Finished Apr 04 04:14:05 PM PDT 24
Peak memory 265100 kb
Host smart-e15e9eed-3041-44c6-9f97-32cd05a25773
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126570464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.4126570464
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2161680837
Short name T800
Test name
Test status
Simulation time 1043866701 ps
CPU time 20.17 seconds
Started Apr 04 04:05:37 PM PDT 24
Finished Apr 04 04:05:58 PM PDT 24
Peak memory 248324 kb
Host smart-e5bb8a4f-e44f-4e79-bb4e-c7c345210fd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2161680837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2161680837
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3615174356
Short name T765
Test name
Test status
Simulation time 42959526 ps
CPU time 6.77 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:05:45 PM PDT 24
Peak memory 256420 kb
Host smart-46b5fc2e-52e9-46f9-b01e-1a0b9d464cb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615174356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3615174356
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2471612101
Short name T795
Test name
Test status
Simulation time 52039381 ps
CPU time 5.63 seconds
Started Apr 04 04:05:36 PM PDT 24
Finished Apr 04 04:05:42 PM PDT 24
Peak memory 240016 kb
Host smart-9f90d06d-bbd0-4e2f-8f3f-bcc1ff505fb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2471612101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2471612101
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.218873836
Short name T728
Test name
Test status
Simulation time 30155128 ps
CPU time 1.35 seconds
Started Apr 04 04:05:41 PM PDT 24
Finished Apr 04 04:05:42 PM PDT 24
Peak memory 235528 kb
Host smart-65642064-e575-42b7-b05c-ef3896b644ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=218873836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.218873836
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1037075224
Short name T737
Test name
Test status
Simulation time 1982869402 ps
CPU time 40.29 seconds
Started Apr 04 04:05:38 PM PDT 24
Finished Apr 04 04:06:19 PM PDT 24
Peak memory 243712 kb
Host smart-67c32011-c404-4100-8f70-917b7a05bd76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1037075224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1037075224
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2630959929
Short name T124
Test name
Test status
Simulation time 16322634616 ps
CPU time 335.28 seconds
Started Apr 04 04:05:37 PM PDT 24
Finished Apr 04 04:11:12 PM PDT 24
Peak memory 273204 kb
Host smart-d3307135-d3e4-4e53-8209-d82bf19ed909
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2630959929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2630959929
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3212308390
Short name T733
Test name
Test status
Simulation time 1776051092 ps
CPU time 12.9 seconds
Started Apr 04 04:05:36 PM PDT 24
Finished Apr 04 04:05:49 PM PDT 24
Peak memory 247812 kb
Host smart-f11b1c70-ab68-4179-858f-dda9d8acc6f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3212308390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3212308390
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.968101429
Short name T175
Test name
Test status
Simulation time 58347098 ps
CPU time 2.37 seconds
Started Apr 04 04:05:36 PM PDT 24
Finished Apr 04 04:05:38 PM PDT 24
Peak memory 237424 kb
Host smart-0d849791-7b60-4146-9594-ac427998956b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=968101429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.968101429
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1435135010
Short name T745
Test name
Test status
Simulation time 67022729 ps
CPU time 12.81 seconds
Started Apr 04 04:05:56 PM PDT 24
Finished Apr 04 04:06:08 PM PDT 24
Peak memory 248392 kb
Host smart-4eb6d709-e439-412a-a920-58a785836dc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435135010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1435135010
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.623173432
Short name T190
Test name
Test status
Simulation time 39631893 ps
CPU time 5.59 seconds
Started Apr 04 04:05:27 PM PDT 24
Finished Apr 04 04:05:33 PM PDT 24
Peak memory 236384 kb
Host smart-638e93a4-d5b4-4560-9003-c63a941bb4c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=623173432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.623173432
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3608074924
Short name T193
Test name
Test status
Simulation time 493748049 ps
CPU time 32.95 seconds
Started Apr 04 04:05:37 PM PDT 24
Finished Apr 04 04:06:10 PM PDT 24
Peak memory 248244 kb
Host smart-28a1b521-e149-4209-af74-5aff79e965d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3608074924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3608074924
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3248165747
Short name T123
Test name
Test status
Simulation time 10249511867 ps
CPU time 179.53 seconds
Started Apr 04 04:05:38 PM PDT 24
Finished Apr 04 04:08:38 PM PDT 24
Peak memory 265616 kb
Host smart-d26a1b15-6e4b-4543-ab4a-067276628991
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3248165747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3248165747
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2642642467
Short name T144
Test name
Test status
Simulation time 46473301438 ps
CPU time 920.4 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:20:59 PM PDT 24
Peak memory 265008 kb
Host smart-4de0e808-3c2c-4e0d-8c20-01ad87dc8cad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642642467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2642642467
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.478344299
Short name T769
Test name
Test status
Simulation time 204294090 ps
CPU time 14.64 seconds
Started Apr 04 04:05:38 PM PDT 24
Finished Apr 04 04:05:53 PM PDT 24
Peak memory 254924 kb
Host smart-a027aeb5-a4e6-43ca-a924-c8f95eaa0432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=478344299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.478344299
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.895002763
Short name T173
Test name
Test status
Simulation time 33259527 ps
CPU time 5.22 seconds
Started Apr 04 04:05:51 PM PDT 24
Finished Apr 04 04:05:56 PM PDT 24
Peak memory 238868 kb
Host smart-d58fd48b-60cd-43dd-84a4-b5d514e1ba91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895002763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.895002763
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.176250300
Short name T742
Test name
Test status
Simulation time 383785333 ps
CPU time 4.74 seconds
Started Apr 04 04:05:52 PM PDT 24
Finished Apr 04 04:05:57 PM PDT 24
Peak memory 235360 kb
Host smart-3665dcfa-9790-4be7-bb30-78a3ebf3c1cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=176250300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.176250300
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1609367181
Short name T824
Test name
Test status
Simulation time 18086244 ps
CPU time 1.33 seconds
Started Apr 04 04:05:56 PM PDT 24
Finished Apr 04 04:05:57 PM PDT 24
Peak memory 234540 kb
Host smart-157273a8-ce20-4f19-a0bd-237809503796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1609367181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1609367181
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.4004875615
Short name T823
Test name
Test status
Simulation time 8622133555 ps
CPU time 54.35 seconds
Started Apr 04 04:05:56 PM PDT 24
Finished Apr 04 04:06:51 PM PDT 24
Peak memory 248408 kb
Host smart-3b982f78-08ca-46fc-a896-754eb149cf84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4004875615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.4004875615
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.26374917
Short name T122
Test name
Test status
Simulation time 3426482734 ps
CPU time 124.64 seconds
Started Apr 04 04:05:52 PM PDT 24
Finished Apr 04 04:07:57 PM PDT 24
Peak memory 265100 kb
Host smart-9f2fd172-81d7-485f-907c-5b346e432aac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=26374917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_error
s.26374917
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1430645016
Short name T140
Test name
Test status
Simulation time 50340329402 ps
CPU time 1001.1 seconds
Started Apr 04 04:05:52 PM PDT 24
Finished Apr 04 04:22:33 PM PDT 24
Peak memory 265104 kb
Host smart-991142ec-e132-4a61-9957-efdcfdef8b3f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430645016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1430645016
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3330239297
Short name T757
Test name
Test status
Simulation time 532426162 ps
CPU time 9.81 seconds
Started Apr 04 04:05:52 PM PDT 24
Finished Apr 04 04:06:02 PM PDT 24
Peak memory 248296 kb
Host smart-6cd88fb2-174b-4db2-bb57-dcd662c6e70d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3330239297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3330239297
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2691858204
Short name T725
Test name
Test status
Simulation time 236838082 ps
CPU time 5.24 seconds
Started Apr 04 04:05:52 PM PDT 24
Finished Apr 04 04:05:58 PM PDT 24
Peak memory 236952 kb
Host smart-9afe192a-db0e-43fd-9dab-b9587e5c63c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691858204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2691858204
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2088597065
Short name T820
Test name
Test status
Simulation time 234760602 ps
CPU time 6.16 seconds
Started Apr 04 04:05:56 PM PDT 24
Finished Apr 04 04:06:03 PM PDT 24
Peak memory 236400 kb
Host smart-3cec39c2-1493-4548-a733-6dbcf3a3f5ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2088597065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2088597065
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.840944989
Short name T825
Test name
Test status
Simulation time 7426625 ps
CPU time 1.27 seconds
Started Apr 04 04:05:50 PM PDT 24
Finished Apr 04 04:05:52 PM PDT 24
Peak memory 235548 kb
Host smart-8e64b08f-cf1c-4b48-8426-05edae00a6ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=840944989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.840944989
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3262472978
Short name T752
Test name
Test status
Simulation time 740301077 ps
CPU time 25.95 seconds
Started Apr 04 04:05:52 PM PDT 24
Finished Apr 04 04:06:18 PM PDT 24
Peak memory 244612 kb
Host smart-ecc64cb8-a55f-4842-a41d-99fcadde7c26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3262472978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3262472978
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.359941973
Short name T730
Test name
Test status
Simulation time 190230685 ps
CPU time 13.85 seconds
Started Apr 04 04:05:56 PM PDT 24
Finished Apr 04 04:06:09 PM PDT 24
Peak memory 247688 kb
Host smart-57752bd5-f9a8-4b44-8d85-0567c181b88a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=359941973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.359941973
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3150454301
Short name T755
Test name
Test status
Simulation time 282716314 ps
CPU time 7.51 seconds
Started Apr 04 04:05:51 PM PDT 24
Finished Apr 04 04:05:59 PM PDT 24
Peak memory 238660 kb
Host smart-8124ffa9-bbb6-4105-a47a-eca8d4dee3ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150454301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3150454301
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3823926841
Short name T172
Test name
Test status
Simulation time 489245060 ps
CPU time 11.12 seconds
Started Apr 04 04:05:56 PM PDT 24
Finished Apr 04 04:06:07 PM PDT 24
Peak memory 236408 kb
Host smart-87d67163-2e2e-43a4-8281-8eb56c130cf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3823926841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3823926841
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2264674856
Short name T736
Test name
Test status
Simulation time 6458835 ps
CPU time 1.5 seconds
Started Apr 04 04:05:54 PM PDT 24
Finished Apr 04 04:05:55 PM PDT 24
Peak memory 236352 kb
Host smart-9d354aae-5eed-472f-a6fe-a9cf10807282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2264674856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2264674856
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3613713341
Short name T784
Test name
Test status
Simulation time 85378212 ps
CPU time 15.74 seconds
Started Apr 04 04:05:51 PM PDT 24
Finished Apr 04 04:06:07 PM PDT 24
Peak memory 240108 kb
Host smart-efbbc4c2-8c12-415b-9a19-976e76aca36e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3613713341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3613713341
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4292710072
Short name T152
Test name
Test status
Simulation time 6485191007 ps
CPU time 449.54 seconds
Started Apr 04 04:05:57 PM PDT 24
Finished Apr 04 04:13:26 PM PDT 24
Peak memory 267212 kb
Host smart-020bdbe4-4421-4388-a911-9fe111ac0e6d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292710072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4292710072
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.444540281
Short name T829
Test name
Test status
Simulation time 2222342942 ps
CPU time 21.52 seconds
Started Apr 04 04:05:52 PM PDT 24
Finished Apr 04 04:06:14 PM PDT 24
Peak memory 248464 kb
Host smart-2165c0cd-fe5c-44dc-844e-1140150ce0f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=444540281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.444540281
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1304213561
Short name T822
Test name
Test status
Simulation time 69789500 ps
CPU time 5.61 seconds
Started Apr 04 04:06:12 PM PDT 24
Finished Apr 04 04:06:18 PM PDT 24
Peak memory 236528 kb
Host smart-d79db5ff-2fe0-45b4-a7c1-5658b0b53b52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304213561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1304213561
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3576552265
Short name T751
Test name
Test status
Simulation time 61733908 ps
CPU time 5.48 seconds
Started Apr 04 04:06:15 PM PDT 24
Finished Apr 04 04:06:20 PM PDT 24
Peak memory 239996 kb
Host smart-85291119-e98e-4fa5-84c1-42ff0d2b1ef5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3576552265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3576552265
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1220962940
Short name T775
Test name
Test status
Simulation time 9064893 ps
CPU time 1.62 seconds
Started Apr 04 04:06:12 PM PDT 24
Finished Apr 04 04:06:14 PM PDT 24
Peak memory 235508 kb
Host smart-28fc9e6f-33da-48d0-a8f5-a2a1fa8902b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1220962940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1220962940
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1218065452
Short name T195
Test name
Test status
Simulation time 690971044 ps
CPU time 43.05 seconds
Started Apr 04 04:06:12 PM PDT 24
Finished Apr 04 04:06:55 PM PDT 24
Peak memory 243696 kb
Host smart-d3c6cb83-94bf-4203-a6c4-8f4e698f41ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1218065452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1218065452
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1649832630
Short name T139
Test name
Test status
Simulation time 968177066 ps
CPU time 84.01 seconds
Started Apr 04 04:05:56 PM PDT 24
Finished Apr 04 04:07:20 PM PDT 24
Peak memory 256760 kb
Host smart-533315a6-c117-445d-b2dd-b6fdcb5a0660
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1649832630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1649832630
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.853335027
Short name T787
Test name
Test status
Simulation time 780589050 ps
CPU time 8.88 seconds
Started Apr 04 04:06:13 PM PDT 24
Finished Apr 04 04:06:22 PM PDT 24
Peak memory 248160 kb
Host smart-9ed83de7-64f4-4c5a-9def-122ca873258f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=853335027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.853335027
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2581636558
Short name T191
Test name
Test status
Simulation time 5552010557 ps
CPU time 271.95 seconds
Started Apr 04 04:05:03 PM PDT 24
Finished Apr 04 04:09:39 PM PDT 24
Peak memory 240932 kb
Host smart-99027c7d-8ab9-4d11-b33c-72d657a06672
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2581636558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2581636558
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.374496635
Short name T811
Test name
Test status
Simulation time 1672239498 ps
CPU time 194.08 seconds
Started Apr 04 04:05:02 PM PDT 24
Finished Apr 04 04:08:16 PM PDT 24
Peak memory 235460 kb
Host smart-edb9d5e3-5395-4249-a0c1-32f522c573db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=374496635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.374496635
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.346193686
Short name T720
Test name
Test status
Simulation time 77024640 ps
CPU time 4.7 seconds
Started Apr 04 04:04:48 PM PDT 24
Finished Apr 04 04:04:53 PM PDT 24
Peak memory 240060 kb
Host smart-28560ccd-70cc-411a-ad41-f6b820515ebf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=346193686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.346193686
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2276312867
Short name T362
Test name
Test status
Simulation time 189568295 ps
CPU time 4.68 seconds
Started Apr 04 04:05:03 PM PDT 24
Finished Apr 04 04:05:11 PM PDT 24
Peak memory 237464 kb
Host smart-e1794228-4a37-4e13-bc49-95e0d37a3969
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276312867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2276312867
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2023101643
Short name T198
Test name
Test status
Simulation time 45341952 ps
CPU time 5.01 seconds
Started Apr 04 04:05:01 PM PDT 24
Finished Apr 04 04:05:07 PM PDT 24
Peak memory 239988 kb
Host smart-9c029422-cee6-4a53-9009-865ffdd7761f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2023101643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2023101643
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1556509730
Short name T797
Test name
Test status
Simulation time 6355657 ps
CPU time 1.37 seconds
Started Apr 04 04:04:48 PM PDT 24
Finished Apr 04 04:04:49 PM PDT 24
Peak memory 235528 kb
Host smart-54af5a62-96e4-4644-91d1-af5e40921140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1556509730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1556509730
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1893191285
Short name T808
Test name
Test status
Simulation time 169555348 ps
CPU time 22.96 seconds
Started Apr 04 04:05:05 PM PDT 24
Finished Apr 04 04:05:30 PM PDT 24
Peak memory 244476 kb
Host smart-134bf712-4206-4e93-8272-0d5f26ea7eeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1893191285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1893191285
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1433577438
Short name T136
Test name
Test status
Simulation time 4312019979 ps
CPU time 303.31 seconds
Started Apr 04 04:04:52 PM PDT 24
Finished Apr 04 04:09:56 PM PDT 24
Peak memory 265216 kb
Host smart-358cb2a1-2342-4aff-9c6a-e2156f705b22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1433577438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1433577438
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2755295193
Short name T714
Test name
Test status
Simulation time 194366251 ps
CPU time 14.53 seconds
Started Apr 04 04:04:49 PM PDT 24
Finished Apr 04 04:05:04 PM PDT 24
Peak memory 248348 kb
Host smart-3704a648-7227-4091-8605-e64b50a23a52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2755295193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2755295193
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1028090997
Short name T793
Test name
Test status
Simulation time 13875628 ps
CPU time 1.26 seconds
Started Apr 04 04:06:14 PM PDT 24
Finished Apr 04 04:06:16 PM PDT 24
Peak memory 236352 kb
Host smart-a9c019f9-00c6-4095-8b1c-1dc20c5b0cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1028090997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1028090997
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1647207212
Short name T816
Test name
Test status
Simulation time 11734970 ps
CPU time 1.53 seconds
Started Apr 04 04:06:11 PM PDT 24
Finished Apr 04 04:06:13 PM PDT 24
Peak memory 234496 kb
Host smart-f22fb5a3-84ba-492d-8781-037653558a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1647207212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1647207212
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2701873508
Short name T721
Test name
Test status
Simulation time 9787654 ps
CPU time 1.42 seconds
Started Apr 04 04:06:13 PM PDT 24
Finished Apr 04 04:06:15 PM PDT 24
Peak memory 236412 kb
Host smart-b6a4cb6f-f149-4830-add0-c5f9b8e1d6bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2701873508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2701873508
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3103860326
Short name T717
Test name
Test status
Simulation time 8913995 ps
CPU time 1.67 seconds
Started Apr 04 04:06:12 PM PDT 24
Finished Apr 04 04:06:13 PM PDT 24
Peak memory 235532 kb
Host smart-f618298a-91e6-469e-887c-444b3a6a8e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3103860326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3103860326
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2617302080
Short name T358
Test name
Test status
Simulation time 11370552 ps
CPU time 1.34 seconds
Started Apr 04 04:06:16 PM PDT 24
Finished Apr 04 04:06:17 PM PDT 24
Peak memory 236320 kb
Host smart-19e4352b-ff93-43e3-9557-dab19048e296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2617302080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2617302080
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.4145703863
Short name T807
Test name
Test status
Simulation time 8843057 ps
CPU time 1.46 seconds
Started Apr 04 04:06:12 PM PDT 24
Finished Apr 04 04:06:13 PM PDT 24
Peak memory 236432 kb
Host smart-8f386583-106e-458e-87cc-5ba4bf35c1b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4145703863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.4145703863
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2762111816
Short name T799
Test name
Test status
Simulation time 13050121 ps
CPU time 1.69 seconds
Started Apr 04 04:06:11 PM PDT 24
Finished Apr 04 04:06:12 PM PDT 24
Peak memory 235544 kb
Host smart-bea83fa6-2416-4896-89d8-42da62c7e8c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2762111816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2762111816
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2192960929
Short name T812
Test name
Test status
Simulation time 11441357 ps
CPU time 1.38 seconds
Started Apr 04 04:06:13 PM PDT 24
Finished Apr 04 04:06:14 PM PDT 24
Peak memory 236432 kb
Host smart-fa9ebbeb-9aa9-4cbd-bc22-17c808dc3a5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2192960929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2192960929
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2726754624
Short name T727
Test name
Test status
Simulation time 17953626 ps
CPU time 1.44 seconds
Started Apr 04 04:06:13 PM PDT 24
Finished Apr 04 04:06:15 PM PDT 24
Peak memory 236424 kb
Host smart-ae73b02b-881c-45b1-b3a8-ab7544509103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2726754624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2726754624
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3100946353
Short name T815
Test name
Test status
Simulation time 35597199 ps
CPU time 1.32 seconds
Started Apr 04 04:06:13 PM PDT 24
Finished Apr 04 04:06:15 PM PDT 24
Peak memory 236408 kb
Host smart-ef871ff0-ee4c-43c8-a8c5-5f52aefdca2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3100946353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3100946353
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.796160345
Short name T368
Test name
Test status
Simulation time 4539950324 ps
CPU time 153.58 seconds
Started Apr 04 04:05:05 PM PDT 24
Finished Apr 04 04:07:40 PM PDT 24
Peak memory 236528 kb
Host smart-594a4f6a-c310-47e0-86c4-cef67b885fa1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=796160345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.796160345
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3921493678
Short name T767
Test name
Test status
Simulation time 1670345350 ps
CPU time 226.25 seconds
Started Apr 04 04:05:03 PM PDT 24
Finished Apr 04 04:08:53 PM PDT 24
Peak memory 240024 kb
Host smart-42c0d31f-3266-4ea5-b1fd-39678347b03b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3921493678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3921493678
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.559169054
Short name T804
Test name
Test status
Simulation time 1125334884 ps
CPU time 5.37 seconds
Started Apr 04 04:05:05 PM PDT 24
Finished Apr 04 04:05:12 PM PDT 24
Peak memory 240012 kb
Host smart-0c6f36fc-1ec7-413e-a48b-8c6e34e393a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=559169054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.559169054
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3767467350
Short name T828
Test name
Test status
Simulation time 233706496 ps
CPU time 5.3 seconds
Started Apr 04 04:05:01 PM PDT 24
Finished Apr 04 04:05:06 PM PDT 24
Peak memory 250792 kb
Host smart-a29b667f-d07b-473f-8391-b4c9feb72e21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767467350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3767467350
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3157096168
Short name T764
Test name
Test status
Simulation time 61379311 ps
CPU time 6.06 seconds
Started Apr 04 04:05:01 PM PDT 24
Finished Apr 04 04:05:08 PM PDT 24
Peak memory 240060 kb
Host smart-fd76a9c5-2692-4d48-9008-03ef70d33d4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3157096168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3157096168
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1583595857
Short name T746
Test name
Test status
Simulation time 9200517 ps
CPU time 1.48 seconds
Started Apr 04 04:05:05 PM PDT 24
Finished Apr 04 04:05:08 PM PDT 24
Peak memory 234540 kb
Host smart-9ecee76e-6c14-4994-9fa9-35825251080f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1583595857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1583595857
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2078586674
Short name T819
Test name
Test status
Simulation time 1771802459 ps
CPU time 18.32 seconds
Started Apr 04 04:05:02 PM PDT 24
Finished Apr 04 04:05:24 PM PDT 24
Peak memory 244604 kb
Host smart-05eb0c01-0742-495a-ae9f-9e1b2e8b9103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2078586674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2078586674
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.690500473
Short name T143
Test name
Test status
Simulation time 846116226 ps
CPU time 117.79 seconds
Started Apr 04 04:05:03 PM PDT 24
Finished Apr 04 04:07:04 PM PDT 24
Peak memory 264268 kb
Host smart-c92ddb4f-3d67-47c4-ad6c-f6b5427f433e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=690500473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.690500473
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1113494944
Short name T148
Test name
Test status
Simulation time 15391518393 ps
CPU time 1165.66 seconds
Started Apr 04 04:05:05 PM PDT 24
Finished Apr 04 04:24:33 PM PDT 24
Peak memory 265040 kb
Host smart-a4935325-dc48-4667-b6e3-85d2a993a027
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113494944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1113494944
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1328262681
Short name T732
Test name
Test status
Simulation time 209486702 ps
CPU time 7.71 seconds
Started Apr 04 04:05:03 PM PDT 24
Finished Apr 04 04:05:14 PM PDT 24
Peak memory 248168 kb
Host smart-d3212226-dd48-439e-9568-1941fa0cff52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1328262681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1328262681
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1445332315
Short name T778
Test name
Test status
Simulation time 13251792 ps
CPU time 1.24 seconds
Started Apr 04 04:06:12 PM PDT 24
Finished Apr 04 04:06:14 PM PDT 24
Peak memory 234536 kb
Host smart-6d5d6986-2607-41d2-8505-e35ba8b7cb70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1445332315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1445332315
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2775996927
Short name T356
Test name
Test status
Simulation time 7751023 ps
CPU time 1.4 seconds
Started Apr 04 04:06:10 PM PDT 24
Finished Apr 04 04:06:12 PM PDT 24
Peak memory 234532 kb
Host smart-4a15c6f6-720e-4fb3-a28f-4a027b51ee2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2775996927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2775996927
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1442431053
Short name T354
Test name
Test status
Simulation time 6466204 ps
CPU time 1.53 seconds
Started Apr 04 04:06:13 PM PDT 24
Finished Apr 04 04:06:14 PM PDT 24
Peak memory 236420 kb
Host smart-8a18b73d-fd14-4ac6-bff5-fb00a0fe8b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1442431053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1442431053
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1232759404
Short name T718
Test name
Test status
Simulation time 7375717 ps
CPU time 1.4 seconds
Started Apr 04 04:06:11 PM PDT 24
Finished Apr 04 04:06:13 PM PDT 24
Peak memory 236408 kb
Host smart-34c7af22-8b79-43b5-8719-63600bc68b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1232759404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1232759404
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.4145263747
Short name T789
Test name
Test status
Simulation time 11708978 ps
CPU time 1.42 seconds
Started Apr 04 04:06:13 PM PDT 24
Finished Apr 04 04:06:14 PM PDT 24
Peak memory 234500 kb
Host smart-22f75e56-a702-463a-80ee-1299d0353435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4145263747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.4145263747
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1668244086
Short name T748
Test name
Test status
Simulation time 22098754 ps
CPU time 1.3 seconds
Started Apr 04 04:06:29 PM PDT 24
Finished Apr 04 04:06:30 PM PDT 24
Peak memory 236392 kb
Host smart-0cac75d0-0880-43e9-b93a-f0a4d3b0259a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1668244086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1668244086
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.4117802792
Short name T735
Test name
Test status
Simulation time 10856739 ps
CPU time 1.28 seconds
Started Apr 04 04:06:30 PM PDT 24
Finished Apr 04 04:06:31 PM PDT 24
Peak memory 236344 kb
Host smart-d2276884-ddc7-4d00-a479-49f296b18e1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4117802792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.4117802792
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1483410862
Short name T786
Test name
Test status
Simulation time 9320396 ps
CPU time 1.39 seconds
Started Apr 04 04:06:26 PM PDT 24
Finished Apr 04 04:06:28 PM PDT 24
Peak memory 234460 kb
Host smart-d0af4c92-24fd-495e-8a98-ade6b421cde1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1483410862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1483410862
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3756622748
Short name T359
Test name
Test status
Simulation time 10730924 ps
CPU time 1.39 seconds
Started Apr 04 04:06:28 PM PDT 24
Finished Apr 04 04:06:30 PM PDT 24
Peak memory 234488 kb
Host smart-55f3702a-64cd-4561-9911-e4472aead68b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3756622748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3756622748
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3061448543
Short name T157
Test name
Test status
Simulation time 8769127 ps
CPU time 1.64 seconds
Started Apr 04 04:06:29 PM PDT 24
Finished Apr 04 04:06:31 PM PDT 24
Peak memory 236420 kb
Host smart-a97121a9-adcf-479c-84b1-6cfa1a76b972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3061448543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3061448543
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1077014667
Short name T770
Test name
Test status
Simulation time 4271336454 ps
CPU time 168.69 seconds
Started Apr 04 04:05:03 PM PDT 24
Finished Apr 04 04:07:55 PM PDT 24
Peak memory 236492 kb
Host smart-94c9d26e-0a15-4631-bff7-6007bca44ac5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1077014667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1077014667
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.458253327
Short name T776
Test name
Test status
Simulation time 3335098762 ps
CPU time 254.16 seconds
Started Apr 04 04:05:03 PM PDT 24
Finished Apr 04 04:09:21 PM PDT 24
Peak memory 236528 kb
Host smart-8fd1ef6b-2e7b-47c7-8376-8efed94ae129
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=458253327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.458253327
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3631855990
Short name T801
Test name
Test status
Simulation time 607674191 ps
CPU time 6.51 seconds
Started Apr 04 04:05:03 PM PDT 24
Finished Apr 04 04:05:13 PM PDT 24
Peak memory 240044 kb
Host smart-b79fa137-571a-425e-9b21-d4f011361c3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3631855990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3631855990
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2135004028
Short name T788
Test name
Test status
Simulation time 76668006 ps
CPU time 6.32 seconds
Started Apr 04 04:05:02 PM PDT 24
Finished Apr 04 04:05:13 PM PDT 24
Peak memory 238756 kb
Host smart-019583f3-1a38-4528-9b6f-52472158dfd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135004028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2135004028
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.546226034
Short name T798
Test name
Test status
Simulation time 256400711 ps
CPU time 9.37 seconds
Started Apr 04 04:05:02 PM PDT 24
Finished Apr 04 04:05:16 PM PDT 24
Peak memory 236352 kb
Host smart-96be3822-fc0d-40ba-9723-f88e098d50c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=546226034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.546226034
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.322584714
Short name T817
Test name
Test status
Simulation time 8215299 ps
CPU time 1.43 seconds
Started Apr 04 04:05:02 PM PDT 24
Finished Apr 04 04:05:08 PM PDT 24
Peak memory 235516 kb
Host smart-fdef8a8e-8fb3-47da-964e-40e1a7b746b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=322584714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.322584714
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2798837468
Short name T741
Test name
Test status
Simulation time 193362263 ps
CPU time 19.72 seconds
Started Apr 04 04:05:03 PM PDT 24
Finished Apr 04 04:05:26 PM PDT 24
Peak memory 243672 kb
Host smart-ba40fe4e-19cc-407f-97b2-03c893de6ee3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2798837468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2798837468
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1162795833
Short name T125
Test name
Test status
Simulation time 2855220405 ps
CPU time 209.69 seconds
Started Apr 04 04:05:05 PM PDT 24
Finished Apr 04 04:08:36 PM PDT 24
Peak memory 256800 kb
Host smart-f329566b-fd1a-41a8-905a-ca894d832fee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1162795833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1162795833
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1905301285
Short name T150
Test name
Test status
Simulation time 4707217640 ps
CPU time 307.66 seconds
Started Apr 04 04:05:02 PM PDT 24
Finished Apr 04 04:10:14 PM PDT 24
Peak memory 265124 kb
Host smart-8cc159e8-8e73-4545-b1a2-368180de7e92
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905301285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1905301285
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1077209804
Short name T753
Test name
Test status
Simulation time 280182721 ps
CPU time 20.01 seconds
Started Apr 04 04:05:02 PM PDT 24
Finished Apr 04 04:05:26 PM PDT 24
Peak memory 254340 kb
Host smart-6a7dedd5-0d68-4a4c-b75e-a7f2256a6c00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1077209804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1077209804
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.4183974547
Short name T771
Test name
Test status
Simulation time 6889831 ps
CPU time 1.41 seconds
Started Apr 04 04:06:29 PM PDT 24
Finished Apr 04 04:06:30 PM PDT 24
Peak memory 236420 kb
Host smart-e15aea2a-7096-45d8-ab2e-59d980427fae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4183974547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.4183974547
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2065663694
Short name T716
Test name
Test status
Simulation time 24690673 ps
CPU time 1.45 seconds
Started Apr 04 04:06:29 PM PDT 24
Finished Apr 04 04:06:31 PM PDT 24
Peak memory 236392 kb
Host smart-be9dad13-dac1-476c-aa50-6b02d08b03ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2065663694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2065663694
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1935974645
Short name T738
Test name
Test status
Simulation time 6417171 ps
CPU time 1.46 seconds
Started Apr 04 04:06:31 PM PDT 24
Finished Apr 04 04:06:33 PM PDT 24
Peak memory 235468 kb
Host smart-bca76bf7-28d8-4712-8b94-0e959b8f394f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1935974645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1935974645
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3614682594
Short name T772
Test name
Test status
Simulation time 13552524 ps
CPU time 1.34 seconds
Started Apr 04 04:06:32 PM PDT 24
Finished Apr 04 04:06:34 PM PDT 24
Peak memory 234448 kb
Host smart-e0add968-64e3-4f77-a4fd-7582c6019731
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3614682594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3614682594
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.593894455
Short name T357
Test name
Test status
Simulation time 41664359 ps
CPU time 1.5 seconds
Started Apr 04 04:06:28 PM PDT 24
Finished Apr 04 04:06:30 PM PDT 24
Peak memory 236400 kb
Host smart-18b49a7c-ac73-4d5d-b49a-ae77390c5a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=593894455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.593894455
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3673092436
Short name T756
Test name
Test status
Simulation time 9875197 ps
CPU time 1.7 seconds
Started Apr 04 04:06:31 PM PDT 24
Finished Apr 04 04:06:33 PM PDT 24
Peak memory 236424 kb
Host smart-d17d25d7-9739-446b-aa15-e42b5a71bb42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3673092436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3673092436
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1429327688
Short name T763
Test name
Test status
Simulation time 14265335 ps
CPU time 1.73 seconds
Started Apr 04 04:06:28 PM PDT 24
Finished Apr 04 04:06:29 PM PDT 24
Peak memory 234568 kb
Host smart-a8b1d518-8d29-4124-8ffe-3604b1fc485e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1429327688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1429327688
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3685233637
Short name T719
Test name
Test status
Simulation time 7438042 ps
CPU time 1.48 seconds
Started Apr 04 04:06:27 PM PDT 24
Finished Apr 04 04:06:29 PM PDT 24
Peak memory 234508 kb
Host smart-3c2effeb-1ae9-447a-b6c7-abb3e3555b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3685233637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3685233637
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3527443453
Short name T355
Test name
Test status
Simulation time 31590730 ps
CPU time 1.4 seconds
Started Apr 04 04:06:28 PM PDT 24
Finished Apr 04 04:06:30 PM PDT 24
Peak memory 236372 kb
Host smart-a34bf267-18a4-4d4b-9ec1-5e14a6cf247a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3527443453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3527443453
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2877932100
Short name T749
Test name
Test status
Simulation time 63920596 ps
CPU time 9.63 seconds
Started Apr 04 04:05:21 PM PDT 24
Finished Apr 04 04:05:31 PM PDT 24
Peak memory 256268 kb
Host smart-b306474a-d213-4e50-955b-9bac4ed7bd71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877932100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2877932100
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.667004547
Short name T818
Test name
Test status
Simulation time 725979233 ps
CPU time 7.71 seconds
Started Apr 04 04:05:20 PM PDT 24
Finished Apr 04 04:05:28 PM PDT 24
Peak memory 236324 kb
Host smart-6da88abe-86bb-4d1a-bb8a-ef0160d65aa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=667004547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.667004547
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1698734285
Short name T747
Test name
Test status
Simulation time 9566786 ps
CPU time 1.48 seconds
Started Apr 04 04:05:21 PM PDT 24
Finished Apr 04 04:05:22 PM PDT 24
Peak memory 235532 kb
Host smart-7b992c21-393a-4efe-9289-de7136eb4be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1698734285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1698734285
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.946852250
Short name T781
Test name
Test status
Simulation time 1061921786 ps
CPU time 35.46 seconds
Started Apr 04 04:05:18 PM PDT 24
Finished Apr 04 04:05:54 PM PDT 24
Peak memory 244588 kb
Host smart-178edbfa-d955-4d1b-a371-537ce45ad12c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=946852250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.946852250
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.893056349
Short name T821
Test name
Test status
Simulation time 715668602 ps
CPU time 18.52 seconds
Started Apr 04 04:05:03 PM PDT 24
Finished Apr 04 04:05:25 PM PDT 24
Peak memory 248344 kb
Host smart-697f3bd1-9389-4dcd-864f-3675ed86eb7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=893056349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.893056349
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2296192778
Short name T826
Test name
Test status
Simulation time 857947572 ps
CPU time 9.81 seconds
Started Apr 04 04:05:19 PM PDT 24
Finished Apr 04 04:05:30 PM PDT 24
Peak memory 240120 kb
Host smart-6c6c21b5-7a55-4f95-9e93-9051608cbac6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296192778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2296192778
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.709537427
Short name T194
Test name
Test status
Simulation time 20572546 ps
CPU time 4.04 seconds
Started Apr 04 04:05:19 PM PDT 24
Finished Apr 04 04:05:23 PM PDT 24
Peak memory 239276 kb
Host smart-fa899b8b-1a4b-42bd-a042-4168c9833ef5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=709537427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.709537427
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2381258144
Short name T790
Test name
Test status
Simulation time 7536394 ps
CPU time 1.52 seconds
Started Apr 04 04:05:23 PM PDT 24
Finished Apr 04 04:05:24 PM PDT 24
Peak memory 235568 kb
Host smart-1628c788-cf72-496a-b58e-7dea09910cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2381258144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2381258144
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3110325756
Short name T782
Test name
Test status
Simulation time 181313884 ps
CPU time 13.33 seconds
Started Apr 04 04:05:20 PM PDT 24
Finished Apr 04 04:05:34 PM PDT 24
Peak memory 244596 kb
Host smart-73c72221-116d-4b15-9eb8-30147997fa32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3110325756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3110325756
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1641807992
Short name T247
Test name
Test status
Simulation time 321799029 ps
CPU time 19.81 seconds
Started Apr 04 04:05:20 PM PDT 24
Finished Apr 04 04:05:40 PM PDT 24
Peak memory 247448 kb
Host smart-4757edfb-5e93-4d5f-9c71-5148ec845f15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1641807992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1641807992
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3210666272
Short name T806
Test name
Test status
Simulation time 128100567 ps
CPU time 9.85 seconds
Started Apr 04 04:05:22 PM PDT 24
Finished Apr 04 04:05:32 PM PDT 24
Peak memory 250360 kb
Host smart-c7fdb09e-5e01-45e0-b539-701dd73a94bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210666272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3210666272
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2402777528
Short name T363
Test name
Test status
Simulation time 182861345 ps
CPU time 9.42 seconds
Started Apr 04 04:05:22 PM PDT 24
Finished Apr 04 04:05:32 PM PDT 24
Peak memory 235496 kb
Host smart-dd982414-e591-4693-8c1b-3be5c6360e32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2402777528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2402777528
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3324940737
Short name T360
Test name
Test status
Simulation time 16938843 ps
CPU time 1.44 seconds
Started Apr 04 04:05:21 PM PDT 24
Finished Apr 04 04:05:23 PM PDT 24
Peak memory 236292 kb
Host smart-40d6a363-a61d-4eb2-b917-a2b4aecc4670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3324940737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3324940737
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2570498072
Short name T196
Test name
Test status
Simulation time 321682078 ps
CPU time 20.06 seconds
Started Apr 04 04:05:21 PM PDT 24
Finished Apr 04 04:05:42 PM PDT 24
Peak memory 243776 kb
Host smart-0a79fe65-93e5-4c26-a1d9-a02020cba19f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2570498072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2570498072
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3327577974
Short name T118
Test name
Test status
Simulation time 1927289995 ps
CPU time 214.27 seconds
Started Apr 04 04:05:20 PM PDT 24
Finished Apr 04 04:08:54 PM PDT 24
Peak memory 264964 kb
Host smart-33adc515-5b5b-4bf3-a616-084b0c4e6c82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3327577974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3327577974
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1602455022
Short name T367
Test name
Test status
Simulation time 34106869432 ps
CPU time 1236.45 seconds
Started Apr 04 04:05:20 PM PDT 24
Finished Apr 04 04:25:57 PM PDT 24
Peak memory 265076 kb
Host smart-0ac5ff88-7841-4c1b-9d06-2b6004e2685b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602455022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1602455022
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.522683229
Short name T715
Test name
Test status
Simulation time 183086207 ps
CPU time 16.78 seconds
Started Apr 04 04:05:20 PM PDT 24
Finished Apr 04 04:05:37 PM PDT 24
Peak memory 255112 kb
Host smart-69a25f53-33f0-4e6c-a922-98bf78612c83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=522683229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.522683229
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1907170976
Short name T171
Test name
Test status
Simulation time 133274824 ps
CPU time 9.9 seconds
Started Apr 04 04:05:22 PM PDT 24
Finished Apr 04 04:05:32 PM PDT 24
Peak memory 239380 kb
Host smart-965757b8-c3a1-4bfb-b578-400b60def079
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907170976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1907170976
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3115836707
Short name T750
Test name
Test status
Simulation time 136171049 ps
CPU time 5.48 seconds
Started Apr 04 04:05:20 PM PDT 24
Finished Apr 04 04:05:26 PM PDT 24
Peak memory 240016 kb
Host smart-8096834b-f355-40ec-9293-0002d3d1d9ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3115836707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3115836707
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2176437848
Short name T731
Test name
Test status
Simulation time 15968331 ps
CPU time 1.59 seconds
Started Apr 04 04:05:22 PM PDT 24
Finished Apr 04 04:05:24 PM PDT 24
Peak memory 235560 kb
Host smart-e2de5dc6-695f-4400-971a-442e5c930db3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2176437848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2176437848
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.170379779
Short name T791
Test name
Test status
Simulation time 668052580 ps
CPU time 26.95 seconds
Started Apr 04 04:05:20 PM PDT 24
Finished Apr 04 04:05:47 PM PDT 24
Peak memory 248188 kb
Host smart-48918b11-c3fc-49b6-9144-8bd62369f2fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=170379779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.170379779
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2310347775
Short name T134
Test name
Test status
Simulation time 15699442388 ps
CPU time 320.52 seconds
Started Apr 04 04:05:21 PM PDT 24
Finished Apr 04 04:10:42 PM PDT 24
Peak memory 265180 kb
Host smart-40e34aef-4eba-4df2-8e2a-248c93ec3432
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310347775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2310347775
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1901790668
Short name T813
Test name
Test status
Simulation time 386458116 ps
CPU time 6.38 seconds
Started Apr 04 04:05:19 PM PDT 24
Finished Apr 04 04:05:25 PM PDT 24
Peak memory 248348 kb
Host smart-229365d3-0907-4138-b760-f3e5466c562d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1901790668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1901790668
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.314316864
Short name T361
Test name
Test status
Simulation time 69570440 ps
CPU time 8.37 seconds
Started Apr 04 04:05:35 PM PDT 24
Finished Apr 04 04:05:44 PM PDT 24
Peak memory 256452 kb
Host smart-70716e4b-813a-4921-bd3e-489aacedb88a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314316864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.314316864
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3564158845
Short name T729
Test name
Test status
Simulation time 234265621 ps
CPU time 5.38 seconds
Started Apr 04 04:05:36 PM PDT 24
Finished Apr 04 04:05:42 PM PDT 24
Peak memory 240012 kb
Host smart-b978a179-3f48-414c-ac1d-c1f2ce96aa23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3564158845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3564158845
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3939358069
Short name T726
Test name
Test status
Simulation time 8606568 ps
CPU time 1.61 seconds
Started Apr 04 04:05:39 PM PDT 24
Finished Apr 04 04:05:40 PM PDT 24
Peak memory 236428 kb
Host smart-f38dd74d-b330-4ddb-947c-50f8edcac7fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3939358069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3939358069
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3975759496
Short name T762
Test name
Test status
Simulation time 262602869 ps
CPU time 19.51 seconds
Started Apr 04 04:05:37 PM PDT 24
Finished Apr 04 04:05:57 PM PDT 24
Peak memory 244604 kb
Host smart-accfb9a9-a939-40f8-9aa7-3cd3c087460f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3975759496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3975759496
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1538119531
Short name T151
Test name
Test status
Simulation time 1775352915 ps
CPU time 206.14 seconds
Started Apr 04 04:05:20 PM PDT 24
Finished Apr 04 04:08:46 PM PDT 24
Peak memory 270216 kb
Host smart-22c41359-ac3a-4f96-9004-5072383c36d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1538119531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1538119531
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3396143774
Short name T116
Test name
Test status
Simulation time 24111026318 ps
CPU time 1101.91 seconds
Started Apr 04 04:05:21 PM PDT 24
Finished Apr 04 04:23:44 PM PDT 24
Peak memory 265144 kb
Host smart-7b68a0b4-2183-47d2-922e-8b741f7fee62
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396143774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3396143774
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1801452072
Short name T810
Test name
Test status
Simulation time 580401531 ps
CPU time 9.12 seconds
Started Apr 04 04:05:21 PM PDT 24
Finished Apr 04 04:05:30 PM PDT 24
Peak memory 252956 kb
Host smart-65e6e9c3-a55b-434d-b5e5-654989d2a22e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1801452072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1801452072
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1187686849
Short name T432
Test name
Test status
Simulation time 86547885827 ps
CPU time 1775.67 seconds
Started Apr 04 03:13:43 PM PDT 24
Finished Apr 04 03:43:20 PM PDT 24
Peak memory 273668 kb
Host smart-b1951f27-67bd-4be6-b667-5ca5d8828b4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187686849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1187686849
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.701058203
Short name T230
Test name
Test status
Simulation time 2082709891 ps
CPU time 9.88 seconds
Started Apr 04 03:13:44 PM PDT 24
Finished Apr 04 03:13:54 PM PDT 24
Peak memory 240816 kb
Host smart-371a81df-1c49-4394-b80f-2f7e39b89911
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=701058203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.701058203
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3570168271
Short name T582
Test name
Test status
Simulation time 969404803 ps
CPU time 88.04 seconds
Started Apr 04 03:13:44 PM PDT 24
Finished Apr 04 03:15:13 PM PDT 24
Peak memory 256844 kb
Host smart-0e95f5bc-7d1c-4da0-a3af-74362f1bb997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35701
68271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3570168271
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1167428961
Short name T406
Test name
Test status
Simulation time 3223951509 ps
CPU time 49.38 seconds
Started Apr 04 03:13:44 PM PDT 24
Finished Apr 04 03:14:35 PM PDT 24
Peak memory 255808 kb
Host smart-a6ce00be-2ff6-4f0e-8a28-631318a6d3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11674
28961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1167428961
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3427044855
Short name T623
Test name
Test status
Simulation time 52738582939 ps
CPU time 2915.32 seconds
Started Apr 04 03:13:40 PM PDT 24
Finished Apr 04 04:02:16 PM PDT 24
Peak memory 281484 kb
Host smart-ffe24a22-1fcf-42cb-818a-021edebcf92f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427044855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3427044855
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3255633162
Short name T465
Test name
Test status
Simulation time 215869275429 ps
CPU time 1044.58 seconds
Started Apr 04 03:13:42 PM PDT 24
Finished Apr 04 03:31:07 PM PDT 24
Peak memory 272692 kb
Host smart-c9b01e02-230f-4ec5-b78f-3459a9fa4425
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255633162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3255633162
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2395594456
Short name T336
Test name
Test status
Simulation time 18173535196 ps
CPU time 210.72 seconds
Started Apr 04 03:13:39 PM PDT 24
Finished Apr 04 03:17:10 PM PDT 24
Peak memory 248216 kb
Host smart-235962d7-9192-4f0e-9ce9-93f816767f66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395594456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2395594456
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.285675654
Short name T6
Test name
Test status
Simulation time 80839400 ps
CPU time 7.8 seconds
Started Apr 04 03:13:43 PM PDT 24
Finished Apr 04 03:13:51 PM PDT 24
Peak memory 254428 kb
Host smart-247113b2-bbe1-46ac-967e-646fa89df044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28567
5654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.285675654
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2838447995
Short name T569
Test name
Test status
Simulation time 1142914367 ps
CPU time 19.15 seconds
Started Apr 04 03:13:41 PM PDT 24
Finished Apr 04 03:14:01 PM PDT 24
Peak memory 254516 kb
Host smart-afe49884-0cc3-4eab-9574-340aca6f5ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28384
47995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2838447995
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2284014136
Short name T627
Test name
Test status
Simulation time 1360142910 ps
CPU time 41.66 seconds
Started Apr 04 03:13:42 PM PDT 24
Finished Apr 04 03:14:25 PM PDT 24
Peak memory 248996 kb
Host smart-bf460666-d98a-49d4-943e-851214a82577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22840
14136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2284014136
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2128693502
Short name T504
Test name
Test status
Simulation time 56039795 ps
CPU time 4.23 seconds
Started Apr 04 03:13:44 PM PDT 24
Finished Apr 04 03:13:49 PM PDT 24
Peak memory 240904 kb
Host smart-3bb46d68-378a-4092-9d40-3f37089f182b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21286
93502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2128693502
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.4000333916
Short name T635
Test name
Test status
Simulation time 31377598549 ps
CPU time 1960.76 seconds
Started Apr 04 03:13:44 PM PDT 24
Finished Apr 04 03:46:26 PM PDT 24
Peak memory 273736 kb
Host smart-10c8da8d-c579-46d9-8a31-f15f8fad9f6d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000333916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.4000333916
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.421908400
Short name T430
Test name
Test status
Simulation time 33089388835 ps
CPU time 1853.8 seconds
Started Apr 04 03:13:38 PM PDT 24
Finished Apr 04 03:44:32 PM PDT 24
Peak memory 285044 kb
Host smart-82bf29e6-03de-48f8-ad85-7071861826c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421908400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.421908400
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.771994500
Short name T613
Test name
Test status
Simulation time 254532454 ps
CPU time 14.59 seconds
Started Apr 04 03:13:46 PM PDT 24
Finished Apr 04 03:14:01 PM PDT 24
Peak memory 249048 kb
Host smart-c4ffc751-0a3b-4435-b1cb-cee832d760d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=771994500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.771994500
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1537675626
Short name T228
Test name
Test status
Simulation time 1408020653 ps
CPU time 85.09 seconds
Started Apr 04 03:13:44 PM PDT 24
Finished Apr 04 03:15:10 PM PDT 24
Peak memory 248884 kb
Host smart-7ad03fab-2983-439d-81a0-86ce7e42dfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15376
75626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1537675626
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.24498987
Short name T514
Test name
Test status
Simulation time 280284579 ps
CPU time 11.25 seconds
Started Apr 04 03:13:44 PM PDT 24
Finished Apr 04 03:13:56 PM PDT 24
Peak memory 248476 kb
Host smart-42b56bfc-2dc1-4d39-b586-0f0720865c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24498
987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.24498987
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2314309350
Short name T296
Test name
Test status
Simulation time 67733944354 ps
CPU time 1808.7 seconds
Started Apr 04 03:13:46 PM PDT 24
Finished Apr 04 03:43:55 PM PDT 24
Peak memory 273740 kb
Host smart-b2ba9cd3-c1ba-44d0-af63-010489656ff6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314309350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2314309350
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1232745617
Short name T590
Test name
Test status
Simulation time 3542261488 ps
CPU time 52.95 seconds
Started Apr 04 03:13:44 PM PDT 24
Finished Apr 04 03:14:38 PM PDT 24
Peak memory 248312 kb
Host smart-5cd4e683-e84c-4bae-9c3b-088fa44e52c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12327
45617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1232745617
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1463751584
Short name T576
Test name
Test status
Simulation time 4738042948 ps
CPU time 31.84 seconds
Started Apr 04 03:13:40 PM PDT 24
Finished Apr 04 03:14:12 PM PDT 24
Peak memory 257040 kb
Host smart-66d51b45-14f9-4ec1-ab9e-042eebf6a2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14637
51584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1463751584
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1745238042
Short name T33
Test name
Test status
Simulation time 450642346 ps
CPU time 13.66 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:14:06 PM PDT 24
Peak memory 270600 kb
Host smart-399beea1-ba3f-4901-aff9-07b17506968f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1745238042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1745238042
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2981132677
Short name T711
Test name
Test status
Simulation time 254977938 ps
CPU time 27.74 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:14:19 PM PDT 24
Peak memory 255192 kb
Host smart-a15806a4-9135-422d-9b9a-484613aab0bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29811
32677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2981132677
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3005837829
Short name T403
Test name
Test status
Simulation time 282127578 ps
CPU time 9.54 seconds
Started Apr 04 03:13:42 PM PDT 24
Finished Apr 04 03:13:52 PM PDT 24
Peak memory 249064 kb
Host smart-9b083edc-35d2-406a-9f1e-1b5ab8555a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30058
37829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3005837829
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3415985224
Short name T287
Test name
Test status
Simulation time 3606970568 ps
CPU time 189.61 seconds
Started Apr 04 03:13:45 PM PDT 24
Finished Apr 04 03:16:55 PM PDT 24
Peak memory 257256 kb
Host smart-43a927ce-10cc-4bcb-abe8-2af990248b9a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415985224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3415985224
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3235948516
Short name T421
Test name
Test status
Simulation time 450735602 ps
CPU time 12.47 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:24 PM PDT 24
Peak memory 248768 kb
Host smart-35281b09-8902-4cad-ae03-f94506ad911f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3235948516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3235948516
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.195922492
Short name T438
Test name
Test status
Simulation time 3120542327 ps
CPU time 164.23 seconds
Started Apr 04 03:14:10 PM PDT 24
Finished Apr 04 03:16:54 PM PDT 24
Peak memory 250156 kb
Host smart-71ddb511-bf64-403e-9d6b-74ed2e7f52c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19592
2492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.195922492
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1020678280
Short name T239
Test name
Test status
Simulation time 756602874 ps
CPU time 14.87 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:26 PM PDT 24
Peak memory 252340 kb
Host smart-bf1ed5cc-2e3f-4584-a48d-49e276a16042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10206
78280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1020678280
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2275887872
Short name T666
Test name
Test status
Simulation time 11970933687 ps
CPU time 841.1 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:28:13 PM PDT 24
Peak memory 273680 kb
Host smart-38df270f-0463-4a32-b9e4-b9aac3b52b17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275887872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2275887872
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1245511818
Short name T688
Test name
Test status
Simulation time 7836327752 ps
CPU time 670.04 seconds
Started Apr 04 03:14:00 PM PDT 24
Finished Apr 04 03:25:11 PM PDT 24
Peak memory 265628 kb
Host smart-f0c476ce-5429-4c30-b819-6f80d01f22f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245511818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1245511818
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1251868586
Short name T311
Test name
Test status
Simulation time 8024392085 ps
CPU time 174.04 seconds
Started Apr 04 03:14:00 PM PDT 24
Finished Apr 04 03:16:54 PM PDT 24
Peak memory 248292 kb
Host smart-2d0878e2-ee33-4e20-979e-6e2d28bec1ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251868586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1251868586
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1431784450
Short name T293
Test name
Test status
Simulation time 3149430142 ps
CPU time 39.91 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:51 PM PDT 24
Peak memory 256296 kb
Host smart-22299783-8eb3-4266-b91c-07006f503047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14317
84450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1431784450
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.996436009
Short name T629
Test name
Test status
Simulation time 1774530500 ps
CPU time 79.43 seconds
Started Apr 04 03:14:10 PM PDT 24
Finished Apr 04 03:15:30 PM PDT 24
Peak memory 255632 kb
Host smart-8f492bb7-0ecd-4e9d-9815-ebe7eae78b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99643
6009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.996436009
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.272054619
Short name T475
Test name
Test status
Simulation time 7646173113 ps
CPU time 57.73 seconds
Started Apr 04 03:14:05 PM PDT 24
Finished Apr 04 03:15:03 PM PDT 24
Peak memory 248972 kb
Host smart-0adf94bd-54ca-4802-8a02-c89434e4260c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27205
4619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.272054619
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3924961269
Short name T231
Test name
Test status
Simulation time 2573340792 ps
CPU time 37.12 seconds
Started Apr 04 03:13:59 PM PDT 24
Finished Apr 04 03:14:36 PM PDT 24
Peak memory 256336 kb
Host smart-e1fb9dad-3ccd-4960-b684-58e22685df2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39249
61269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3924961269
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2812586020
Short name T213
Test name
Test status
Simulation time 107777691 ps
CPU time 4.59 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 03:14:02 PM PDT 24
Peak memory 249260 kb
Host smart-e016805c-f220-4a82-8d13-e14ef80aaf71
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2812586020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2812586020
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.355886611
Short name T536
Test name
Test status
Simulation time 9511279775 ps
CPU time 921.51 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 03:29:19 PM PDT 24
Peak memory 288876 kb
Host smart-bc9ffa98-b227-4306-8e7c-64f9cc738869
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355886611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.355886611
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1770331868
Short name T541
Test name
Test status
Simulation time 2204097757 ps
CPU time 14.37 seconds
Started Apr 04 03:13:58 PM PDT 24
Finished Apr 04 03:14:12 PM PDT 24
Peak memory 240884 kb
Host smart-f15cbf14-8ded-4276-ae98-a6016579cf14
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1770331868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1770331868
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2452608252
Short name T371
Test name
Test status
Simulation time 2440563309 ps
CPU time 37.64 seconds
Started Apr 04 03:14:00 PM PDT 24
Finished Apr 04 03:14:38 PM PDT 24
Peak memory 257088 kb
Host smart-305ae35a-326e-49a5-a236-eb40f96ea1b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24526
08252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2452608252
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.629297493
Short name T70
Test name
Test status
Simulation time 45674675 ps
CPU time 6.73 seconds
Started Apr 04 03:14:05 PM PDT 24
Finished Apr 04 03:14:12 PM PDT 24
Peak memory 240700 kb
Host smart-a6c7f0dc-7b6a-4dca-b2b6-3022fd4a64b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62929
7493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.629297493
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.666781993
Short name T352
Test name
Test status
Simulation time 11544738808 ps
CPU time 1007.82 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 03:30:45 PM PDT 24
Peak memory 267608 kb
Host smart-863c46bd-405d-4c1a-abe1-892dd1f9ae9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666781993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.666781993
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2751450125
Short name T385
Test name
Test status
Simulation time 295092838134 ps
CPU time 3217.39 seconds
Started Apr 04 03:13:58 PM PDT 24
Finished Apr 04 04:07:36 PM PDT 24
Peak memory 281940 kb
Host smart-6f14c62b-3101-4787-afb3-08fd1f8bac83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751450125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2751450125
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3617756975
Short name T544
Test name
Test status
Simulation time 470916606 ps
CPU time 28.17 seconds
Started Apr 04 03:14:09 PM PDT 24
Finished Apr 04 03:14:37 PM PDT 24
Peak memory 249036 kb
Host smart-1dc1c0cc-684c-4483-be9e-639d12c13932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36177
56975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3617756975
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2316527946
Short name T457
Test name
Test status
Simulation time 1843980321 ps
CPU time 24.88 seconds
Started Apr 04 03:13:56 PM PDT 24
Finished Apr 04 03:14:21 PM PDT 24
Peak memory 254864 kb
Host smart-090d0759-9bb2-4358-a20e-a7923e1b1f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23165
27946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2316527946
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3152189119
Short name T466
Test name
Test status
Simulation time 449548516 ps
CPU time 14.68 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:26 PM PDT 24
Peak memory 249032 kb
Host smart-9809cca4-707a-4a9d-a368-b397a02509e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31521
89119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3152189119
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1419415230
Short name T622
Test name
Test status
Simulation time 64006009879 ps
CPU time 1973.4 seconds
Started Apr 04 03:13:59 PM PDT 24
Finished Apr 04 03:46:53 PM PDT 24
Peak memory 273736 kb
Host smart-94a53f6b-1529-4f54-80ab-5d4a8f18ee14
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419415230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1419415230
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3044960872
Short name T199
Test name
Test status
Simulation time 57917632 ps
CPU time 4.05 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:15 PM PDT 24
Peak memory 249316 kb
Host smart-9b9c624b-5441-4f8d-869d-c9ec5cafb893
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3044960872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3044960872
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3746642392
Short name T509
Test name
Test status
Simulation time 209225291695 ps
CPU time 2965.42 seconds
Started Apr 04 03:14:02 PM PDT 24
Finished Apr 04 04:03:28 PM PDT 24
Peak memory 289000 kb
Host smart-6a4ecefb-80fb-4f75-a672-2cda9e4a26a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746642392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3746642392
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.374777310
Short name T677
Test name
Test status
Simulation time 260885032 ps
CPU time 14.59 seconds
Started Apr 04 03:14:13 PM PDT 24
Finished Apr 04 03:14:27 PM PDT 24
Peak memory 240848 kb
Host smart-90614471-ca08-49e8-a9a2-d9e29ab657ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=374777310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.374777310
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2777964924
Short name T538
Test name
Test status
Simulation time 888056191 ps
CPU time 75.22 seconds
Started Apr 04 03:13:58 PM PDT 24
Finished Apr 04 03:15:13 PM PDT 24
Peak memory 256924 kb
Host smart-caabfc15-cea4-4b36-98b0-65e6baea2461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27779
64924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2777964924
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.683903347
Short name T476
Test name
Test status
Simulation time 647819913 ps
CPU time 21.43 seconds
Started Apr 04 03:13:59 PM PDT 24
Finished Apr 04 03:14:21 PM PDT 24
Peak memory 249096 kb
Host smart-92ac7593-b779-4a47-bcf2-96184472e423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68390
3347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.683903347
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3508114653
Short name T351
Test name
Test status
Simulation time 63191825008 ps
CPU time 3404.56 seconds
Started Apr 04 03:14:08 PM PDT 24
Finished Apr 04 04:10:53 PM PDT 24
Peak memory 289408 kb
Host smart-0a3df2df-4e9f-460a-a8bc-b1691f61724f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508114653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3508114653
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2389134725
Short name T667
Test name
Test status
Simulation time 69487705425 ps
CPU time 1270.53 seconds
Started Apr 04 03:14:18 PM PDT 24
Finished Apr 04 03:35:29 PM PDT 24
Peak memory 273608 kb
Host smart-0fff9afc-83cb-4935-a094-b0f2d5cf1d0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389134725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2389134725
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1427002329
Short name T674
Test name
Test status
Simulation time 13072922901 ps
CPU time 123.09 seconds
Started Apr 04 03:13:59 PM PDT 24
Finished Apr 04 03:16:02 PM PDT 24
Peak memory 248076 kb
Host smart-dd4c1ae3-db96-4c14-8920-8781652f193c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427002329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1427002329
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1467154934
Short name T370
Test name
Test status
Simulation time 425511320 ps
CPU time 7.3 seconds
Started Apr 04 03:13:58 PM PDT 24
Finished Apr 04 03:14:05 PM PDT 24
Peak memory 251724 kb
Host smart-3f01f7b6-b220-4785-927d-eebc4b86205b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14671
54934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1467154934
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3424635300
Short name T679
Test name
Test status
Simulation time 1041414570 ps
CPU time 39.66 seconds
Started Apr 04 03:13:59 PM PDT 24
Finished Apr 04 03:14:39 PM PDT 24
Peak memory 255760 kb
Host smart-5095393e-ccc3-4219-b639-ce79bacc747e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34246
35300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3424635300
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1617573110
Short name T556
Test name
Test status
Simulation time 60176301 ps
CPU time 7.72 seconds
Started Apr 04 03:13:59 PM PDT 24
Finished Apr 04 03:14:07 PM PDT 24
Peak memory 248992 kb
Host smart-75034cbc-0225-4a0e-91e6-dd1f1796f2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16175
73110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1617573110
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2073141342
Short name T707
Test name
Test status
Simulation time 4032252349 ps
CPU time 251.84 seconds
Started Apr 04 03:14:12 PM PDT 24
Finished Apr 04 03:18:24 PM PDT 24
Peak memory 257336 kb
Host smart-4d6f8c4b-4225-43fd-9c5d-aca32276bdce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073141342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2073141342
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3401255995
Short name T177
Test name
Test status
Simulation time 38829139652 ps
CPU time 3377.69 seconds
Started Apr 04 03:14:13 PM PDT 24
Finished Apr 04 04:10:31 PM PDT 24
Peak memory 339068 kb
Host smart-fc52dd7e-c570-4871-bfc0-a002ed9caac9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401255995 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3401255995
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2863476688
Short name T210
Test name
Test status
Simulation time 57688993 ps
CPU time 3.87 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:15 PM PDT 24
Peak memory 249288 kb
Host smart-3aecdf35-6630-4297-b728-f8efea9cc8d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2863476688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2863476688
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2730811434
Short name T420
Test name
Test status
Simulation time 140805281844 ps
CPU time 1996.73 seconds
Started Apr 04 03:14:09 PM PDT 24
Finished Apr 04 03:47:27 PM PDT 24
Peak memory 273764 kb
Host smart-f13b68b5-c647-4789-acce-26a83f11b729
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730811434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2730811434
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3353906060
Short name T700
Test name
Test status
Simulation time 1210668570 ps
CPU time 17.07 seconds
Started Apr 04 03:14:12 PM PDT 24
Finished Apr 04 03:14:29 PM PDT 24
Peak memory 249036 kb
Host smart-8f3db538-285f-4b28-98ac-d11fd2027606
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3353906060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3353906060
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3959287344
Short name T621
Test name
Test status
Simulation time 1560895733 ps
CPU time 131.25 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:16:23 PM PDT 24
Peak memory 256900 kb
Host smart-e53de1b5-634a-4a94-8397-71e30b026db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39592
87344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3959287344
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2856648256
Short name T527
Test name
Test status
Simulation time 50544211 ps
CPU time 2.56 seconds
Started Apr 04 03:14:09 PM PDT 24
Finished Apr 04 03:14:11 PM PDT 24
Peak memory 240876 kb
Host smart-b6064e56-fed0-4c42-b082-ad631025e817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28566
48256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2856648256
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.645614315
Short name T280
Test name
Test status
Simulation time 52546767973 ps
CPU time 1476.49 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:38:48 PM PDT 24
Peak memory 265508 kb
Host smart-ae9390a6-bb0f-4f7f-964e-d3f87cd0583b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645614315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.645614315
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3153543029
Short name T523
Test name
Test status
Simulation time 46681468138 ps
CPU time 1142.13 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:33:14 PM PDT 24
Peak memory 284548 kb
Host smart-6b3260f0-4e61-47b9-a149-d628516b4397
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153543029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3153543029
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3507550386
Short name T309
Test name
Test status
Simulation time 12316543358 ps
CPU time 246.06 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:18:17 PM PDT 24
Peak memory 247224 kb
Host smart-6c22935b-f24f-46c7-a100-f954fef615d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507550386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3507550386
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1075551923
Short name T573
Test name
Test status
Simulation time 306069725 ps
CPU time 10.28 seconds
Started Apr 04 03:14:16 PM PDT 24
Finished Apr 04 03:14:27 PM PDT 24
Peak memory 249016 kb
Host smart-16956f7d-f0ba-4356-8aad-807a316ab8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10755
51923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1075551923
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1462594504
Short name T510
Test name
Test status
Simulation time 860358277 ps
CPU time 13.74 seconds
Started Apr 04 03:14:17 PM PDT 24
Finished Apr 04 03:14:30 PM PDT 24
Peak memory 249460 kb
Host smart-a9f227f2-4aac-441e-b0d1-04a19a9d27ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14625
94504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1462594504
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.231404880
Short name T439
Test name
Test status
Simulation time 2135040538 ps
CPU time 45.23 seconds
Started Apr 04 03:14:08 PM PDT 24
Finished Apr 04 03:14:53 PM PDT 24
Peak memory 255604 kb
Host smart-ba2f5fb9-5447-4eb5-ae4e-67c6e8c9681c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23140
4880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.231404880
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3909863613
Short name T546
Test name
Test status
Simulation time 33930840 ps
CPU time 4.68 seconds
Started Apr 04 03:14:10 PM PDT 24
Finished Apr 04 03:14:15 PM PDT 24
Peak memory 240840 kb
Host smart-d920cb99-5890-4951-a00f-d115256f78d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39098
63613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3909863613
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2016863678
Short name T111
Test name
Test status
Simulation time 229160028 ps
CPU time 3.53 seconds
Started Apr 04 03:14:17 PM PDT 24
Finished Apr 04 03:14:20 PM PDT 24
Peak memory 249312 kb
Host smart-8b64afdc-9a03-482c-8e58-a91113110cf4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2016863678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2016863678
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3478243658
Short name T284
Test name
Test status
Simulation time 39803895964 ps
CPU time 777.82 seconds
Started Apr 04 03:14:09 PM PDT 24
Finished Apr 04 03:27:07 PM PDT 24
Peak memory 267572 kb
Host smart-d86e4cae-57e3-4012-ad3c-44f2121c0fcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478243658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3478243658
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1610502948
Short name T221
Test name
Test status
Simulation time 2118662418 ps
CPU time 25.53 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:37 PM PDT 24
Peak memory 252708 kb
Host smart-35390c44-260b-44d5-809f-0e0c83fc5462
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1610502948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1610502948
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.287028561
Short name T678
Test name
Test status
Simulation time 4522246957 ps
CPU time 142.03 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:16:33 PM PDT 24
Peak memory 257356 kb
Host smart-377843d3-5009-4d51-b5f2-d54622bfa022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28702
8561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.287028561
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1132103856
Short name T691
Test name
Test status
Simulation time 228643530 ps
CPU time 21.33 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:33 PM PDT 24
Peak memory 254948 kb
Host smart-9b456252-8863-49bf-b94f-829e677aa181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11321
03856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1132103856
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3324388256
Short name T328
Test name
Test status
Simulation time 507322651875 ps
CPU time 1839.65 seconds
Started Apr 04 03:14:17 PM PDT 24
Finished Apr 04 03:44:57 PM PDT 24
Peak memory 273604 kb
Host smart-7073f79b-a39e-4dcb-a1e1-f3426cebe4d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324388256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3324388256
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.852433306
Short name T64
Test name
Test status
Simulation time 39687466251 ps
CPU time 1264.48 seconds
Started Apr 04 03:14:14 PM PDT 24
Finished Apr 04 03:35:19 PM PDT 24
Peak memory 273692 kb
Host smart-6e961a87-3554-44f3-a905-4dfe1aafe3e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852433306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.852433306
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.469438949
Short name T112
Test name
Test status
Simulation time 2919758272 ps
CPU time 103.1 seconds
Started Apr 04 03:14:08 PM PDT 24
Finished Apr 04 03:15:52 PM PDT 24
Peak memory 248044 kb
Host smart-2af189cb-a362-4f9c-9273-7dabdb450bc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469438949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.469438949
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3841844804
Short name T566
Test name
Test status
Simulation time 184650709 ps
CPU time 17.61 seconds
Started Apr 04 03:14:17 PM PDT 24
Finished Apr 04 03:14:35 PM PDT 24
Peak memory 257216 kb
Host smart-c9c2c77f-0c7c-45c7-87db-795dd7fdb7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38418
44804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3841844804
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1471492550
Short name T409
Test name
Test status
Simulation time 745449018 ps
CPU time 9.34 seconds
Started Apr 04 03:14:13 PM PDT 24
Finished Apr 04 03:14:23 PM PDT 24
Peak memory 253612 kb
Host smart-3ebf10ad-f65d-48d6-8f3c-44d6406667f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14714
92550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1471492550
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2713037934
Short name T668
Test name
Test status
Simulation time 298194228 ps
CPU time 4.22 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:16 PM PDT 24
Peak memory 251152 kb
Host smart-59700fb3-86df-4ea5-9f3b-5ab34aeb586c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27130
37934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2713037934
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1364598590
Short name T561
Test name
Test status
Simulation time 175615974042 ps
CPU time 2138.97 seconds
Started Apr 04 03:14:12 PM PDT 24
Finished Apr 04 03:49:51 PM PDT 24
Peak memory 286224 kb
Host smart-1940a265-8fd5-46ea-ba2b-8623ae287a43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364598590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1364598590
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3901309203
Short name T602
Test name
Test status
Simulation time 777590716 ps
CPU time 34.28 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:46 PM PDT 24
Peak memory 240840 kb
Host smart-0b541207-6645-4477-82e5-7d1d70f918c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3901309203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3901309203
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1396303749
Short name T3
Test name
Test status
Simulation time 23644663776 ps
CPU time 309.33 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:19:20 PM PDT 24
Peak memory 251204 kb
Host smart-2408fa77-9431-4e6f-bddc-67807e8282b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13963
03749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1396303749
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.75605538
Short name T415
Test name
Test status
Simulation time 256150763 ps
CPU time 16 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:27 PM PDT 24
Peak memory 252972 kb
Host smart-8d13924b-81c5-4cf6-a9c0-ba679d4417ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75605
538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.75605538
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3597308522
Short name T487
Test name
Test status
Simulation time 7756937272 ps
CPU time 679.05 seconds
Started Apr 04 03:14:12 PM PDT 24
Finished Apr 04 03:25:31 PM PDT 24
Peak memory 273148 kb
Host smart-ca893f8c-3f7c-4b8b-af28-ccd34cfb4a2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597308522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3597308522
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2018147050
Short name T297
Test name
Test status
Simulation time 18124681865 ps
CPU time 1080.98 seconds
Started Apr 04 03:14:17 PM PDT 24
Finished Apr 04 03:32:18 PM PDT 24
Peak memory 281936 kb
Host smart-91dbf28c-5c0a-4ac5-a97e-726a2998f3fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018147050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2018147050
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3582303178
Short name T12
Test name
Test status
Simulation time 9849998550 ps
CPU time 413.33 seconds
Started Apr 04 03:14:13 PM PDT 24
Finished Apr 04 03:21:07 PM PDT 24
Peak memory 248024 kb
Host smart-9a9adc7a-f598-42c7-85db-ec62d2ec8c61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582303178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3582303178
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.249325603
Short name T532
Test name
Test status
Simulation time 897055576 ps
CPU time 52.53 seconds
Started Apr 04 03:14:14 PM PDT 24
Finished Apr 04 03:15:06 PM PDT 24
Peak memory 249340 kb
Host smart-64fa6ba2-6159-40fe-be12-871d7bd99897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24932
5603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.249325603
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2352731393
Short name T389
Test name
Test status
Simulation time 4584358070 ps
CPU time 41.56 seconds
Started Apr 04 03:14:14 PM PDT 24
Finished Apr 04 03:14:56 PM PDT 24
Peak memory 255724 kb
Host smart-6ee48d18-499d-430a-86bd-9b0f7837d178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23527
31393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2352731393
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1603621992
Short name T1
Test name
Test status
Simulation time 579691591 ps
CPU time 17.55 seconds
Started Apr 04 03:14:12 PM PDT 24
Finished Apr 04 03:14:30 PM PDT 24
Peak memory 247560 kb
Host smart-df471334-eb4b-44b9-8576-43e1477dbe2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16036
21992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1603621992
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2303947319
Short name T545
Test name
Test status
Simulation time 2483706863 ps
CPU time 35.93 seconds
Started Apr 04 03:14:13 PM PDT 24
Finished Apr 04 03:14:49 PM PDT 24
Peak memory 255752 kb
Host smart-0f552f7e-31de-4c71-99aa-4ed3e71e4f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23039
47319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2303947319
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.49927475
Short name T610
Test name
Test status
Simulation time 47490941433 ps
CPU time 2454.62 seconds
Started Apr 04 03:14:10 PM PDT 24
Finished Apr 04 03:55:05 PM PDT 24
Peak memory 287068 kb
Host smart-cc48e324-ab2b-486e-8166-3d9ee94c510e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49927475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_hand
ler_stress_all.49927475
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.4044813472
Short name T212
Test name
Test status
Simulation time 84317685 ps
CPU time 3.28 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:14:29 PM PDT 24
Peak memory 249340 kb
Host smart-070e47cb-164c-4829-923a-b545ec6bf430
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4044813472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.4044813472
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3800226924
Short name T520
Test name
Test status
Simulation time 132578013093 ps
CPU time 2060.36 seconds
Started Apr 04 03:14:26 PM PDT 24
Finished Apr 04 03:48:47 PM PDT 24
Peak memory 289516 kb
Host smart-c9104660-8f1f-4e7f-a8db-1321f1b60397
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800226924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3800226924
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.4069249154
Short name T428
Test name
Test status
Simulation time 1551095859 ps
CPU time 66.32 seconds
Started Apr 04 03:14:21 PM PDT 24
Finished Apr 04 03:15:27 PM PDT 24
Peak memory 249072 kb
Host smart-2440c27e-1dff-42a2-b17a-266395ec1ed2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4069249154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.4069249154
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2309669403
Short name T543
Test name
Test status
Simulation time 2334510498 ps
CPU time 152.81 seconds
Started Apr 04 03:14:24 PM PDT 24
Finished Apr 04 03:16:57 PM PDT 24
Peak memory 257008 kb
Host smart-cea9a792-c47e-40c5-aa60-8a6886aa71c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23096
69403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2309669403
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.201081478
Short name T62
Test name
Test status
Simulation time 459699978 ps
CPU time 14.85 seconds
Started Apr 04 03:14:22 PM PDT 24
Finished Apr 04 03:14:37 PM PDT 24
Peak memory 255092 kb
Host smart-5a3aa6d1-9d0a-484d-ae5b-56b9cc1220d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20108
1478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.201081478
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1299469143
Short name T615
Test name
Test status
Simulation time 92148796311 ps
CPU time 1392.4 seconds
Started Apr 04 03:14:21 PM PDT 24
Finished Apr 04 03:37:34 PM PDT 24
Peak memory 273700 kb
Host smart-ffe85e89-8d12-4922-81bc-163cdb019f3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299469143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1299469143
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2928466422
Short name T533
Test name
Test status
Simulation time 1981266527 ps
CPU time 81.81 seconds
Started Apr 04 03:14:28 PM PDT 24
Finished Apr 04 03:15:50 PM PDT 24
Peak memory 248112 kb
Host smart-ae22b73c-6354-45d3-bcb3-17361453dd15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928466422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2928466422
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2266513131
Short name T562
Test name
Test status
Simulation time 1346327511 ps
CPU time 7.21 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:14:32 PM PDT 24
Peak memory 257288 kb
Host smart-2daf5d37-a14f-4d35-99ac-0a6c566fa16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22665
13131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2266513131
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1209752474
Short name T182
Test name
Test status
Simulation time 380291381 ps
CPU time 23.08 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:14:48 PM PDT 24
Peak memory 255740 kb
Host smart-d0871e1e-5f62-4610-96fe-4491f14b9831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12097
52474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1209752474
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.418234042
Short name T411
Test name
Test status
Simulation time 444224365 ps
CPU time 22.81 seconds
Started Apr 04 03:14:23 PM PDT 24
Finished Apr 04 03:14:46 PM PDT 24
Peak memory 249036 kb
Host smart-52092470-6922-4d15-a4d6-0984573fb32e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41823
4042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.418234042
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2608737857
Short name T393
Test name
Test status
Simulation time 873087254 ps
CPU time 34.83 seconds
Started Apr 04 03:14:17 PM PDT 24
Finished Apr 04 03:14:52 PM PDT 24
Peak memory 257216 kb
Host smart-a912982b-c2d9-4eaf-8a5f-a3b4e0d5d7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26087
37857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2608737857
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.779607994
Short name T488
Test name
Test status
Simulation time 4554451462 ps
CPU time 252.71 seconds
Started Apr 04 03:14:26 PM PDT 24
Finished Apr 04 03:18:39 PM PDT 24
Peak memory 257352 kb
Host smart-eafa78e3-8ee6-454b-81b5-3c5177453209
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779607994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.779607994
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.425577178
Short name T59
Test name
Test status
Simulation time 138855425794 ps
CPU time 6882.36 seconds
Started Apr 04 03:14:28 PM PDT 24
Finished Apr 04 05:09:11 PM PDT 24
Peak memory 387480 kb
Host smart-5cdda2c5-789b-44ae-82c8-df9eac5a2c03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425577178 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.425577178
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2037568206
Short name T205
Test name
Test status
Simulation time 24127642 ps
CPU time 2.56 seconds
Started Apr 04 03:14:28 PM PDT 24
Finished Apr 04 03:14:30 PM PDT 24
Peak memory 249340 kb
Host smart-8f51cd9c-b165-42a8-b614-efdabfeb9d08
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2037568206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2037568206
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.517411924
Short name T227
Test name
Test status
Simulation time 41228884152 ps
CPU time 2417.53 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:54:43 PM PDT 24
Peak memory 281944 kb
Host smart-a89cc076-99a9-4628-9e71-666acc591ede
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517411924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.517411924
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2583621870
Short name T462
Test name
Test status
Simulation time 231472945 ps
CPU time 13.04 seconds
Started Apr 04 03:14:24 PM PDT 24
Finished Apr 04 03:14:37 PM PDT 24
Peak memory 240848 kb
Host smart-037c4b98-c13f-4392-b15b-261a67fea8f9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2583621870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2583621870
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1369754472
Short name T24
Test name
Test status
Simulation time 391455144 ps
CPU time 23.89 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:14:49 PM PDT 24
Peak memory 256156 kb
Host smart-ceb45a33-f997-41a6-b6d6-26393a3d720a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13697
54472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1369754472
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1731916840
Short name T275
Test name
Test status
Simulation time 1123546677 ps
CPU time 45.95 seconds
Started Apr 04 03:14:22 PM PDT 24
Finished Apr 04 03:15:08 PM PDT 24
Peak memory 255608 kb
Host smart-badbe68d-073f-45ba-a236-87ae42cf87b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17319
16840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1731916840
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1956281983
Short name T553
Test name
Test status
Simulation time 15361090201 ps
CPU time 1443.63 seconds
Started Apr 04 03:14:23 PM PDT 24
Finished Apr 04 03:38:27 PM PDT 24
Peak memory 281928 kb
Host smart-594ee8ae-17f4-4fe9-bbe3-01db37467516
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956281983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1956281983
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.698886256
Short name T331
Test name
Test status
Simulation time 10642075097 ps
CPU time 113.01 seconds
Started Apr 04 03:14:28 PM PDT 24
Finished Apr 04 03:16:21 PM PDT 24
Peak memory 255332 kb
Host smart-716e59e9-5785-48d6-918a-a2f79703f485
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698886256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.698886256
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.352337772
Short name T618
Test name
Test status
Simulation time 643716603 ps
CPU time 38.24 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:15:03 PM PDT 24
Peak memory 256164 kb
Host smart-2fcb91b3-6b7f-4173-9c83-9feb04654da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35233
7772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.352337772
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3763583749
Short name T588
Test name
Test status
Simulation time 513603329 ps
CPU time 21.45 seconds
Started Apr 04 03:14:23 PM PDT 24
Finished Apr 04 03:14:45 PM PDT 24
Peak memory 256312 kb
Host smart-ac194d4c-aa94-4998-8541-863a5bae359d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37635
83749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3763583749
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.596029754
Short name T252
Test name
Test status
Simulation time 92129027767 ps
CPU time 734.57 seconds
Started Apr 04 03:14:31 PM PDT 24
Finished Apr 04 03:26:46 PM PDT 24
Peak memory 265552 kb
Host smart-1cf1b1f4-e519-4d55-ab0e-97c837824f18
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596029754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.596029754
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.4048756236
Short name T262
Test name
Test status
Simulation time 274384521840 ps
CPU time 3045.65 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 04:05:11 PM PDT 24
Peak memory 322568 kb
Host smart-466335ef-c6c2-4c54-8bef-82eb0346126c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048756236 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.4048756236
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2842813340
Short name T200
Test name
Test status
Simulation time 34114132 ps
CPU time 3.37 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:14:29 PM PDT 24
Peak memory 249336 kb
Host smart-f431337c-f975-4e0b-9c66-a177bac52a1b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2842813340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2842813340
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3852049116
Short name T91
Test name
Test status
Simulation time 36131292416 ps
CPU time 1743.94 seconds
Started Apr 04 03:14:24 PM PDT 24
Finished Apr 04 03:43:28 PM PDT 24
Peak memory 288628 kb
Host smart-7791507a-df20-4830-b9ed-587d7b714fb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852049116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3852049116
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.4142841472
Short name T377
Test name
Test status
Simulation time 13531243595 ps
CPU time 42.22 seconds
Started Apr 04 03:14:28 PM PDT 24
Finished Apr 04 03:15:10 PM PDT 24
Peak memory 249184 kb
Host smart-d4175418-f2d5-45f8-81cb-a8d0a16086fc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4142841472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.4142841472
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3649108033
Short name T390
Test name
Test status
Simulation time 4326694988 ps
CPU time 78.69 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:15:52 PM PDT 24
Peak memory 248916 kb
Host smart-0158fc2d-58b4-472a-871c-ae245d7e5ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36491
08033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3649108033
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1905365847
Short name T37
Test name
Test status
Simulation time 2306386871 ps
CPU time 41.81 seconds
Started Apr 04 03:14:27 PM PDT 24
Finished Apr 04 03:15:08 PM PDT 24
Peak memory 255816 kb
Host smart-d7308cbc-697e-43f4-8567-2c77dbb517ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19053
65847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1905365847
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1709859814
Short name T289
Test name
Test status
Simulation time 251310937854 ps
CPU time 2609.87 seconds
Started Apr 04 03:14:27 PM PDT 24
Finished Apr 04 03:57:57 PM PDT 24
Peak memory 281864 kb
Host smart-df948ea0-f478-49e3-b088-801e7f66cf6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709859814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1709859814
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3073840405
Short name T300
Test name
Test status
Simulation time 49595788020 ps
CPU time 411.89 seconds
Started Apr 04 03:14:24 PM PDT 24
Finished Apr 04 03:21:16 PM PDT 24
Peak memory 248304 kb
Host smart-eb5c050e-37e2-4a3c-9eec-a85f1d19f43a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073840405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3073840405
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2693317292
Short name T223
Test name
Test status
Simulation time 606587042 ps
CPU time 15.12 seconds
Started Apr 04 03:14:23 PM PDT 24
Finished Apr 04 03:14:38 PM PDT 24
Peak memory 249064 kb
Host smart-805ce377-7785-4044-9f2f-a85b83263dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26933
17292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2693317292
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.714317963
Short name T107
Test name
Test status
Simulation time 215734634 ps
CPU time 23.51 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:14:57 PM PDT 24
Peak memory 255576 kb
Host smart-64963c18-948c-48a0-b34d-79ac32121bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71431
7963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.714317963
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2398511839
Short name T184
Test name
Test status
Simulation time 254169246 ps
CPU time 26.56 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:14:52 PM PDT 24
Peak memory 256052 kb
Host smart-d4fb4734-5353-4e01-90e5-15cec837e39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23985
11839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2398511839
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3986144603
Short name T651
Test name
Test status
Simulation time 330508034 ps
CPU time 14.51 seconds
Started Apr 04 03:14:24 PM PDT 24
Finished Apr 04 03:14:38 PM PDT 24
Peak memory 249012 kb
Host smart-823a19db-0459-47ec-b340-bf02f4a49c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39861
44603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3986144603
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.72569030
Short name T241
Test name
Test status
Simulation time 9661623549 ps
CPU time 881.09 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:29:06 PM PDT 24
Peak memory 273496 kb
Host smart-72229e3a-b22e-4c05-a86b-649cf0c775c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72569030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_hand
ler_stress_all.72569030
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1537646047
Short name T36
Test name
Test status
Simulation time 141343678 ps
CPU time 3.75 seconds
Started Apr 04 03:14:26 PM PDT 24
Finished Apr 04 03:14:30 PM PDT 24
Peak memory 249240 kb
Host smart-93082063-12b9-4554-8956-e685a3df68d8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1537646047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1537646047
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1850593682
Short name T559
Test name
Test status
Simulation time 28721539840 ps
CPU time 736.92 seconds
Started Apr 04 03:14:32 PM PDT 24
Finished Apr 04 03:26:49 PM PDT 24
Peak memory 273708 kb
Host smart-c56b812f-b3a9-492b-9ebc-aaff9ae14bc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850593682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1850593682
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1447865044
Short name T425
Test name
Test status
Simulation time 339253755 ps
CPU time 8.5 seconds
Started Apr 04 03:14:26 PM PDT 24
Finished Apr 04 03:14:35 PM PDT 24
Peak memory 240848 kb
Host smart-8b0dfd5f-d9a3-4144-b533-3cb0a646a70a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1447865044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1447865044
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.603578879
Short name T612
Test name
Test status
Simulation time 5554338432 ps
CPU time 121.07 seconds
Started Apr 04 03:14:30 PM PDT 24
Finished Apr 04 03:16:31 PM PDT 24
Peak memory 257272 kb
Host smart-83bc8b84-bdd5-4e1c-a559-93a4892f551d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60357
8879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.603578879
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2245892981
Short name T401
Test name
Test status
Simulation time 2287230980 ps
CPU time 25.13 seconds
Started Apr 04 03:14:23 PM PDT 24
Finished Apr 04 03:14:49 PM PDT 24
Peak memory 255828 kb
Host smart-e2fa9cd3-7075-41ee-b8f8-88d973f34283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22458
92981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2245892981
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3084313883
Short name T584
Test name
Test status
Simulation time 33938432354 ps
CPU time 1102.47 seconds
Started Apr 04 03:14:23 PM PDT 24
Finished Apr 04 03:32:46 PM PDT 24
Peak memory 271808 kb
Host smart-d908480b-50c2-4101-a3e4-ab8df0142d68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084313883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3084313883
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3840924115
Short name T665
Test name
Test status
Simulation time 186576000918 ps
CPU time 2678.35 seconds
Started Apr 04 03:14:31 PM PDT 24
Finished Apr 04 03:59:10 PM PDT 24
Peak memory 288492 kb
Host smart-e40577a2-8c6c-4c40-ab0b-a95a94123e85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840924115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3840924115
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2393033281
Short name T713
Test name
Test status
Simulation time 147043865061 ps
CPU time 395.04 seconds
Started Apr 04 03:14:26 PM PDT 24
Finished Apr 04 03:21:01 PM PDT 24
Peak memory 248072 kb
Host smart-496f32d3-ec2d-4e50-a0fc-70dd35624779
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393033281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2393033281
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.391100474
Short name T515
Test name
Test status
Simulation time 613024888 ps
CPU time 19.81 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:14:45 PM PDT 24
Peak memory 256216 kb
Host smart-18dc0bf3-7c1a-4759-af3b-4a97a20d5e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39110
0474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.391100474
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1177093053
Short name T554
Test name
Test status
Simulation time 606387181 ps
CPU time 35.61 seconds
Started Apr 04 03:14:24 PM PDT 24
Finished Apr 04 03:15:00 PM PDT 24
Peak memory 248588 kb
Host smart-f37b55fb-00aa-40ae-982d-e5e27cc14b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11770
93053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1177093053
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.65950615
Short name T535
Test name
Test status
Simulation time 6576245835 ps
CPU time 42.81 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 03:15:18 PM PDT 24
Peak memory 249172 kb
Host smart-d7f9aa13-0213-4218-942b-123f45f8fa75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65950
615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.65950615
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3921544322
Short name T519
Test name
Test status
Simulation time 517085001 ps
CPU time 22.97 seconds
Started Apr 04 03:14:27 PM PDT 24
Finished Apr 04 03:14:50 PM PDT 24
Peak memory 248968 kb
Host smart-d6373637-2a05-4c23-ba45-a75f18c7d337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215
44322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3921544322
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1444098528
Short name T88
Test name
Test status
Simulation time 4906011740 ps
CPU time 116.34 seconds
Started Apr 04 03:14:31 PM PDT 24
Finished Apr 04 03:16:27 PM PDT 24
Peak memory 257316 kb
Host smart-999341d1-cdfe-4247-a492-92e6552cefac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444098528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1444098528
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3572795254
Short name T236
Test name
Test status
Simulation time 137063024091 ps
CPU time 2234.39 seconds
Started Apr 04 03:14:26 PM PDT 24
Finished Apr 04 03:51:40 PM PDT 24
Peak memory 290244 kb
Host smart-a47fe3c8-413e-4bb0-9e5c-d9b776814b87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572795254 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3572795254
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3088939477
Short name T203
Test name
Test status
Simulation time 123504301 ps
CPU time 3.46 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:13:54 PM PDT 24
Peak memory 249200 kb
Host smart-8a3ff557-a57f-4fc8-a0d0-0a6871848705
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3088939477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3088939477
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.4248694061
Short name T90
Test name
Test status
Simulation time 54516601741 ps
CPU time 1560.72 seconds
Started Apr 04 03:13:45 PM PDT 24
Finished Apr 04 03:39:47 PM PDT 24
Peak memory 281932 kb
Host smart-bd251c40-1d81-4014-8471-128d0823546f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248694061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.4248694061
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3354106092
Short name T384
Test name
Test status
Simulation time 3894943294 ps
CPU time 80.63 seconds
Started Apr 04 03:13:49 PM PDT 24
Finished Apr 04 03:15:10 PM PDT 24
Peak memory 253204 kb
Host smart-fb3958a7-96d3-4ecb-92d9-7979f99ed6b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3354106092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3354106092
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3271901963
Short name T663
Test name
Test status
Simulation time 4688167153 ps
CPU time 30.25 seconds
Started Apr 04 03:13:44 PM PDT 24
Finished Apr 04 03:14:15 PM PDT 24
Peak memory 248892 kb
Host smart-2dc0da48-1cd5-40a4-82dc-21d3126f587b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32719
01963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3271901963
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.150014462
Short name T423
Test name
Test status
Simulation time 843374711 ps
CPU time 46.82 seconds
Started Apr 04 03:13:44 PM PDT 24
Finished Apr 04 03:14:31 PM PDT 24
Peak memory 255768 kb
Host smart-d745438f-9d2d-470b-a486-fd9f5e0a181f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15001
4462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.150014462
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3931953615
Short name T40
Test name
Test status
Simulation time 18476129445 ps
CPU time 1137.36 seconds
Started Apr 04 03:13:48 PM PDT 24
Finished Apr 04 03:32:46 PM PDT 24
Peak memory 265460 kb
Host smart-38726532-0895-42c9-aefc-4ec45f139196
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931953615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3931953615
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1410306005
Short name T683
Test name
Test status
Simulation time 27761250788 ps
CPU time 1534.8 seconds
Started Apr 04 03:13:42 PM PDT 24
Finished Apr 04 03:39:17 PM PDT 24
Peak memory 289588 kb
Host smart-ce0bf119-0bed-4c31-9896-2e2c05d81475
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410306005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1410306005
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.895813654
Short name T595
Test name
Test status
Simulation time 6430428092 ps
CPU time 280.8 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:18:34 PM PDT 24
Peak memory 248304 kb
Host smart-e0966a98-c724-40ce-8442-ad21895bbe72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895813654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.895813654
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2714664603
Short name T410
Test name
Test status
Simulation time 541893095 ps
CPU time 13.55 seconds
Started Apr 04 03:13:44 PM PDT 24
Finished Apr 04 03:13:59 PM PDT 24
Peak memory 256204 kb
Host smart-d9a60a85-16e0-47ba-b4dc-431104607297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27146
64603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2714664603
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3411539928
Short name T652
Test name
Test status
Simulation time 2908286463 ps
CPU time 39.03 seconds
Started Apr 04 03:13:48 PM PDT 24
Finished Apr 04 03:14:28 PM PDT 24
Peak memory 249136 kb
Host smart-7bb74ab2-2887-4ba8-9585-5830dc90cf81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34115
39928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3411539928
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1006849033
Short name T15
Test name
Test status
Simulation time 744671111 ps
CPU time 14.25 seconds
Started Apr 04 03:13:58 PM PDT 24
Finished Apr 04 03:14:12 PM PDT 24
Peak memory 265532 kb
Host smart-50caf40c-f3cb-4371-9b08-3c4d8504b003
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1006849033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1006849033
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3588958876
Short name T521
Test name
Test status
Simulation time 76298734 ps
CPU time 9.38 seconds
Started Apr 04 03:13:48 PM PDT 24
Finished Apr 04 03:13:58 PM PDT 24
Peak memory 249064 kb
Host smart-f50fb63b-6900-42ca-a27c-b7436c06fbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35889
58876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3588958876
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2785137426
Short name T578
Test name
Test status
Simulation time 140745676884 ps
CPU time 2341.37 seconds
Started Apr 04 03:13:50 PM PDT 24
Finished Apr 04 03:52:53 PM PDT 24
Peak memory 289368 kb
Host smart-6e280cfc-414e-4410-b793-e1d9705ca973
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785137426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2785137426
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2943651389
Short name T271
Test name
Test status
Simulation time 30938032549 ps
CPU time 2982.33 seconds
Started Apr 04 03:13:48 PM PDT 24
Finished Apr 04 04:03:31 PM PDT 24
Peak memory 320784 kb
Host smart-6814452d-6295-4a1f-901b-fbb7594fc8a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943651389 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2943651389
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3969803271
Short name T435
Test name
Test status
Simulation time 11002046284 ps
CPU time 673.51 seconds
Started Apr 04 03:14:36 PM PDT 24
Finished Apr 04 03:25:49 PM PDT 24
Peak memory 273420 kb
Host smart-0acbc219-1fed-4628-afd0-d5580a6a1844
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969803271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3969803271
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2212465611
Short name T464
Test name
Test status
Simulation time 213679837 ps
CPU time 7.01 seconds
Started Apr 04 03:14:28 PM PDT 24
Finished Apr 04 03:14:35 PM PDT 24
Peak memory 240528 kb
Host smart-0c5a5465-ebbb-4eb5-9565-e6044adf2ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22124
65611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2212465611
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.931123007
Short name T78
Test name
Test status
Simulation time 207747490 ps
CPU time 7.85 seconds
Started Apr 04 03:14:30 PM PDT 24
Finished Apr 04 03:14:38 PM PDT 24
Peak memory 249032 kb
Host smart-4ef34b20-2ea0-48e0-aec3-d6c3a3067aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93112
3007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.931123007
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.673159214
Short name T344
Test name
Test status
Simulation time 69710701701 ps
CPU time 637.02 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:25:12 PM PDT 24
Peak memory 265568 kb
Host smart-547e8888-1c78-4a9f-85f1-7ea386b9d88e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673159214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.673159214
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.4057912395
Short name T474
Test name
Test status
Simulation time 30931002805 ps
CPU time 1362.66 seconds
Started Apr 04 03:14:32 PM PDT 24
Finished Apr 04 03:37:15 PM PDT 24
Peak memory 289584 kb
Host smart-35380da2-392f-4b8c-ab76-3c9368191725
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057912395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.4057912395
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1917018010
Short name T692
Test name
Test status
Simulation time 1500677293 ps
CPU time 37.32 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:15:12 PM PDT 24
Peak memory 256376 kb
Host smart-083eca15-3d25-45fb-beb8-b5e66fd42803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19170
18010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1917018010
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3188704295
Short name T29
Test name
Test status
Simulation time 114288982 ps
CPU time 14.95 seconds
Started Apr 04 03:14:26 PM PDT 24
Finished Apr 04 03:14:41 PM PDT 24
Peak memory 253968 kb
Host smart-30a93192-8f13-4866-97e0-60002288fe5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31887
04295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3188704295
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2538027390
Short name T105
Test name
Test status
Simulation time 844649549 ps
CPU time 11.74 seconds
Started Apr 04 03:14:27 PM PDT 24
Finished Apr 04 03:14:39 PM PDT 24
Peak memory 254232 kb
Host smart-4d05fc9b-4146-455e-94df-54378aa57fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25380
27390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2538027390
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3262326529
Short name T405
Test name
Test status
Simulation time 409034319 ps
CPU time 22.86 seconds
Started Apr 04 03:14:28 PM PDT 24
Finished Apr 04 03:14:51 PM PDT 24
Peak memory 249352 kb
Host smart-a373f054-d5ee-4068-ac48-5bb7b7a9249b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32623
26529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3262326529
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.4007799279
Short name T92
Test name
Test status
Simulation time 111569368283 ps
CPU time 2967.46 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 04:04:03 PM PDT 24
Peak memory 290140 kb
Host smart-8e170f3e-bdad-48a4-9c2e-aa2f4c95ca3b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007799279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.4007799279
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.711206074
Short name T185
Test name
Test status
Simulation time 10228605720 ps
CPU time 969.33 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:30:35 PM PDT 24
Peak memory 286316 kb
Host smart-e9827bb8-e810-4093-a203-60775ae497f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711206074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.711206074
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3953759429
Short name T443
Test name
Test status
Simulation time 1622176203 ps
CPU time 88.16 seconds
Started Apr 04 03:14:29 PM PDT 24
Finished Apr 04 03:15:58 PM PDT 24
Peak memory 257036 kb
Host smart-1fb12ea2-fda5-4faa-b0f5-6b982cd4b4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537
59429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3953759429
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3807456496
Short name T697
Test name
Test status
Simulation time 4964043417 ps
CPU time 75.76 seconds
Started Apr 04 03:14:31 PM PDT 24
Finished Apr 04 03:15:47 PM PDT 24
Peak memory 255872 kb
Host smart-9b7fd4a4-0ba5-4c40-a57f-c425e73a9dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38074
56496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3807456496
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3761851897
Short name T429
Test name
Test status
Simulation time 578448144649 ps
CPU time 2359.16 seconds
Started Apr 04 03:14:30 PM PDT 24
Finished Apr 04 03:53:50 PM PDT 24
Peak memory 289044 kb
Host smart-e3028791-2145-490d-9e51-793a543beeb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761851897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3761851897
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.921139161
Short name T314
Test name
Test status
Simulation time 6867529906 ps
CPU time 267.74 seconds
Started Apr 04 03:14:29 PM PDT 24
Finished Apr 04 03:18:57 PM PDT 24
Peak memory 248320 kb
Host smart-eb14cd60-9834-4fa8-b409-b03589df7f8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921139161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.921139161
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2207812579
Short name T449
Test name
Test status
Simulation time 380169326 ps
CPU time 12.5 seconds
Started Apr 04 03:14:30 PM PDT 24
Finished Apr 04 03:14:42 PM PDT 24
Peak memory 249012 kb
Host smart-a329a687-6736-49c5-bfeb-a198518b6b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22078
12579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2207812579
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.4064727591
Short name T23
Test name
Test status
Simulation time 245691662 ps
CPU time 10.04 seconds
Started Apr 04 03:14:30 PM PDT 24
Finished Apr 04 03:14:40 PM PDT 24
Peak memory 248864 kb
Host smart-999d5a36-5b31-4cd1-9da5-17a76a516ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40647
27591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.4064727591
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.570545095
Short name T636
Test name
Test status
Simulation time 4335576119 ps
CPU time 50.37 seconds
Started Apr 04 03:14:32 PM PDT 24
Finished Apr 04 03:15:22 PM PDT 24
Peak memory 249152 kb
Host smart-0490e745-f779-49b2-bf4d-0f98d15e2942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57054
5095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.570545095
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2182834853
Short name T374
Test name
Test status
Simulation time 326334749 ps
CPU time 32.98 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 03:15:09 PM PDT 24
Peak memory 249204 kb
Host smart-2dc7306d-bbb1-4b66-b416-b1837c6f4642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21828
34853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2182834853
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1336969784
Short name T2
Test name
Test status
Simulation time 765738003004 ps
CPU time 3006.41 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 04:04:41 PM PDT 24
Peak memory 289708 kb
Host smart-a714270f-4f26-4d08-b748-3cc219f48398
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336969784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1336969784
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3667390403
Short name T279
Test name
Test status
Simulation time 326290755257 ps
CPU time 5066.54 seconds
Started Apr 04 03:14:23 PM PDT 24
Finished Apr 04 04:38:50 PM PDT 24
Peak memory 304056 kb
Host smart-1e70aeb1-7d5c-4f2f-b5fd-6c765c428bb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667390403 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3667390403
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.109765607
Short name T67
Test name
Test status
Simulation time 7841183092 ps
CPU time 609.68 seconds
Started Apr 04 03:14:28 PM PDT 24
Finished Apr 04 03:24:38 PM PDT 24
Peak memory 273056 kb
Host smart-b5e3b9f7-bc1a-46ea-975f-27c60c2bdfc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109765607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.109765607
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3215116746
Short name T639
Test name
Test status
Simulation time 1332907001 ps
CPU time 78.22 seconds
Started Apr 04 03:14:25 PM PDT 24
Finished Apr 04 03:15:43 PM PDT 24
Peak memory 256872 kb
Host smart-a9e01156-e5d4-46f1-be99-c0a6e9ed4a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32151
16746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3215116746
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2077062460
Short name T381
Test name
Test status
Simulation time 422948572 ps
CPU time 15.04 seconds
Started Apr 04 03:14:26 PM PDT 24
Finished Apr 04 03:14:41 PM PDT 24
Peak memory 255080 kb
Host smart-5569f4e6-5a21-4f57-987e-ee54bf1c15d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20770
62460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2077062460
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1623355606
Short name T8
Test name
Test status
Simulation time 19397830749 ps
CPU time 1090.87 seconds
Started Apr 04 03:14:36 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 287068 kb
Host smart-051007c5-5365-44a0-bf60-1aaa8fb4a7b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623355606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1623355606
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1978703137
Short name T682
Test name
Test status
Simulation time 6558386239 ps
CPU time 219.38 seconds
Started Apr 04 03:14:33 PM PDT 24
Finished Apr 04 03:18:13 PM PDT 24
Peak memory 248324 kb
Host smart-b25713d9-9c4b-45a4-826a-904c51925a4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978703137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1978703137
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.760243603
Short name T51
Test name
Test status
Simulation time 199827530 ps
CPU time 6.37 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 03:14:41 PM PDT 24
Peak memory 254216 kb
Host smart-adcf9314-e63f-4955-aa28-c6f846f0ff72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76024
3603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.760243603
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1181468401
Short name T402
Test name
Test status
Simulation time 64299129 ps
CPU time 5.17 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 03:14:40 PM PDT 24
Peak memory 239328 kb
Host smart-93429161-6537-4927-bc18-e4d4d8d65ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11814
68401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1181468401
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2250196475
Short name T95
Test name
Test status
Simulation time 645352164 ps
CPU time 25.95 seconds
Started Apr 04 03:14:33 PM PDT 24
Finished Apr 04 03:14:59 PM PDT 24
Peak memory 254864 kb
Host smart-84530ec1-2eb7-4781-8f7a-869850b0edb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22501
96475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2250196475
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3722883114
Short name T418
Test name
Test status
Simulation time 235838060 ps
CPU time 23.99 seconds
Started Apr 04 03:14:32 PM PDT 24
Finished Apr 04 03:14:56 PM PDT 24
Peak memory 249116 kb
Host smart-74058349-d5b5-47ce-84e2-1b9ef7d60c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37228
83114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3722883114
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.4096510064
Short name T676
Test name
Test status
Simulation time 28359084828 ps
CPU time 925.95 seconds
Started Apr 04 03:14:33 PM PDT 24
Finished Apr 04 03:29:59 PM PDT 24
Peak memory 273172 kb
Host smart-f03078c7-9835-4d98-a74d-a11ea31ab4e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096510064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.4096510064
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.628179156
Short name T705
Test name
Test status
Simulation time 7754683818 ps
CPU time 716.64 seconds
Started Apr 04 03:14:32 PM PDT 24
Finished Apr 04 03:26:29 PM PDT 24
Peak memory 272700 kb
Host smart-6111beb5-c42b-42a3-b3e7-98fc1a76c9fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628179156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.628179156
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.538793996
Short name T19
Test name
Test status
Simulation time 2845051268 ps
CPU time 121.9 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:16:36 PM PDT 24
Peak memory 257176 kb
Host smart-458faee1-28b1-429e-bb6f-ed2bfd199112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53879
3996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.538793996
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.234172254
Short name T395
Test name
Test status
Simulation time 312026854 ps
CPU time 8.46 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 03:14:43 PM PDT 24
Peak memory 254836 kb
Host smart-7ba8d4ca-2209-4fc3-be6b-b714478e4b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23417
2254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.234172254
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1880954831
Short name T233
Test name
Test status
Simulation time 24334803230 ps
CPU time 1188.09 seconds
Started Apr 04 03:14:38 PM PDT 24
Finished Apr 04 03:34:26 PM PDT 24
Peak memory 289928 kb
Host smart-8b787e53-a1f0-426d-9f6f-5d8f557f709f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880954831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1880954831
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3389290959
Short name T288
Test name
Test status
Simulation time 33418074154 ps
CPU time 1731.95 seconds
Started Apr 04 03:14:30 PM PDT 24
Finished Apr 04 03:43:22 PM PDT 24
Peak memory 273728 kb
Host smart-b8b640b0-9156-4d31-bb4b-157c031994b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389290959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3389290959
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.227840275
Short name T338
Test name
Test status
Simulation time 10512402040 ps
CPU time 414.97 seconds
Started Apr 04 03:14:37 PM PDT 24
Finished Apr 04 03:21:32 PM PDT 24
Peak memory 248108 kb
Host smart-6f3c60f8-5a53-46f9-9526-756f911319cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227840275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.227840275
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3336861638
Short name T440
Test name
Test status
Simulation time 731522910 ps
CPU time 9.64 seconds
Started Apr 04 03:14:38 PM PDT 24
Finished Apr 04 03:14:48 PM PDT 24
Peak memory 249288 kb
Host smart-60eb4e65-a0e7-435d-841c-157304c8cf5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33368
61638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3336861638
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3330187021
Short name T408
Test name
Test status
Simulation time 204015437 ps
CPU time 13.85 seconds
Started Apr 04 03:14:38 PM PDT 24
Finished Apr 04 03:14:52 PM PDT 24
Peak memory 252000 kb
Host smart-e0847ff2-0a6d-49d5-9947-20773d5a48be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33301
87021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3330187021
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4252934308
Short name T44
Test name
Test status
Simulation time 268752380 ps
CPU time 30.7 seconds
Started Apr 04 03:14:38 PM PDT 24
Finished Apr 04 03:15:09 PM PDT 24
Peak memory 247496 kb
Host smart-85cf0724-f554-47e0-85ac-fb5ee77d52d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42529
34308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4252934308
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1059109445
Short name T686
Test name
Test status
Simulation time 1158288536 ps
CPU time 23.18 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:14:57 PM PDT 24
Peak memory 256080 kb
Host smart-7f234637-0426-4866-8643-71e74ef19f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10591
09445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1059109445
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1799104931
Short name T113
Test name
Test status
Simulation time 59851418730 ps
CPU time 3946.79 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 04:20:21 PM PDT 24
Peak memory 282036 kb
Host smart-a0a56f8a-59fe-4a50-af55-64df6f9592ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799104931 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1799104931
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.112475727
Short name T568
Test name
Test status
Simulation time 86012299354 ps
CPU time 2428.68 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 03:55:04 PM PDT 24
Peak memory 281952 kb
Host smart-3683ce40-53fa-44b2-8e95-0ecac9edd9e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112475727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.112475727
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3617811608
Short name T605
Test name
Test status
Simulation time 1857120253 ps
CPU time 165.89 seconds
Started Apr 04 03:14:30 PM PDT 24
Finished Apr 04 03:17:16 PM PDT 24
Peak memory 257184 kb
Host smart-5fb598a5-ebdd-4d2b-87b3-85c4a529c58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36178
11608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3617811608
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3264643089
Short name T382
Test name
Test status
Simulation time 2377907154 ps
CPU time 33.47 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:15:07 PM PDT 24
Peak memory 255156 kb
Host smart-fa6a98b5-691f-4d25-bed2-eb6c9408ed18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32646
43089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3264643089
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1415506720
Short name T672
Test name
Test status
Simulation time 18598258993 ps
CPU time 1484.56 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:39:19 PM PDT 24
Peak memory 290004 kb
Host smart-8f9de6d9-5f38-4bea-a6bb-a4f2df42b955
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415506720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1415506720
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1575172222
Short name T552
Test name
Test status
Simulation time 54753441344 ps
CPU time 115.84 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 03:16:31 PM PDT 24
Peak memory 247964 kb
Host smart-6f354956-a6b3-4008-a51a-903681e7b2ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575172222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1575172222
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.228275744
Short name T414
Test name
Test status
Simulation time 50929017 ps
CPU time 5.99 seconds
Started Apr 04 03:14:24 PM PDT 24
Finished Apr 04 03:14:30 PM PDT 24
Peak memory 250872 kb
Host smart-05c5141d-0fc6-4182-b42f-6abbe55e17e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22827
5744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.228275744
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3314489947
Short name T606
Test name
Test status
Simulation time 274623676 ps
CPU time 30.39 seconds
Started Apr 04 03:14:32 PM PDT 24
Finished Apr 04 03:15:02 PM PDT 24
Peak memory 255656 kb
Host smart-d900f15c-867a-40c7-8c05-2e0cbabc05d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33144
89947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3314489947
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1024369898
Short name T218
Test name
Test status
Simulation time 1093927971 ps
CPU time 32.38 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:15:06 PM PDT 24
Peak memory 249020 kb
Host smart-02e24c83-680e-4fc7-ac69-1f950867d248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10243
69898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1024369898
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2727162676
Short name T695
Test name
Test status
Simulation time 11959009662 ps
CPU time 959.39 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:30:34 PM PDT 24
Peak memory 273092 kb
Host smart-17ba2155-322f-402e-9d03-336a80816e17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727162676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2727162676
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1218642146
Short name T217
Test name
Test status
Simulation time 2574609320 ps
CPU time 56.31 seconds
Started Apr 04 03:14:31 PM PDT 24
Finished Apr 04 03:15:28 PM PDT 24
Peak memory 256844 kb
Host smart-988162f2-c0e1-4ed3-a0ab-95d81fe05e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12186
42146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1218642146
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1372540594
Short name T77
Test name
Test status
Simulation time 8127087138 ps
CPU time 35.94 seconds
Started Apr 04 03:14:31 PM PDT 24
Finished Apr 04 03:15:07 PM PDT 24
Peak memory 255260 kb
Host smart-a8ea71f1-9a33-4df1-9a56-c30e24d14428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13725
40594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1372540594
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3722175952
Short name T501
Test name
Test status
Simulation time 326157596660 ps
CPU time 2333.52 seconds
Started Apr 04 03:14:41 PM PDT 24
Finished Apr 04 03:53:35 PM PDT 24
Peak memory 289340 kb
Host smart-47b60598-5da4-4f67-a29f-bda2f71d5f61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722175952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3722175952
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.897717341
Short name T292
Test name
Test status
Simulation time 635231031 ps
CPU time 19.12 seconds
Started Apr 04 03:14:30 PM PDT 24
Finished Apr 04 03:14:49 PM PDT 24
Peak memory 255192 kb
Host smart-8ce8ce19-eeca-44d6-83ed-6e1f588db618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89771
7341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.897717341
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1817581672
Short name T616
Test name
Test status
Simulation time 114529418 ps
CPU time 13.58 seconds
Started Apr 04 03:14:32 PM PDT 24
Finished Apr 04 03:14:46 PM PDT 24
Peak memory 249036 kb
Host smart-a8730dd2-4c19-4e9b-a6d7-a18e124ccfbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18175
81672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1817581672
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3374615404
Short name T484
Test name
Test status
Simulation time 232981282 ps
CPU time 4.54 seconds
Started Apr 04 03:14:29 PM PDT 24
Finished Apr 04 03:14:34 PM PDT 24
Peak memory 239228 kb
Host smart-c5b7a8db-7552-4804-82a2-29456be12f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33746
15404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3374615404
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.4195139145
Short name T461
Test name
Test status
Simulation time 1251580302 ps
CPU time 33.42 seconds
Started Apr 04 03:14:32 PM PDT 24
Finished Apr 04 03:15:06 PM PDT 24
Peak memory 256100 kb
Host smart-c0ddf111-28f2-469f-a1f9-b925b2fd2c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41951
39145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.4195139145
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.4039880240
Short name T567
Test name
Test status
Simulation time 1291171806 ps
CPU time 18.96 seconds
Started Apr 04 03:14:37 PM PDT 24
Finished Apr 04 03:14:56 PM PDT 24
Peak memory 247388 kb
Host smart-c2003704-3e4d-4f5b-aed9-62440ae64951
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039880240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.4039880240
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.4061369177
Short name T57
Test name
Test status
Simulation time 14707906826 ps
CPU time 710.83 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:26:25 PM PDT 24
Peak memory 272696 kb
Host smart-184ec1cf-0a1c-476b-ba35-dde8c58f2493
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061369177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4061369177
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3253975355
Short name T497
Test name
Test status
Simulation time 708514886 ps
CPU time 35.2 seconds
Started Apr 04 03:14:44 PM PDT 24
Finished Apr 04 03:15:19 PM PDT 24
Peak memory 256764 kb
Host smart-65bcdcc5-120c-406e-b39d-e2c2d8a1550b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32539
75355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3253975355
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2767459023
Short name T690
Test name
Test status
Simulation time 644451986 ps
CPU time 36.26 seconds
Started Apr 04 03:14:38 PM PDT 24
Finished Apr 04 03:15:15 PM PDT 24
Peak memory 248972 kb
Host smart-ac0591ea-e933-42c5-85ca-29aeb53abc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27674
59023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2767459023
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3901601855
Short name T341
Test name
Test status
Simulation time 12985061001 ps
CPU time 682.93 seconds
Started Apr 04 03:14:38 PM PDT 24
Finished Apr 04 03:26:01 PM PDT 24
Peak memory 265552 kb
Host smart-e0145452-fb4d-40ed-92e3-cee5402fcb94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901601855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3901601855
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.391050005
Short name T547
Test name
Test status
Simulation time 83067210658 ps
CPU time 2432.41 seconds
Started Apr 04 03:14:47 PM PDT 24
Finished Apr 04 03:55:20 PM PDT 24
Peak memory 284880 kb
Host smart-666267d5-c2f9-4ad9-a1f3-6c70d6a66940
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391050005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.391050005
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.403343920
Short name T312
Test name
Test status
Simulation time 7144538539 ps
CPU time 276.54 seconds
Started Apr 04 03:14:36 PM PDT 24
Finished Apr 04 03:19:12 PM PDT 24
Peak memory 248316 kb
Host smart-382ada20-9913-4802-9f68-a538bf9510b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403343920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.403343920
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.24871618
Short name T30
Test name
Test status
Simulation time 754701528 ps
CPU time 13.5 seconds
Started Apr 04 03:14:49 PM PDT 24
Finished Apr 04 03:15:03 PM PDT 24
Peak memory 253072 kb
Host smart-f377c7de-f655-4c97-8218-04e61c7697bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24871
618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.24871618
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3508816272
Short name T276
Test name
Test status
Simulation time 2245733257 ps
CPU time 34.87 seconds
Started Apr 04 03:14:45 PM PDT 24
Finished Apr 04 03:15:20 PM PDT 24
Peak memory 255832 kb
Host smart-65a2ab5a-c4ef-4b84-86af-25f4ff1d8a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35088
16272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3508816272
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3775754120
Short name T585
Test name
Test status
Simulation time 688894451 ps
CPU time 38.02 seconds
Started Apr 04 03:14:49 PM PDT 24
Finished Apr 04 03:15:27 PM PDT 24
Peak memory 249044 kb
Host smart-eaf15b74-1635-49bb-9c9b-405a3493541d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37757
54120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3775754120
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2550535321
Short name T234
Test name
Test status
Simulation time 17690665137 ps
CPU time 1102.76 seconds
Started Apr 04 03:14:44 PM PDT 24
Finished Apr 04 03:33:07 PM PDT 24
Peak memory 273360 kb
Host smart-519ac7c5-f5f7-4dd6-a17e-235db5d4f4cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550535321 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2550535321
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.790555447
Short name T467
Test name
Test status
Simulation time 48113563702 ps
CPU time 2791.18 seconds
Started Apr 04 03:14:48 PM PDT 24
Finished Apr 04 04:01:20 PM PDT 24
Peak memory 289136 kb
Host smart-233a987d-3b4e-402b-bae4-7c16a5eca062
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790555447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.790555447
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1406450927
Short name T21
Test name
Test status
Simulation time 20235799888 ps
CPU time 277.63 seconds
Started Apr 04 03:14:49 PM PDT 24
Finished Apr 04 03:19:26 PM PDT 24
Peak memory 257228 kb
Host smart-1b2f6ac4-c937-46f1-900a-f03b9572baf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14064
50927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1406450927
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2036144594
Short name T422
Test name
Test status
Simulation time 1448914673 ps
CPU time 18.53 seconds
Started Apr 04 03:14:37 PM PDT 24
Finished Apr 04 03:14:56 PM PDT 24
Peak memory 249228 kb
Host smart-c2922d54-a50b-4331-81c5-40266d5d47ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20361
44594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2036144594
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1399804193
Short name T353
Test name
Test status
Simulation time 31847409766 ps
CPU time 1720.25 seconds
Started Apr 04 03:14:44 PM PDT 24
Finished Apr 04 03:43:25 PM PDT 24
Peak memory 272028 kb
Host smart-62670996-7f49-446d-80e5-d5e36ee742b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399804193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1399804193
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3716506040
Short name T427
Test name
Test status
Simulation time 73124712633 ps
CPU time 2371.1 seconds
Started Apr 04 03:14:38 PM PDT 24
Finished Apr 04 03:54:10 PM PDT 24
Peak memory 272044 kb
Host smart-4bc70bf2-95e1-4847-8ac5-841f4e11c6d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716506040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3716506040
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2279182102
Short name T225
Test name
Test status
Simulation time 105395985805 ps
CPU time 452.48 seconds
Started Apr 04 03:14:43 PM PDT 24
Finished Apr 04 03:22:16 PM PDT 24
Peak memory 248280 kb
Host smart-841485aa-e24a-49a2-8aa6-1f718327e907
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279182102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2279182102
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.521819108
Short name T243
Test name
Test status
Simulation time 219504908 ps
CPU time 16.97 seconds
Started Apr 04 03:14:35 PM PDT 24
Finished Apr 04 03:14:52 PM PDT 24
Peak memory 255472 kb
Host smart-48f33bd7-f478-42a4-b866-80e3f8717c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52181
9108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.521819108
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3408586186
Short name T412
Test name
Test status
Simulation time 89901294 ps
CPU time 9.05 seconds
Started Apr 04 03:14:47 PM PDT 24
Finished Apr 04 03:14:56 PM PDT 24
Peak memory 247448 kb
Host smart-980ad2d6-668a-482e-9a46-782dd35ed545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34085
86186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3408586186
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3853592376
Short name T517
Test name
Test status
Simulation time 1090380825 ps
CPU time 32.03 seconds
Started Apr 04 03:14:39 PM PDT 24
Finished Apr 04 03:15:11 PM PDT 24
Peak memory 255528 kb
Host smart-ed5c59ec-de57-4905-a2bb-5614983360b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38535
92376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3853592376
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2348646734
Short name T709
Test name
Test status
Simulation time 623234080 ps
CPU time 39.51 seconds
Started Apr 04 03:14:37 PM PDT 24
Finished Apr 04 03:15:16 PM PDT 24
Peak memory 249280 kb
Host smart-1bbfaa6c-dd1a-4de4-85c6-5c40eccd20da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23486
46734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2348646734
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.443113107
Short name T433
Test name
Test status
Simulation time 1327123737 ps
CPU time 38.73 seconds
Started Apr 04 03:14:37 PM PDT 24
Finished Apr 04 03:15:15 PM PDT 24
Peak memory 256520 kb
Host smart-c5fb52c3-54e8-4920-b7b5-307e176fec31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443113107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.443113107
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1914080487
Short name T103
Test name
Test status
Simulation time 200755474971 ps
CPU time 1930.17 seconds
Started Apr 04 03:14:43 PM PDT 24
Finished Apr 04 03:46:53 PM PDT 24
Peak memory 289028 kb
Host smart-5d6637f5-e12f-47a0-bc77-3fd2679aee9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914080487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1914080487
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1010734506
Short name T699
Test name
Test status
Simulation time 3989389837 ps
CPU time 240.88 seconds
Started Apr 04 03:14:45 PM PDT 24
Finished Apr 04 03:18:46 PM PDT 24
Peak memory 257292 kb
Host smart-736ac7b7-6792-4032-a0ae-278c508ff6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10107
34506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1010734506
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1040382133
Short name T72
Test name
Test status
Simulation time 122977970 ps
CPU time 6.94 seconds
Started Apr 04 03:14:44 PM PDT 24
Finished Apr 04 03:14:51 PM PDT 24
Peak memory 248608 kb
Host smart-765a1fd1-a982-4a2b-88eb-965fe5243c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10403
82133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1040382133
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3859103155
Short name T340
Test name
Test status
Simulation time 35994298401 ps
CPU time 2065.2 seconds
Started Apr 04 03:14:44 PM PDT 24
Finished Apr 04 03:49:10 PM PDT 24
Peak memory 289292 kb
Host smart-b4e03e7c-49da-4147-bfc4-0b69de51b91b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859103155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3859103155
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.763065254
Short name T436
Test name
Test status
Simulation time 909124944 ps
CPU time 25.77 seconds
Started Apr 04 03:14:49 PM PDT 24
Finished Apr 04 03:15:15 PM PDT 24
Peak memory 248992 kb
Host smart-657c2f60-bba9-4292-bf31-5ad77c56a7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76306
5254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.763065254
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1005247953
Short name T518
Test name
Test status
Simulation time 298388037 ps
CPU time 33.29 seconds
Started Apr 04 03:14:48 PM PDT 24
Finished Apr 04 03:15:22 PM PDT 24
Peak memory 255640 kb
Host smart-52fad93d-409b-4fb1-8f2e-496bd4f771e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10052
47953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1005247953
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.895143901
Short name T55
Test name
Test status
Simulation time 5077136504 ps
CPU time 31.8 seconds
Started Apr 04 03:14:37 PM PDT 24
Finished Apr 04 03:15:09 PM PDT 24
Peak memory 248780 kb
Host smart-18577e37-1c51-4814-8b7f-e9326bb522f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89514
3901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.895143901
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1608032400
Short name T560
Test name
Test status
Simulation time 640020518 ps
CPU time 44.67 seconds
Started Apr 04 03:14:45 PM PDT 24
Finished Apr 04 03:15:30 PM PDT 24
Peak memory 249000 kb
Host smart-74b79dbe-fc3e-4de4-9998-727e1938f713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16080
32400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1608032400
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.694218486
Short name T102
Test name
Test status
Simulation time 29937869185 ps
CPU time 282.3 seconds
Started Apr 04 03:14:50 PM PDT 24
Finished Apr 04 03:19:32 PM PDT 24
Peak memory 257228 kb
Host smart-d16d794c-894a-4176-8ff0-e9f9b8f81e59
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694218486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.694218486
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2750820403
Short name T557
Test name
Test status
Simulation time 3921793324 ps
CPU time 219.94 seconds
Started Apr 04 03:14:48 PM PDT 24
Finished Apr 04 03:18:28 PM PDT 24
Peak memory 257172 kb
Host smart-c1b54f03-f204-4021-ae1c-2554651b34b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27508
20403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2750820403
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1356523090
Short name T608
Test name
Test status
Simulation time 51444801 ps
CPU time 8.61 seconds
Started Apr 04 03:14:49 PM PDT 24
Finished Apr 04 03:14:58 PM PDT 24
Peak memory 248988 kb
Host smart-cbd22b45-34f7-4abf-bea4-49f0f8d296dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13565
23090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1356523090
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.121650515
Short name T662
Test name
Test status
Simulation time 137362935082 ps
CPU time 2080.67 seconds
Started Apr 04 03:14:40 PM PDT 24
Finished Apr 04 03:49:21 PM PDT 24
Peak memory 281932 kb
Host smart-e86938f1-86ae-4586-af98-cb33448a5136
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121650515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.121650515
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.4015694729
Short name T318
Test name
Test status
Simulation time 11656579307 ps
CPU time 268.35 seconds
Started Apr 04 03:14:50 PM PDT 24
Finished Apr 04 03:19:19 PM PDT 24
Peak memory 247992 kb
Host smart-1592a6cb-c648-44e3-8a29-0021cf2c4bf9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015694729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.4015694729
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3349205081
Short name T609
Test name
Test status
Simulation time 135063626 ps
CPU time 9.35 seconds
Started Apr 04 03:14:47 PM PDT 24
Finished Apr 04 03:14:57 PM PDT 24
Peak memory 249040 kb
Host smart-29270ce7-6253-4421-9141-5d14cb9ed585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33492
05081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3349205081
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.692904767
Short name T380
Test name
Test status
Simulation time 770858883 ps
CPU time 17.2 seconds
Started Apr 04 03:14:34 PM PDT 24
Finished Apr 04 03:14:52 PM PDT 24
Peak memory 248916 kb
Host smart-eb67a679-7551-4fc3-92cc-9252c9649ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69290
4767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.692904767
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1333829896
Short name T444
Test name
Test status
Simulation time 893322647 ps
CPU time 27.92 seconds
Started Apr 04 03:14:44 PM PDT 24
Finished Apr 04 03:15:12 PM PDT 24
Peak memory 255960 kb
Host smart-2b7212c7-8684-4854-ab2f-92839c40dfab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13338
29896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1333829896
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3280317073
Short name T454
Test name
Test status
Simulation time 1055922044 ps
CPU time 68.08 seconds
Started Apr 04 03:14:44 PM PDT 24
Finished Apr 04 03:15:53 PM PDT 24
Peak memory 256760 kb
Host smart-dd444e65-d58e-4154-9576-782232f75026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32803
17073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3280317073
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2409343349
Short name T58
Test name
Test status
Simulation time 23848826671 ps
CPU time 1308.27 seconds
Started Apr 04 03:14:50 PM PDT 24
Finished Apr 04 03:36:38 PM PDT 24
Peak memory 273252 kb
Host smart-3e7de7ea-b919-4368-b4b8-d674e387bdee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409343349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2409343349
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2468648824
Short name T214
Test name
Test status
Simulation time 14240476 ps
CPU time 2.47 seconds
Started Apr 04 03:13:50 PM PDT 24
Finished Apr 04 03:13:52 PM PDT 24
Peak memory 249332 kb
Host smart-28853cee-9aee-4454-8d88-44339d35aa7d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2468648824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2468648824
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1347529830
Short name T35
Test name
Test status
Simulation time 68056930927 ps
CPU time 1657.43 seconds
Started Apr 04 03:13:53 PM PDT 24
Finished Apr 04 03:41:32 PM PDT 24
Peak memory 289332 kb
Host smart-dc57c76c-0fd5-45e9-9c98-3eee6be00d14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347529830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1347529830
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1775106644
Short name T20
Test name
Test status
Simulation time 1452404227 ps
CPU time 9.92 seconds
Started Apr 04 03:13:49 PM PDT 24
Finished Apr 04 03:14:00 PM PDT 24
Peak memory 240832 kb
Host smart-b671af95-2619-4dd4-a98e-97db73e457ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1775106644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1775106644
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2592816167
Short name T596
Test name
Test status
Simulation time 1705445250 ps
CPU time 86.62 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:15:18 PM PDT 24
Peak memory 256968 kb
Host smart-fc5e6c54-32f9-401a-a189-abe92aade2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25928
16167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2592816167
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3060933822
Short name T480
Test name
Test status
Simulation time 399850238 ps
CPU time 7.71 seconds
Started Apr 04 03:13:53 PM PDT 24
Finished Apr 04 03:14:02 PM PDT 24
Peak memory 250960 kb
Host smart-5c657022-bb12-409d-bebb-3859037bc30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30609
33822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3060933822
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.895312164
Short name T661
Test name
Test status
Simulation time 9762551287 ps
CPU time 715.62 seconds
Started Apr 04 03:13:54 PM PDT 24
Finished Apr 04 03:25:50 PM PDT 24
Peak memory 265560 kb
Host smart-d2a9d15c-641b-422f-bc6e-46bc46fb4438
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895312164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.895312164
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2206295305
Short name T388
Test name
Test status
Simulation time 53604543489 ps
CPU time 3122.6 seconds
Started Apr 04 03:13:53 PM PDT 24
Finished Apr 04 04:05:57 PM PDT 24
Peak memory 290080 kb
Host smart-f978c761-5f7c-415a-82ea-8aedc75ad8f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206295305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2206295305
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.148059146
Short name T337
Test name
Test status
Simulation time 36909278894 ps
CPU time 346.26 seconds
Started Apr 04 03:13:53 PM PDT 24
Finished Apr 04 03:19:41 PM PDT 24
Peak memory 248420 kb
Host smart-2d915417-0abd-4ebb-8e07-6deacd493274
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148059146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.148059146
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.734656163
Short name T478
Test name
Test status
Simulation time 731952982 ps
CPU time 43 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:14:35 PM PDT 24
Peak memory 249076 kb
Host smart-71608db7-ea3b-49ee-8949-500aa086beac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73465
6163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.734656163
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1638242417
Short name T451
Test name
Test status
Simulation time 19442335842 ps
CPU time 55.47 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:14:47 PM PDT 24
Peak memory 255624 kb
Host smart-056f5327-dfc9-4a6f-bdb8-be0ef013ef70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16382
42417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1638242417
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3092540230
Short name T17
Test name
Test status
Simulation time 3585581367 ps
CPU time 25.07 seconds
Started Apr 04 03:13:54 PM PDT 24
Finished Apr 04 03:14:20 PM PDT 24
Peak memory 269848 kb
Host smart-a13b0d33-096c-4a94-9292-e7e1b5f1b77b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3092540230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3092540230
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.444992300
Short name T614
Test name
Test status
Simulation time 325008588 ps
CPU time 20.69 seconds
Started Apr 04 03:13:53 PM PDT 24
Finished Apr 04 03:14:15 PM PDT 24
Peak memory 255924 kb
Host smart-d776f581-1778-42f3-add9-c056eb934553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44499
2300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.444992300
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2121326060
Short name T468
Test name
Test status
Simulation time 62074889 ps
CPU time 8.33 seconds
Started Apr 04 03:13:52 PM PDT 24
Finished Apr 04 03:14:01 PM PDT 24
Peak memory 249032 kb
Host smart-efc76796-dcb5-4559-9bdd-8fec52c9d020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21213
26060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2121326060
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1872415192
Short name T624
Test name
Test status
Simulation time 1425223331 ps
CPU time 78.88 seconds
Started Apr 04 03:13:54 PM PDT 24
Finished Apr 04 03:15:13 PM PDT 24
Peak memory 257100 kb
Host smart-d01c1d2a-0e45-4892-b450-7d73632ef755
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872415192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1872415192
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2680861147
Short name T96
Test name
Test status
Simulation time 40199620596 ps
CPU time 2349.74 seconds
Started Apr 04 03:14:48 PM PDT 24
Finished Apr 04 03:53:58 PM PDT 24
Peak memory 283320 kb
Host smart-13f3826e-e617-4397-9c93-804f9deb5c13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680861147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2680861147
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1281313230
Short name T653
Test name
Test status
Simulation time 5028036976 ps
CPU time 260.38 seconds
Started Apr 04 03:14:51 PM PDT 24
Finished Apr 04 03:19:12 PM PDT 24
Peak memory 257076 kb
Host smart-e6fa0850-b459-4f9f-ad2a-bb86b85eee07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12813
13230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1281313230
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2325245786
Short name T79
Test name
Test status
Simulation time 1016361118 ps
CPU time 34.04 seconds
Started Apr 04 03:14:51 PM PDT 24
Finished Apr 04 03:15:26 PM PDT 24
Peak memory 247620 kb
Host smart-c6912654-e3e1-4c34-8577-135d49114caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23252
45786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2325245786
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.4156406844
Short name T342
Test name
Test status
Simulation time 16430839904 ps
CPU time 1252.49 seconds
Started Apr 04 03:14:48 PM PDT 24
Finished Apr 04 03:35:41 PM PDT 24
Peak memory 289940 kb
Host smart-7c7cf82f-a0c0-4716-bbb6-81009a201b10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156406844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.4156406844
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.4164842431
Short name T301
Test name
Test status
Simulation time 147616339966 ps
CPU time 2531.9 seconds
Started Apr 04 03:14:48 PM PDT 24
Finished Apr 04 03:57:00 PM PDT 24
Peak memory 289628 kb
Host smart-df45f924-1532-4738-b2f9-2813affa25ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164842431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.4164842431
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1990114861
Short name T179
Test name
Test status
Simulation time 1907133128 ps
CPU time 42.73 seconds
Started Apr 04 03:14:48 PM PDT 24
Finished Apr 04 03:15:31 PM PDT 24
Peak memory 248960 kb
Host smart-37b29ac2-718c-4e89-83be-13712a9bbb45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19901
14861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1990114861
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3581311041
Short name T698
Test name
Test status
Simulation time 418613227 ps
CPU time 29.8 seconds
Started Apr 04 03:14:53 PM PDT 24
Finished Apr 04 03:15:23 PM PDT 24
Peak memory 249008 kb
Host smart-001228ca-a7b6-4467-b53d-c4e1831eaf6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35813
11041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3581311041
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3682676498
Short name T659
Test name
Test status
Simulation time 278117435 ps
CPU time 16.27 seconds
Started Apr 04 03:14:49 PM PDT 24
Finished Apr 04 03:15:06 PM PDT 24
Peak memory 249292 kb
Host smart-ec30c420-d4e3-4b41-aa11-ca6d2a5cfd5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36826
76498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3682676498
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1546931417
Short name T76
Test name
Test status
Simulation time 138338280405 ps
CPU time 2070.87 seconds
Started Apr 04 03:14:48 PM PDT 24
Finished Apr 04 03:49:19 PM PDT 24
Peak memory 273136 kb
Host smart-22fb71f1-d280-4cf4-bb9c-04ad7cf126ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546931417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1546931417
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2257790289
Short name T534
Test name
Test status
Simulation time 54796599353 ps
CPU time 2785.11 seconds
Started Apr 04 03:14:51 PM PDT 24
Finished Apr 04 04:01:16 PM PDT 24
Peak memory 289816 kb
Host smart-8563cbba-c809-44dd-89ad-d0ad7670e4f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257790289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2257790289
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.779539573
Short name T502
Test name
Test status
Simulation time 2265170835 ps
CPU time 127.72 seconds
Started Apr 04 03:14:49 PM PDT 24
Finished Apr 04 03:16:57 PM PDT 24
Peak memory 256912 kb
Host smart-318d8008-64ed-4425-885a-da3d71a2fb07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77953
9573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.779539573
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1557925263
Short name T455
Test name
Test status
Simulation time 46495837809 ps
CPU time 972.98 seconds
Started Apr 04 03:14:49 PM PDT 24
Finished Apr 04 03:31:02 PM PDT 24
Peak memory 273336 kb
Host smart-f46364b4-52ec-426e-b312-4292397a4bc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557925263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1557925263
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.416702399
Short name T101
Test name
Test status
Simulation time 18500236335 ps
CPU time 1077.8 seconds
Started Apr 04 03:14:47 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 273144 kb
Host smart-0ecd6455-a770-4881-a4d7-771b0444a1d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416702399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.416702399
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.831245595
Short name T452
Test name
Test status
Simulation time 1347292472 ps
CPU time 78.02 seconds
Started Apr 04 03:14:53 PM PDT 24
Finished Apr 04 03:16:11 PM PDT 24
Peak memory 256168 kb
Host smart-2b7da382-92b2-4e3c-b2ec-bb71c55c7f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83124
5595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.831245595
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.336360418
Short name T413
Test name
Test status
Simulation time 406887910 ps
CPU time 28.27 seconds
Started Apr 04 03:14:52 PM PDT 24
Finished Apr 04 03:15:20 PM PDT 24
Peak memory 256132 kb
Host smart-c4a8d09c-bac7-41c0-95cb-5075e7b6e588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33636
0418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.336360418
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.31134077
Short name T694
Test name
Test status
Simulation time 1128230338 ps
CPU time 32.16 seconds
Started Apr 04 03:14:47 PM PDT 24
Finished Apr 04 03:15:20 PM PDT 24
Peak memory 247560 kb
Host smart-7b44a1fb-409a-4fe7-aea1-a05056637aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31134
077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.31134077
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2926425202
Short name T240
Test name
Test status
Simulation time 317191331 ps
CPU time 25.89 seconds
Started Apr 04 03:14:52 PM PDT 24
Finished Apr 04 03:15:18 PM PDT 24
Peak memory 248980 kb
Host smart-b766a4a2-2dfd-42e5-9e30-e6e688220935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29264
25202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2926425202
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1941732091
Short name T593
Test name
Test status
Simulation time 11849670688 ps
CPU time 1257.97 seconds
Started Apr 04 03:14:48 PM PDT 24
Finished Apr 04 03:35:46 PM PDT 24
Peak memory 290120 kb
Host smart-ac433b71-4686-46a5-86c9-a668322baa1a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941732091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1941732091
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2195838135
Short name T597
Test name
Test status
Simulation time 45970075467 ps
CPU time 722.11 seconds
Started Apr 04 03:14:50 PM PDT 24
Finished Apr 04 03:26:52 PM PDT 24
Peak memory 265640 kb
Host smart-2ddc9b85-3014-44fb-bf98-baf35ed88216
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195838135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2195838135
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3718279124
Short name T706
Test name
Test status
Simulation time 5440925049 ps
CPU time 258.69 seconds
Started Apr 04 03:14:51 PM PDT 24
Finished Apr 04 03:19:09 PM PDT 24
Peak memory 257216 kb
Host smart-17be75e3-5b5b-431b-a60a-de7648c4e1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37182
79124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3718279124
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2066334933
Short name T459
Test name
Test status
Simulation time 1380501452 ps
CPU time 23.3 seconds
Started Apr 04 03:14:51 PM PDT 24
Finished Apr 04 03:15:14 PM PDT 24
Peak memory 249084 kb
Host smart-061c1b96-37ac-4fc8-ad58-b26265bb8f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20663
34933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2066334933
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2468152625
Short name T347
Test name
Test status
Simulation time 115698411625 ps
CPU time 1143.92 seconds
Started Apr 04 03:15:00 PM PDT 24
Finished Apr 04 03:34:04 PM PDT 24
Peak memory 289044 kb
Host smart-c7ad7f6d-0f9c-4bfb-b2b3-e8a7229577fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468152625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2468152625
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.391108079
Short name T10
Test name
Test status
Simulation time 35441488633 ps
CPU time 2037.28 seconds
Started Apr 04 03:14:59 PM PDT 24
Finished Apr 04 03:48:57 PM PDT 24
Peak memory 273208 kb
Host smart-c88eb5b7-7666-42e2-8bae-a69cf0c13a11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391108079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.391108079
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.737788429
Short name T183
Test name
Test status
Simulation time 106382560664 ps
CPU time 430.26 seconds
Started Apr 04 03:15:01 PM PDT 24
Finished Apr 04 03:22:13 PM PDT 24
Peak memory 248068 kb
Host smart-4ebba87e-ce9e-4a11-89f0-0aaa6c0d6541
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737788429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.737788429
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1124366219
Short name T472
Test name
Test status
Simulation time 108957486 ps
CPU time 14.29 seconds
Started Apr 04 03:14:50 PM PDT 24
Finished Apr 04 03:15:05 PM PDT 24
Peak memory 249028 kb
Host smart-d492a1a8-4ea6-4952-9808-d5da04a09c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11243
66219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1124366219
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3157419252
Short name T579
Test name
Test status
Simulation time 697469884 ps
CPU time 35.34 seconds
Started Apr 04 03:14:52 PM PDT 24
Finished Apr 04 03:15:27 PM PDT 24
Peak memory 255688 kb
Host smart-d0a52d84-670e-40ad-b8e3-ab1f60417573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31574
19252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3157419252
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1357876797
Short name T283
Test name
Test status
Simulation time 574849321 ps
CPU time 30.51 seconds
Started Apr 04 03:14:52 PM PDT 24
Finished Apr 04 03:15:23 PM PDT 24
Peak memory 255940 kb
Host smart-e664a825-f7b4-4380-bac2-53fade634aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13578
76797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1357876797
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1377945159
Short name T548
Test name
Test status
Simulation time 765616360 ps
CPU time 18.6 seconds
Started Apr 04 03:14:49 PM PDT 24
Finished Apr 04 03:15:07 PM PDT 24
Peak memory 256208 kb
Host smart-2c817fa2-a4e3-48ee-a9b0-f316aef45685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13779
45159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1377945159
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1579451103
Short name T98
Test name
Test status
Simulation time 60068945292 ps
CPU time 2933.46 seconds
Started Apr 04 03:15:03 PM PDT 24
Finished Apr 04 04:03:57 PM PDT 24
Peak memory 299116 kb
Host smart-8056ba83-a148-4232-b14f-01713e681434
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579451103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1579451103
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2348596532
Short name T540
Test name
Test status
Simulation time 5401285622 ps
CPU time 41.84 seconds
Started Apr 04 03:15:01 PM PDT 24
Finished Apr 04 03:15:43 PM PDT 24
Peak memory 256248 kb
Host smart-370bfcab-373d-4818-a3fb-58657140ba2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23485
96532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2348596532
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1556635431
Short name T22
Test name
Test status
Simulation time 1443527710 ps
CPU time 40.41 seconds
Started Apr 04 03:15:00 PM PDT 24
Finished Apr 04 03:15:41 PM PDT 24
Peak memory 255440 kb
Host smart-c3ab3ccf-2798-468d-9453-89c811848143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15566
35431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1556635431
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.913470987
Short name T329
Test name
Test status
Simulation time 37861113491 ps
CPU time 818.44 seconds
Started Apr 04 03:15:01 PM PDT 24
Finished Apr 04 03:28:41 PM PDT 24
Peak memory 267580 kb
Host smart-f529dc13-1a48-4bf3-b8f9-d55b64d0c83c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913470987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.913470987
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2212420626
Short name T570
Test name
Test status
Simulation time 39353155915 ps
CPU time 859.11 seconds
Started Apr 04 03:15:02 PM PDT 24
Finished Apr 04 03:29:22 PM PDT 24
Peak memory 268628 kb
Host smart-0095fc1a-6762-4bc7-b821-408c5723fc94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212420626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2212420626
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1846044906
Short name T323
Test name
Test status
Simulation time 24316249336 ps
CPU time 204.03 seconds
Started Apr 04 03:15:02 PM PDT 24
Finished Apr 04 03:18:27 PM PDT 24
Peak memory 248224 kb
Host smart-0b9c07f8-9cef-4e7c-8a2e-3317f0a739f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846044906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1846044906
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3831974927
Short name T26
Test name
Test status
Simulation time 1830967512 ps
CPU time 29.27 seconds
Started Apr 04 03:14:59 PM PDT 24
Finished Apr 04 03:15:29 PM PDT 24
Peak memory 249080 kb
Host smart-b683b94c-b361-4e5b-955e-68e08cfe8be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38319
74927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3831974927
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.457671332
Short name T416
Test name
Test status
Simulation time 1193195735 ps
CPU time 37.15 seconds
Started Apr 04 03:14:59 PM PDT 24
Finished Apr 04 03:15:37 PM PDT 24
Peak memory 255564 kb
Host smart-4973f2eb-a5ee-43a0-9cbe-aefbb07e96d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45767
1332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.457671332
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.702164109
Short name T448
Test name
Test status
Simulation time 261329747 ps
CPU time 33.77 seconds
Started Apr 04 03:15:01 PM PDT 24
Finished Apr 04 03:15:36 PM PDT 24
Peak memory 247668 kb
Host smart-d36c7bf7-b9c0-4798-a67b-cd86424e6ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70216
4109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.702164109
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2133193428
Short name T63
Test name
Test status
Simulation time 1353709345 ps
CPU time 42.21 seconds
Started Apr 04 03:15:02 PM PDT 24
Finished Apr 04 03:15:45 PM PDT 24
Peak memory 249024 kb
Host smart-faf5d513-2cd2-476e-966b-a87f43672871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21331
93428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2133193428
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.1943567938
Short name T641
Test name
Test status
Simulation time 51489985453 ps
CPU time 5429.33 seconds
Started Apr 04 03:15:01 PM PDT 24
Finished Apr 04 04:45:31 PM PDT 24
Peak memory 338720 kb
Host smart-4e934a1b-48ff-4607-8789-d98f7d53cbfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943567938 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.1943567938
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1812871720
Short name T298
Test name
Test status
Simulation time 5416703977 ps
CPU time 93.86 seconds
Started Apr 04 03:15:02 PM PDT 24
Finished Apr 04 03:16:37 PM PDT 24
Peak memory 257032 kb
Host smart-3657edee-7960-4303-ab4d-8ab9415920d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18128
71720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1812871720
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2821809811
Short name T529
Test name
Test status
Simulation time 1071212206 ps
CPU time 23.88 seconds
Started Apr 04 03:15:00 PM PDT 24
Finished Apr 04 03:15:24 PM PDT 24
Peak memory 255736 kb
Host smart-edf2aeb1-a710-49ae-aa5a-1ba564e5d069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28218
09811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2821809811
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2689641836
Short name T645
Test name
Test status
Simulation time 351647493629 ps
CPU time 2423.68 seconds
Started Apr 04 03:15:00 PM PDT 24
Finished Apr 04 03:55:24 PM PDT 24
Peak memory 289396 kb
Host smart-0f10472c-8fd7-4316-9882-ed889399405a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689641836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2689641836
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.159281131
Short name T335
Test name
Test status
Simulation time 50353362321 ps
CPU time 539.82 seconds
Started Apr 04 03:14:59 PM PDT 24
Finished Apr 04 03:24:00 PM PDT 24
Peak memory 248216 kb
Host smart-9f051e09-21e9-436b-948c-d2223d403da9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159281131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.159281131
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3288067993
Short name T404
Test name
Test status
Simulation time 381460435 ps
CPU time 24.06 seconds
Started Apr 04 03:15:02 PM PDT 24
Finished Apr 04 03:15:28 PM PDT 24
Peak memory 249068 kb
Host smart-311a0890-04eb-481d-adbe-9088547f2d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32880
67993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3288067993
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3731791233
Short name T447
Test name
Test status
Simulation time 2226317687 ps
CPU time 43.21 seconds
Started Apr 04 03:15:01 PM PDT 24
Finished Apr 04 03:15:45 PM PDT 24
Peak memory 256252 kb
Host smart-cba11f96-0d22-4e7b-b1e1-49f51d93dbd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37317
91233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3731791233
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3798520462
Short name T264
Test name
Test status
Simulation time 418325661 ps
CPU time 9.84 seconds
Started Apr 04 03:15:00 PM PDT 24
Finished Apr 04 03:15:11 PM PDT 24
Peak memory 247604 kb
Host smart-55600210-3b19-481e-a2fd-0100c518f87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37985
20462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3798520462
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.934101277
Short name T407
Test name
Test status
Simulation time 177836763 ps
CPU time 15.36 seconds
Started Apr 04 03:15:01 PM PDT 24
Finished Apr 04 03:15:18 PM PDT 24
Peak memory 249428 kb
Host smart-b8b06eb3-3ce6-476f-a0db-20263e037e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93410
1277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.934101277
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.4251967801
Short name T53
Test name
Test status
Simulation time 8294900182 ps
CPU time 144.5 seconds
Started Apr 04 03:15:02 PM PDT 24
Finished Apr 04 03:17:27 PM PDT 24
Peak memory 257360 kb
Host smart-c41d5a08-d641-456d-9834-dda7e3b98722
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251967801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.4251967801
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.4049352306
Short name T178
Test name
Test status
Simulation time 31030027683 ps
CPU time 688.64 seconds
Started Apr 04 03:15:01 PM PDT 24
Finished Apr 04 03:26:30 PM PDT 24
Peak memory 273712 kb
Host smart-33d6ecd7-8d4c-42fa-90f7-45a4c14910c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049352306 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.4049352306
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1886324042
Short name T86
Test name
Test status
Simulation time 36512810358 ps
CPU time 2146.15 seconds
Started Apr 04 03:15:15 PM PDT 24
Finished Apr 04 03:51:01 PM PDT 24
Peak memory 289608 kb
Host smart-399b472d-1e77-4508-aee3-3eaefc3cdcdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886324042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1886324042
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.531745090
Short name T373
Test name
Test status
Simulation time 1725989079 ps
CPU time 61.93 seconds
Started Apr 04 03:15:14 PM PDT 24
Finished Apr 04 03:16:16 PM PDT 24
Peak memory 248948 kb
Host smart-861910dc-3e8c-4758-b60a-c4ad21582091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53174
5090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.531745090
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3045182172
Short name T670
Test name
Test status
Simulation time 2840155473 ps
CPU time 51.63 seconds
Started Apr 04 03:15:14 PM PDT 24
Finished Apr 04 03:16:06 PM PDT 24
Peak memory 249036 kb
Host smart-469f5568-901c-4c98-9cab-74fc14875b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30451
82172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3045182172
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1645912410
Short name T633
Test name
Test status
Simulation time 220865105242 ps
CPU time 3079.98 seconds
Started Apr 04 03:15:15 PM PDT 24
Finished Apr 04 04:06:35 PM PDT 24
Peak memory 289216 kb
Host smart-8fb9229e-901c-4be0-9033-57cf771ba83b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645912410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1645912410
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1762213751
Short name T483
Test name
Test status
Simulation time 98140439416 ps
CPU time 2821.78 seconds
Started Apr 04 03:15:12 PM PDT 24
Finished Apr 04 04:02:14 PM PDT 24
Peak memory 289376 kb
Host smart-86f96115-912b-4c4f-a6b9-ab8337f0b003
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762213751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1762213751
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1101576560
Short name T322
Test name
Test status
Simulation time 12325178662 ps
CPU time 432.61 seconds
Started Apr 04 03:15:15 PM PDT 24
Finished Apr 04 03:22:28 PM PDT 24
Peak memory 248028 kb
Host smart-103831b4-efac-4335-ae9d-0e34114dcff9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101576560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1101576560
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.644735126
Short name T600
Test name
Test status
Simulation time 200808183 ps
CPU time 21.58 seconds
Started Apr 04 03:15:15 PM PDT 24
Finished Apr 04 03:15:36 PM PDT 24
Peak memory 249024 kb
Host smart-0449ef4b-0866-4eae-8c23-60ce9ce82d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64473
5126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.644735126
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.489961095
Short name T80
Test name
Test status
Simulation time 760232626 ps
CPU time 49.02 seconds
Started Apr 04 03:15:14 PM PDT 24
Finished Apr 04 03:16:03 PM PDT 24
Peak memory 248908 kb
Host smart-1f632948-29a7-48a9-9ae6-7984a35f0088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48996
1095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.489961095
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.659526055
Short name T592
Test name
Test status
Simulation time 4488988427 ps
CPU time 45.54 seconds
Started Apr 04 03:15:15 PM PDT 24
Finished Apr 04 03:16:01 PM PDT 24
Peak memory 249172 kb
Host smart-cc0091d2-ba5b-4068-a9d8-78671b06eea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65952
6055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.659526055
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.720207723
Short name T495
Test name
Test status
Simulation time 365704147 ps
CPU time 35.05 seconds
Started Apr 04 03:15:16 PM PDT 24
Finished Apr 04 03:15:52 PM PDT 24
Peak memory 256212 kb
Host smart-3713a4b5-74dc-42d5-9f9b-4c8af87bdde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72020
7723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.720207723
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.408117700
Short name T28
Test name
Test status
Simulation time 142644905645 ps
CPU time 3916.64 seconds
Started Apr 04 03:15:13 PM PDT 24
Finished Apr 04 04:20:31 PM PDT 24
Peak memory 301440 kb
Host smart-bfc83bb6-b38d-46b9-829a-ec38c3c6a9a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408117700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.408117700
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1057747012
Short name T710
Test name
Test status
Simulation time 89463038827 ps
CPU time 1571.52 seconds
Started Apr 04 03:15:16 PM PDT 24
Finished Apr 04 03:41:28 PM PDT 24
Peak memory 273736 kb
Host smart-d67b29d1-f01e-4b41-8651-8db41d2c3304
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057747012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1057747012
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.4022622453
Short name T563
Test name
Test status
Simulation time 23457647783 ps
CPU time 303.6 seconds
Started Apr 04 03:15:14 PM PDT 24
Finished Apr 04 03:20:18 PM PDT 24
Peak memory 257276 kb
Host smart-b0769618-4fee-4166-b52a-4b5c6dc4ed1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40226
22453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4022622453
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3515050581
Short name T693
Test name
Test status
Simulation time 1279999793 ps
CPU time 19.49 seconds
Started Apr 04 03:15:13 PM PDT 24
Finished Apr 04 03:15:33 PM PDT 24
Peak memory 254936 kb
Host smart-656ca454-ce7e-499b-8aa1-02782bd000ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35150
50581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3515050581
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3367624342
Short name T242
Test name
Test status
Simulation time 225617735114 ps
CPU time 3276.09 seconds
Started Apr 04 03:15:13 PM PDT 24
Finished Apr 04 04:09:50 PM PDT 24
Peak memory 289188 kb
Host smart-b5c81b3a-541a-438a-9b09-d1eb0094b7d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367624342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3367624342
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3361612054
Short name T400
Test name
Test status
Simulation time 36048240040 ps
CPU time 1237.82 seconds
Started Apr 04 03:15:16 PM PDT 24
Finished Apr 04 03:35:54 PM PDT 24
Peak memory 267760 kb
Host smart-78a22d9f-bf28-41cf-be37-986403649652
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361612054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3361612054
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.67881835
Short name T310
Test name
Test status
Simulation time 16190507515 ps
CPU time 595.26 seconds
Started Apr 04 03:15:16 PM PDT 24
Finished Apr 04 03:25:11 PM PDT 24
Peak memory 247292 kb
Host smart-f859b558-0895-4b1f-b3f7-408aac2b7934
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67881835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.67881835
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.260175984
Short name T446
Test name
Test status
Simulation time 842652597 ps
CPU time 39.45 seconds
Started Apr 04 03:15:16 PM PDT 24
Finished Apr 04 03:15:55 PM PDT 24
Peak memory 248928 kb
Host smart-8e1dacc1-d5d3-4f84-aeb7-68045a435a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26017
5984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.260175984
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2399225092
Short name T537
Test name
Test status
Simulation time 1330401241 ps
CPU time 44.51 seconds
Started Apr 04 03:15:16 PM PDT 24
Finished Apr 04 03:16:01 PM PDT 24
Peak memory 254960 kb
Host smart-8c2baa9f-0b5e-4d49-87f1-cda373778291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23992
25092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2399225092
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1776240472
Short name T54
Test name
Test status
Simulation time 837642697 ps
CPU time 55.87 seconds
Started Apr 04 03:15:14 PM PDT 24
Finished Apr 04 03:16:10 PM PDT 24
Peak memory 255792 kb
Host smart-8ff90126-f86f-4d67-b8fc-462e25a83c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17762
40472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1776240472
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3824081524
Short name T506
Test name
Test status
Simulation time 303356479 ps
CPU time 4.38 seconds
Started Apr 04 03:15:16 PM PDT 24
Finished Apr 04 03:15:20 PM PDT 24
Peak memory 240732 kb
Host smart-cdccea57-2297-4c99-9d5b-f4739269458c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38240
81524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3824081524
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2836777051
Short name T237
Test name
Test status
Simulation time 24794439260 ps
CPU time 1711.18 seconds
Started Apr 04 03:15:13 PM PDT 24
Finished Apr 04 03:43:44 PM PDT 24
Peak memory 271132 kb
Host smart-afe4daea-2255-4426-9cba-ad534da1f803
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836777051 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2836777051
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.351304631
Short name T632
Test name
Test status
Simulation time 11801934771 ps
CPU time 1068.66 seconds
Started Apr 04 03:15:15 PM PDT 24
Finished Apr 04 03:33:04 PM PDT 24
Peak memory 273240 kb
Host smart-76f3609b-e19a-45f7-8141-07eda9a2c50f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351304631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.351304631
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2482840670
Short name T485
Test name
Test status
Simulation time 9122217246 ps
CPU time 44.98 seconds
Started Apr 04 03:15:15 PM PDT 24
Finished Apr 04 03:16:00 PM PDT 24
Peak memory 256588 kb
Host smart-38089954-ce17-4525-9683-459592fe77a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24828
40670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2482840670
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.299123263
Short name T99
Test name
Test status
Simulation time 2185439747 ps
CPU time 33.9 seconds
Started Apr 04 03:15:13 PM PDT 24
Finished Apr 04 03:15:47 PM PDT 24
Peak memory 256004 kb
Host smart-0d41970d-865b-43ef-987a-001332bbfeb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29912
3263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.299123263
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2833644427
Short name T350
Test name
Test status
Simulation time 91060584471 ps
CPU time 2570.51 seconds
Started Apr 04 03:15:13 PM PDT 24
Finished Apr 04 03:58:04 PM PDT 24
Peak memory 289140 kb
Host smart-34a600e8-5b0c-4e9b-a3c9-33aae33ad2ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833644427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2833644427
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3106126627
Short name T226
Test name
Test status
Simulation time 23651369667 ps
CPU time 871.96 seconds
Started Apr 04 03:15:14 PM PDT 24
Finished Apr 04 03:29:46 PM PDT 24
Peak memory 273024 kb
Host smart-cd4d1668-f7d7-47b4-83a4-109ac91cb638
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106126627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3106126627
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2999627929
Short name T326
Test name
Test status
Simulation time 4926012356 ps
CPU time 199.64 seconds
Started Apr 04 03:15:15 PM PDT 24
Finished Apr 04 03:18:35 PM PDT 24
Peak memory 248392 kb
Host smart-650f12a6-1721-4895-8380-25c36962342c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999627929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2999627929
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1743619758
Short name T222
Test name
Test status
Simulation time 1203107838 ps
CPU time 44.48 seconds
Started Apr 04 03:15:14 PM PDT 24
Finished Apr 04 03:15:59 PM PDT 24
Peak memory 249064 kb
Host smart-f9c07c45-7016-4b9a-99f6-2f9a260cd932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17436
19758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1743619758
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2630084806
Short name T630
Test name
Test status
Simulation time 3382846458 ps
CPU time 43.5 seconds
Started Apr 04 03:15:14 PM PDT 24
Finished Apr 04 03:15:57 PM PDT 24
Peak memory 249184 kb
Host smart-14b523e3-de6d-4b16-8c29-d06ffbb12df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26300
84806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2630084806
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3389794412
Short name T525
Test name
Test status
Simulation time 276088885 ps
CPU time 31.96 seconds
Started Apr 04 03:15:15 PM PDT 24
Finished Apr 04 03:15:48 PM PDT 24
Peak memory 255676 kb
Host smart-19e05955-96c4-4178-8f0b-fb89560c7151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33897
94412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3389794412
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1077051412
Short name T477
Test name
Test status
Simulation time 2265034553 ps
CPU time 67.86 seconds
Started Apr 04 03:15:14 PM PDT 24
Finished Apr 04 03:16:22 PM PDT 24
Peak memory 249204 kb
Host smart-ff9ce63e-f6bd-426e-86d8-4ba3ba4437df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10770
51412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1077051412
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1614577311
Short name T277
Test name
Test status
Simulation time 9301222598 ps
CPU time 1268.1 seconds
Started Apr 04 03:15:14 PM PDT 24
Finished Apr 04 03:36:22 PM PDT 24
Peak memory 285560 kb
Host smart-4b9b058e-746b-4f4c-8889-0c58fcf1e085
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614577311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1614577311
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2059730721
Short name T607
Test name
Test status
Simulation time 77222294559 ps
CPU time 1153.04 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:34:44 PM PDT 24
Peak memory 265544 kb
Host smart-44579af6-1bfe-4d13-8727-080181f87801
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059730721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2059730721
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3908555063
Short name T704
Test name
Test status
Simulation time 5154960576 ps
CPU time 141.94 seconds
Started Apr 04 03:15:29 PM PDT 24
Finished Apr 04 03:17:51 PM PDT 24
Peak memory 257064 kb
Host smart-bfcd418b-9e6d-40ee-b45f-7341d5a508af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39085
55063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3908555063
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.4248040383
Short name T38
Test name
Test status
Simulation time 3782049239 ps
CPU time 32.15 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:16:03 PM PDT 24
Peak memory 255856 kb
Host smart-c6b0f4ce-d55f-441c-bbb0-2affe7829d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42480
40383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.4248040383
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.313802185
Short name T327
Test name
Test status
Simulation time 186531522578 ps
CPU time 2548.19 seconds
Started Apr 04 03:15:31 PM PDT 24
Finished Apr 04 03:58:00 PM PDT 24
Peak memory 289372 kb
Host smart-352cea40-b576-4840-b6e9-6509948b0a6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313802185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.313802185
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.516981553
Short name T642
Test name
Test status
Simulation time 10276189805 ps
CPU time 1126.21 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:34:17 PM PDT 24
Peak memory 281732 kb
Host smart-f4d00bea-e687-4f98-be27-5b7520fced1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516981553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.516981553
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.868761647
Short name T308
Test name
Test status
Simulation time 10077559155 ps
CPU time 403.14 seconds
Started Apr 04 03:15:29 PM PDT 24
Finished Apr 04 03:22:13 PM PDT 24
Peak memory 248280 kb
Host smart-359b8329-03c8-490e-bc65-420ca4472f77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868761647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.868761647
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.392120709
Short name T583
Test name
Test status
Simulation time 1288707753 ps
CPU time 36 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:16:07 PM PDT 24
Peak memory 249000 kb
Host smart-aa869192-0b5d-4c2b-84ac-555269e65ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39212
0709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.392120709
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2216023042
Short name T456
Test name
Test status
Simulation time 759913645 ps
CPU time 26.08 seconds
Started Apr 04 03:15:32 PM PDT 24
Finished Apr 04 03:15:58 PM PDT 24
Peak memory 248848 kb
Host smart-8a32a7ab-65fc-4f1c-85dc-b37cf971093e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22160
23042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2216023042
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2622013743
Short name T272
Test name
Test status
Simulation time 2313320469 ps
CPU time 36.42 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:16:07 PM PDT 24
Peak memory 249168 kb
Host smart-82b8fb37-0e53-4581-9227-cae8dbad9e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26220
13743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2622013743
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2429132661
Short name T431
Test name
Test status
Simulation time 3610277262 ps
CPU time 57.13 seconds
Started Apr 04 03:15:17 PM PDT 24
Finished Apr 04 03:16:14 PM PDT 24
Peak memory 256540 kb
Host smart-7b47c313-41ba-46bd-86c9-60c2aeceb0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24291
32661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2429132661
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2552567290
Short name T81
Test name
Test status
Simulation time 406989148 ps
CPU time 28.9 seconds
Started Apr 04 03:15:35 PM PDT 24
Finished Apr 04 03:16:04 PM PDT 24
Peak memory 255576 kb
Host smart-d3cc5857-45ba-4d1b-a946-c7adf5076694
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552567290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2552567290
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3271744947
Short name T654
Test name
Test status
Simulation time 385224981682 ps
CPU time 1395.57 seconds
Started Apr 04 03:15:32 PM PDT 24
Finished Apr 04 03:38:48 PM PDT 24
Peak memory 273708 kb
Host smart-cd6cb45f-8756-46c2-9cd9-262597e172c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271744947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3271744947
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.169138649
Short name T285
Test name
Test status
Simulation time 4876013187 ps
CPU time 50.95 seconds
Started Apr 04 03:15:35 PM PDT 24
Finished Apr 04 03:16:26 PM PDT 24
Peak memory 255872 kb
Host smart-8f2ff761-80a5-4656-bded-ed415e46d67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16913
8649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.169138649
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1668069800
Short name T482
Test name
Test status
Simulation time 175633488 ps
CPU time 7.2 seconds
Started Apr 04 03:15:32 PM PDT 24
Finished Apr 04 03:15:40 PM PDT 24
Peak memory 250104 kb
Host smart-f932f890-02c9-450d-adad-4338d14e41ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16680
69800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1668069800
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3004936498
Short name T617
Test name
Test status
Simulation time 81641898051 ps
CPU time 2247.8 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:52:59 PM PDT 24
Peak memory 281928 kb
Host smart-5b7ec82f-1fc9-4dbd-9c94-fecc14ee7eec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004936498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3004936498
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1234560616
Short name T316
Test name
Test status
Simulation time 9455545369 ps
CPU time 192.18 seconds
Started Apr 04 03:15:35 PM PDT 24
Finished Apr 04 03:18:47 PM PDT 24
Peak memory 248220 kb
Host smart-a1d22680-9c29-43df-a524-8d506d612e24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234560616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1234560616
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1753604372
Short name T491
Test name
Test status
Simulation time 1722185392 ps
CPU time 53.68 seconds
Started Apr 04 03:15:29 PM PDT 24
Finished Apr 04 03:16:23 PM PDT 24
Peak memory 249348 kb
Host smart-3f582072-85d7-49fd-a246-461b18133d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17536
04372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1753604372
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.4130814298
Short name T437
Test name
Test status
Simulation time 288669007 ps
CPU time 31.25 seconds
Started Apr 04 03:15:35 PM PDT 24
Finished Apr 04 03:16:06 PM PDT 24
Peak memory 256756 kb
Host smart-a0ef7670-f832-48c9-83c0-168fe7561380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41308
14298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.4130814298
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2964538332
Short name T453
Test name
Test status
Simulation time 680554806 ps
CPU time 41.6 seconds
Started Apr 04 03:15:31 PM PDT 24
Finished Apr 04 03:16:13 PM PDT 24
Peak memory 256152 kb
Host smart-0c66ec6b-0943-46ce-9e5f-2e98aa838298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29645
38332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2964538332
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2819689590
Short name T494
Test name
Test status
Simulation time 35704167101 ps
CPU time 712.18 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:27:23 PM PDT 24
Peak memory 269636 kb
Host smart-01584231-756a-4a51-be1d-039307a06157
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819689590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2819689590
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3181045725
Short name T43
Test name
Test status
Simulation time 60224864 ps
CPU time 2.6 seconds
Started Apr 04 03:13:45 PM PDT 24
Finished Apr 04 03:13:48 PM PDT 24
Peak memory 249364 kb
Host smart-d36263b4-a23c-4cd4-93e2-f22a33eb7111
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3181045725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3181045725
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.807934626
Short name T69
Test name
Test status
Simulation time 175405446977 ps
CPU time 2336.11 seconds
Started Apr 04 03:13:54 PM PDT 24
Finished Apr 04 03:52:51 PM PDT 24
Peak memory 289476 kb
Host smart-8d01abfe-cc94-4df5-8d1d-d502f22d9453
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807934626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.807934626
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2082144422
Short name T458
Test name
Test status
Simulation time 189252447 ps
CPU time 10.86 seconds
Started Apr 04 03:13:46 PM PDT 24
Finished Apr 04 03:13:57 PM PDT 24
Peak memory 240836 kb
Host smart-6a749a8d-cb96-44d0-a3f7-10bf53e0b4a7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2082144422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2082144422
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.4027662901
Short name T248
Test name
Test status
Simulation time 2479348464 ps
CPU time 116.61 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:15:50 PM PDT 24
Peak memory 257080 kb
Host smart-3ac65e05-158a-4fe0-abe2-6353470e2203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40276
62901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.4027662901
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1748614014
Short name T565
Test name
Test status
Simulation time 649870409 ps
CPU time 39.3 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:14:31 PM PDT 24
Peak memory 255172 kb
Host smart-d1b5f88f-8c69-4b06-9606-74fc76c99012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17486
14014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1748614014
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2000666336
Short name T426
Test name
Test status
Simulation time 66143590986 ps
CPU time 1538.07 seconds
Started Apr 04 03:13:54 PM PDT 24
Finished Apr 04 03:39:33 PM PDT 24
Peak memory 290124 kb
Host smart-cda1b37e-841b-45f2-8b3f-2987f3a1de08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000666336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2000666336
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3549944396
Short name T68
Test name
Test status
Simulation time 102564719846 ps
CPU time 1594.55 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:40:26 PM PDT 24
Peak memory 267604 kb
Host smart-937d99b7-b6d8-44de-8210-30adaabba8a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549944396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3549944396
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1418717726
Short name T473
Test name
Test status
Simulation time 683917031 ps
CPU time 38.63 seconds
Started Apr 04 03:13:52 PM PDT 24
Finished Apr 04 03:14:32 PM PDT 24
Peak memory 256220 kb
Host smart-a4fa490b-f5ac-4fa7-9fc9-63332d4d94e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14187
17726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1418717726
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.340506993
Short name T469
Test name
Test status
Simulation time 304718989 ps
CPU time 9.44 seconds
Started Apr 04 03:13:53 PM PDT 24
Finished Apr 04 03:14:03 PM PDT 24
Peak memory 252668 kb
Host smart-c86d7938-d6ae-4a98-99b8-2b40e6668ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34050
6993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.340506993
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.313457368
Short name T32
Test name
Test status
Simulation time 424976563 ps
CPU time 13.48 seconds
Started Apr 04 03:13:46 PM PDT 24
Finished Apr 04 03:14:00 PM PDT 24
Peak memory 265660 kb
Host smart-49094e7f-78ed-4d2e-83c1-d7331b29bfb7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=313457368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.313457368
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3279463532
Short name T114
Test name
Test status
Simulation time 3371936095 ps
CPU time 42.07 seconds
Started Apr 04 03:13:45 PM PDT 24
Finished Apr 04 03:14:27 PM PDT 24
Peak memory 255656 kb
Host smart-4e3609aa-6ae8-4921-be36-f430367047a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32794
63532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3279463532
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3906752325
Short name T701
Test name
Test status
Simulation time 460776402 ps
CPU time 25.03 seconds
Started Apr 04 03:13:49 PM PDT 24
Finished Apr 04 03:14:15 PM PDT 24
Peak memory 256236 kb
Host smart-d97bd425-d372-424b-96af-78a3ac30ab6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39067
52325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3906752325
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.4046472578
Short name T591
Test name
Test status
Simulation time 26818207524 ps
CPU time 1872.68 seconds
Started Apr 04 03:13:50 PM PDT 24
Finished Apr 04 03:45:03 PM PDT 24
Peak memory 281944 kb
Host smart-290bdad6-6efa-4a8d-97bc-7ddb4b1c231e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046472578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.4046472578
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3768343706
Short name T513
Test name
Test status
Simulation time 45198675964 ps
CPU time 1069.69 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:33:20 PM PDT 24
Peak memory 284428 kb
Host smart-04dbf220-6f5e-4805-abdc-f02b4d02dc2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768343706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3768343706
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1027877812
Short name T229
Test name
Test status
Simulation time 2712402793 ps
CPU time 121.78 seconds
Started Apr 04 03:15:31 PM PDT 24
Finished Apr 04 03:17:33 PM PDT 24
Peak memory 250084 kb
Host smart-d4f8fabd-1d64-4b22-90c2-0899469d2542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10278
77812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1027877812
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2507790343
Short name T577
Test name
Test status
Simulation time 170031715 ps
CPU time 7.45 seconds
Started Apr 04 03:15:32 PM PDT 24
Finished Apr 04 03:15:39 PM PDT 24
Peak memory 249160 kb
Host smart-f9f1d5d8-022b-40f5-a14e-33808959e132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25077
90343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2507790343
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.83582900
Short name T13
Test name
Test status
Simulation time 56223962385 ps
CPU time 1552.04 seconds
Started Apr 04 03:15:31 PM PDT 24
Finished Apr 04 03:41:23 PM PDT 24
Peak memory 265640 kb
Host smart-6adbe103-a2d3-422d-a1e1-dd7b47f4a4b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83582900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.83582900
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1244926665
Short name T442
Test name
Test status
Simulation time 55043767249 ps
CPU time 2441.77 seconds
Started Apr 04 03:15:31 PM PDT 24
Finished Apr 04 03:56:13 PM PDT 24
Peak memory 289704 kb
Host smart-0d09faac-8f4b-4428-b257-47608b3eab8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244926665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1244926665
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.197439500
Short name T379
Test name
Test status
Simulation time 131997349 ps
CPU time 4.83 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:15:35 PM PDT 24
Peak memory 240880 kb
Host smart-a009f6a9-335b-4723-bbde-b9c4c7620994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19743
9500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.197439500
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3663172778
Short name T669
Test name
Test status
Simulation time 947527052 ps
CPU time 17.55 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:15:48 PM PDT 24
Peak memory 253292 kb
Host smart-edc3ed64-e639-44de-b627-3c0a86d33b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36631
72778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3663172778
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.10206676
Short name T265
Test name
Test status
Simulation time 3308689310 ps
CPU time 62.06 seconds
Started Apr 04 03:15:32 PM PDT 24
Finished Apr 04 03:16:34 PM PDT 24
Peak memory 248148 kb
Host smart-fe1f4ab5-b690-4cd9-8d74-56d48370ec02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10206
676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.10206676
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.319804093
Short name T60
Test name
Test status
Simulation time 731000540 ps
CPU time 27.27 seconds
Started Apr 04 03:15:31 PM PDT 24
Finished Apr 04 03:15:59 PM PDT 24
Peak memory 249064 kb
Host smart-08e3aedd-a0af-40f5-9c2f-2a3a063c198e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31980
4093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.319804093
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2583088603
Short name T260
Test name
Test status
Simulation time 81296818357 ps
CPU time 300.23 seconds
Started Apr 04 03:15:29 PM PDT 24
Finished Apr 04 03:20:30 PM PDT 24
Peak memory 252172 kb
Host smart-43be754e-9d07-4e80-841e-360ba1f160a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583088603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2583088603
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1802129522
Short name T251
Test name
Test status
Simulation time 31932171225 ps
CPU time 2886.94 seconds
Started Apr 04 03:15:31 PM PDT 24
Finished Apr 04 04:03:38 PM PDT 24
Peak memory 322968 kb
Host smart-4316719a-42d4-457f-a9a7-c6a6cff4be02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802129522 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1802129522
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3785279917
Short name T56
Test name
Test status
Simulation time 56826656281 ps
CPU time 1029.62 seconds
Started Apr 04 03:15:45 PM PDT 24
Finished Apr 04 03:32:54 PM PDT 24
Peak memory 270764 kb
Host smart-89d70ef1-788d-4087-9cdc-44c70186184a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785279917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3785279917
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2448599541
Short name T186
Test name
Test status
Simulation time 1131360729 ps
CPU time 19.64 seconds
Started Apr 04 03:15:44 PM PDT 24
Finished Apr 04 03:16:04 PM PDT 24
Peak memory 256128 kb
Host smart-1941eb13-54da-4301-813c-853c7fb36980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24485
99541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2448599541
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1858228263
Short name T486
Test name
Test status
Simulation time 2811361947 ps
CPU time 46.78 seconds
Started Apr 04 03:15:43 PM PDT 24
Finished Apr 04 03:16:30 PM PDT 24
Peak memory 255184 kb
Host smart-909545ab-b263-417f-b6e4-1b62740cc125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18582
28263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1858228263
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3407609056
Short name T334
Test name
Test status
Simulation time 197912797147 ps
CPU time 1727.69 seconds
Started Apr 04 03:15:44 PM PDT 24
Finished Apr 04 03:44:32 PM PDT 24
Peak memory 273016 kb
Host smart-738f2d55-b44e-419d-b935-a1e351f0b09c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407609056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3407609056
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1706758608
Short name T644
Test name
Test status
Simulation time 49352369188 ps
CPU time 1141.57 seconds
Started Apr 04 03:15:45 PM PDT 24
Finished Apr 04 03:34:47 PM PDT 24
Peak memory 283652 kb
Host smart-8c8bbf97-cdc5-4106-a3a4-014dcb2f43b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706758608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1706758608
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3741245166
Short name T703
Test name
Test status
Simulation time 3792959844 ps
CPU time 79.71 seconds
Started Apr 04 03:15:45 PM PDT 24
Finished Apr 04 03:17:04 PM PDT 24
Peak memory 248328 kb
Host smart-5f4186de-c7d0-4446-aa29-13f299dad76c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741245166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3741245166
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.241272531
Short name T383
Test name
Test status
Simulation time 830148003 ps
CPU time 21.47 seconds
Started Apr 04 03:15:31 PM PDT 24
Finished Apr 04 03:15:53 PM PDT 24
Peak memory 249036 kb
Host smart-1fd980cb-5a85-4ec5-8c03-f926ded5f90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24127
2531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.241272531
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3543296233
Short name T295
Test name
Test status
Simulation time 888564680 ps
CPU time 12.87 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:15:43 PM PDT 24
Peak memory 249272 kb
Host smart-beafb0e8-128f-4ee7-8fe3-f7845b292cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35432
96233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3543296233
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.42091066
Short name T647
Test name
Test status
Simulation time 263004530 ps
CPU time 34.33 seconds
Started Apr 04 03:15:47 PM PDT 24
Finished Apr 04 03:16:22 PM PDT 24
Peak memory 255792 kb
Host smart-0ca1d220-98c3-4e8b-9643-546de76975ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42091
066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.42091066
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.64683224
Short name T572
Test name
Test status
Simulation time 1265536498 ps
CPU time 21.17 seconds
Started Apr 04 03:15:30 PM PDT 24
Finished Apr 04 03:15:52 PM PDT 24
Peak memory 249176 kb
Host smart-e312b25a-fb7c-49d2-b421-5449c47758bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64683
224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.64683224
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3895635532
Short name T104
Test name
Test status
Simulation time 43138347257 ps
CPU time 4448.72 seconds
Started Apr 04 03:15:43 PM PDT 24
Finished Apr 04 04:29:52 PM PDT 24
Peak memory 338860 kb
Host smart-861b3a10-a713-4a12-9ae9-e55192b1081a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895635532 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3895635532
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2834266971
Short name T505
Test name
Test status
Simulation time 90845015789 ps
CPU time 1775.68 seconds
Started Apr 04 03:15:45 PM PDT 24
Finished Apr 04 03:45:21 PM PDT 24
Peak memory 273732 kb
Host smart-c7844e18-3575-4786-acbb-1291332d82d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834266971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2834266971
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3234311237
Short name T399
Test name
Test status
Simulation time 1857336827 ps
CPU time 105.42 seconds
Started Apr 04 03:15:47 PM PDT 24
Finished Apr 04 03:17:33 PM PDT 24
Peak memory 256920 kb
Host smart-0fdda0b8-8205-40a3-8207-7c8116ded106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32343
11237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3234311237
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1046496525
Short name T386
Test name
Test status
Simulation time 388476817 ps
CPU time 36.01 seconds
Started Apr 04 03:15:49 PM PDT 24
Finished Apr 04 03:16:25 PM PDT 24
Peak memory 255744 kb
Host smart-05d5e51c-274f-4ce1-be19-12d2dce2d7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10464
96525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1046496525
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1178118354
Short name T555
Test name
Test status
Simulation time 43091349348 ps
CPU time 2513.48 seconds
Started Apr 04 03:15:44 PM PDT 24
Finished Apr 04 03:57:38 PM PDT 24
Peak memory 289124 kb
Host smart-4ac5c9a7-fda0-440d-b661-ff11c63d2b47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178118354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1178118354
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3366624450
Short name T619
Test name
Test status
Simulation time 14732623826 ps
CPU time 369.93 seconds
Started Apr 04 03:15:44 PM PDT 24
Finished Apr 04 03:21:54 PM PDT 24
Peak memory 249144 kb
Host smart-407c4d49-c094-4ca6-9af8-27e404cc0838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366624450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3366624450
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3747467428
Short name T372
Test name
Test status
Simulation time 146368986 ps
CPU time 10.54 seconds
Started Apr 04 03:15:48 PM PDT 24
Finished Apr 04 03:15:59 PM PDT 24
Peak memory 249084 kb
Host smart-1fe23c7d-9747-427e-a68a-e8077e7ef749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37474
67428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3747467428
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2164500710
Short name T594
Test name
Test status
Simulation time 399458987 ps
CPU time 34.02 seconds
Started Apr 04 03:15:48 PM PDT 24
Finished Apr 04 03:16:22 PM PDT 24
Peak memory 255044 kb
Host smart-f787b1c0-6ba7-4afc-a76e-c0b8d336ec86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21645
00710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2164500710
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1941853339
Short name T110
Test name
Test status
Simulation time 2144951424 ps
CPU time 28.15 seconds
Started Apr 04 03:15:46 PM PDT 24
Finished Apr 04 03:16:15 PM PDT 24
Peak memory 249084 kb
Host smart-ba4d73b4-6b05-4891-b007-f3b67dad8c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19418
53339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1941853339
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1162152652
Short name T496
Test name
Test status
Simulation time 589209675 ps
CPU time 36.41 seconds
Started Apr 04 03:15:42 PM PDT 24
Finished Apr 04 03:16:19 PM PDT 24
Peak memory 256208 kb
Host smart-446d2981-184a-4896-a7d4-24755e5c172d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11621
52652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1162152652
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2715077071
Short name T628
Test name
Test status
Simulation time 14302822809 ps
CPU time 1103.01 seconds
Started Apr 04 03:15:43 PM PDT 24
Finished Apr 04 03:34:06 PM PDT 24
Peak memory 283260 kb
Host smart-b138da3a-07e8-442e-9b69-64fc5c52f1de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715077071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2715077071
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3218807897
Short name T586
Test name
Test status
Simulation time 235987536224 ps
CPU time 2740.81 seconds
Started Apr 04 03:15:45 PM PDT 24
Finished Apr 04 04:01:27 PM PDT 24
Peak memory 290248 kb
Host smart-6bb470f8-1363-49a1-9bca-824aa5b594e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218807897 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3218807897
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1800456853
Short name T294
Test name
Test status
Simulation time 195949552207 ps
CPU time 2072.33 seconds
Started Apr 04 03:15:44 PM PDT 24
Finished Apr 04 03:50:16 PM PDT 24
Peak memory 281908 kb
Host smart-4587936c-9c16-4fa7-bef0-3a9597ad8645
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800456853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1800456853
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.134060876
Short name T574
Test name
Test status
Simulation time 565723561 ps
CPU time 19.92 seconds
Started Apr 04 03:15:46 PM PDT 24
Finished Apr 04 03:16:06 PM PDT 24
Peak memory 256552 kb
Host smart-9bd795d2-c149-4b5c-bb46-faf4f62b40a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13406
0876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.134060876
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2419290122
Short name T245
Test name
Test status
Simulation time 292601353 ps
CPU time 33.29 seconds
Started Apr 04 03:15:45 PM PDT 24
Finished Apr 04 03:16:18 PM PDT 24
Peak memory 255568 kb
Host smart-b793e308-ade9-458a-8963-f7dfc62c17a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24192
90122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2419290122
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1907292804
Short name T302
Test name
Test status
Simulation time 46959850211 ps
CPU time 927.74 seconds
Started Apr 04 03:15:47 PM PDT 24
Finished Apr 04 03:31:15 PM PDT 24
Peak memory 268604 kb
Host smart-752167f9-4729-4d4b-b6e3-6a56f1c730c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907292804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1907292804
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2771743100
Short name T66
Test name
Test status
Simulation time 20910972820 ps
CPU time 1168.35 seconds
Started Apr 04 03:15:44 PM PDT 24
Finished Apr 04 03:35:13 PM PDT 24
Peak memory 273720 kb
Host smart-2132b7d6-0889-4210-80ac-5bfde9416e18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771743100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2771743100
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.86370822
Short name T325
Test name
Test status
Simulation time 8267224928 ps
CPU time 90.77 seconds
Started Apr 04 03:15:46 PM PDT 24
Finished Apr 04 03:17:17 PM PDT 24
Peak memory 248336 kb
Host smart-9ae91e6f-d4c5-4d2d-8362-0256f8506f4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86370822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.86370822
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3010087012
Short name T50
Test name
Test status
Simulation time 2311251097 ps
CPU time 31.39 seconds
Started Apr 04 03:15:44 PM PDT 24
Finished Apr 04 03:16:16 PM PDT 24
Peak memory 255628 kb
Host smart-31510989-8001-4563-8428-2b0df2538eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30100
87012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3010087012
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2501326280
Short name T490
Test name
Test status
Simulation time 6773537454 ps
CPU time 43.75 seconds
Started Apr 04 03:15:46 PM PDT 24
Finished Apr 04 03:16:30 PM PDT 24
Peak memory 248960 kb
Host smart-1caa376e-38a9-4f60-aee5-499ca7274a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25013
26280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2501326280
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.741083854
Short name T256
Test name
Test status
Simulation time 655969204 ps
CPU time 45.42 seconds
Started Apr 04 03:15:47 PM PDT 24
Finished Apr 04 03:16:32 PM PDT 24
Peak memory 249032 kb
Host smart-8827a950-a509-4e19-8b59-71433a55526e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74108
3854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.741083854
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.191668816
Short name T31
Test name
Test status
Simulation time 655228140 ps
CPU time 26.26 seconds
Started Apr 04 03:15:47 PM PDT 24
Finished Apr 04 03:16:14 PM PDT 24
Peak memory 248992 kb
Host smart-4ce989ef-aa26-4112-90a4-79b4d07b6b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19166
8816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.191668816
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3953111336
Short name T656
Test name
Test status
Simulation time 95067589924 ps
CPU time 2774.53 seconds
Started Apr 04 03:15:44 PM PDT 24
Finished Apr 04 04:01:59 PM PDT 24
Peak memory 289896 kb
Host smart-9c981576-44be-43c0-b24d-cef6f0bd1cc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953111336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3953111336
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2049092354
Short name T500
Test name
Test status
Simulation time 2258028828 ps
CPU time 120.77 seconds
Started Apr 04 03:15:45 PM PDT 24
Finished Apr 04 03:17:45 PM PDT 24
Peak memory 257336 kb
Host smart-8771e1ef-fe7c-4601-826f-dedda211494d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20490
92354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2049092354
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2447603201
Short name T587
Test name
Test status
Simulation time 27685748 ps
CPU time 5.38 seconds
Started Apr 04 03:15:44 PM PDT 24
Finished Apr 04 03:15:50 PM PDT 24
Peak memory 240720 kb
Host smart-5951d34e-d2ef-40e9-b10e-7063337186a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24476
03201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2447603201
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2855551936
Short name T346
Test name
Test status
Simulation time 47731175764 ps
CPU time 1589.66 seconds
Started Apr 04 03:15:46 PM PDT 24
Finished Apr 04 03:42:16 PM PDT 24
Peak memory 289188 kb
Host smart-3716cb5b-bb34-406e-b756-eb1f1ac80680
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855551936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2855551936
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.4275137187
Short name T378
Test name
Test status
Simulation time 49881614028 ps
CPU time 2607.82 seconds
Started Apr 04 03:15:46 PM PDT 24
Finished Apr 04 03:59:14 PM PDT 24
Peak memory 281768 kb
Host smart-8d338d77-7389-4630-acd2-e44260a570fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275137187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.4275137187
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1921061374
Short name T650
Test name
Test status
Simulation time 60255384909 ps
CPU time 481.62 seconds
Started Apr 04 03:15:46 PM PDT 24
Finished Apr 04 03:23:48 PM PDT 24
Peak memory 248308 kb
Host smart-1932968d-5d74-42a2-9d7a-15efc6f30949
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921061374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1921061374
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2743373752
Short name T479
Test name
Test status
Simulation time 420105246 ps
CPU time 11.77 seconds
Started Apr 04 03:15:47 PM PDT 24
Finished Apr 04 03:15:59 PM PDT 24
Peak memory 249388 kb
Host smart-07859840-0136-488b-b0db-c807807b36da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27433
73752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2743373752
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1698416446
Short name T392
Test name
Test status
Simulation time 282142965 ps
CPU time 32.46 seconds
Started Apr 04 03:15:47 PM PDT 24
Finished Apr 04 03:16:19 PM PDT 24
Peak memory 247544 kb
Host smart-da2ead0b-9128-4d28-9464-aa5d1b4fe36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16984
16446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1698416446
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2929531191
Short name T530
Test name
Test status
Simulation time 6862506646 ps
CPU time 48.63 seconds
Started Apr 04 03:15:47 PM PDT 24
Finished Apr 04 03:16:36 PM PDT 24
Peak memory 255736 kb
Host smart-17e13601-9ffb-473d-a125-08bae1de39dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29295
31191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2929531191
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.363212339
Short name T286
Test name
Test status
Simulation time 564597431 ps
CPU time 35.86 seconds
Started Apr 04 03:15:43 PM PDT 24
Finished Apr 04 03:16:19 PM PDT 24
Peak memory 249060 kb
Host smart-25710601-bff8-4e0f-832b-db9fe30a3231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36321
2339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.363212339
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.750063388
Short name T109
Test name
Test status
Simulation time 37528970571 ps
CPU time 2241.71 seconds
Started Apr 04 03:15:43 PM PDT 24
Finished Apr 04 03:53:05 PM PDT 24
Peak memory 290156 kb
Host smart-79bfd3fa-e5fd-4298-a5a6-c6d6ceca18c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750063388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.750063388
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.4007725182
Short name T258
Test name
Test status
Simulation time 51444421780 ps
CPU time 3476.38 seconds
Started Apr 04 03:15:44 PM PDT 24
Finished Apr 04 04:13:40 PM PDT 24
Peak memory 305508 kb
Host smart-410b4850-1b15-4842-877a-43049987e6a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007725182 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.4007725182
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3840876817
Short name T643
Test name
Test status
Simulation time 16087811874 ps
CPU time 1316.22 seconds
Started Apr 04 03:15:59 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 287160 kb
Host smart-8e9303ef-6482-4732-822c-aa89c007a70c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840876817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3840876817
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3297277612
Short name T601
Test name
Test status
Simulation time 1828300201 ps
CPU time 153.35 seconds
Started Apr 04 03:16:01 PM PDT 24
Finished Apr 04 03:18:35 PM PDT 24
Peak memory 256880 kb
Host smart-b7c2700b-ebef-4b18-becd-04aa4757062f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32972
77612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3297277612
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.592826640
Short name T71
Test name
Test status
Simulation time 767295393 ps
CPU time 46.91 seconds
Started Apr 04 03:15:59 PM PDT 24
Finished Apr 04 03:16:46 PM PDT 24
Peak memory 255784 kb
Host smart-9dfd5488-f52e-4977-9c29-b5795de2ce5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59282
6640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.592826640
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2000888571
Short name T655
Test name
Test status
Simulation time 39258894128 ps
CPU time 2089.46 seconds
Started Apr 04 03:16:02 PM PDT 24
Finished Apr 04 03:50:52 PM PDT 24
Peak memory 272868 kb
Host smart-d0c05a9a-e707-42d9-8505-5615771322ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000888571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2000888571
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2097107563
Short name T634
Test name
Test status
Simulation time 32798253825 ps
CPU time 660.5 seconds
Started Apr 04 03:16:02 PM PDT 24
Finished Apr 04 03:27:03 PM PDT 24
Peak memory 265556 kb
Host smart-3d6ebdad-aaa5-4dbc-9110-628fdc5ad93f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097107563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2097107563
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2839705141
Short name T339
Test name
Test status
Simulation time 28537949400 ps
CPU time 298.47 seconds
Started Apr 04 03:15:59 PM PDT 24
Finished Apr 04 03:20:58 PM PDT 24
Peak memory 248304 kb
Host smart-9bbec9bb-59ba-4614-bf36-cabf31d3223e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839705141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2839705141
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1969039170
Short name T648
Test name
Test status
Simulation time 9889877494 ps
CPU time 75.61 seconds
Started Apr 04 03:16:04 PM PDT 24
Finished Apr 04 03:17:20 PM PDT 24
Peak memory 249144 kb
Host smart-fc1c9110-2961-4bc9-b27c-70e280b01306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19690
39170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1969039170
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1230184285
Short name T100
Test name
Test status
Simulation time 592721902 ps
CPU time 21.59 seconds
Started Apr 04 03:16:01 PM PDT 24
Finished Apr 04 03:16:22 PM PDT 24
Peak memory 248844 kb
Host smart-9ec26ac0-4d1f-4d75-8bfe-94d4a77f6180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12301
84285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1230184285
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.64252535
Short name T551
Test name
Test status
Simulation time 515330716 ps
CPU time 31.55 seconds
Started Apr 04 03:16:04 PM PDT 24
Finished Apr 04 03:16:35 PM PDT 24
Peak memory 256452 kb
Host smart-6b1f2017-8f1e-4dff-a8b8-e8313b0b317c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64252
535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.64252535
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.833854178
Short name T463
Test name
Test status
Simulation time 2506301776 ps
CPU time 44.04 seconds
Started Apr 04 03:16:00 PM PDT 24
Finished Apr 04 03:16:44 PM PDT 24
Peak memory 256304 kb
Host smart-206946aa-c7eb-4ed7-bb7e-d1d2224481af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83385
4178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.833854178
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2191432274
Short name T261
Test name
Test status
Simulation time 95776891876 ps
CPU time 2639.69 seconds
Started Apr 04 03:16:00 PM PDT 24
Finished Apr 04 04:00:00 PM PDT 24
Peak memory 286156 kb
Host smart-6b28d997-9d79-4fd2-915e-a869d0fc9e51
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191432274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2191432274
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1128798894
Short name T249
Test name
Test status
Simulation time 67900523777 ps
CPU time 3282.61 seconds
Started Apr 04 03:15:59 PM PDT 24
Finished Apr 04 04:10:42 PM PDT 24
Peak memory 306080 kb
Host smart-e9da21d6-3251-433f-a5e9-c6f83592c6aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128798894 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1128798894
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3995148839
Short name T424
Test name
Test status
Simulation time 11455972765 ps
CPU time 1286.88 seconds
Started Apr 04 03:15:59 PM PDT 24
Finished Apr 04 03:37:26 PM PDT 24
Peak memory 281840 kb
Host smart-23a6dc10-eef5-4bb0-8742-bf107a60096a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995148839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3995148839
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2075807055
Short name T658
Test name
Test status
Simulation time 1769298885 ps
CPU time 150.14 seconds
Started Apr 04 03:15:59 PM PDT 24
Finished Apr 04 03:18:29 PM PDT 24
Peak memory 251100 kb
Host smart-3182c9fc-6910-44a7-9cf8-acffe047ae85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20758
07055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2075807055
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2105848235
Short name T94
Test name
Test status
Simulation time 177550511 ps
CPU time 19.12 seconds
Started Apr 04 03:16:00 PM PDT 24
Finished Apr 04 03:16:19 PM PDT 24
Peak memory 255284 kb
Host smart-e4cbdafa-5eb3-45df-85f6-bfc48f8199f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21058
48235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2105848235
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2991883154
Short name T696
Test name
Test status
Simulation time 105070352151 ps
CPU time 2806.34 seconds
Started Apr 04 03:16:04 PM PDT 24
Finished Apr 04 04:02:50 PM PDT 24
Peak memory 286880 kb
Host smart-4fe85879-b044-4cd5-af00-70066eb77032
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991883154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2991883154
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2465631347
Short name T93
Test name
Test status
Simulation time 70668060417 ps
CPU time 1407.25 seconds
Started Apr 04 03:16:02 PM PDT 24
Finished Apr 04 03:39:29 PM PDT 24
Peak memory 265556 kb
Host smart-18bf8bae-1dab-4eac-b679-0ec88f9c65cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465631347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2465631347
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2373620618
Short name T580
Test name
Test status
Simulation time 10783049484 ps
CPU time 469.81 seconds
Started Apr 04 03:16:01 PM PDT 24
Finished Apr 04 03:23:51 PM PDT 24
Peak memory 248432 kb
Host smart-4ff0c0ac-3a6e-48da-8922-ea37d09b6313
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373620618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2373620618
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.23265268
Short name T470
Test name
Test status
Simulation time 116264979 ps
CPU time 9.5 seconds
Started Apr 04 03:16:00 PM PDT 24
Finished Apr 04 03:16:09 PM PDT 24
Peak memory 249076 kb
Host smart-81f7d002-e2fb-4b87-b2f1-022010e401fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23265
268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.23265268
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2137721811
Short name T49
Test name
Test status
Simulation time 1078057923 ps
CPU time 36.31 seconds
Started Apr 04 03:16:01 PM PDT 24
Finished Apr 04 03:16:38 PM PDT 24
Peak memory 247716 kb
Host smart-b4f0c56a-b461-4811-9c78-1f2936664da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21377
21811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2137721811
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1136252810
Short name T564
Test name
Test status
Simulation time 650653677 ps
CPU time 16.76 seconds
Started Apr 04 03:16:02 PM PDT 24
Finished Apr 04 03:16:18 PM PDT 24
Peak memory 249072 kb
Host smart-ceff6a65-1e50-4217-9ad1-b73d37f78ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11362
52810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1136252810
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2628306408
Short name T598
Test name
Test status
Simulation time 5559554467 ps
CPU time 29.38 seconds
Started Apr 04 03:16:03 PM PDT 24
Finished Apr 04 03:16:32 PM PDT 24
Peak memory 256360 kb
Host smart-a377915d-b604-4b19-9e28-1971da38606b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26283
06408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2628306408
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.660685040
Short name T82
Test name
Test status
Simulation time 99805096142 ps
CPU time 2585.16 seconds
Started Apr 04 03:16:01 PM PDT 24
Finished Apr 04 03:59:06 PM PDT 24
Peak memory 289672 kb
Host smart-47f4f0f7-5d5a-435f-b3dc-58a9d0247c9d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660685040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.660685040
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2192124519
Short name T460
Test name
Test status
Simulation time 36918610066 ps
CPU time 2480.3 seconds
Started Apr 04 03:16:00 PM PDT 24
Finished Apr 04 03:57:21 PM PDT 24
Peak memory 290120 kb
Host smart-b3151c95-0d40-444b-b5f8-93ceba3d6832
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192124519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2192124519
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1629350167
Short name T657
Test name
Test status
Simulation time 931356990 ps
CPU time 57.7 seconds
Started Apr 04 03:15:59 PM PDT 24
Finished Apr 04 03:16:57 PM PDT 24
Peak memory 256584 kb
Host smart-6a15b90b-1328-4209-b942-0f8dc40f878c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16293
50167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1629350167
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.872184408
Short name T391
Test name
Test status
Simulation time 5353421718 ps
CPU time 18.63 seconds
Started Apr 04 03:16:02 PM PDT 24
Finished Apr 04 03:16:20 PM PDT 24
Peak memory 252752 kb
Host smart-a24d05cd-0aeb-4115-bb75-b3623a8eaea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87218
4408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.872184408
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3242993905
Short name T348
Test name
Test status
Simulation time 22810490334 ps
CPU time 1194.63 seconds
Started Apr 04 03:16:14 PM PDT 24
Finished Apr 04 03:36:09 PM PDT 24
Peak memory 272856 kb
Host smart-a5ef6321-59ff-49bf-918f-a0e1e63252b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242993905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3242993905
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3092292081
Short name T419
Test name
Test status
Simulation time 97372277062 ps
CPU time 1728.04 seconds
Started Apr 04 03:16:15 PM PDT 24
Finished Apr 04 03:45:03 PM PDT 24
Peak memory 273624 kb
Host smart-1f4d530b-2917-4758-bb92-4ac256b0e39d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092292081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3092292081
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.761512990
Short name T671
Test name
Test status
Simulation time 37438871617 ps
CPU time 408.39 seconds
Started Apr 04 03:16:01 PM PDT 24
Finished Apr 04 03:22:49 PM PDT 24
Peak memory 248192 kb
Host smart-1dbe7906-2714-4042-9077-0f9b0142b3f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761512990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.761512990
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.853119944
Short name T375
Test name
Test status
Simulation time 403167069 ps
CPU time 16.54 seconds
Started Apr 04 03:16:02 PM PDT 24
Finished Apr 04 03:16:19 PM PDT 24
Peak memory 248960 kb
Host smart-2ab6cfe0-12bc-4147-b706-9aeac825bf86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85311
9944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.853119944
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1716015681
Short name T270
Test name
Test status
Simulation time 5996904920 ps
CPU time 63.45 seconds
Started Apr 04 03:16:02 PM PDT 24
Finished Apr 04 03:17:05 PM PDT 24
Peak memory 248108 kb
Host smart-14969140-be93-4476-bacc-61508327b35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17160
15681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1716015681
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1048354247
Short name T660
Test name
Test status
Simulation time 354934120 ps
CPU time 23.14 seconds
Started Apr 04 03:16:01 PM PDT 24
Finished Apr 04 03:16:24 PM PDT 24
Peak memory 255304 kb
Host smart-56bc003d-2ba6-4887-8f7e-9f32f65dab91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10483
54247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1048354247
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.107996178
Short name T398
Test name
Test status
Simulation time 486243980 ps
CPU time 35.78 seconds
Started Apr 04 03:16:00 PM PDT 24
Finished Apr 04 03:16:36 PM PDT 24
Peak memory 249076 kb
Host smart-7b458af6-c0bd-462f-91bb-a8c793d29338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10799
6178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.107996178
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2310360251
Short name T549
Test name
Test status
Simulation time 4611145293 ps
CPU time 164 seconds
Started Apr 04 03:16:18 PM PDT 24
Finished Apr 04 03:19:02 PM PDT 24
Peak memory 257272 kb
Host smart-c03e94e6-18ae-4e30-bab7-917fe8450ebf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310360251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2310360251
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2776931972
Short name T507
Test name
Test status
Simulation time 96383347540 ps
CPU time 1487.08 seconds
Started Apr 04 03:16:16 PM PDT 24
Finished Apr 04 03:41:04 PM PDT 24
Peak memory 265592 kb
Host smart-0cc75f7b-2af6-4cca-97e2-929920cb7861
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776931972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2776931972
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1901319049
Short name T550
Test name
Test status
Simulation time 2345279751 ps
CPU time 77.32 seconds
Started Apr 04 03:16:14 PM PDT 24
Finished Apr 04 03:17:31 PM PDT 24
Peak memory 257000 kb
Host smart-48ca7162-b798-49a4-b7d7-daee7dd40378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19013
19049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1901319049
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.739967601
Short name T481
Test name
Test status
Simulation time 336247828 ps
CPU time 37.31 seconds
Started Apr 04 03:16:18 PM PDT 24
Finished Apr 04 03:16:55 PM PDT 24
Peak memory 255700 kb
Host smart-5f8f9d77-f755-4a35-b1dc-e9436d4e2f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73996
7601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.739967601
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.62777034
Short name T321
Test name
Test status
Simulation time 155810950495 ps
CPU time 2033.49 seconds
Started Apr 04 03:16:17 PM PDT 24
Finished Apr 04 03:50:10 PM PDT 24
Peak memory 269640 kb
Host smart-4caf65b8-2663-4d31-8a5e-775254374afd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62777034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.62777034
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3020291265
Short name T508
Test name
Test status
Simulation time 54378439876 ps
CPU time 3122.7 seconds
Started Apr 04 03:16:22 PM PDT 24
Finished Apr 04 04:08:25 PM PDT 24
Peak memory 289408 kb
Host smart-66f528aa-d5a0-481d-b821-9fe692a32769
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020291265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3020291265
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2948019728
Short name T620
Test name
Test status
Simulation time 46995229629 ps
CPU time 493.19 seconds
Started Apr 04 03:16:22 PM PDT 24
Finished Apr 04 03:24:35 PM PDT 24
Peak memory 247112 kb
Host smart-23c01488-5f5d-432d-87f0-ceb078d23843
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948019728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2948019728
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2561295677
Short name T684
Test name
Test status
Simulation time 1218034319 ps
CPU time 32.92 seconds
Started Apr 04 03:16:16 PM PDT 24
Finished Apr 04 03:16:49 PM PDT 24
Peak memory 256288 kb
Host smart-b8f4fb42-15b8-45af-8927-75f17bcc2188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25612
95677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2561295677
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3956483861
Short name T524
Test name
Test status
Simulation time 75476673 ps
CPU time 6.25 seconds
Started Apr 04 03:16:17 PM PDT 24
Finished Apr 04 03:16:23 PM PDT 24
Peak memory 239376 kb
Host smart-4797e4fb-a34f-43c4-a171-cf7fb9bb93c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39564
83861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3956483861
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1892016067
Short name T499
Test name
Test status
Simulation time 2069086429 ps
CPU time 31.01 seconds
Started Apr 04 03:16:15 PM PDT 24
Finished Apr 04 03:16:46 PM PDT 24
Peak memory 255740 kb
Host smart-60387531-5fbb-455d-a664-4fa52db6672d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18920
16067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1892016067
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2655333740
Short name T74
Test name
Test status
Simulation time 584741441 ps
CPU time 40.93 seconds
Started Apr 04 03:16:14 PM PDT 24
Finished Apr 04 03:16:55 PM PDT 24
Peak memory 256232 kb
Host smart-19e2faf4-a4e8-4840-a4e3-3fb7860d8e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26553
33740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2655333740
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.813775842
Short name T106
Test name
Test status
Simulation time 128264967477 ps
CPU time 4517.29 seconds
Started Apr 04 03:16:15 PM PDT 24
Finished Apr 04 04:31:33 PM PDT 24
Peak memory 322912 kb
Host smart-2b224ca4-fc86-4c9f-9015-190c3b7d1ac4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813775842 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.813775842
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2695812694
Short name T48
Test name
Test status
Simulation time 32745780988 ps
CPU time 1696.25 seconds
Started Apr 04 03:16:20 PM PDT 24
Finished Apr 04 03:44:36 PM PDT 24
Peak memory 271732 kb
Host smart-7e944180-4b30-41ea-8870-585ba29899c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695812694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2695812694
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3596092899
Short name T493
Test name
Test status
Simulation time 3152210066 ps
CPU time 49.02 seconds
Started Apr 04 03:16:19 PM PDT 24
Finished Apr 04 03:17:08 PM PDT 24
Peak memory 255532 kb
Host smart-0484b919-76c5-43ac-923f-51dd577e884f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35960
92899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3596092899
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2230708786
Short name T599
Test name
Test status
Simulation time 356466250 ps
CPU time 18.48 seconds
Started Apr 04 03:16:16 PM PDT 24
Finished Apr 04 03:16:34 PM PDT 24
Peak memory 248840 kb
Host smart-38d20331-ccd8-47b4-ab73-687b913278b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22307
08786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2230708786
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1534194306
Short name T299
Test name
Test status
Simulation time 32707055405 ps
CPU time 2035.09 seconds
Started Apr 04 03:16:15 PM PDT 24
Finished Apr 04 03:50:10 PM PDT 24
Peak memory 268680 kb
Host smart-0d5bcdd1-16c2-49ea-9bde-3be640db2bf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534194306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1534194306
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.4049619703
Short name T394
Test name
Test status
Simulation time 21968722895 ps
CPU time 1376.16 seconds
Started Apr 04 03:16:19 PM PDT 24
Finished Apr 04 03:39:15 PM PDT 24
Peak memory 273748 kb
Host smart-0bd0ccf4-a436-41cd-a0d9-c6fe5ace4f02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049619703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.4049619703
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2796676215
Short name T330
Test name
Test status
Simulation time 21672518468 ps
CPU time 421.16 seconds
Started Apr 04 03:16:17 PM PDT 24
Finished Apr 04 03:23:18 PM PDT 24
Peak memory 248340 kb
Host smart-ceb531f8-ae7a-4437-8eee-e29e9a6be825
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796676215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2796676215
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1265929688
Short name T396
Test name
Test status
Simulation time 927375064 ps
CPU time 15.4 seconds
Started Apr 04 03:16:16 PM PDT 24
Finished Apr 04 03:16:31 PM PDT 24
Peak memory 249016 kb
Host smart-315a7637-fcdd-406e-86aa-4cad6a9d3d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12659
29688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1265929688
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1459056800
Short name T611
Test name
Test status
Simulation time 411754857 ps
CPU time 9.14 seconds
Started Apr 04 03:16:18 PM PDT 24
Finished Apr 04 03:16:27 PM PDT 24
Peak memory 248980 kb
Host smart-c2ce89de-1a32-4ea8-a04c-dbc3b9435cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14590
56800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1459056800
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1988482682
Short name T522
Test name
Test status
Simulation time 214134130 ps
CPU time 10.25 seconds
Started Apr 04 03:16:18 PM PDT 24
Finished Apr 04 03:16:28 PM PDT 24
Peak memory 247368 kb
Host smart-1b49a56d-4f14-4108-9856-0aa2f9a5ff6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19884
82682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1988482682
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1885656432
Short name T489
Test name
Test status
Simulation time 484019625 ps
CPU time 12.7 seconds
Started Apr 04 03:16:16 PM PDT 24
Finished Apr 04 03:16:29 PM PDT 24
Peak memory 254436 kb
Host smart-e0fd6e80-34f4-46c1-a2cb-a8fbd7fc33a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18856
56432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1885656432
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1396154799
Short name T685
Test name
Test status
Simulation time 46110850392 ps
CPU time 2637.49 seconds
Started Apr 04 03:16:21 PM PDT 24
Finished Apr 04 04:00:18 PM PDT 24
Peak memory 287536 kb
Host smart-94e99c7b-d74d-4e63-b6d6-ebd266ddb50b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396154799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1396154799
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.723821257
Short name T204
Test name
Test status
Simulation time 15531110 ps
CPU time 2.52 seconds
Started Apr 04 03:13:49 PM PDT 24
Finished Apr 04 03:13:52 PM PDT 24
Peak memory 249284 kb
Host smart-13777034-11d6-46b0-8015-5978f7b493b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=723821257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.723821257
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.737720037
Short name T675
Test name
Test status
Simulation time 190714547756 ps
CPU time 2829.16 seconds
Started Apr 04 03:13:50 PM PDT 24
Finished Apr 04 04:01:01 PM PDT 24
Peak memory 281944 kb
Host smart-09720276-d18f-4cf5-8f1f-6c8474a618b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737720037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.737720037
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2543809458
Short name T216
Test name
Test status
Simulation time 718767089 ps
CPU time 10.3 seconds
Started Apr 04 03:13:46 PM PDT 24
Finished Apr 04 03:13:56 PM PDT 24
Peak memory 240792 kb
Host smart-0c251781-fcce-4b9d-9b14-3f69c1bee5ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2543809458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2543809458
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.4279235261
Short name T219
Test name
Test status
Simulation time 15295840224 ps
CPU time 169.79 seconds
Started Apr 04 03:13:45 PM PDT 24
Finished Apr 04 03:16:35 PM PDT 24
Peak memory 257372 kb
Host smart-45c50fb2-8f60-4319-9293-e84ab43d091c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42792
35261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.4279235261
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2165030149
Short name T575
Test name
Test status
Simulation time 762161953 ps
CPU time 19.39 seconds
Started Apr 04 03:13:45 PM PDT 24
Finished Apr 04 03:14:05 PM PDT 24
Peak memory 255688 kb
Host smart-fd5b3549-965c-473c-a59b-5d4bcf8829a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21650
30149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2165030149
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.554072482
Short name T638
Test name
Test status
Simulation time 138514038319 ps
CPU time 1941.57 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:46:14 PM PDT 24
Peak memory 268580 kb
Host smart-1c0b9655-f038-4a7d-9e37-ec0b8208c8f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554072482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.554072482
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3266208740
Short name T39
Test name
Test status
Simulation time 25303307958 ps
CPU time 1085.55 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:31:58 PM PDT 24
Peak memory 281972 kb
Host smart-ebf94486-cc8a-4633-bb65-936c28ed7531
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266208740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3266208740
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2086482360
Short name T333
Test name
Test status
Simulation time 4609781548 ps
CPU time 206.56 seconds
Started Apr 04 03:13:46 PM PDT 24
Finished Apr 04 03:17:13 PM PDT 24
Peak memory 248416 kb
Host smart-0ac8a46c-d17c-4ed6-b10e-85de705f4dcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086482360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2086482360
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.4175861847
Short name T528
Test name
Test status
Simulation time 832385222 ps
CPU time 59.44 seconds
Started Apr 04 03:13:54 PM PDT 24
Finished Apr 04 03:14:54 PM PDT 24
Peak memory 256204 kb
Host smart-c235b510-00af-4fa4-af77-536275d356a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41758
61847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.4175861847
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2444221688
Short name T511
Test name
Test status
Simulation time 1855780235 ps
CPU time 32.39 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:14:24 PM PDT 24
Peak memory 255504 kb
Host smart-828b818b-7cae-41bd-bf13-5c73d8fdfc26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24442
21688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2444221688
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2520018199
Short name T589
Test name
Test status
Simulation time 250463144 ps
CPU time 15.86 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:14:08 PM PDT 24
Peak memory 249172 kb
Host smart-03b3c132-6c92-4e45-96fd-a8d778cc7233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25200
18199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2520018199
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3234165990
Short name T75
Test name
Test status
Simulation time 2947809418 ps
CPU time 49.45 seconds
Started Apr 04 03:13:45 PM PDT 24
Finished Apr 04 03:14:35 PM PDT 24
Peak memory 249376 kb
Host smart-3b94a106-4576-4964-a4d2-830394d50825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32341
65990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3234165990
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.3704663778
Short name T52
Test name
Test status
Simulation time 99555610905 ps
CPU time 2882.69 seconds
Started Apr 04 03:13:48 PM PDT 24
Finished Apr 04 04:01:53 PM PDT 24
Peak memory 322484 kb
Host smart-3442c9c6-0c45-455b-92bb-3cebcce13647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704663778 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.3704663778
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1414538831
Short name T201
Test name
Test status
Simulation time 27391829 ps
CPU time 2.65 seconds
Started Apr 04 03:13:49 PM PDT 24
Finished Apr 04 03:13:53 PM PDT 24
Peak memory 249308 kb
Host smart-d7993f7a-7936-4aba-8f9f-d429c8f1d080
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1414538831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1414538831
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3495269692
Short name T503
Test name
Test status
Simulation time 21870766336 ps
CPU time 1533.09 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:39:24 PM PDT 24
Peak memory 273628 kb
Host smart-0dd1db37-2571-495f-bb88-1871a2ab2830
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495269692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3495269692
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.407125806
Short name T512
Test name
Test status
Simulation time 492518221 ps
CPU time 13.42 seconds
Started Apr 04 03:13:52 PM PDT 24
Finished Apr 04 03:14:07 PM PDT 24
Peak memory 249044 kb
Host smart-d3b75914-6999-4a6f-8cd1-7fa5ce48c7eb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=407125806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.407125806
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.73253648
Short name T689
Test name
Test status
Simulation time 4115025506 ps
CPU time 56.77 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:14:49 PM PDT 24
Peak memory 249008 kb
Host smart-3131c45c-879c-47a0-8735-5ed4f5198676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73253
648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.73253648
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3313569227
Short name T450
Test name
Test status
Simulation time 3945538182 ps
CPU time 43.24 seconds
Started Apr 04 03:13:41 PM PDT 24
Finished Apr 04 03:14:25 PM PDT 24
Peak memory 249336 kb
Host smart-692eea61-e721-486f-a3b1-ee6bb2ac93b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33135
69227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3313569227
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.4046305633
Short name T303
Test name
Test status
Simulation time 173386782537 ps
CPU time 2215.71 seconds
Started Apr 04 03:13:52 PM PDT 24
Finished Apr 04 03:50:49 PM PDT 24
Peak memory 272724 kb
Host smart-151dfa89-894e-450a-8fb2-ec7cc783a0cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046305633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.4046305633
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2436521691
Short name T180
Test name
Test status
Simulation time 41532885293 ps
CPU time 920.68 seconds
Started Apr 04 03:13:53 PM PDT 24
Finished Apr 04 03:29:15 PM PDT 24
Peak memory 273000 kb
Host smart-c1d2b083-4a83-4d8e-af9e-5af729790ca0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436521691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2436521691
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2030407281
Short name T42
Test name
Test status
Simulation time 30196208588 ps
CPU time 313.18 seconds
Started Apr 04 03:13:48 PM PDT 24
Finished Apr 04 03:19:02 PM PDT 24
Peak memory 247212 kb
Host smart-a1903f94-9c6c-46d6-87c1-62cdeaeb486f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030407281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2030407281
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1605357016
Short name T558
Test name
Test status
Simulation time 422172419 ps
CPU time 10.92 seconds
Started Apr 04 03:13:45 PM PDT 24
Finished Apr 04 03:13:57 PM PDT 24
Peak memory 255800 kb
Host smart-80fc006b-da70-4f26-911d-487fce6e7204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16053
57016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1605357016
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.4243700607
Short name T97
Test name
Test status
Simulation time 827840620 ps
CPU time 50.92 seconds
Started Apr 04 03:13:48 PM PDT 24
Finished Apr 04 03:14:40 PM PDT 24
Peak memory 247652 kb
Host smart-33f52e62-fd21-4ea4-89b8-886da2760668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42437
00607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.4243700607
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1719573896
Short name T259
Test name
Test status
Simulation time 238621002 ps
CPU time 27.46 seconds
Started Apr 04 03:13:53 PM PDT 24
Finished Apr 04 03:14:22 PM PDT 24
Peak memory 249020 kb
Host smart-9291b27a-2f67-4066-826c-8acf48341566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17195
73896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1719573896
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1145783964
Short name T581
Test name
Test status
Simulation time 1403645423 ps
CPU time 47.32 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:14:39 PM PDT 24
Peak memory 249040 kb
Host smart-7886589d-c81f-473d-a2c3-f0c5163b76cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11457
83964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1145783964
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2147059695
Short name T542
Test name
Test status
Simulation time 42314280457 ps
CPU time 2766.46 seconds
Started Apr 04 03:13:53 PM PDT 24
Finished Apr 04 04:00:01 PM PDT 24
Peak memory 289536 kb
Host smart-050d6d5c-13b3-443e-9968-c0d7906c8700
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147059695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2147059695
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1285345245
Short name T244
Test name
Test status
Simulation time 54384198815 ps
CPU time 1290.33 seconds
Started Apr 04 03:13:43 PM PDT 24
Finished Apr 04 03:35:14 PM PDT 24
Peak memory 289940 kb
Host smart-82e33205-235c-4964-989a-a8552c94f7f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285345245 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1285345245
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1595294296
Short name T208
Test name
Test status
Simulation time 44877213 ps
CPU time 2.49 seconds
Started Apr 04 03:13:56 PM PDT 24
Finished Apr 04 03:13:59 PM PDT 24
Peak memory 249388 kb
Host smart-033546e9-8611-48f0-bb79-65705efe9e7e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1595294296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1595294296
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1461130489
Short name T708
Test name
Test status
Simulation time 30081059319 ps
CPU time 1670.9 seconds
Started Apr 04 03:13:51 PM PDT 24
Finished Apr 04 03:41:44 PM PDT 24
Peak memory 290120 kb
Host smart-4aac1f46-fdd7-408e-91c5-c0f62ac6e73e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461130489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1461130489
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.584626957
Short name T246
Test name
Test status
Simulation time 1016043562 ps
CPU time 14.87 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 03:14:12 PM PDT 24
Peak memory 250820 kb
Host smart-07e22ec4-ccf9-404f-ac16-bf9841ddd15e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=584626957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.584626957
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.4138961024
Short name T434
Test name
Test status
Simulation time 60710370 ps
CPU time 7.11 seconds
Started Apr 04 03:13:50 PM PDT 24
Finished Apr 04 03:13:58 PM PDT 24
Peak memory 254204 kb
Host smart-64967a97-6029-4848-ac86-7fd9dcc84e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41389
61024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.4138961024
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.273031376
Short name T441
Test name
Test status
Simulation time 1079896421 ps
CPU time 20.39 seconds
Started Apr 04 03:13:54 PM PDT 24
Finished Apr 04 03:14:15 PM PDT 24
Peak memory 253968 kb
Host smart-3d8ab8d3-6e83-4b0b-bc77-f38d72a48b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27303
1376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.273031376
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2227365458
Short name T305
Test name
Test status
Simulation time 14235379484 ps
CPU time 998.62 seconds
Started Apr 04 03:13:56 PM PDT 24
Finished Apr 04 03:30:34 PM PDT 24
Peak memory 273480 kb
Host smart-7064b465-49ae-429d-9734-1d26d2233a23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227365458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2227365458
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3206148941
Short name T626
Test name
Test status
Simulation time 21971031555 ps
CPU time 686.91 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 03:25:24 PM PDT 24
Peak memory 273100 kb
Host smart-1ddb6367-f260-4cb9-acb2-f697edc3a293
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206148941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3206148941
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2784310011
Short name T637
Test name
Test status
Simulation time 36268238774 ps
CPU time 513.41 seconds
Started Apr 04 03:13:53 PM PDT 24
Finished Apr 04 03:22:27 PM PDT 24
Peak memory 248384 kb
Host smart-1f4b8ee1-3dc6-4bd6-8b5b-a09d6ff9bccd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784310011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2784310011
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.494336893
Short name T531
Test name
Test status
Simulation time 394926619 ps
CPU time 7.4 seconds
Started Apr 04 03:13:45 PM PDT 24
Finished Apr 04 03:13:53 PM PDT 24
Peak memory 248968 kb
Host smart-4149b979-0e45-48bd-93a0-f1aafbe803f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49433
6893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.494336893
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2702046153
Short name T702
Test name
Test status
Simulation time 2552935435 ps
CPU time 57.16 seconds
Started Apr 04 03:13:54 PM PDT 24
Finished Apr 04 03:14:52 PM PDT 24
Peak memory 256392 kb
Host smart-5d5f09bd-401f-491a-b82e-613e4903fe4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27020
46153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2702046153
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.4114551950
Short name T664
Test name
Test status
Simulation time 212229796 ps
CPU time 33.53 seconds
Started Apr 04 03:13:54 PM PDT 24
Finished Apr 04 03:14:28 PM PDT 24
Peak memory 247568 kb
Host smart-606e398d-52c7-4409-84ef-7780dd9cbbdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41145
51950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.4114551950
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.407278658
Short name T397
Test name
Test status
Simulation time 203052126 ps
CPU time 7.49 seconds
Started Apr 04 03:13:44 PM PDT 24
Finished Apr 04 03:13:53 PM PDT 24
Peak memory 249100 kb
Host smart-85259b76-f9cb-46e3-9a9c-c76211927830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40727
8658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.407278658
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.4163710532
Short name T267
Test name
Test status
Simulation time 33827034843 ps
CPU time 1838.76 seconds
Started Apr 04 03:13:58 PM PDT 24
Finished Apr 04 03:44:37 PM PDT 24
Peak memory 281924 kb
Host smart-9f22ad27-198e-4e6a-b9b2-86ce85f69a2c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163710532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.4163710532
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1908746026
Short name T235
Test name
Test status
Simulation time 126119029285 ps
CPU time 4133.29 seconds
Started Apr 04 03:13:55 PM PDT 24
Finished Apr 04 04:22:49 PM PDT 24
Peak memory 302032 kb
Host smart-2ee36532-2252-47e6-a946-19034946e138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908746026 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1908746026
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3907318933
Short name T206
Test name
Test status
Simulation time 537264456 ps
CPU time 3.42 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 03:14:00 PM PDT 24
Peak memory 249340 kb
Host smart-87e14f2f-5182-4a43-ad3d-efef9d22e5b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3907318933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3907318933
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3017070197
Short name T492
Test name
Test status
Simulation time 126902492147 ps
CPU time 1771.19 seconds
Started Apr 04 03:14:01 PM PDT 24
Finished Apr 04 03:43:33 PM PDT 24
Peak memory 273552 kb
Host smart-891f3dd0-93c9-40ea-a93d-dec4ae63ed90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017070197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3017070197
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3089040616
Short name T498
Test name
Test status
Simulation time 604205683 ps
CPU time 27.72 seconds
Started Apr 04 03:13:58 PM PDT 24
Finished Apr 04 03:14:26 PM PDT 24
Peak memory 240848 kb
Host smart-4e097606-7287-4c85-862d-31e75c8ea10b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3089040616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3089040616
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.979643395
Short name T640
Test name
Test status
Simulation time 3215287146 ps
CPU time 150.81 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 03:16:28 PM PDT 24
Peak memory 257288 kb
Host smart-9d59ae1a-3937-4f65-b74e-62d259671820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97964
3395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.979643395
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.62445139
Short name T445
Test name
Test status
Simulation time 1410326957 ps
CPU time 23.77 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 03:14:21 PM PDT 24
Peak memory 255664 kb
Host smart-bc599464-4133-42bf-9269-952133f1b955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62445
139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.62445139
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3571118275
Short name T306
Test name
Test status
Simulation time 75199898357 ps
CPU time 1940.5 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 03:46:18 PM PDT 24
Peak memory 289092 kb
Host smart-612d4668-7796-41b3-b6f4-9712ff9a63dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571118275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3571118275
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.725827366
Short name T571
Test name
Test status
Simulation time 57478951317 ps
CPU time 1627.58 seconds
Started Apr 04 03:13:59 PM PDT 24
Finished Apr 04 03:41:07 PM PDT 24
Peak memory 267548 kb
Host smart-2dd1e8f0-04b2-4ed4-ab63-c5ed34958304
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725827366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.725827366
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2015746127
Short name T649
Test name
Test status
Simulation time 4457735777 ps
CPU time 176.46 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 03:16:53 PM PDT 24
Peak memory 255160 kb
Host smart-da64feb0-382c-4bea-b8a7-06fb219a30e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015746127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2015746127
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3833071015
Short name T387
Test name
Test status
Simulation time 1148496381 ps
CPU time 35.53 seconds
Started Apr 04 03:14:11 PM PDT 24
Finished Apr 04 03:14:47 PM PDT 24
Peak memory 248968 kb
Host smart-113bcd55-ad6e-4b58-9ec1-0ee935450c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38330
71015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3833071015
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.525249780
Short name T680
Test name
Test status
Simulation time 154311226 ps
CPU time 8.48 seconds
Started Apr 04 03:13:54 PM PDT 24
Finished Apr 04 03:14:03 PM PDT 24
Peak memory 253960 kb
Host smart-1d3448d0-1169-45cd-8f48-4c9c2adb6f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52524
9780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.525249780
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1781237320
Short name T224
Test name
Test status
Simulation time 1225276426 ps
CPU time 15.62 seconds
Started Apr 04 03:13:58 PM PDT 24
Finished Apr 04 03:14:14 PM PDT 24
Peak memory 255444 kb
Host smart-4222f056-13e6-4c97-a4a9-a407f511805b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17812
37320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1781237320
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3220589641
Short name T516
Test name
Test status
Simulation time 3099782408 ps
CPU time 31.74 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 03:14:29 PM PDT 24
Peak memory 256444 kb
Host smart-747d7141-2529-4b6c-ace4-ca943e363ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32205
89641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3220589641
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3162841366
Short name T539
Test name
Test status
Simulation time 61849337270 ps
CPU time 3487.74 seconds
Started Apr 04 03:13:59 PM PDT 24
Finished Apr 04 04:12:08 PM PDT 24
Peak memory 305080 kb
Host smart-0918d593-299a-4250-9e7b-29e86fa1c072
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162841366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3162841366
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2867864420
Short name T646
Test name
Test status
Simulation time 528421594888 ps
CPU time 4995.57 seconds
Started Apr 04 03:13:57 PM PDT 24
Finished Apr 04 04:37:14 PM PDT 24
Peak memory 330908 kb
Host smart-c64f7296-c722-45a7-a401-ed5c4eadd716
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867864420 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2867864420
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3951534999
Short name T215
Test name
Test status
Simulation time 56146975 ps
CPU time 4.38 seconds
Started Apr 04 03:14:07 PM PDT 24
Finished Apr 04 03:14:12 PM PDT 24
Peak memory 249308 kb
Host smart-a8e31b14-8fef-4c59-83ef-63d9fc789730
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3951534999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3951534999
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.546435432
Short name T5
Test name
Test status
Simulation time 42836111339 ps
CPU time 1333.52 seconds
Started Apr 04 03:14:07 PM PDT 24
Finished Apr 04 03:36:20 PM PDT 24
Peak memory 289520 kb
Host smart-3378d74d-a780-4ac9-a16b-5ba92ae8fef4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546435432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.546435432
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.368307444
Short name T34
Test name
Test status
Simulation time 463349975 ps
CPU time 7.1 seconds
Started Apr 04 03:14:06 PM PDT 24
Finished Apr 04 03:14:14 PM PDT 24
Peak memory 240836 kb
Host smart-76f9035d-0505-4843-bc2b-be3587ad082c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=368307444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.368307444
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.261780613
Short name T254
Test name
Test status
Simulation time 7424874492 ps
CPU time 86.96 seconds
Started Apr 04 03:14:09 PM PDT 24
Finished Apr 04 03:15:36 PM PDT 24
Peak memory 249092 kb
Host smart-d8ac3fd3-d26c-436e-9650-655f832d39ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26178
0613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.261780613
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3730940106
Short name T220
Test name
Test status
Simulation time 372330080 ps
CPU time 12.8 seconds
Started Apr 04 03:14:01 PM PDT 24
Finished Apr 04 03:14:14 PM PDT 24
Peak memory 253728 kb
Host smart-52235e21-a2cf-4180-a85d-04643ae5fa52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37309
40106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3730940106
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1005745922
Short name T712
Test name
Test status
Simulation time 163719253163 ps
CPU time 2402.68 seconds
Started Apr 04 03:14:07 PM PDT 24
Finished Apr 04 03:54:10 PM PDT 24
Peak memory 273620 kb
Host smart-4a1a8905-e643-401c-89bb-e7f68a7c0cc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005745922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1005745922
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1586119715
Short name T417
Test name
Test status
Simulation time 31146387167 ps
CPU time 1868.23 seconds
Started Apr 04 03:14:08 PM PDT 24
Finished Apr 04 03:45:16 PM PDT 24
Peak memory 289116 kb
Host smart-e1288fd7-ec2f-4354-9676-b1e90e14f87d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586119715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1586119715
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1904952340
Short name T681
Test name
Test status
Simulation time 11492458010 ps
CPU time 223.8 seconds
Started Apr 04 03:14:07 PM PDT 24
Finished Apr 04 03:17:51 PM PDT 24
Peak memory 248260 kb
Host smart-47e0aa12-9ac1-4060-8c2a-0d70798237ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904952340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1904952340
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3348730175
Short name T61
Test name
Test status
Simulation time 347920203 ps
CPU time 10.59 seconds
Started Apr 04 03:13:59 PM PDT 24
Finished Apr 04 03:14:10 PM PDT 24
Peak memory 249032 kb
Host smart-1f1b8ff9-d33a-4a0a-97e0-dd2f17662aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33487
30175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3348730175
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.766492359
Short name T673
Test name
Test status
Simulation time 3227682681 ps
CPU time 35.37 seconds
Started Apr 04 03:14:08 PM PDT 24
Finished Apr 04 03:14:44 PM PDT 24
Peak memory 255748 kb
Host smart-023f38cb-e64d-416a-a07b-282718deb18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76649
2359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.766492359
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.37142042
Short name T603
Test name
Test status
Simulation time 3650322358 ps
CPU time 56.78 seconds
Started Apr 04 03:13:59 PM PDT 24
Finished Apr 04 03:14:56 PM PDT 24
Peak memory 255884 kb
Host smart-22f6f68e-125a-4020-97e2-bbbe984e908b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37142
042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.37142042
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3007442626
Short name T376
Test name
Test status
Simulation time 226670554 ps
CPU time 14.95 seconds
Started Apr 04 03:14:02 PM PDT 24
Finished Apr 04 03:14:17 PM PDT 24
Peak memory 248968 kb
Host smart-f68296e3-d1b6-4c59-a9aa-480176a7936f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30074
42626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3007442626
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1147930426
Short name T41
Test name
Test status
Simulation time 16743343798 ps
CPU time 1874.29 seconds
Started Apr 04 03:14:10 PM PDT 24
Finished Apr 04 03:45:25 PM PDT 24
Peak memory 302200 kb
Host smart-fcfc871a-5cba-4e59-ae46-1d4268ed4f3c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147930426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1147930426
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1174844594
Short name T187
Test name
Test status
Simulation time 201344069317 ps
CPU time 2986.2 seconds
Started Apr 04 03:14:10 PM PDT 24
Finished Apr 04 04:03:57 PM PDT 24
Peak memory 299284 kb
Host smart-0f3b9dc0-d174-48b4-88ae-af5f2622f83c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174844594 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1174844594
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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