Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	71407	1			T2	20		T12	3773		T7	8
class_i[0x1]	41011	1			T6	2		T13	5		T14	3
class_i[0x2]	65998	1			T3	86		T6	2		T7	17
class_i[0x3]	44595	1			T2	28		T17	463		T12	191

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	55715	1			T2	15		T3	16		T17	5
alert[0x1]	54721	1			T2	16		T3	70		T6	1
alert[0x2]	54914	1			T2	5		T6	2		T17	312
alert[0x3]	57661	1			T2	12		T6	1		T17	142

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

222701

1

T2

48

T3

86

T17

463

esc_ping_fail

310

1

T6

4

T7

8

T8

4

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	55636	1			T2	15		T3	16		T17	5
esc_integrity_fail	alert[0x1]	54634	1			T2	16		T3	70		T17	4
esc_integrity_fail	alert[0x2]	54836	1			T2	5		T17	312		T12	1035
esc_integrity_fail	alert[0x3]	57595	1			T2	12		T17	142		T12	810
esc_ping_fail	alert[0x0]	79	1			T7	2		T8	1		T236	4
esc_ping_fail	alert[0x1]	87	1			T6	1		T7	3		T8	1
esc_ping_fail	alert[0x2]	78	1			T6	2		T7	2		T8	1
esc_ping_fail	alert[0x3]	66	1			T6	1		T7	1		T8	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	71308	1			T2	20		T12	3773		T13	3189
esc_integrity_fail	class_i[0x1]	40924	1			T13	5		T14	3		T19	12
esc_integrity_fail	class_i[0x2]	65932	1			T3	86		T7	17		T13	5
esc_integrity_fail	class_i[0x3]	44537	1			T2	28		T17	463		T12	191
esc_ping_fail	class_i[0x0]	99	1			T7	8		T236	1		T232	7
esc_ping_fail	class_i[0x1]	87	1			T6	2		T304	1		T236	8
esc_ping_fail	class_i[0x2]	66	1			T6	2		T8	4		T236	1
esc_ping_fail	class_i[0x3]	58	1			T236	3		T220	8		T310	1