Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	675487858	0	0	623
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	675487858	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	675487858	675352961	0	0
tb.dut.CheckAccuCntDw	0	0	623	623	0	0
tb.dut.CheckEscCntDw	0	0	623	623	0	0
tb.dut.CheckNAlerts	0	0	623	623	0	0
tb.dut.CheckNClasses	0	0	623	623	0	0
tb.dut.CheckNEscSev	0	0	623	623	0	0
tb.dut.CrashdumpKnownO_A	0	0	675487858	675352961	0	0
tb.dut.EdnKnownO_A	0	0	675487858	675352961	0	0
tb.dut.EscPKnownO_A	0	0	675487858	675352961	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	675487858	50	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	675487858	50	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	675487858	50	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	675487858	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	675487858	50	0	0
tb.dut.IrqAKnownO_A	0	0	675487858	675352961	0	0
tb.dut.IrqBKnownO_A	0	0	675487858	675352961	0	0
tb.dut.IrqCKnownO_A	0	0	675487858	675352961	0	0
tb.dut.IrqDKnownO_A	0	0	675487858	675352961	0	0
tb.dut.TlAReadyKnownO_A	0	0	675487858	675352961	0	0
tb.dut.TlDValidKnownO_A	0	0	675487858	675352961	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	698354498	2830304	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	698354498	11180	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	698354498	11076	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	698354498	11617	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	698354498	13116	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	698354498	11754	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	698354498	11506	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	698354498	13780	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	698354498	12428	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	698354498	11154	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	698354498	11640	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	698354498	11928	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	698354498	12867	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	698354498	12322	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	698354498	11573	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	698354498	12365	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	698354498	12125	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	698354498	12109	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	698354498	12128	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	698354498	11363	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	698354498	12082	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	698354498	10980	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	698354498	10969	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	698354498	11398	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	698354498	11711	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	698354498	11086	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	698354498	12217	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	698354498	11019	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	698354498	11076	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	698354498	10860	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	698354498	11810	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	698354498	10855	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	698354498	12602	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	698354498	13500	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	698354498	11645	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	698354498	11402	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	698354498	11334	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	698354498	12521	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	698354498	11028	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	698354498	11728	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	698354498	11506	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	698354498	11015	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	698354498	11217	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	698354498	11055	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	698354498	11297	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	698354498	11558	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	698354498	12969	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	698354498	11097	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	698354498	11220	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	698354498	11158	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	698354498	11198	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	698354498	12432	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	698354498	11108	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	698354498	11688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	698354498	12699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	698354498	10877	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	698354498	11551	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	698354498	12028	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	698354498	12318	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	698354498	11387	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	698354498	12022	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	698354498	11302	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	698354498	13025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	698354498	11057	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	698354498	11451	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	698354498	11056	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	698354498	11254	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	698354498	10893	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	698354498	12365	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	698354498	11139	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	698354498	17618	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	698354498	10777	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	698354498	11663	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	698354498	12925	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	698354498	11473	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	698354498	11064	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	698354498	10830	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	698354498	11251	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	698354498	11324	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	675487858	50	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	675487858	50	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	675487858	50	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	675487858	2377	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	675487858	247517	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	675487858	338078587	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	675487858	192	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	675487858	813	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	675487858	46	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	675487858	399	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	675393729	263795250	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	675487858	891	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	675487858	870	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	675487858	855	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	675487858	837	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	675487858	1552	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	675487858	115878	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	675487858	1446	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	675487858	60	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	675487858	892	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	675487858	742	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	675487858	675352961	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	675487858	50	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	675487858	50	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	675487858	50	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	675487858	1599	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	675487858	185303	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	675487858	391458897	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	675487858	162	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	675487858	432	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	675487858	27	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	675487858	190	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	675393729	310661323	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	675487858	521	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	675487858	510	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	675487858	504	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	675487858	495	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	675487858	2123	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	675487858	183416	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	675487858	2025	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	675487858	69	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	675487858	865	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	675487858	715	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	675487858	675352961	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	675487858	50	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	675487858	50	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	675487858	50	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	675487858	6153	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	675487858	188081	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	675487858	389849581	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	675487858	165	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	675487858	452	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	675487858	23	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	675487858	209	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	675393729	327782188	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	675487858	521	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	675487858	514	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	675487858	507	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	675487858	499	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	675487858	1905	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	675487858	168384	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	675487858	1827	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	675487858	53	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	675487858	893	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	675487858	743	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	675487858	675352961	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	675487858	50	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	675487858	50	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	675487858	50	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	675487858	3549	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	675487858	212736	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	675487858	360637020	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	675487858	177	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	675487858	511	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	675487858	18	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	675487858	219	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	675393729	279422762	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	675487858	574	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	675487858	565	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	675487858	557	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	675487858	549	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	675487858	1162	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	675487858	115859	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	675487858	1085	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	675487858	58	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	675487858	903	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	675487858	753	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	675487858	675352961	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	698354498	131457698	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	698354498	697722639	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	698354498	697722639	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	698354498	183822892	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	698354498	697722639	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	698354498	697722639	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	828	828	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	828	828	0	0
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