Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	160	1			T12	1		T28	3		T39	1
index[0x1]	166	1			T2	1		T3	1		T30	1
index[0x2]	143	1			T12	1		T23	1		T28	3
index[0x3]	175	1			T23	2		T20	1		T28	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	203	1			T2	1		T3	1		T12	1
lens_less_than_1000[1]	107	1			T12	1		T20	1		T37	1
lens_less_than_1000[2]	111	1			T55	1		T28	1		T78	1
lens_less_than_1000[3]	70	1			T23	1		T28	2		T24	1
lens_less_than_1000[4]	42	1			T28	1		T58	1		T265	1
lens_less_than_1000[5]	44	1			T23	1		T26	1		T41	2
lens_less_than_1000[6]	25	1			T28	1		T236	1		T235	1
lens_less_than_1000[7]	16	1			T219	1		T178	1		T266	1
lens_less_than_1000[8]	20	1			T267	1		T268	1		T269	6
lens_less_than_1000[9]	1	1			T270	1		-	-		-	-
len_2	5	1			T222	1		T271	1		T86	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0] , index[0x1] , index[0x2]]	[lens_less_than_1000[9]]	--	--	3

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	60	1			T12	1		T28	1		T39	1
index[0x0]	lens_less_than_1000[1]	32	1			T72	2		T93	1		T233	1
index[0x0]	lens_less_than_1000[2]	22	1			T272	1		T235	1		T273	1
index[0x0]	lens_less_than_1000[3]	12	1			T274	1		T49	1		T91	1
index[0x0]	lens_less_than_1000[4]	13	1			T28	1		T58	1		T275	1
index[0x0]	lens_less_than_1000[5]	6	1			T222	1		T276	1		T179	1
index[0x0]	lens_less_than_1000[6]	6	1			T28	1		T277	1		T278	1
index[0x0]	lens_less_than_1000[7]	2	1			T219	1		T105	1		-	-
index[0x0]	lens_less_than_1000[8]	5	1			T267	1		T268	1		T91	1
index[0x0]	len_2	2	1			T86	1		T243	1		-	-
index[0x1]	lens_less_than_1000[0]	49	1			T2	1		T3	1		T30	1
index[0x1]	lens_less_than_1000[1]	17	1			T37	1		T21	1		T72	1
index[0x1]	lens_less_than_1000[2]	31	1			T55	1		T28	1		T219	1
index[0x1]	lens_less_than_1000[3]	23	1			T267	1		T72	1		T69	2
index[0x1]	lens_less_than_1000[4]	13	1			T279	1		T280	1		T281	2
index[0x1]	lens_less_than_1000[5]	8	1			T26	1		T45	1		T179	2
index[0x1]	lens_less_than_1000[6]	6	1			T75	1		T182	1		T282	1
index[0x1]	lens_less_than_1000[7]	9	1			T266	1		T102	1		T283	4
index[0x1]	lens_less_than_1000[8]	9	1			T269	6		T86	1		T284	1
index[0x1]	len_2	1	1			T271	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	47	1			T28	1		T21	1		T41	2
index[0x2]	lens_less_than_1000[1]	31	1			T12	1		T285	1		T41	1
index[0x2]	lens_less_than_1000[2]	25	1			T25	1		T98	1		T286	1
index[0x2]	lens_less_than_1000[3]	14	1			T23	1		T28	2		T21	1
index[0x2]	lens_less_than_1000[4]	8	1			T265	1		T235	1		T281	1
index[0x2]	lens_less_than_1000[5]	10	1			T93	1		T248	1		T256	1
index[0x2]	lens_less_than_1000[6]	3	1			T236	1		T235	1		T287	1
index[0x2]	lens_less_than_1000[7]	3	1			T178	1		T288	1		T289	1
index[0x2]	lens_less_than_1000[8]	1	1			T86	1		-	-		-	-
index[0x2]	len_2	1	1			T243	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	47	1			T23	1		T28	1		T26	1
index[0x3]	lens_less_than_1000[1]	27	1			T20	1		T26	1		T25	1
index[0x3]	lens_less_than_1000[2]	33	1			T78	1		T21	1		T290	1
index[0x3]	lens_less_than_1000[3]	21	1			T24	1		T291	1		T77	2
index[0x3]	lens_less_than_1000[4]	8	1			T292	1		T106	1		T293	1
index[0x3]	lens_less_than_1000[5]	20	1			T23	1		T41	2		T273	1
index[0x3]	lens_less_than_1000[6]	10	1			T47	1		T251	3		T294	1
index[0x3]	lens_less_than_1000[7]	2	1			T295	1		T296	1		-	-
index[0x3]	lens_less_than_1000[8]	5	1			T86	1		T297	3		T298	1
index[0x3]	lens_less_than_1000[9]	1	1			T270	1		-	-		-	-
index[0x3]	len_2	1	1			T222	1		-	-		-	-