Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	60	1			T12	2		T23	1		T37	1
class_index[0x1]	69	1			T12	1		T23	1		T64	1
class_index[0x2]	53	1			T3	1		T18	1		T28	1
class_index[0x3]	58	1			T28	1		T65	1		T27	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	108	1			T18	1		T12	3		T64	1
intr_timeout_cnt[1]	46	1			T41	1		T108	1		T100	1
intr_timeout_cnt[2]	21	1			T3	1		T23	1		T65	2
intr_timeout_cnt[3]	9	1			T110	1		T101	1		T91	1
intr_timeout_cnt[4]	12	1			T28	1		T58	1		T72	1
intr_timeout_cnt[5]	12	1			T28	1		T58	2		T45	1
intr_timeout_cnt[6]	9	1			T61	1		T248	1		T74	1
intr_timeout_cnt[7]	9	1			T23	1		T60	1		T61	1
intr_timeout_cnt[8]	8	1			T37	1		T60	1		T109	1
intr_timeout_cnt[9]	6	1			T72	1		T101	1		T249	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	21	1			T12	2		T44	1		T47	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T41	1		T100	1		T250	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T63	1		T73	1		T76	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T110	1		T101	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	2	1			T251	1		T52	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	3	1			T58	1		T45	1		T252	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T74	1		T253	1		T254	1
class_index[0x0]	intr_timeout_cnt[7]	2	1			T23	1		T255	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	5	1			T37	1		T109	1		T101	1
class_index[0x0]	intr_timeout_cnt[9]	1	1			T249	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	40	1			T12	1		T64	1		T58	1
class_index[0x1]	intr_timeout_cnt[1]	9	1			T256	1		T91	1		T257	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T23	1		T65	1		T58	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T91	1		T86	1		T106	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T72	1		T86	1		T258	1
class_index[0x1]	intr_timeout_cnt[5]	4	1			T58	1		T109	1		T22	1
class_index[0x1]	intr_timeout_cnt[6]	3	1			T61	1		T248	1		T259	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T60	1		T61	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	21	1			T18	1		T75	1		T49	1
class_index[0x2]	intr_timeout_cnt[1]	10	1			T110	3		T51	1		T256	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T3	1		T72	1		T76	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T106	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	4	1			T28	1		T58	1		T45	1
class_index[0x2]	intr_timeout_cnt[6]	2	1			T90	1		T252	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	5	1			T260	1		T252	4		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T60	1		T86	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T72	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	26	1			T27	1		T58	1		T41	1
class_index[0x3]	intr_timeout_cnt[1]	12	1			T108	1		T110	1		T101	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T65	1		T101	2		T261	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T262	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	3	1			T109	1		T87	1		T239	1
class_index[0x3]	intr_timeout_cnt[5]	5	1			T28	1		T90	1		T263	2
class_index[0x3]	intr_timeout_cnt[6]	1	1			T257	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T91	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	4	1			T101	1		T86	1		T264	1