Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	352734	1			T1	1215		T2	1487		T3	11
all_values[1]	352734	1			T1	1215		T2	1487		T3	11
all_values[2]	352734	1			T1	1215		T2	1487		T3	11
all_values[3]	352734	1			T1	1215		T2	1487		T3	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

702365

1

T1

2402

T2

3030

T3

17

auto[1]

708571

1

T1

2458

T2

2918

T3

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

844514

1

T1

4002

T2

3021

T3

6

auto[1]

566422

1

T1

858

T2

2927

T3

38

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99880	1			T1	622		T2	386		T3	1
all_values[0]	auto[0]	auto[1]	76034	1			T2	381		T3	7		T4	360
all_values[0]	auto[1]	auto[0]	100922	1			T1	592		T2	367		T4	389
all_values[0]	auto[1]	auto[1]	75898	1			T1	1		T2	353		T3	3
all_values[1]	auto[0]	auto[0]	106263	1			T1	344		T2	387		T4	385
all_values[1]	auto[0]	auto[1]	69233	1			T1	277		T2	385		T4	379
all_values[1]	auto[1]	auto[0]	107679	1			T1	337		T2	358		T3	1
all_values[1]	auto[1]	auto[1]	69559	1			T1	257		T2	357		T3	10
all_values[2]	auto[0]	auto[0]	107150	1			T1	409		T2	373		T4	382
all_values[2]	auto[0]	auto[1]	68648	1			T1	174		T2	343		T3	3
all_values[2]	auto[1]	auto[0]	108443	1			T1	485		T2	405		T3	2
all_values[2]	auto[1]	auto[1]	68493	1			T1	147		T2	366		T3	6
all_values[3]	auto[0]	auto[0]	106184	1			T1	575		T2	388		T3	1
all_values[3]	auto[0]	auto[1]	68973	1			T1	1		T2	387		T3	5
all_values[3]	auto[1]	auto[0]	107993	1			T1	638		T2	357		T3	1
all_values[3]	auto[1]	auto[1]	69584	1			T1	1		T2	355		T3	4