Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	352734	1			T1	1215		T2	1487		T3	11
all_pins[1]	352734	1			T1	1215		T2	1487		T3	11
all_pins[2]	352734	1			T1	1215		T2	1487		T3	11
all_pins[3]	352734	1			T1	1215		T2	1487		T3	11

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1127402	1			T1	4454		T2	4517		T3	21
values[0x1]	283534	1			T1	406		T2	1431		T3	23
transitions[0x0=>0x1]	189597	1			T1	349		T2	918		T3	11
transitions[0x1=>0x0]	189851	1			T1	349		T2	919		T3	11

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	276836	1			T1	1214		T2	1134		T3	8
all_pins[0]	values[0x1]	75898	1			T1	1		T2	353		T3	3
all_pins[0]	transitions[0x0=>0x1]	75260	1			T1	1		T2	352		T3	2
all_pins[0]	transitions[0x1=>0x0]	69200	1			T1	1		T2	355		T3	3
all_pins[1]	values[0x0]	283175	1			T1	958		T2	1130		T3	1
all_pins[1]	values[0x1]	69559	1			T1	257		T2	357		T3	10
all_pins[1]	transitions[0x0=>0x1]	38074	1			T1	257		T2	195		T3	7
all_pins[1]	transitions[0x1=>0x0]	44413	1			T1	1		T2	191		T4	205
all_pins[2]	values[0x0]	284241	1			T1	1068		T2	1121		T3	5
all_pins[2]	values[0x1]	68493	1			T1	147		T2	366		T3	6
all_pins[2]	transitions[0x0=>0x1]	37608	1			T1	90		T2	185		T4	192
all_pins[2]	transitions[0x1=>0x0]	38674	1			T1	200		T2	176		T3	4
all_pins[3]	values[0x0]	283150	1			T1	1214		T2	1132		T3	7
all_pins[3]	values[0x1]	69584	1			T1	1		T2	355		T3	4
all_pins[3]	transitions[0x0=>0x1]	38655	1			T1	1		T2	186		T3	2
all_pins[3]	transitions[0x1=>0x0]	37564	1			T1	147		T2	197		T3	4