Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87309	1			T2	708		T4	531		T5	975
accum_cnt_1000	228133	1			T2	1208		T4	488		T5	980
accum_cnt_100	26530	1			T2	63		T3	13		T4	23
accum_cnt_50	69603	1			T2	55		T3	4		T4	25
accum_cnt_10	159823	1			T1	1019		T2	14		T3	36
accum_cnt_0	417482	1			T1	2569		T2	2155		T3	3

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	259789	1			T1	897		T2	1077		T3	14
class_index[0x1]	259789	1			T1	897		T2	1077		T3	14
class_index[0x2]	259789	1			T1	897		T2	1077		T3	14
class_index[0x3]	259789	1			T1	897		T2	1077		T3	14

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22284	1			T5	545		T17	300		T12	625
class_index[0x0]	accum_cnt_1000	62401	1			T5	594		T17	725		T12	823
class_index[0x0]	accum_cnt_100	7634	1			T5	36		T17	31		T12	106
class_index[0x0]	accum_cnt_50	18516	1			T3	2		T15	5		T5	24
class_index[0x0]	accum_cnt_10	44088	1			T1	893		T3	12		T15	3
class_index[0x0]	accum_cnt_0	91115	1			T1	4		T2	1077		T4	1112
class_index[0x1]	accum_cnt_2000	21613	1			T2	476		T4	531		T24	443
class_index[0x1]	accum_cnt_1000	52992	1			T2	439		T4	488		T17	936
class_index[0x1]	accum_cnt_100	5668	1			T2	26		T4	23		T17	88
class_index[0x1]	accum_cnt_50	15907	1			T2	26		T4	25		T17	49
class_index[0x1]	accum_cnt_10	46035	1			T2	5		T3	11		T4	7
class_index[0x1]	accum_cnt_0	105390	1			T1	897		T3	3		T4	3
class_index[0x2]	accum_cnt_2000	23464	1			T2	232		T14	212		T19	238
class_index[0x2]	accum_cnt_1000	53359	1			T2	769		T14	627		T19	174
class_index[0x2]	accum_cnt_100	6232	1			T2	37		T3	13		T13	968
class_index[0x2]	accum_cnt_50	12078	1			T2	29		T18	14		T12	514
class_index[0x2]	accum_cnt_10	34843	1			T1	1		T2	9		T3	1
class_index[0x2]	accum_cnt_0	117218	1			T1	896		T2	1		T4	1112
class_index[0x3]	accum_cnt_2000	19948	1			T5	430		T28	217		T39	532
class_index[0x3]	accum_cnt_1000	59381	1			T5	386		T12	833		T38	679
class_index[0x3]	accum_cnt_100	6996	1			T5	21		T12	43		T38	161
class_index[0x3]	accum_cnt_50	23102	1			T3	2		T5	17		T18	16
class_index[0x3]	accum_cnt_10	34857	1			T1	125		T3	12		T4	1
class_index[0x3]	accum_cnt_0	103759	1			T1	772		T2	1077		T4	1111