Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	13724	1			T2	279		T12	688		T7	1
alert[0x1]	3271	1			T2	130		T13	754		T19	30
alert[0x2]	5437	1			T12	9		T58	6		T267	4
alert[0x3]	9121	1			T12	48		T13	456		T23	12
alert[0x4]	3082	1			T58	1		T98	52		T21	2
alert[0x5]	3799	1			T2	106		T12	27		T7	1
alert[0x6]	4700	1			T19	142		T8	1		T216	6
alert[0x7]	12887	1			T13	92		T14	1		T216	164
alert[0x8]	2666	1			T13	27		T36	1		T58	4
alert[0x9]	12993	1			T7	1		T13	5		T56	6
alert[0xa]	4638	1			T2	1686		T6	1		T12	19
alert[0xb]	8835	1			T12	8		T7	1		T19	1686
alert[0xc]	6378	1			T2	20		T7	1		T13	213
alert[0xd]	8835	1			T19	109		T216	23		T235	5
alert[0xe]	5180	1			T98	3		T236	1		T69	1
alert[0xf]	3988	1			T13	54		T220	1		T42	35
alert[0x10]	3511	1			T2	97		T12	27		T13	101
alert[0x11]	23304	1			T12	2139		T13	73		T23	11
alert[0x12]	3750	1			T6	1		T12	62		T41	6
alert[0x13]	19015	1			T2	3527		T6	1		T58	2
alert[0x14]	3327	1			T2	471		T41	1		T216	21
alert[0x15]	3265	1			T6	1		T12	14		T72	825
alert[0x16]	7317	1			T2	1085		T6	1		T12	1
alert[0x17]	2440	1			T2	74		T12	31		T7	1
alert[0x18]	4454	1			T12	49		T7	1		T13	122
alert[0x19]	3469	1			T12	497		T7	1		T23	5
alert[0x1a]	5360	1			T12	491		T13	1737		T303	1
alert[0x1b]	6261	1			T13	28		T19	233		T58	5
alert[0x1c]	3286	1			T12	6		T7	2		T36	1
alert[0x1d]	7689	1			T2	479		T12	1		T8	1
alert[0x1e]	3307	1			T2	166		T6	1		T12	106
alert[0x1f]	5083	1			T2	79		T13	181		T23	1
alert[0x20]	5867	1			T12	10		T13	163		T23	13
alert[0x21]	8148	1			T12	33		T8	1		T236	1
alert[0x22]	4039	1			T2	124		T12	56		T236	1
alert[0x23]	4825	1			T13	1318		T19	84		T65	62
alert[0x24]	3856	1			T3	4		T12	1		T19	14
alert[0x25]	6934	1			T2	408		T6	1		T13	200
alert[0x26]	12230	1			T2	19		T12	69		T19	17
alert[0x27]	7546	1			T2	77		T7	1		T13	292
alert[0x28]	7644	1			T2	797		T12	251		T7	1
alert[0x29]	6919	1			T2	8		T19	10		T216	32
alert[0x2a]	5769	1			T2	648		T13	21		T58	1
alert[0x2b]	3801	1			T7	1		T13	56		T19	2
alert[0x2c]	9473	1			T12	6		T23	1		T107	1
alert[0x2d]	15492	1			T2	1209		T6	1		T23	57
alert[0x2e]	2952	1			T12	55		T13	15		T58	2
alert[0x2f]	2992	1			T19	77		T58	7		T304	1
alert[0x30]	7171	1			T1	1		T12	5		T56	2
alert[0x31]	3223	1			T6	1		T12	2		T19	206
alert[0x32]	3598	1			T36	2		T65	1		T98	56
alert[0x33]	3976	1			T98	4		T236	1		T235	35
alert[0x34]	1346	1			T6	2		T36	1		T65	8
alert[0x35]	7533	1			T2	24		T56	2		T65	1
alert[0x36]	9591	1			T19	37		T216	6		T219	5
alert[0x37]	5859	1			T2	3		T3	6		T13	26
alert[0x38]	5997	1			T12	42		T7	1		T36	1
alert[0x39]	12671	1			T2	33		T12	226		T41	3
alert[0x3a]	4526	1			T7	1		T19	38		T232	1
alert[0x3b]	4668	1			T7	1		T8	1		T236	1
alert[0x3c]	1561	1			T3	24		T7	1		T19	15
alert[0x3d]	2204	1			T58	12		T236	2		T42	1
alert[0x3e]	2988	1			T2	79		T7	1		T19	44
alert[0x3f]	9282	1			T2	1532		T12	3		T13	21
alert[0x40]	3008	1			T2	42		T12	1		T19	451

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	128588	1			T2	13145		T3	1		T6	8
class_i[0x1]	78902	1			T2	11		T3	33		T6	1
class_i[0x2]	71305	1			T2	10		T6	2		T12	767
class_i[0x3]	133266	1			T1	1		T2	36		T23	13

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

411353

1

T2

13202

T3

34

T12

4983

alert_ping_fail

708

1

T1

1

T6

11

T7

18

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	13718	1			T2	279		T12	688		T13	661
alert_integrity_fail	alert[0x1]	3263	1			T2	130		T13	754		T19	30
alert_integrity_fail	alert[0x2]	5432	1			T12	9		T58	6		T267	4
alert_integrity_fail	alert[0x3]	9115	1			T12	48		T13	456		T23	12
alert_integrity_fail	alert[0x4]	3071	1			T58	1		T98	52		T21	2
alert_integrity_fail	alert[0x5]	3777	1			T2	106		T12	27		T65	1
alert_integrity_fail	alert[0x6]	4676	1			T19	142		T216	6		T74	2
alert_integrity_fail	alert[0x7]	12874	1			T13	92		T14	1		T216	164
alert_integrity_fail	alert[0x8]	2657	1			T13	27		T36	1		T58	4
alert_integrity_fail	alert[0x9]	12980	1			T13	5		T56	6		T41	1
alert_integrity_fail	alert[0xa]	4626	1			T2	1686		T12	19		T13	21
alert_integrity_fail	alert[0xb]	8822	1			T12	8		T19	1686		T36	2
alert_integrity_fail	alert[0xc]	6368	1			T2	20		T13	213		T19	78
alert_integrity_fail	alert[0xd]	8829	1			T19	109		T216	23		T235	5
alert_integrity_fail	alert[0xe]	5170	1			T98	3		T69	1		T305	2
alert_integrity_fail	alert[0xf]	3983	1			T13	54		T42	35		T235	647
alert_integrity_fail	alert[0x10]	3498	1			T2	97		T12	27		T13	101
alert_integrity_fail	alert[0x11]	23297	1			T12	2139		T13	73		T23	11
alert_integrity_fail	alert[0x12]	3740	1			T12	62		T41	6		T235	180
alert_integrity_fail	alert[0x13]	19000	1			T2	3527		T58	2		T216	3
alert_integrity_fail	alert[0x14]	3313	1			T2	471		T41	1		T216	21
alert_integrity_fail	alert[0x15]	3256	1			T12	14		T72	825		T235	258
alert_integrity_fail	alert[0x16]	7295	1			T2	1085		T12	1		T13	667
alert_integrity_fail	alert[0x17]	2427	1			T2	74		T12	31		T13	20
alert_integrity_fail	alert[0x18]	4445	1			T12	49		T13	122		T19	443
alert_integrity_fail	alert[0x19]	3457	1			T12	497		T23	5		T28	32
alert_integrity_fail	alert[0x1a]	5351	1			T12	491		T13	1737		T235	460
alert_integrity_fail	alert[0x1b]	6246	1			T13	28		T19	233		T58	5
alert_integrity_fail	alert[0x1c]	3274	1			T12	6		T36	1		T56	2
alert_integrity_fail	alert[0x1d]	7677	1			T2	479		T12	1		T216	9
alert_integrity_fail	alert[0x1e]	3299	1			T2	166		T12	106		T19	878
alert_integrity_fail	alert[0x1f]	5068	1			T2	79		T13	181		T23	1
alert_integrity_fail	alert[0x20]	5862	1			T12	10		T13	163		T23	13
alert_integrity_fail	alert[0x21]	8133	1			T12	33		T216	3		T248	13
alert_integrity_fail	alert[0x22]	4032	1			T2	124		T12	56		T72	157
alert_integrity_fail	alert[0x23]	4814	1			T13	1318		T19	84		T65	62
alert_integrity_fail	alert[0x24]	3846	1			T3	4		T12	1		T19	14
alert_integrity_fail	alert[0x25]	6920	1			T2	408		T13	200		T19	22
alert_integrity_fail	alert[0x26]	12222	1			T2	19		T12	69		T19	17
alert_integrity_fail	alert[0x27]	7537	1			T2	77		T13	292		T23	41
alert_integrity_fail	alert[0x28]	7631	1			T2	797		T12	251		T23	14
alert_integrity_fail	alert[0x29]	6915	1			T2	8		T19	10		T216	32
alert_integrity_fail	alert[0x2a]	5761	1			T2	648		T13	21		T58	1
alert_integrity_fail	alert[0x2b]	3795	1			T13	56		T19	2		T235	87
alert_integrity_fail	alert[0x2c]	9456	1			T12	6		T23	1		T216	8
alert_integrity_fail	alert[0x2d]	15477	1			T2	1209		T23	57		T267	1
alert_integrity_fail	alert[0x2e]	2946	1			T12	55		T13	15		T58	2
alert_integrity_fail	alert[0x2f]	2983	1			T19	77		T58	7		T21	4
alert_integrity_fail	alert[0x30]	7156	1			T12	5		T56	2		T65	18
alert_integrity_fail	alert[0x31]	3217	1			T12	2		T19	206		T36	5
alert_integrity_fail	alert[0x32]	3588	1			T36	2		T65	1		T98	56
alert_integrity_fail	alert[0x33]	3964	1			T98	4		T235	35		T47	2
alert_integrity_fail	alert[0x34]	1334	1			T36	1		T65	8		T41	9
alert_integrity_fail	alert[0x35]	7525	1			T2	24		T56	2		T65	1
alert_integrity_fail	alert[0x36]	9578	1			T19	37		T216	6		T219	5
alert_integrity_fail	alert[0x37]	5848	1			T2	3		T3	6		T13	26
alert_integrity_fail	alert[0x38]	5986	1			T12	42		T36	1		T56	12
alert_integrity_fail	alert[0x39]	12658	1			T2	33		T12	226		T41	3
alert_integrity_fail	alert[0x3a]	4516	1			T19	38		T235	42		T45	9
alert_integrity_fail	alert[0x3b]	4656	1			T219	1		T69	4		T45	3
alert_integrity_fail	alert[0x3c]	1546	1			T3	24		T19	15		T248	4
alert_integrity_fail	alert[0x3d]	2188	1			T58	12		T42	1		T248	2
alert_integrity_fail	alert[0x3e]	2980	1			T2	79		T19	44		T72	39
alert_integrity_fail	alert[0x3f]	9275	1			T2	1532		T12	3		T13	21
alert_integrity_fail	alert[0x40]	3004	1			T2	42		T12	1		T19	451
alert_ping_fail	alert[0x0]	6	1			T7	1		T236	1		T306	1
alert_ping_fail	alert[0x1]	8	1			T303	1		T307	1		T188	1
alert_ping_fail	alert[0x2]	5	1			T232	1		T227	1		T306	1
alert_ping_fail	alert[0x3]	6	1			T308	1		T269	1		T309	1
alert_ping_fail	alert[0x4]	11	1			T303	1		T310	1		T308	1
alert_ping_fail	alert[0x5]	22	1			T7	1		T232	1		T308	1
alert_ping_fail	alert[0x6]	24	1			T8	1		T220	1		T303	2
alert_ping_fail	alert[0x7]	13	1			T220	1		T232	1		T301	1
alert_ping_fail	alert[0x8]	9	1			T236	1		T303	1		T310	1
alert_ping_fail	alert[0x9]	13	1			T7	1		T220	1		T232	2
alert_ping_fail	alert[0xa]	12	1			T6	1		T8	1		T310	1
alert_ping_fail	alert[0xb]	13	1			T7	1		T8	1		T310	1
alert_ping_fail	alert[0xc]	10	1			T7	1		T236	1		T220	2
alert_ping_fail	alert[0xd]	6	1			T310	1		T227	1		T311	1
alert_ping_fail	alert[0xe]	10	1			T236	1		T311	1		T312	1
alert_ping_fail	alert[0xf]	5	1			T220	1		T313	1		T314	1
alert_ping_fail	alert[0x10]	13	1			T303	1		T315	1		T316	1
alert_ping_fail	alert[0x11]	7	1			T232	1		T308	1		T317	1
alert_ping_fail	alert[0x12]	10	1			T6	1		T220	1		T303	1
alert_ping_fail	alert[0x13]	15	1			T6	1		T300	3		T318	3
alert_ping_fail	alert[0x14]	14	1			T232	1		T302	1		T316	2
alert_ping_fail	alert[0x15]	9	1			T6	1		T269	1		T319	1
alert_ping_fail	alert[0x16]	22	1			T6	1		T38	1		T8	2
alert_ping_fail	alert[0x17]	13	1			T7	1		T8	1		T316	2
alert_ping_fail	alert[0x18]	9	1			T7	1		T8	1		T220	1
alert_ping_fail	alert[0x19]	12	1			T7	1		T227	1		T320	1
alert_ping_fail	alert[0x1a]	9	1			T303	1		T308	2		T312	1
alert_ping_fail	alert[0x1b]	15	1			T227	1		T321	1		T269	1
alert_ping_fail	alert[0x1c]	12	1			T7	2		T8	1		T306	1
alert_ping_fail	alert[0x1d]	12	1			T8	1		T303	1		T307	1
alert_ping_fail	alert[0x1e]	8	1			T6	1		T8	1		T220	1
alert_ping_fail	alert[0x1f]	15	1			T304	1		T310	1		T315	1
alert_ping_fail	alert[0x20]	5	1			T236	1		T220	1		T311	1
alert_ping_fail	alert[0x21]	15	1			T8	1		T236	1		T220	1
alert_ping_fail	alert[0x22]	7	1			T236	1		T322	1		T323	1
alert_ping_fail	alert[0x23]	11	1			T304	1		T236	1		T220	1
alert_ping_fail	alert[0x24]	10	1			T315	1		T316	1		T321	1
alert_ping_fail	alert[0x25]	14	1			T6	1		T310	1		T316	1
alert_ping_fail	alert[0x26]	8	1			T307	1		T312	1		T324	1
alert_ping_fail	alert[0x27]	9	1			T7	1		T220	1		T232	1
alert_ping_fail	alert[0x28]	13	1			T7	1		T236	1		T316	1
alert_ping_fail	alert[0x29]	4	1			T220	1		T314	1		T325	1
alert_ping_fail	alert[0x2a]	8	1			T303	1		T302	2		T326	1
alert_ping_fail	alert[0x2b]	6	1			T7	1		T310	1		T308	1
alert_ping_fail	alert[0x2c]	17	1			T107	1		T232	1		T308	1
alert_ping_fail	alert[0x2d]	15	1			T6	1		T232	1		T326	1
alert_ping_fail	alert[0x2e]	6	1			T220	1		T302	2		T316	1
alert_ping_fail	alert[0x2f]	9	1			T304	1		T310	1		T301	2
alert_ping_fail	alert[0x30]	15	1			T1	1		T304	1		T310	1
alert_ping_fail	alert[0x31]	6	1			T6	1		T8	1		T307	1
alert_ping_fail	alert[0x32]	10	1			T306	1		T312	1		T317	1
alert_ping_fail	alert[0x33]	12	1			T236	1		T310	1		T316	1
alert_ping_fail	alert[0x34]	12	1			T6	2		T303	1		T292	2
alert_ping_fail	alert[0x35]	8	1			T327	1		T292	1		T269	1
alert_ping_fail	alert[0x36]	13	1			T308	1		T316	1		T227	1
alert_ping_fail	alert[0x37]	11	1			T187	1		T103	1		T328	1
alert_ping_fail	alert[0x38]	11	1			T7	1		T304	1		T308	2
alert_ping_fail	alert[0x39]	13	1			T303	2		T315	1		T227	1
alert_ping_fail	alert[0x3a]	10	1			T7	1		T232	1		T310	2
alert_ping_fail	alert[0x3b]	12	1			T7	1		T8	1		T236	1
alert_ping_fail	alert[0x3c]	15	1			T7	1		T304	1		T308	1
alert_ping_fail	alert[0x3d]	16	1			T236	2		T303	1		T308	1
alert_ping_fail	alert[0x3e]	8	1			T7	1		T8	1		T327	2
alert_ping_fail	alert[0x3f]	7	1			T312	1		T314	1		T271	1
alert_ping_fail	alert[0x40]	4	1			T319	1		T313	1		T271	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	128502	1			T2	13145		T3	1		T12	3923
alert_integrity_fail	class_i[0x1]	78713	1			T2	11		T3	33		T12	293
alert_integrity_fail	class_i[0x2]	71129	1			T2	10		T12	767		T13	7322
alert_integrity_fail	class_i[0x3]	133009	1			T2	36		T23	13		T19	3
alert_ping_fail	class_i[0x0]	86	1			T6	8		T8	2		T304	1
alert_ping_fail	class_i[0x1]	189	1			T6	1		T7	1		T8	1
alert_ping_fail	class_i[0x2]	176	1			T6	2		T7	17		T38	1
alert_ping_fail	class_i[0x3]	257	1			T1	1		T107	1		T8	11