Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.72 100.00 100.00 100.00 99.38 99.52


Total test records in report: 828
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T772 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4008899695 Apr 15 12:36:46 PM PDT 24 Apr 15 12:36:49 PM PDT 24 17438879 ps
T773 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3895094502 Apr 15 12:36:45 PM PDT 24 Apr 15 12:36:51 PM PDT 24 164039366 ps
T774 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1251398944 Apr 15 12:36:44 PM PDT 24 Apr 15 12:36:51 PM PDT 24 40279171 ps
T775 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2290885740 Apr 15 12:36:45 PM PDT 24 Apr 15 12:38:20 PM PDT 24 1996018390 ps
T776 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1747198863 Apr 15 12:36:46 PM PDT 24 Apr 15 12:39:47 PM PDT 24 2210458299 ps
T777 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4016218899 Apr 15 12:37:06 PM PDT 24 Apr 15 12:37:12 PM PDT 24 294895956 ps
T778 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2773773013 Apr 15 12:36:52 PM PDT 24 Apr 15 12:37:16 PM PDT 24 169477171 ps
T779 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1764259216 Apr 15 12:37:24 PM PDT 24 Apr 15 12:37:33 PM PDT 24 270541367 ps
T167 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.322058402 Apr 15 12:37:00 PM PDT 24 Apr 15 12:37:04 PM PDT 24 58082113 ps
T158 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2853984394 Apr 15 12:36:57 PM PDT 24 Apr 15 12:37:19 PM PDT 24 305786661 ps
T780 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3220100641 Apr 15 12:36:57 PM PDT 24 Apr 15 12:37:03 PM PDT 24 270818761 ps
T149 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.961553797 Apr 15 12:36:52 PM PDT 24 Apr 15 12:44:58 PM PDT 24 6944525301 ps
T781 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1034268799 Apr 15 12:37:00 PM PDT 24 Apr 15 12:37:10 PM PDT 24 94008818 ps
T782 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1074828551 Apr 15 12:37:08 PM PDT 24 Apr 15 12:37:11 PM PDT 24 8339255 ps
T783 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3643109441 Apr 15 12:36:45 PM PDT 24 Apr 15 12:36:54 PM PDT 24 159389693 ps
T784 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2794870593 Apr 15 12:36:54 PM PDT 24 Apr 15 12:37:02 PM PDT 24 234096240 ps
T785 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3504664081 Apr 15 12:37:00 PM PDT 24 Apr 15 12:37:03 PM PDT 24 6507688 ps
T145 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1112847965 Apr 15 12:36:51 PM PDT 24 Apr 15 12:56:01 PM PDT 24 17362296829 ps
T786 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.905510948 Apr 15 12:36:57 PM PDT 24 Apr 15 12:37:00 PM PDT 24 6189297 ps
T787 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.889932390 Apr 15 12:36:47 PM PDT 24 Apr 15 12:36:55 PM PDT 24 52168568 ps
T788 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3421128606 Apr 15 12:36:56 PM PDT 24 Apr 15 12:37:20 PM PDT 24 1384172272 ps
T789 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3722499488 Apr 15 12:36:57 PM PDT 24 Apr 15 12:37:00 PM PDT 24 13451929 ps
T790 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1711150533 Apr 15 12:36:56 PM PDT 24 Apr 15 12:36:58 PM PDT 24 10906815 ps
T791 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3236490412 Apr 15 12:36:50 PM PDT 24 Apr 15 12:37:16 PM PDT 24 2276463226 ps
T792 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2113575253 Apr 15 12:36:52 PM PDT 24 Apr 15 12:36:54 PM PDT 24 19824862 ps
T168 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3873984709 Apr 15 12:36:54 PM PDT 24 Apr 15 12:36:57 PM PDT 24 357222490 ps
T793 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2281253094 Apr 15 12:36:54 PM PDT 24 Apr 15 12:37:01 PM PDT 24 139399913 ps
T148 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1089716711 Apr 15 12:36:46 PM PDT 24 Apr 15 12:44:58 PM PDT 24 14656844690 ps
T137 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.634463978 Apr 15 12:37:06 PM PDT 24 Apr 15 12:42:23 PM PDT 24 35578713195 ps
T794 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3211635720 Apr 15 12:37:07 PM PDT 24 Apr 15 12:37:13 PM PDT 24 49752714 ps
T795 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3213270101 Apr 15 12:37:01 PM PDT 24 Apr 15 12:37:33 PM PDT 24 1803839255 ps
T796 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2125919763 Apr 15 12:36:59 PM PDT 24 Apr 15 12:37:32 PM PDT 24 495511691 ps
T170 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1142886047 Apr 15 12:37:07 PM PDT 24 Apr 15 12:37:11 PM PDT 24 94282746 ps
T797 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2070294951 Apr 15 12:36:47 PM PDT 24 Apr 15 12:36:53 PM PDT 24 97448958 ps
T798 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2241009462 Apr 15 12:36:46 PM PDT 24 Apr 15 12:37:51 PM PDT 24 2234255401 ps
T143 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3005629474 Apr 15 12:36:53 PM PDT 24 Apr 15 12:42:24 PM PDT 24 3107477715 ps
T799 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.388781375 Apr 15 12:36:50 PM PDT 24 Apr 15 12:36:56 PM PDT 24 222679294 ps
T800 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.508610267 Apr 15 12:36:58 PM PDT 24 Apr 15 12:37:01 PM PDT 24 7587913 ps
T150 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2113809343 Apr 15 12:37:07 PM PDT 24 Apr 15 12:43:15 PM PDT 24 9914333432 ps
T146 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3544855387 Apr 15 12:36:49 PM PDT 24 Apr 15 12:39:44 PM PDT 24 16153383306 ps
T801 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2825403655 Apr 15 12:36:45 PM PDT 24 Apr 15 12:36:53 PM PDT 24 76079155 ps
T147 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.251767894 Apr 15 12:37:02 PM PDT 24 Apr 15 12:40:18 PM PDT 24 3039813401 ps
T134 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3693389791 Apr 15 12:36:57 PM PDT 24 Apr 15 12:40:17 PM PDT 24 6716118594 ps
T802 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2152377330 Apr 15 12:36:48 PM PDT 24 Apr 15 12:37:31 PM PDT 24 3652457629 ps
T803 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2812651730 Apr 15 12:36:55 PM PDT 24 Apr 15 12:37:03 PM PDT 24 198389508 ps
T804 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2139784083 Apr 15 12:37:01 PM PDT 24 Apr 15 12:37:07 PM PDT 24 272739800 ps
T151 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3295526493 Apr 15 12:36:56 PM PDT 24 Apr 15 12:54:45 PM PDT 24 78253693909 ps
T805 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2617797177 Apr 15 12:37:00 PM PDT 24 Apr 15 12:37:03 PM PDT 24 6734752 ps
T359 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4153882450 Apr 15 12:36:58 PM PDT 24 Apr 15 12:44:41 PM PDT 24 21618469672 ps
T360 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3404688554 Apr 15 12:36:56 PM PDT 24 Apr 15 12:44:24 PM PDT 24 6038075152 ps
T806 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2302001709 Apr 15 12:36:59 PM PDT 24 Apr 15 12:37:05 PM PDT 24 105183111 ps
T807 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1497809672 Apr 15 12:36:59 PM PDT 24 Apr 15 12:37:18 PM PDT 24 1004486599 ps
T808 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2617081847 Apr 15 12:36:46 PM PDT 24 Apr 15 12:36:59 PM PDT 24 173407403 ps
T361 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2246985305 Apr 15 12:36:44 PM PDT 24 Apr 15 12:41:35 PM PDT 24 2224092151 ps
T809 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.388859314 Apr 15 12:37:06 PM PDT 24 Apr 15 12:37:26 PM PDT 24 280837198 ps
T810 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.325368679 Apr 15 12:36:56 PM PDT 24 Apr 15 12:37:10 PM PDT 24 184156958 ps
T164 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3212904326 Apr 15 12:36:52 PM PDT 24 Apr 15 12:36:58 PM PDT 24 92211558 ps
T811 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.878302113 Apr 15 12:37:09 PM PDT 24 Apr 15 12:37:11 PM PDT 24 9271791 ps
T144 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.829446807 Apr 15 12:37:06 PM PDT 24 Apr 15 12:41:42 PM PDT 24 4067916149 ps
T812 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4202815140 Apr 15 12:36:46 PM PDT 24 Apr 15 12:36:56 PM PDT 24 90688818 ps
T813 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1422249473 Apr 15 12:37:00 PM PDT 24 Apr 15 12:37:03 PM PDT 24 12548969 ps
T814 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2167966392 Apr 15 12:36:49 PM PDT 24 Apr 15 12:37:24 PM PDT 24 1041437208 ps
T815 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1602169672 Apr 15 12:37:01 PM PDT 24 Apr 15 12:37:03 PM PDT 24 6778674 ps
T816 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.203987004 Apr 15 12:36:53 PM PDT 24 Apr 15 12:37:03 PM PDT 24 575733076 ps
T817 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3934674131 Apr 15 12:36:57 PM PDT 24 Apr 15 12:37:05 PM PDT 24 111641060 ps
T818 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3702447591 Apr 15 12:37:01 PM PDT 24 Apr 15 12:37:04 PM PDT 24 8532739 ps
T819 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2357674171 Apr 15 12:36:50 PM PDT 24 Apr 15 12:37:06 PM PDT 24 897814932 ps
T820 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3403918247 Apr 15 12:37:03 PM PDT 24 Apr 15 12:37:46 PM PDT 24 667532797 ps
T821 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2399798980 Apr 15 12:36:57 PM PDT 24 Apr 15 12:36:59 PM PDT 24 9203547 ps
T822 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2934057152 Apr 15 12:36:57 PM PDT 24 Apr 15 12:36:59 PM PDT 24 6367993 ps
T823 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2632892739 Apr 15 12:37:01 PM PDT 24 Apr 15 12:37:07 PM PDT 24 96657857 ps
T824 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3389726091 Apr 15 12:36:54 PM PDT 24 Apr 15 12:37:00 PM PDT 24 243122043 ps
T825 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2791762880 Apr 15 12:37:00 PM PDT 24 Apr 15 12:37:03 PM PDT 24 42258166 ps
T826 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1796761496 Apr 15 12:36:48 PM PDT 24 Apr 15 12:37:12 PM PDT 24 1344609162 ps
T827 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1065141045 Apr 15 12:36:47 PM PDT 24 Apr 15 12:36:56 PM PDT 24 270017734 ps
T176 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3988000146 Apr 15 12:36:55 PM PDT 24 Apr 15 12:37:31 PM PDT 24 872455731 ps
T828 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1887043534 Apr 15 12:36:59 PM PDT 24 Apr 15 12:37:01 PM PDT 24 8977689 ps
T165 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3024373561 Apr 15 12:37:00 PM PDT 24 Apr 15 12:37:06 PM PDT 24 97722590 ps

Test location /workspace/coverage/default/40.alert_handler_entropy.948976008
Short name T2
Test name
Test status
Simulation time 11801226860 ps
CPU time 1018.57 seconds
Started Apr 15 01:12:10 PM PDT 24
Finished Apr 15 01:29:10 PM PDT 24
Peak memory 285032 kb
Host smart-110a1081-45a0-491b-bc68-ad20ccbb2745
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948976008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.948976008
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2266548132
Short name T12
Test name
Test status
Simulation time 105453807386 ps
CPU time 8425.48 seconds
Started Apr 15 01:11:57 PM PDT 24
Finished Apr 15 03:32:24 PM PDT 24
Peak memory 363336 kb
Host smart-e9fc0847-6105-4139-ab37-3d1f492de1b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266548132 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2266548132
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2262007533
Short name T9
Test name
Test status
Simulation time 226164812 ps
CPU time 13.63 seconds
Started Apr 15 01:11:04 PM PDT 24
Finished Apr 15 01:11:18 PM PDT 24
Peak memory 277872 kb
Host smart-d163167f-f08c-4dcc-9451-29c2ea8d288f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2262007533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2262007533
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3140885645
Short name T27
Test name
Test status
Simulation time 22407472756 ps
CPU time 1232.1 seconds
Started Apr 15 01:11:47 PM PDT 24
Finished Apr 15 01:32:20 PM PDT 24
Peak memory 273724 kb
Host smart-02bdab24-dc6d-4c44-8f97-a531e7d74222
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140885645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3140885645
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2039422583
Short name T240
Test name
Test status
Simulation time 257509653 ps
CPU time 10.46 seconds
Started Apr 15 12:36:56 PM PDT 24
Finished Apr 15 12:37:07 PM PDT 24
Peak memory 238492 kb
Host smart-a7cc8cb8-558f-410f-b472-9d3ece9df76b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039422583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2039422583
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1056698176
Short name T21
Test name
Test status
Simulation time 70014651453 ps
CPU time 2294.89 seconds
Started Apr 15 01:11:56 PM PDT 24
Finished Apr 15 01:50:12 PM PDT 24
Peak memory 282052 kb
Host smart-b5dbd999-1929-41dc-8f1e-340887293673
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056698176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1056698176
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1755375467
Short name T50
Test name
Test status
Simulation time 177499929674 ps
CPU time 2357.95 seconds
Started Apr 15 01:11:33 PM PDT 24
Finished Apr 15 01:50:51 PM PDT 24
Peak memory 290120 kb
Host smart-df172ada-9786-4085-8e10-3567ba7b87fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755375467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1755375467
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2243165904
Short name T118
Test name
Test status
Simulation time 17609625951 ps
CPU time 632.62 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:47:34 PM PDT 24
Peak memory 265988 kb
Host smart-93fc7cf9-2ca1-4608-aecd-c65f3f876a5b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243165904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2243165904
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.515853004
Short name T77
Test name
Test status
Simulation time 82043417811 ps
CPU time 2264.01 seconds
Started Apr 15 01:11:35 PM PDT 24
Finished Apr 15 01:49:21 PM PDT 24
Peak memory 273768 kb
Host smart-7303cb2f-f1b1-4f1f-bd09-db3ea5da0873
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515853004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.515853004
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1528122912
Short name T231
Test name
Test status
Simulation time 136786850916 ps
CPU time 1646.24 seconds
Started Apr 15 01:12:02 PM PDT 24
Finished Apr 15 01:39:29 PM PDT 24
Peak memory 268852 kb
Host smart-96c90c71-934f-48f5-b41a-229e13788090
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528122912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1528122912
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3947377216
Short name T117
Test name
Test status
Simulation time 10230099980 ps
CPU time 337.8 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:42:38 PM PDT 24
Peak memory 264856 kb
Host smart-0c72cf00-c6d5-49b7-b60f-8c911b49a7db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3947377216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3947377216
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1674157783
Short name T97
Test name
Test status
Simulation time 138157435365 ps
CPU time 9784.96 seconds
Started Apr 15 01:11:23 PM PDT 24
Finished Apr 15 03:54:30 PM PDT 24
Peak memory 371460 kb
Host smart-da132fbd-fe46-4b4e-a858-5a220a24d7c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674157783 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1674157783
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3644466598
Short name T128
Test name
Test status
Simulation time 4804839610 ps
CPU time 309.22 seconds
Started Apr 15 12:37:16 PM PDT 24
Finished Apr 15 12:42:26 PM PDT 24
Peak memory 270584 kb
Host smart-79117e61-b42a-4cd1-a5f2-7e460aa51b7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3644466598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3644466598
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3022278305
Short name T153
Test name
Test status
Simulation time 3710260960 ps
CPU time 62.4 seconds
Started Apr 15 12:37:01 PM PDT 24
Finished Apr 15 12:38:04 PM PDT 24
Peak memory 239212 kb
Host smart-536ea96d-11e1-4050-954f-ee57732c3dd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3022278305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3022278305
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1346055264
Short name T86
Test name
Test status
Simulation time 60804330106 ps
CPU time 1854.45 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:42:09 PM PDT 24
Peak memory 285688 kb
Host smart-2faf79f9-d808-4a86-b452-09de109b9ba0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346055264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1346055264
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3930515674
Short name T69
Test name
Test status
Simulation time 71605722407 ps
CPU time 2239.87 seconds
Started Apr 15 01:11:09 PM PDT 24
Finished Apr 15 01:48:30 PM PDT 24
Peak memory 290248 kb
Host smart-431bb552-eb25-4f2b-8435-037375661b35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930515674 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3930515674
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.619858081
Short name T114
Test name
Test status
Simulation time 4497015767 ps
CPU time 44.12 seconds
Started Apr 15 01:11:19 PM PDT 24
Finished Apr 15 01:12:04 PM PDT 24
Peak memory 249200 kb
Host smart-d49d7009-b9b2-4184-9217-640f724d1074
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=619858081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.619858081
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3839067279
Short name T122
Test name
Test status
Simulation time 25754598799 ps
CPU time 1027.34 seconds
Started Apr 15 12:36:47 PM PDT 24
Finished Apr 15 12:53:57 PM PDT 24
Peak memory 265012 kb
Host smart-3f956ef0-cadd-4c39-8a48-aa9ba6d70c94
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839067279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3839067279
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.306969649
Short name T28
Test name
Test status
Simulation time 69335880696 ps
CPU time 2367.99 seconds
Started Apr 15 01:10:54 PM PDT 24
Finished Apr 15 01:50:23 PM PDT 24
Peak memory 289808 kb
Host smart-b5c79911-d7f7-49a0-8402-25e2a93c87d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306969649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.306969649
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2517572762
Short name T300
Test name
Test status
Simulation time 387416772671 ps
CPU time 2363.06 seconds
Started Apr 15 01:12:04 PM PDT 24
Finished Apr 15 01:51:28 PM PDT 24
Peak memory 282280 kb
Host smart-155c5e2f-bf8e-412e-ad3e-36046ff89116
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517572762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2517572762
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3012775220
Short name T138
Test name
Test status
Simulation time 5973967052 ps
CPU time 397.86 seconds
Started Apr 15 12:37:03 PM PDT 24
Finished Apr 15 12:43:42 PM PDT 24
Peak memory 264520 kb
Host smart-5325f05a-8932-4467-b4a1-28cc4747fee8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3012775220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3012775220
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.567182401
Short name T356
Test name
Test status
Simulation time 100193554 ps
CPU time 7.78 seconds
Started Apr 15 12:36:58 PM PDT 24
Finished Apr 15 12:37:06 PM PDT 24
Peak memory 237384 kb
Host smart-fd460b53-cd84-48bd-8c07-03fefd1ba7f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567182401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.567182401
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3416841215
Short name T7
Test name
Test status
Simulation time 28918437820 ps
CPU time 551.19 seconds
Started Apr 15 01:12:14 PM PDT 24
Finished Apr 15 01:21:26 PM PDT 24
Peak memory 248216 kb
Host smart-b006d7f0-5c4d-4f53-aeda-578f68a29d20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416841215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3416841215
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2258665236
Short name T351
Test name
Test status
Simulation time 11844461 ps
CPU time 1.32 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:36:59 PM PDT 24
Peak memory 235452 kb
Host smart-025f69ef-91d9-49c1-8c81-0766b0fd0cda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2258665236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2258665236
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3549600509
Short name T235
Test name
Test status
Simulation time 171657260333 ps
CPU time 2380.61 seconds
Started Apr 15 01:11:57 PM PDT 24
Finished Apr 15 01:51:39 PM PDT 24
Peak memory 289876 kb
Host smart-52c3294c-a8d0-4a07-be53-1e9b0b40c84b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549600509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3549600509
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3796461410
Short name T326
Test name
Test status
Simulation time 313690489795 ps
CPU time 2495.53 seconds
Started Apr 15 01:11:08 PM PDT 24
Finished Apr 15 01:52:45 PM PDT 24
Peak memory 289504 kb
Host smart-afb62b43-bb4f-4fc6-b7bc-4fc75a0ea10c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796461410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3796461410
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3031375962
Short name T133
Test name
Test status
Simulation time 3856128992 ps
CPU time 217.05 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:40:38 PM PDT 24
Peak memory 264856 kb
Host smart-cd741a61-383f-4426-9d37-963effa1f268
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3031375962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3031375962
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1529664277
Short name T316
Test name
Test status
Simulation time 16338867793 ps
CPU time 668.6 seconds
Started Apr 15 01:12:10 PM PDT 24
Finished Apr 15 01:23:20 PM PDT 24
Peak memory 248076 kb
Host smart-ed95c3d7-576b-441e-9997-c1db4e54f9d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529664277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1529664277
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3077749959
Short name T183
Test name
Test status
Simulation time 44641269740 ps
CPU time 2347.84 seconds
Started Apr 15 01:12:26 PM PDT 24
Finished Apr 15 01:51:35 PM PDT 24
Peak memory 282872 kb
Host smart-f3a6f362-7b1e-4641-a2ef-e9bbb401b2a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077749959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3077749959
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1112847965
Short name T145
Test name
Test status
Simulation time 17362296829 ps
CPU time 1148.94 seconds
Started Apr 15 12:36:51 PM PDT 24
Finished Apr 15 12:56:01 PM PDT 24
Peak memory 264964 kb
Host smart-f3453203-feb3-4a47-9858-e244127ad8fb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112847965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1112847965
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3295526493
Short name T151
Test name
Test status
Simulation time 78253693909 ps
CPU time 1068.57 seconds
Started Apr 15 12:36:56 PM PDT 24
Finished Apr 15 12:54:45 PM PDT 24
Peak memory 264920 kb
Host smart-b2ee4a68-5942-4458-aa21-e75c8db4cd29
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295526493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3295526493
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2227973565
Short name T6
Test name
Test status
Simulation time 8049066681 ps
CPU time 321.71 seconds
Started Apr 15 01:11:59 PM PDT 24
Finished Apr 15 01:17:21 PM PDT 24
Peak memory 248092 kb
Host smart-5836bd57-bff1-4f18-a43a-9e708ead8420
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227973565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2227973565
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2913146071
Short name T334
Test name
Test status
Simulation time 155768952381 ps
CPU time 2452.23 seconds
Started Apr 15 01:11:09 PM PDT 24
Finished Apr 15 01:52:03 PM PDT 24
Peak memory 289112 kb
Host smart-d42a1fcd-5bd8-4e32-8971-d0920ba49b8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913146071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2913146071
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.4010256208
Short name T23
Test name
Test status
Simulation time 4191668699 ps
CPU time 236.14 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:15:10 PM PDT 24
Peak memory 257368 kb
Host smart-0aefc3aa-885e-460f-930b-fa0e71ba2310
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010256208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.4010256208
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.675061407
Short name T342
Test name
Test status
Simulation time 95567261568 ps
CPU time 2382 seconds
Started Apr 15 01:12:27 PM PDT 24
Finished Apr 15 01:52:11 PM PDT 24
Peak memory 282756 kb
Host smart-ca639eb5-b6a5-4231-bc09-fab2d78bde69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675061407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.675061407
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3693389791
Short name T134
Test name
Test status
Simulation time 6716118594 ps
CPU time 199.4 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:40:17 PM PDT 24
Peak memory 264812 kb
Host smart-3c06164b-d8ba-46d2-a93e-a636bba98965
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3693389791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3693389791
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3031818180
Short name T352
Test name
Test status
Simulation time 6185439 ps
CPU time 1.52 seconds
Started Apr 15 12:36:48 PM PDT 24
Finished Apr 15 12:36:52 PM PDT 24
Peak memory 236244 kb
Host smart-4c3bc6a1-c5e4-4ba5-ad53-b2ed65923637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3031818180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3031818180
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1704843704
Short name T103
Test name
Test status
Simulation time 23079649439 ps
CPU time 506.69 seconds
Started Apr 15 01:11:14 PM PDT 24
Finished Apr 15 01:19:42 PM PDT 24
Peak memory 248396 kb
Host smart-56078a94-be21-48b2-9239-678d664edecd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704843704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1704843704
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3763909974
Short name T271
Test name
Test status
Simulation time 141703383072 ps
CPU time 428.66 seconds
Started Apr 15 01:11:43 PM PDT 24
Finished Apr 15 01:18:53 PM PDT 24
Peak memory 247312 kb
Host smart-028310aa-3869-4011-a165-2992302cb15b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763909974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3763909974
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4153882450
Short name T359
Test name
Test status
Simulation time 21618469672 ps
CPU time 462.73 seconds
Started Apr 15 12:36:58 PM PDT 24
Finished Apr 15 12:44:41 PM PDT 24
Peak memory 264824 kb
Host smart-091dda4d-82b2-415f-b008-744fad5eb605
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153882450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4153882450
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1174719330
Short name T220
Test name
Test status
Simulation time 26787957039 ps
CPU time 426.95 seconds
Started Apr 15 01:12:02 PM PDT 24
Finished Apr 15 01:19:09 PM PDT 24
Peak memory 248372 kb
Host smart-80d1060a-6b7d-444f-a0ff-99d38de38c57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174719330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1174719330
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3485249553
Short name T101
Test name
Test status
Simulation time 321282847126 ps
CPU time 2946.2 seconds
Started Apr 15 01:11:04 PM PDT 24
Finished Apr 15 02:00:11 PM PDT 24
Peak memory 305776 kb
Host smart-48b8cac0-3d2d-4289-804a-5d80a1846a2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485249553 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3485249553
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2113809343
Short name T150
Test name
Test status
Simulation time 9914333432 ps
CPU time 366.63 seconds
Started Apr 15 12:37:07 PM PDT 24
Finished Apr 15 12:43:15 PM PDT 24
Peak memory 264920 kb
Host smart-6c5484c0-7c2f-475c-96d9-3b922b373766
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2113809343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2113809343
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.546542408
Short name T252
Test name
Test status
Simulation time 100097327138 ps
CPU time 4062.66 seconds
Started Apr 15 01:11:05 PM PDT 24
Finished Apr 15 02:18:49 PM PDT 24
Peak memory 302440 kb
Host smart-76df85b1-188d-4dc0-9743-8bfc55cbd791
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546542408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.546542408
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3044786685
Short name T72
Test name
Test status
Simulation time 17527903261 ps
CPU time 886.83 seconds
Started Apr 15 01:12:17 PM PDT 24
Finished Apr 15 01:27:05 PM PDT 24
Peak memory 273680 kb
Host smart-94d13f48-6d64-4f69-8bde-be991eee6d89
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044786685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3044786685
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1950431345
Short name T707
Test name
Test status
Simulation time 43396279131 ps
CPU time 478.54 seconds
Started Apr 15 01:11:07 PM PDT 24
Finished Apr 15 01:19:07 PM PDT 24
Peak memory 248108 kb
Host smart-2f7e8294-8bcc-4ca0-a6a4-34ae8b851473
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950431345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1950431345
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.914473961
Short name T219
Test name
Test status
Simulation time 24349946832 ps
CPU time 1504.38 seconds
Started Apr 15 01:10:52 PM PDT 24
Finished Apr 15 01:35:58 PM PDT 24
Peak memory 273280 kb
Host smart-986071b4-52f6-4429-9fc9-19ade5dac275
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914473961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.914473961
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1097084224
Short name T653
Test name
Test status
Simulation time 47731069315 ps
CPU time 1185.11 seconds
Started Apr 15 01:11:14 PM PDT 24
Finished Apr 15 01:31:00 PM PDT 24
Peak memory 289648 kb
Host smart-f873d894-6589-45a0-b414-eba92a5ae541
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097084224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1097084224
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1350819557
Short name T290
Test name
Test status
Simulation time 341162667113 ps
CPU time 2469.14 seconds
Started Apr 15 01:11:46 PM PDT 24
Finished Apr 15 01:52:57 PM PDT 24
Peak memory 289276 kb
Host smart-e54ca007-397a-4b59-8044-8968ed589857
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350819557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1350819557
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2908410681
Short name T91
Test name
Test status
Simulation time 144726071444 ps
CPU time 7185.95 seconds
Started Apr 15 01:11:19 PM PDT 24
Finished Apr 15 03:11:07 PM PDT 24
Peak memory 371288 kb
Host smart-bfcc9e97-1019-4d87-acfb-ec2473428b5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908410681 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2908410681
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3345344267
Short name T251
Test name
Test status
Simulation time 29067865704 ps
CPU time 1135.15 seconds
Started Apr 15 01:12:26 PM PDT 24
Finished Apr 15 01:31:22 PM PDT 24
Peak memory 281908 kb
Host smart-b407916f-0e52-4b24-8943-5434a6f1f453
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345344267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3345344267
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2490416914
Short name T160
Test name
Test status
Simulation time 108530803 ps
CPU time 3.11 seconds
Started Apr 15 12:36:53 PM PDT 24
Finished Apr 15 12:36:57 PM PDT 24
Peak memory 236376 kb
Host smart-f8c4216d-d520-489f-bfa3-cf474e12c29b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2490416914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2490416914
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.419707810
Short name T129
Test name
Test status
Simulation time 6177009505 ps
CPU time 491.79 seconds
Started Apr 15 12:37:01 PM PDT 24
Finished Apr 15 12:45:14 PM PDT 24
Peak memory 267048 kb
Host smart-b26f6164-ae83-49ad-86bd-2ea5a3fddafe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419707810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.419707810
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.953082545
Short name T206
Test name
Test status
Simulation time 45296622 ps
CPU time 4.08 seconds
Started Apr 15 01:10:58 PM PDT 24
Finished Apr 15 01:11:03 PM PDT 24
Peak memory 249324 kb
Host smart-b51f98d0-48c6-4913-9da1-227427455624
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=953082545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.953082545
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1257576098
Short name T209
Test name
Test status
Simulation time 36442563 ps
CPU time 2.28 seconds
Started Apr 15 01:10:59 PM PDT 24
Finished Apr 15 01:11:02 PM PDT 24
Peak memory 249340 kb
Host smart-f1dee0df-95f4-4b30-a16f-815c3c090ec5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1257576098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1257576098
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2682347162
Short name T195
Test name
Test status
Simulation time 113095468 ps
CPU time 2.87 seconds
Started Apr 15 01:11:18 PM PDT 24
Finished Apr 15 01:11:22 PM PDT 24
Peak memory 249304 kb
Host smart-549fe530-394e-49ff-b11c-c6ca67a5fda8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2682347162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2682347162
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.354225109
Short name T208
Test name
Test status
Simulation time 62821229 ps
CPU time 3.34 seconds
Started Apr 15 01:11:28 PM PDT 24
Finished Apr 15 01:11:32 PM PDT 24
Peak memory 249316 kb
Host smart-4b0f0788-fdb1-4fcb-ba1f-32ae8eb7df36
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=354225109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.354225109
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3527352310
Short name T1
Test name
Test status
Simulation time 125140415375 ps
CPU time 1578.15 seconds
Started Apr 15 01:11:41 PM PDT 24
Finished Apr 15 01:38:00 PM PDT 24
Peak memory 270920 kb
Host smart-f32c9eb1-b115-4766-9b07-06f6873b4cfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527352310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3527352310
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1527888827
Short name T266
Test name
Test status
Simulation time 90558385688 ps
CPU time 757.1 seconds
Started Apr 15 01:10:57 PM PDT 24
Finished Apr 15 01:23:35 PM PDT 24
Peak memory 273732 kb
Host smart-cf8948fc-4425-4227-b448-20748617fe79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527888827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1527888827
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.4256460532
Short name T319
Test name
Test status
Simulation time 30802587972 ps
CPU time 376.79 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:17:18 PM PDT 24
Peak memory 248252 kb
Host smart-3fd94c55-c170-4f20-a4a7-c43be9b17220
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256460532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4256460532
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1258547246
Short name T109
Test name
Test status
Simulation time 959263749 ps
CPU time 53.22 seconds
Started Apr 15 01:11:44 PM PDT 24
Finished Apr 15 01:12:39 PM PDT 24
Peak memory 247676 kb
Host smart-7177efaa-a53d-4639-9cd4-7d03b5c23b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12585
47246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1258547246
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1749663434
Short name T288
Test name
Test status
Simulation time 235741365409 ps
CPU time 1447.7 seconds
Started Apr 15 01:11:04 PM PDT 24
Finished Apr 15 01:35:13 PM PDT 24
Peak memory 272860 kb
Host smart-196ac261-71e2-4b04-9a1e-cdafd1a72b72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749663434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1749663434
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.4080294393
Short name T61
Test name
Test status
Simulation time 1038098133 ps
CPU time 64.19 seconds
Started Apr 15 01:12:21 PM PDT 24
Finished Apr 15 01:13:26 PM PDT 24
Peak memory 247664 kb
Host smart-fc0ef4e5-e5e4-4a8e-bdfe-618d16e84f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40802
94393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.4080294393
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1201963723
Short name T270
Test name
Test status
Simulation time 1350136631 ps
CPU time 44.26 seconds
Started Apr 15 01:12:29 PM PDT 24
Finished Apr 15 01:13:14 PM PDT 24
Peak memory 249412 kb
Host smart-d73adace-1d9c-47c5-b3bb-fc0025338ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12019
63723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1201963723
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3212904326
Short name T164
Test name
Test status
Simulation time 92211558 ps
CPU time 5.87 seconds
Started Apr 15 12:36:52 PM PDT 24
Finished Apr 15 12:36:58 PM PDT 24
Peak memory 236296 kb
Host smart-0a172592-0226-42b4-9865-f9bdec84baa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3212904326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3212904326
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1089716711
Short name T148
Test name
Test status
Simulation time 14656844690 ps
CPU time 489.53 seconds
Started Apr 15 12:36:46 PM PDT 24
Finished Apr 15 12:44:58 PM PDT 24
Peak memory 267644 kb
Host smart-cc6bc159-2801-432b-9fc3-205d47b5686a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089716711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1089716711
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.208938693
Short name T124
Test name
Test status
Simulation time 2402381029 ps
CPU time 291.53 seconds
Started Apr 15 12:36:55 PM PDT 24
Finished Apr 15 12:41:47 PM PDT 24
Peak memory 264804 kb
Host smart-d816daff-17e1-4074-872c-5fc48bcce638
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208938693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.208938693
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.766340395
Short name T355
Test name
Test status
Simulation time 33254469 ps
CPU time 1.57 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:02 PM PDT 24
Peak memory 236336 kb
Host smart-fb501853-ddfc-4168-a844-03983dca79b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=766340395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.766340395
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1273217143
Short name T282
Test name
Test status
Simulation time 13460901632 ps
CPU time 771.54 seconds
Started Apr 15 01:10:57 PM PDT 24
Finished Apr 15 01:23:49 PM PDT 24
Peak memory 267620 kb
Host smart-54dcf0a5-45d1-4a14-b4d7-efac342eb938
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273217143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1273217143
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2222422474
Short name T100
Test name
Test status
Simulation time 21338141051 ps
CPU time 2174.32 seconds
Started Apr 15 01:10:55 PM PDT 24
Finished Apr 15 01:47:11 PM PDT 24
Peak memory 305944 kb
Host smart-5171facc-b1ea-4258-8ad2-9db90ad8bed1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222422474 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2222422474
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.282228601
Short name T587
Test name
Test status
Simulation time 7536613146 ps
CPU time 292.26 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:16:07 PM PDT 24
Peak memory 247320 kb
Host smart-f143490c-28d0-4cc7-8f49-f4b94e969702
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282228601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.282228601
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.4293279379
Short name T694
Test name
Test status
Simulation time 101294556188 ps
CPU time 1646.37 seconds
Started Apr 15 01:11:32 PM PDT 24
Finished Apr 15 01:38:59 PM PDT 24
Peak memory 273112 kb
Host smart-0d56debb-a6a0-4bbe-8953-69cd03130259
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293279379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.4293279379
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.554009833
Short name T222
Test name
Test status
Simulation time 70914796713 ps
CPU time 1051.82 seconds
Started Apr 15 01:11:12 PM PDT 24
Finished Apr 15 01:28:45 PM PDT 24
Peak memory 265552 kb
Host smart-bbbacab3-57d5-4d34-be7e-5750ce098cc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554009833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.554009833
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1356753701
Short name T106
Test name
Test status
Simulation time 129575882875 ps
CPU time 2311.93 seconds
Started Apr 15 01:10:57 PM PDT 24
Finished Apr 15 01:49:30 PM PDT 24
Peak memory 298680 kb
Host smart-e6029e7b-f6f9-4655-a6e1-9769cb5c9d2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356753701 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1356753701
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.895007321
Short name T257
Test name
Test status
Simulation time 5740941923 ps
CPU time 369.82 seconds
Started Apr 15 01:11:25 PM PDT 24
Finished Apr 15 01:17:38 PM PDT 24
Peak memory 257188 kb
Host smart-e8c5eafe-fe43-4273-b975-97678b70fa77
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895007321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.895007321
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.4025716135
Short name T262
Test name
Test status
Simulation time 1831405859 ps
CPU time 19.59 seconds
Started Apr 15 01:11:39 PM PDT 24
Finished Apr 15 01:12:00 PM PDT 24
Peak memory 255548 kb
Host smart-4cc4df4f-4d77-4986-8391-9a1192ba37d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40257
16135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.4025716135
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.164713651
Short name T296
Test name
Test status
Simulation time 610879683 ps
CPU time 38.37 seconds
Started Apr 15 01:11:37 PM PDT 24
Finished Apr 15 01:12:16 PM PDT 24
Peak memory 249060 kb
Host smart-86e61a0e-3ca0-47ba-a3f5-b0778510a0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16471
3651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.164713651
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.209928302
Short name T249
Test name
Test status
Simulation time 2008597568 ps
CPU time 35.92 seconds
Started Apr 15 01:11:47 PM PDT 24
Finished Apr 15 01:12:24 PM PDT 24
Peak memory 249012 kb
Host smart-01adb190-8509-41d2-9f36-a3614289e636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20992
8302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.209928302
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2872129419
Short name T253
Test name
Test status
Simulation time 42987255089 ps
CPU time 2513.53 seconds
Started Apr 15 01:12:01 PM PDT 24
Finished Apr 15 01:53:56 PM PDT 24
Peak memory 299024 kb
Host smart-7c09c7a4-f21f-4563-944f-d1342b056857
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872129419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2872129419
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2970256063
Short name T243
Test name
Test status
Simulation time 128423396648 ps
CPU time 6353.45 seconds
Started Apr 15 01:12:06 PM PDT 24
Finished Apr 15 02:58:01 PM PDT 24
Peak memory 387836 kb
Host smart-43e26557-4db1-4c82-a760-e2ad30d9d487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970256063 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2970256063
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.134372195
Short name T347
Test name
Test status
Simulation time 34743469270 ps
CPU time 1811.89 seconds
Started Apr 15 01:10:58 PM PDT 24
Finished Apr 15 01:41:10 PM PDT 24
Peak memory 273524 kb
Host smart-038f07dd-6eb1-43ed-abfd-55045129fa17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134372195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.134372195
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2600744228
Short name T31
Test name
Test status
Simulation time 657469553 ps
CPU time 11.57 seconds
Started Apr 15 01:10:49 PM PDT 24
Finished Apr 15 01:11:01 PM PDT 24
Peak memory 277008 kb
Host smart-ca13f1a6-0eb9-4102-ba27-b105883f3bd7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2600744228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2600744228
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4111010797
Short name T121
Test name
Test status
Simulation time 4205934321 ps
CPU time 164.68 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:39:46 PM PDT 24
Peak memory 264984 kb
Host smart-443c2a89-2fec-4d78-88d0-f2a68ae87a49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4111010797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.4111010797
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.522763113
Short name T177
Test name
Test status
Simulation time 186259773 ps
CPU time 23.37 seconds
Started Apr 15 12:36:56 PM PDT 24
Finished Apr 15 12:37:21 PM PDT 24
Peak memory 239208 kb
Host smart-dd8d3ec9-8983-40bc-b0f4-9227c5a60c01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=522763113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.522763113
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2813565103
Short name T161
Test name
Test status
Simulation time 11111113456 ps
CPU time 63.11 seconds
Started Apr 15 12:36:51 PM PDT 24
Finished Apr 15 12:37:55 PM PDT 24
Peak memory 239936 kb
Host smart-d3271dc8-a234-4464-8248-2405f8af366a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2813565103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2813565103
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3024373561
Short name T165
Test name
Test status
Simulation time 97722590 ps
CPU time 5.82 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:06 PM PDT 24
Peak memory 235440 kb
Host smart-7547d2ad-c80d-4bb3-b44d-cf9102a98d70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3024373561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3024373561
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.251767894
Short name T147
Test name
Test status
Simulation time 3039813401 ps
CPU time 195.28 seconds
Started Apr 15 12:37:02 PM PDT 24
Finished Apr 15 12:40:18 PM PDT 24
Peak memory 256712 kb
Host smart-dafff960-1270-44d2-b4cc-49c668cfd686
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=251767894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.251767894
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.322058402
Short name T167
Test name
Test status
Simulation time 58082113 ps
CPU time 2.57 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:04 PM PDT 24
Peak memory 236660 kb
Host smart-645aee72-d7c0-4b4a-857c-3e44864dd7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=322058402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.322058402
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1142886047
Short name T170
Test name
Test status
Simulation time 94282746 ps
CPU time 2.61 seconds
Started Apr 15 12:37:07 PM PDT 24
Finished Apr 15 12:37:11 PM PDT 24
Peak memory 235252 kb
Host smart-902eed02-5116-40b7-a43e-5557396b5194
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1142886047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1142886047
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1584234965
Short name T162
Test name
Test status
Simulation time 28723670 ps
CPU time 2.72 seconds
Started Apr 15 12:36:48 PM PDT 24
Finished Apr 15 12:36:53 PM PDT 24
Peak memory 236716 kb
Host smart-c9de41de-5707-49b3-bd59-07bc2aef201a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1584234965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1584234965
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2853984394
Short name T158
Test name
Test status
Simulation time 305786661 ps
CPU time 21.44 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:37:19 PM PDT 24
Peak memory 239164 kb
Host smart-9421713c-dbc8-42f0-8383-48180880e760
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2853984394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2853984394
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3379100718
Short name T163
Test name
Test status
Simulation time 195639090 ps
CPU time 24.55 seconds
Started Apr 15 12:36:49 PM PDT 24
Finished Apr 15 12:37:15 PM PDT 24
Peak memory 236436 kb
Host smart-3f63bf52-2704-42d9-bde8-772e2f076969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3379100718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3379100718
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2657565027
Short name T166
Test name
Test status
Simulation time 173020565 ps
CPU time 3.48 seconds
Started Apr 15 12:36:45 PM PDT 24
Finished Apr 15 12:36:50 PM PDT 24
Peak memory 236836 kb
Host smart-d7759690-b915-4a3c-b790-2a484742a7f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2657565027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2657565027
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3988000146
Short name T176
Test name
Test status
Simulation time 872455731 ps
CPU time 35.23 seconds
Started Apr 15 12:36:55 PM PDT 24
Finished Apr 15 12:37:31 PM PDT 24
Peak memory 236448 kb
Host smart-dad8c024-5afc-439d-8320-2e464302cda0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3988000146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3988000146
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3873984709
Short name T168
Test name
Test status
Simulation time 357222490 ps
CPU time 2.85 seconds
Started Apr 15 12:36:54 PM PDT 24
Finished Apr 15 12:36:57 PM PDT 24
Peak memory 235432 kb
Host smart-cdabc92a-06a2-4597-9f7d-fd51b105201f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3873984709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3873984709
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1812679107
Short name T169
Test name
Test status
Simulation time 1032139968 ps
CPU time 63.78 seconds
Started Apr 15 12:36:53 PM PDT 24
Finished Apr 15 12:37:57 PM PDT 24
Peak memory 239132 kb
Host smart-ef643ad2-ce91-44cc-8092-9c18093fb8cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1812679107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1812679107
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3729917923
Short name T159
Test name
Test status
Simulation time 183899461 ps
CPU time 2.87 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:04 PM PDT 24
Peak memory 236280 kb
Host smart-ad008c9a-5c89-4f37-bea5-abbc837d83d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3729917923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3729917923
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3417410449
Short name T171
Test name
Test status
Simulation time 164684801 ps
CPU time 21.29 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:37:22 PM PDT 24
Peak memory 236564 kb
Host smart-af153f30-d4ab-4840-b927-e0da3774163a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3417410449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3417410449
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3662608422
Short name T154
Test name
Test status
Simulation time 162901612 ps
CPU time 2.27 seconds
Started Apr 15 12:37:32 PM PDT 24
Finished Apr 15 12:37:36 PM PDT 24
Peak memory 236524 kb
Host smart-ff17bb06-e0cb-4570-8934-4ec1dcf531c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3662608422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3662608422
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1424825625
Short name T22
Test name
Test status
Simulation time 169760374771 ps
CPU time 4019.26 seconds
Started Apr 15 01:11:14 PM PDT 24
Finished Apr 15 02:18:16 PM PDT 24
Peak memory 339156 kb
Host smart-425bd24c-732c-4b67-9510-b81ca509223d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424825625 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1424825625
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2241009462
Short name T798
Test name
Test status
Simulation time 2234255401 ps
CPU time 63.25 seconds
Started Apr 15 12:36:46 PM PDT 24
Finished Apr 15 12:37:51 PM PDT 24
Peak memory 239992 kb
Host smart-8677615e-aa3d-442b-bb08-cfeb78961eea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2241009462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2241009462
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2118314238
Short name T766
Test name
Test status
Simulation time 61115883262 ps
CPU time 248.49 seconds
Started Apr 15 12:36:53 PM PDT 24
Finished Apr 15 12:41:02 PM PDT 24
Peak memory 236264 kb
Host smart-1ca1a832-9fa9-4f04-9fd0-4a2163fbe662
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2118314238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2118314238
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.889932390
Short name T787
Test name
Test status
Simulation time 52168568 ps
CPU time 6.31 seconds
Started Apr 15 12:36:47 PM PDT 24
Finished Apr 15 12:36:55 PM PDT 24
Peak memory 239816 kb
Host smart-7b913738-696e-4ebf-a621-2b8f9ff53373
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=889932390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.889932390
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3895094502
Short name T773
Test name
Test status
Simulation time 164039366 ps
CPU time 4.37 seconds
Started Apr 15 12:36:45 PM PDT 24
Finished Apr 15 12:36:51 PM PDT 24
Peak memory 238996 kb
Host smart-6c2f4748-2171-48c3-9bf6-a0d8783c4a8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895094502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3895094502
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4202815140
Short name T812
Test name
Test status
Simulation time 90688818 ps
CPU time 7.68 seconds
Started Apr 15 12:36:46 PM PDT 24
Finished Apr 15 12:36:56 PM PDT 24
Peak memory 239884 kb
Host smart-709e8478-de08-48af-93d3-5ea2b0f13185
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4202815140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.4202815140
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4008899695
Short name T772
Test name
Test status
Simulation time 17438879 ps
CPU time 1.33 seconds
Started Apr 15 12:36:46 PM PDT 24
Finished Apr 15 12:36:49 PM PDT 24
Peak memory 236280 kb
Host smart-8e84f5f5-6e96-45fe-b82f-6026d5b8ea16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4008899695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.4008899695
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2167966392
Short name T814
Test name
Test status
Simulation time 1041437208 ps
CPU time 33.79 seconds
Started Apr 15 12:36:49 PM PDT 24
Finished Apr 15 12:37:24 PM PDT 24
Peak memory 248060 kb
Host smart-ace3f165-4b1c-4497-9332-726db934fad3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2167966392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2167966392
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1327575452
Short name T115
Test name
Test status
Simulation time 8899382495 ps
CPU time 167.95 seconds
Started Apr 15 12:36:46 PM PDT 24
Finished Apr 15 12:39:36 PM PDT 24
Peak memory 264920 kb
Host smart-93f615de-3879-49a7-8df9-0f7021099747
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1327575452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1327575452
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1251398944
Short name T774
Test name
Test status
Simulation time 40279171 ps
CPU time 5.55 seconds
Started Apr 15 12:36:44 PM PDT 24
Finished Apr 15 12:36:51 PM PDT 24
Peak memory 248100 kb
Host smart-0272e7a7-80bf-4b0b-9688-1e7735109883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1251398944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1251398944
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2738518765
Short name T193
Test name
Test status
Simulation time 4283567825 ps
CPU time 151.23 seconds
Started Apr 15 12:36:43 PM PDT 24
Finished Apr 15 12:39:16 PM PDT 24
Peak memory 240184 kb
Host smart-ddd6eba8-6722-495e-86ed-a6954023a10d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2738518765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2738518765
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1943195932
Short name T714
Test name
Test status
Simulation time 6805077624 ps
CPU time 203.7 seconds
Started Apr 15 12:36:47 PM PDT 24
Finished Apr 15 12:40:13 PM PDT 24
Peak memory 239984 kb
Host smart-a879fdcf-e55a-4cd0-b70c-acf9d597f355
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1943195932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1943195932
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2825403655
Short name T801
Test name
Test status
Simulation time 76079155 ps
CPU time 5.86 seconds
Started Apr 15 12:36:45 PM PDT 24
Finished Apr 15 12:36:53 PM PDT 24
Peak memory 239976 kb
Host smart-0566988c-cb21-4a57-a727-31ee64856733
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2825403655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2825403655
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2070294951
Short name T797
Test name
Test status
Simulation time 97448958 ps
CPU time 3.97 seconds
Started Apr 15 12:36:47 PM PDT 24
Finished Apr 15 12:36:53 PM PDT 24
Peak memory 252160 kb
Host smart-3eed2a3a-45e4-478c-86b0-11cd7494c0ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070294951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2070294951
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4104058123
Short name T767
Test name
Test status
Simulation time 654442758 ps
CPU time 4.32 seconds
Started Apr 15 12:36:45 PM PDT 24
Finished Apr 15 12:36:52 PM PDT 24
Peak memory 236136 kb
Host smart-43de9586-c105-43a6-9815-c53ef1afa5d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4104058123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.4104058123
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3773603219
Short name T747
Test name
Test status
Simulation time 11886802 ps
CPU time 1.43 seconds
Started Apr 15 12:36:52 PM PDT 24
Finished Apr 15 12:36:54 PM PDT 24
Peak memory 236256 kb
Host smart-8d027a0a-d443-4cf9-9c68-00db5455f962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3773603219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3773603219
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1181119303
Short name T770
Test name
Test status
Simulation time 176692653 ps
CPU time 20.52 seconds
Started Apr 15 12:36:48 PM PDT 24
Finished Apr 15 12:37:10 PM PDT 24
Peak memory 243596 kb
Host smart-b6e780d5-d560-47ed-9a47-0f4cce786fdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1181119303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1181119303
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2537379568
Short name T126
Test name
Test status
Simulation time 75892451738 ps
CPU time 311.22 seconds
Started Apr 15 12:36:49 PM PDT 24
Finished Apr 15 12:42:01 PM PDT 24
Peak memory 272196 kb
Host smart-681b72a3-210d-44e2-82c8-1f8ba4c7a13d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2537379568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2537379568
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3643109441
Short name T783
Test name
Test status
Simulation time 159389693 ps
CPU time 6.56 seconds
Started Apr 15 12:36:45 PM PDT 24
Finished Apr 15 12:36:54 PM PDT 24
Peak memory 248228 kb
Host smart-3a1c9927-f395-4e24-bb11-2887e11d334c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3643109441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3643109441
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3161549032
Short name T734
Test name
Test status
Simulation time 68306649 ps
CPU time 5.73 seconds
Started Apr 15 12:37:02 PM PDT 24
Finished Apr 15 12:37:08 PM PDT 24
Peak memory 239156 kb
Host smart-4336e062-0666-48db-9a26-dd1e6dfd72ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161549032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3161549032
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.479625950
Short name T730
Test name
Test status
Simulation time 130089438 ps
CPU time 9.57 seconds
Started Apr 15 12:36:55 PM PDT 24
Finished Apr 15 12:37:05 PM PDT 24
Peak memory 236240 kb
Host smart-76f627d8-7c0a-4279-93e5-c769f57da754
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=479625950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.479625950
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2125919763
Short name T796
Test name
Test status
Simulation time 495511691 ps
CPU time 31.73 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:37:32 PM PDT 24
Peak memory 248084 kb
Host smart-3c247a78-e182-4454-a194-9d9031f7a846
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2125919763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2125919763
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.183628185
Short name T131
Test name
Test status
Simulation time 13139971787 ps
CPU time 1065.27 seconds
Started Apr 15 12:36:52 PM PDT 24
Finished Apr 15 12:54:39 PM PDT 24
Peak memory 265156 kb
Host smart-d5fc69e8-ffbc-4805-87b6-b35aeaa01141
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183628185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.183628185
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.388781375
Short name T799
Test name
Test status
Simulation time 222679294 ps
CPU time 4.47 seconds
Started Apr 15 12:36:50 PM PDT 24
Finished Apr 15 12:36:56 PM PDT 24
Peak memory 239584 kb
Host smart-d52de8bf-ddf9-46d7-aef7-7c5f9c41b7e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=388781375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.388781375
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.23073525
Short name T736
Test name
Test status
Simulation time 139722156 ps
CPU time 5.55 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:37:06 PM PDT 24
Peak memory 237316 kb
Host smart-abce69dc-7cda-4e4b-b4f1-5b89b4f6fc98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23073525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.alert_handler_csr_mem_rw_with_rand_reset.23073525
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.287523903
Short name T723
Test name
Test status
Simulation time 357612443 ps
CPU time 7.51 seconds
Started Apr 15 12:37:07 PM PDT 24
Finished Apr 15 12:37:16 PM PDT 24
Peak memory 236208 kb
Host smart-b9d52731-9610-49cc-b72b-2d6a9186b1e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=287523903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.287523903
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1653290176
Short name T728
Test name
Test status
Simulation time 7507097 ps
CPU time 1.46 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:37:01 PM PDT 24
Peak memory 234368 kb
Host smart-e7f6eeeb-fafe-4ec4-b6fd-fb5724db3c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1653290176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1653290176
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3592319062
Short name T189
Test name
Test status
Simulation time 1058473205 ps
CPU time 36.47 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:37 PM PDT 24
Peak memory 243648 kb
Host smart-e31d624b-cc59-4a17-a8dd-aacbe2656db5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3592319062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3592319062
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1681031896
Short name T715
Test name
Test status
Simulation time 1158866468 ps
CPU time 15.83 seconds
Started Apr 15 12:36:49 PM PDT 24
Finished Apr 15 12:37:07 PM PDT 24
Peak memory 247928 kb
Host smart-31ffda16-cb09-477e-b285-0909b01fe504
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1681031896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1681031896
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2302001709
Short name T806
Test name
Test status
Simulation time 105183111 ps
CPU time 5.01 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:37:05 PM PDT 24
Peak memory 238832 kb
Host smart-686625cf-b87d-4f18-810e-08ca0cbee935
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302001709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2302001709
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3171728507
Short name T738
Test name
Test status
Simulation time 621779224 ps
CPU time 8.8 seconds
Started Apr 15 12:37:03 PM PDT 24
Finished Apr 15 12:37:13 PM PDT 24
Peak memory 236020 kb
Host smart-545bbecb-b66f-4ae7-87cd-2f03b185d1d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3171728507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3171728507
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1887043534
Short name T828
Test name
Test status
Simulation time 8977689 ps
CPU time 1.23 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:37:01 PM PDT 24
Peak memory 234384 kb
Host smart-3002f6c1-5fb0-49f1-a817-1d5b20125ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1887043534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1887043534
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.193882533
Short name T739
Test name
Test status
Simulation time 1017890762 ps
CPU time 36.85 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:37:37 PM PDT 24
Peak memory 244432 kb
Host smart-d2aaa203-d1f1-4b27-b591-694fa2cd0632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=193882533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.193882533
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2812651730
Short name T803
Test name
Test status
Simulation time 198389508 ps
CPU time 7.17 seconds
Started Apr 15 12:36:55 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 248244 kb
Host smart-5c25bb4c-f463-4a9e-b9b4-3d691d06877e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2812651730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2812651730
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3880344850
Short name T760
Test name
Test status
Simulation time 268978371 ps
CPU time 4.53 seconds
Started Apr 15 12:36:52 PM PDT 24
Finished Apr 15 12:36:57 PM PDT 24
Peak memory 239976 kb
Host smart-e6ecf46e-1203-43a1-bce0-80ae350804d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3880344850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3880344850
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2791762880
Short name T825
Test name
Test status
Simulation time 42258166 ps
CPU time 1.44 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 236204 kb
Host smart-c5d61b1c-4c75-4623-a495-8bca470d388f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2791762880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2791762880
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3421128606
Short name T788
Test name
Test status
Simulation time 1384172272 ps
CPU time 23.37 seconds
Started Apr 15 12:36:56 PM PDT 24
Finished Apr 15 12:37:20 PM PDT 24
Peak memory 244492 kb
Host smart-b87037d0-074e-411e-96c3-b1e99fa72fc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3421128606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3421128606
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.634463978
Short name T137
Test name
Test status
Simulation time 35578713195 ps
CPU time 316.36 seconds
Started Apr 15 12:37:06 PM PDT 24
Finished Apr 15 12:42:23 PM PDT 24
Peak memory 265008 kb
Host smart-cb5b7393-2bbd-4cfa-8a91-47506cb4e3ad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634463978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.634463978
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2794870593
Short name T784
Test name
Test status
Simulation time 234096240 ps
CPU time 7.7 seconds
Started Apr 15 12:36:54 PM PDT 24
Finished Apr 15 12:37:02 PM PDT 24
Peak memory 247668 kb
Host smart-d8d15246-5ee0-4608-828e-6cf85ec159e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2794870593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2794870593
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2076745305
Short name T757
Test name
Test status
Simulation time 38037050 ps
CPU time 6.66 seconds
Started Apr 15 12:37:07 PM PDT 24
Finished Apr 15 12:37:15 PM PDT 24
Peak memory 243360 kb
Host smart-51cc0b14-79b7-4e4d-a600-6f4040879777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076745305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2076745305
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4016218899
Short name T777
Test name
Test status
Simulation time 294895956 ps
CPU time 3.47 seconds
Started Apr 15 12:37:06 PM PDT 24
Finished Apr 15 12:37:12 PM PDT 24
Peak memory 239140 kb
Host smart-daa14f42-8cee-485f-b412-0d6305fa0850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4016218899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.4016218899
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.624904850
Short name T746
Test name
Test status
Simulation time 25303295 ps
CPU time 1.19 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:02 PM PDT 24
Peak memory 236340 kb
Host smart-1e52412e-1e57-45df-b5a5-c223ae2227f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=624904850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.624904850
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3185278664
Short name T726
Test name
Test status
Simulation time 3683084736 ps
CPU time 49.23 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:37:50 PM PDT 24
Peak memory 244588 kb
Host smart-1f130a06-9aef-4ae5-be9a-855384240b88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3185278664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3185278664
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4036828873
Short name T140
Test name
Test status
Simulation time 1012789809 ps
CPU time 111.86 seconds
Started Apr 15 12:36:54 PM PDT 24
Finished Apr 15 12:38:47 PM PDT 24
Peak memory 264788 kb
Host smart-2c11b3ed-d0af-4856-ad84-0a9d1d66528a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4036828873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.4036828873
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.766172654
Short name T130
Test name
Test status
Simulation time 36050788923 ps
CPU time 299.59 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:42:00 PM PDT 24
Peak memory 264928 kb
Host smart-14ce2cb7-034b-441b-aa08-53e83622b281
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766172654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.766172654
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.325368679
Short name T810
Test name
Test status
Simulation time 184156958 ps
CPU time 13.39 seconds
Started Apr 15 12:36:56 PM PDT 24
Finished Apr 15 12:37:10 PM PDT 24
Peak memory 251928 kb
Host smart-18b6e1f5-c91e-4bb1-bc59-3d38ae462d99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=325368679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.325368679
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1248504987
Short name T191
Test name
Test status
Simulation time 65923916 ps
CPU time 5.72 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 236208 kb
Host smart-d779648b-2c9a-4f6d-bbc9-f47c3b200a16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1248504987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1248504987
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.433098438
Short name T716
Test name
Test status
Simulation time 27159756 ps
CPU time 1.5 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:36:59 PM PDT 24
Peak memory 236244 kb
Host smart-2e2fa111-56c3-4f9a-9892-d3c9c494d04e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=433098438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.433098438
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2792195886
Short name T769
Test name
Test status
Simulation time 269379648 ps
CPU time 18.47 seconds
Started Apr 15 12:37:03 PM PDT 24
Finished Apr 15 12:37:22 PM PDT 24
Peak memory 243492 kb
Host smart-8ec7b831-038c-44f1-90d3-070c6a341488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2792195886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2792195886
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3720035042
Short name T125
Test name
Test status
Simulation time 7401618260 ps
CPU time 330.19 seconds
Started Apr 15 12:37:02 PM PDT 24
Finished Apr 15 12:42:38 PM PDT 24
Peak memory 272692 kb
Host smart-23b2f356-5f84-4d58-b906-ceba74d62558
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3720035042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3720035042
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.852997394
Short name T135
Test name
Test status
Simulation time 5278981825 ps
CPU time 577.21 seconds
Started Apr 15 12:36:58 PM PDT 24
Finished Apr 15 12:46:36 PM PDT 24
Peak memory 264832 kb
Host smart-9a48bfb4-8de4-4d2b-ad86-0258581af275
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852997394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.852997394
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2267273945
Short name T724
Test name
Test status
Simulation time 351242704 ps
CPU time 22.61 seconds
Started Apr 15 12:37:02 PM PDT 24
Finished Apr 15 12:37:26 PM PDT 24
Peak memory 248136 kb
Host smart-2beb9572-992d-4127-a05e-7edf15d58b15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2267273945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2267273945
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2983543167
Short name T764
Test name
Test status
Simulation time 126801839 ps
CPU time 4.75 seconds
Started Apr 15 12:37:08 PM PDT 24
Finished Apr 15 12:37:14 PM PDT 24
Peak memory 239872 kb
Host smart-b1c9b26e-d143-43df-886e-67a454033063
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983543167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2983543167
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3934674131
Short name T817
Test name
Test status
Simulation time 111641060 ps
CPU time 7.72 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:37:05 PM PDT 24
Peak memory 235452 kb
Host smart-d746b123-a213-4ee4-bb4d-c750b9a19f11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3934674131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3934674131
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2801677407
Short name T727
Test name
Test status
Simulation time 22305119 ps
CPU time 1.59 seconds
Started Apr 15 12:37:09 PM PDT 24
Finished Apr 15 12:37:12 PM PDT 24
Peak memory 235352 kb
Host smart-014dbb55-006b-456d-afa9-61e75e57dcc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2801677407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2801677407
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2853626188
Short name T174
Test name
Test status
Simulation time 2663380900 ps
CPU time 19.24 seconds
Started Apr 15 12:36:56 PM PDT 24
Finished Apr 15 12:37:16 PM PDT 24
Peak memory 244552 kb
Host smart-4bbfb7f5-5daa-4d1f-8c91-430b9f2669de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2853626188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2853626188
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1065995434
Short name T718
Test name
Test status
Simulation time 114234173 ps
CPU time 15.14 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:37:13 PM PDT 24
Peak memory 248144 kb
Host smart-2031a484-4254-4367-a887-b494b26da3d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1065995434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1065995434
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2688733608
Short name T751
Test name
Test status
Simulation time 52758455 ps
CPU time 2.48 seconds
Started Apr 15 12:37:07 PM PDT 24
Finished Apr 15 12:37:11 PM PDT 24
Peak memory 236252 kb
Host smart-d21ce36d-5fef-4938-85a7-9d214f7aa1c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2688733608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2688733608
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4243248646
Short name T357
Test name
Test status
Simulation time 154368976 ps
CPU time 12 seconds
Started Apr 15 12:36:55 PM PDT 24
Finished Apr 15 12:37:08 PM PDT 24
Peak memory 250284 kb
Host smart-4f3d2cae-13d4-457c-b6eb-9ff19c94255b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243248646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.4243248646
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2139784083
Short name T804
Test name
Test status
Simulation time 272739800 ps
CPU time 4.86 seconds
Started Apr 15 12:37:01 PM PDT 24
Finished Apr 15 12:37:07 PM PDT 24
Peak memory 239192 kb
Host smart-a4b8fd7c-9a6d-4249-b10a-48f5eadb74ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2139784083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2139784083
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.878302113
Short name T811
Test name
Test status
Simulation time 9271791 ps
CPU time 1.26 seconds
Started Apr 15 12:37:09 PM PDT 24
Finished Apr 15 12:37:11 PM PDT 24
Peak memory 236228 kb
Host smart-a01362ac-a879-428f-a9db-e20307450d78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=878302113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.878302113
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.497772561
Short name T241
Test name
Test status
Simulation time 604822478 ps
CPU time 24.12 seconds
Started Apr 15 12:37:07 PM PDT 24
Finished Apr 15 12:37:33 PM PDT 24
Peak memory 239256 kb
Host smart-5a912b1e-8487-4cfb-b13f-cf4cccc3ddfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=497772561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.497772561
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.829446807
Short name T144
Test name
Test status
Simulation time 4067916149 ps
CPU time 273.67 seconds
Started Apr 15 12:37:06 PM PDT 24
Finished Apr 15 12:41:42 PM PDT 24
Peak memory 272388 kb
Host smart-74f8bef9-efea-475e-ac39-be19e99f0613
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=829446807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.829446807
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2350858243
Short name T127
Test name
Test status
Simulation time 10222356379 ps
CPU time 562.43 seconds
Started Apr 15 12:37:06 PM PDT 24
Finished Apr 15 12:46:30 PM PDT 24
Peak memory 264808 kb
Host smart-109c6583-7650-47db-a325-b39caf2c4bb0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350858243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2350858243
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3213270101
Short name T795
Test name
Test status
Simulation time 1803839255 ps
CPU time 31.17 seconds
Started Apr 15 12:37:01 PM PDT 24
Finished Apr 15 12:37:33 PM PDT 24
Peak memory 247708 kb
Host smart-cfafa3a3-ed26-49c3-aecd-f5aca07248ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3213270101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3213270101
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1349680831
Short name T172
Test name
Test status
Simulation time 224377482 ps
CPU time 5.35 seconds
Started Apr 15 12:37:06 PM PDT 24
Finished Apr 15 12:37:12 PM PDT 24
Peak memory 237296 kb
Host smart-312a9135-342e-4073-94bf-a4497e9849ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349680831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1349680831
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1034268799
Short name T781
Test name
Test status
Simulation time 94008818 ps
CPU time 8.82 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:10 PM PDT 24
Peak memory 236220 kb
Host smart-f14d5369-699a-49dd-b941-bce267767df9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1034268799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1034268799
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3155420195
Short name T722
Test name
Test status
Simulation time 9804437 ps
CPU time 1.31 seconds
Started Apr 15 12:37:07 PM PDT 24
Finished Apr 15 12:37:10 PM PDT 24
Peak memory 236216 kb
Host smart-e3fbbe15-3879-4634-a945-b012d416364c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3155420195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3155420195
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3659071600
Short name T194
Test name
Test status
Simulation time 327002634 ps
CPU time 20.83 seconds
Started Apr 15 12:37:07 PM PDT 24
Finished Apr 15 12:37:30 PM PDT 24
Peak memory 243516 kb
Host smart-9bbcb420-2723-49b2-9c6f-23a82ad81f21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3659071600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3659071600
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.259423357
Short name T119
Test name
Test status
Simulation time 3203965417 ps
CPU time 97.37 seconds
Started Apr 15 12:37:01 PM PDT 24
Finished Apr 15 12:38:39 PM PDT 24
Peak memory 264816 kb
Host smart-e323d9ab-34e0-4070-9cac-f971c9367641
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=259423357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.259423357
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3005629474
Short name T143
Test name
Test status
Simulation time 3107477715 ps
CPU time 330.09 seconds
Started Apr 15 12:36:53 PM PDT 24
Finished Apr 15 12:42:24 PM PDT 24
Peak memory 264980 kb
Host smart-2db0f413-e4c6-48cb-8249-1997521c3eaf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005629474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3005629474
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.388859314
Short name T809
Test name
Test status
Simulation time 280837198 ps
CPU time 18.63 seconds
Started Apr 15 12:37:06 PM PDT 24
Finished Apr 15 12:37:26 PM PDT 24
Peak memory 253748 kb
Host smart-458e0734-72e7-44fc-9356-9d90af97ccf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=388859314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.388859314
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1764259216
Short name T779
Test name
Test status
Simulation time 270541367 ps
CPU time 8.87 seconds
Started Apr 15 12:37:24 PM PDT 24
Finished Apr 15 12:37:33 PM PDT 24
Peak memory 237260 kb
Host smart-7ae1803a-0f55-4dba-b509-a58ef2892a2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764259216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1764259216
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3211635720
Short name T794
Test name
Test status
Simulation time 49752714 ps
CPU time 4.68 seconds
Started Apr 15 12:37:07 PM PDT 24
Finished Apr 15 12:37:13 PM PDT 24
Peak memory 236208 kb
Host smart-6590efe2-a5fe-42e5-9c06-d4f19f09bff3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3211635720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3211635720
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4062456010
Short name T755
Test name
Test status
Simulation time 17620868 ps
CPU time 1.49 seconds
Started Apr 15 12:37:06 PM PDT 24
Finished Apr 15 12:37:09 PM PDT 24
Peak memory 236328 kb
Host smart-7790c424-1625-47fa-b5d2-3769cda0758e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4062456010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.4062456010
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3204610489
Short name T750
Test name
Test status
Simulation time 168304902 ps
CPU time 13.84 seconds
Started Apr 15 12:37:07 PM PDT 24
Finished Apr 15 12:37:22 PM PDT 24
Peak memory 244380 kb
Host smart-e55e2921-6c35-4a46-ae6b-a0054af86548
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3204610489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3204610489
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3404688554
Short name T360
Test name
Test status
Simulation time 6038075152 ps
CPU time 447.15 seconds
Started Apr 15 12:36:56 PM PDT 24
Finished Apr 15 12:44:24 PM PDT 24
Peak memory 266096 kb
Host smart-aeef4e14-9c66-4f47-a144-89b9c1e7e70e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404688554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3404688554
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3993019824
Short name T709
Test name
Test status
Simulation time 71234392 ps
CPU time 9.52 seconds
Started Apr 15 12:37:06 PM PDT 24
Finished Apr 15 12:37:17 PM PDT 24
Peak memory 248080 kb
Host smart-095ad84f-142f-4d7c-ba02-0ef182007cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3993019824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3993019824
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.878540855
Short name T754
Test name
Test status
Simulation time 49628735263 ps
CPU time 272.02 seconds
Started Apr 15 12:36:52 PM PDT 24
Finished Apr 15 12:41:24 PM PDT 24
Peak memory 240024 kb
Host smart-e236ffad-5a57-4329-bc38-0ce89f3667b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=878540855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.878540855
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1747198863
Short name T776
Test name
Test status
Simulation time 2210458299 ps
CPU time 178.26 seconds
Started Apr 15 12:36:46 PM PDT 24
Finished Apr 15 12:39:47 PM PDT 24
Peak memory 239992 kb
Host smart-0b6a89bd-9b83-4676-8840-1d856a73c658
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1747198863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1747198863
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3389726091
Short name T824
Test name
Test status
Simulation time 243122043 ps
CPU time 5.83 seconds
Started Apr 15 12:36:54 PM PDT 24
Finished Apr 15 12:37:00 PM PDT 24
Peak memory 239832 kb
Host smart-d4c2028b-e202-4d62-9572-428e57a51ceb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3389726091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3389726091
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1065141045
Short name T827
Test name
Test status
Simulation time 270017734 ps
CPU time 6.09 seconds
Started Apr 15 12:36:47 PM PDT 24
Finished Apr 15 12:36:56 PM PDT 24
Peak memory 238768 kb
Host smart-7a5fb9ea-f301-403f-9c2f-ebde7c05210e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065141045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1065141045
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4260680763
Short name T190
Test name
Test status
Simulation time 111451717 ps
CPU time 5.02 seconds
Started Apr 15 12:36:54 PM PDT 24
Finished Apr 15 12:37:00 PM PDT 24
Peak memory 236176 kb
Host smart-826464b2-8a25-4b65-a644-1ce7649f10dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4260680763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4260680763
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.959092987
Short name T740
Test name
Test status
Simulation time 10615387 ps
CPU time 1.34 seconds
Started Apr 15 12:36:54 PM PDT 24
Finished Apr 15 12:36:56 PM PDT 24
Peak memory 235468 kb
Host smart-6bf6c6e7-2db8-4f60-9602-f4f7adfca801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=959092987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.959092987
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3236490412
Short name T791
Test name
Test status
Simulation time 2276463226 ps
CPU time 25.37 seconds
Started Apr 15 12:36:50 PM PDT 24
Finished Apr 15 12:37:16 PM PDT 24
Peak memory 244476 kb
Host smart-c0327c69-bd77-43f9-b679-a22d78209f6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3236490412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3236490412
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3073603284
Short name T116
Test name
Test status
Simulation time 1580860708 ps
CPU time 211.22 seconds
Started Apr 15 12:36:49 PM PDT 24
Finished Apr 15 12:40:22 PM PDT 24
Peak memory 264852 kb
Host smart-4f506260-2ee4-447c-b608-0cac2b2d4077
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3073603284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3073603284
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2246985305
Short name T361
Test name
Test status
Simulation time 2224092151 ps
CPU time 289.29 seconds
Started Apr 15 12:36:44 PM PDT 24
Finished Apr 15 12:41:35 PM PDT 24
Peak memory 264932 kb
Host smart-d6d159b0-626a-411c-be4f-37c8717caa82
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246985305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2246985305
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4228826763
Short name T711
Test name
Test status
Simulation time 83726189 ps
CPU time 10.29 seconds
Started Apr 15 12:36:43 PM PDT 24
Finished Apr 15 12:36:55 PM PDT 24
Peak memory 247336 kb
Host smart-a7c54c22-1258-4ba9-a3ed-39f5c95c2b6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4228826763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.4228826763
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.905510948
Short name T786
Test name
Test status
Simulation time 6189297 ps
CPU time 1.37 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:37:00 PM PDT 24
Peak memory 236252 kb
Host smart-e23ff7ba-b5d2-43d5-b942-ef9a3bff84cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=905510948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.905510948
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3702447591
Short name T818
Test name
Test status
Simulation time 8532739 ps
CPU time 1.44 seconds
Started Apr 15 12:37:01 PM PDT 24
Finished Apr 15 12:37:04 PM PDT 24
Peak memory 236220 kb
Host smart-7f6873cd-2eab-45ff-ba01-61a81a02c392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3702447591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3702447591
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1848345196
Short name T735
Test name
Test status
Simulation time 22042671 ps
CPU time 1.38 seconds
Started Apr 15 12:36:58 PM PDT 24
Finished Apr 15 12:37:00 PM PDT 24
Peak memory 234656 kb
Host smart-3678122c-0919-47de-90b6-052e9b990054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1848345196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1848345196
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.508610267
Short name T800
Test name
Test status
Simulation time 7587913 ps
CPU time 1.3 seconds
Started Apr 15 12:36:58 PM PDT 24
Finished Apr 15 12:37:01 PM PDT 24
Peak memory 236336 kb
Host smart-c59d7fa8-8e91-48f8-8465-e16e452fe5db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=508610267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.508610267
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1954388808
Short name T353
Test name
Test status
Simulation time 27975045 ps
CPU time 1.38 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 236292 kb
Host smart-b38c12ee-10dc-4309-bff1-1fa0cbbb58cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1954388808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1954388808
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.234044022
Short name T752
Test name
Test status
Simulation time 6355911 ps
CPU time 1.44 seconds
Started Apr 15 12:36:58 PM PDT 24
Finished Apr 15 12:37:01 PM PDT 24
Peak memory 235380 kb
Host smart-ce6d51c0-4d3b-4356-ba07-9de9adfa4ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=234044022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.234044022
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2399798980
Short name T821
Test name
Test status
Simulation time 9203547 ps
CPU time 1.57 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:36:59 PM PDT 24
Peak memory 236344 kb
Host smart-e4ea42ec-9d1c-4669-a020-1c8881b09e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2399798980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2399798980
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.4007987518
Short name T743
Test name
Test status
Simulation time 12912228 ps
CPU time 1.25 seconds
Started Apr 15 12:36:58 PM PDT 24
Finished Apr 15 12:37:00 PM PDT 24
Peak memory 234340 kb
Host smart-aed8fc03-4220-4ecb-ba21-d1b675ae1572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4007987518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.4007987518
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1274846576
Short name T748
Test name
Test status
Simulation time 12207742 ps
CPU time 1.35 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:08 PM PDT 24
Peak memory 236344 kb
Host smart-ada90e0a-630f-40fd-a81b-f8316a31053a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1274846576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1274846576
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2174251295
Short name T771
Test name
Test status
Simulation time 26193998 ps
CPU time 1.48 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:37:02 PM PDT 24
Peak memory 236340 kb
Host smart-1cf9b098-b0df-4d60-8d2d-c23c7f8102fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2174251295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2174251295
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.460780269
Short name T765
Test name
Test status
Simulation time 4283779627 ps
CPU time 145.68 seconds
Started Apr 15 12:36:55 PM PDT 24
Finished Apr 15 12:39:21 PM PDT 24
Peak memory 239888 kb
Host smart-093e8a30-9594-46bb-9162-246e97fedaf7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=460780269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.460780269
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1004662530
Short name T192
Test name
Test status
Simulation time 21118545866 ps
CPU time 351.51 seconds
Started Apr 15 12:36:45 PM PDT 24
Finished Apr 15 12:42:39 PM PDT 24
Peak memory 239944 kb
Host smart-c98edbfc-bff9-4424-8149-5623acb9801d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1004662530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1004662530
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4070170667
Short name T744
Test name
Test status
Simulation time 135302958 ps
CPU time 10.89 seconds
Started Apr 15 12:36:54 PM PDT 24
Finished Apr 15 12:37:05 PM PDT 24
Peak memory 239852 kb
Host smart-07f7093c-5dc1-4ebe-b0da-7949dd48bc80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4070170667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.4070170667
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2116128478
Short name T242
Test name
Test status
Simulation time 83691173 ps
CPU time 6.42 seconds
Started Apr 15 12:36:45 PM PDT 24
Finished Apr 15 12:36:53 PM PDT 24
Peak memory 239140 kb
Host smart-5a728994-73cd-498b-a666-5ea1fe1b38bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116128478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2116128478
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.697380654
Short name T737
Test name
Test status
Simulation time 34142319 ps
CPU time 3.1 seconds
Started Apr 15 12:36:49 PM PDT 24
Finished Apr 15 12:36:53 PM PDT 24
Peak memory 235344 kb
Host smart-621e3750-2fe0-45cd-8ac9-b5e5998d7a96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=697380654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.697380654
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2113575253
Short name T792
Test name
Test status
Simulation time 19824862 ps
CPU time 1.4 seconds
Started Apr 15 12:36:52 PM PDT 24
Finished Apr 15 12:36:54 PM PDT 24
Peak memory 236228 kb
Host smart-87a323b9-ab0d-431b-a3d2-36a9e157612d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2113575253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2113575253
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2152377330
Short name T802
Test name
Test status
Simulation time 3652457629 ps
CPU time 41.64 seconds
Started Apr 15 12:36:48 PM PDT 24
Finished Apr 15 12:37:31 PM PDT 24
Peak memory 248156 kb
Host smart-3d4591cc-959b-493d-9b14-0c1fbf94c055
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2152377330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2152377330
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1895758892
Short name T142
Test name
Test status
Simulation time 2300389201 ps
CPU time 216.56 seconds
Started Apr 15 12:36:46 PM PDT 24
Finished Apr 15 12:40:25 PM PDT 24
Peak memory 272732 kb
Host smart-8c417568-b50b-4a6e-8e3b-3e8a09ee372b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1895758892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1895758892
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3800468290
Short name T123
Test name
Test status
Simulation time 4701878205 ps
CPU time 363.93 seconds
Started Apr 15 12:36:49 PM PDT 24
Finished Apr 15 12:42:55 PM PDT 24
Peak memory 264804 kb
Host smart-eaddd84f-f2c9-4ee9-a434-be2172370b46
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800468290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3800468290
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2617081847
Short name T808
Test name
Test status
Simulation time 173407403 ps
CPU time 11 seconds
Started Apr 15 12:36:46 PM PDT 24
Finished Apr 15 12:36:59 PM PDT 24
Peak memory 248148 kb
Host smart-685b9fee-8769-48af-b2fc-ab60a64ba831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2617081847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2617081847
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1602169672
Short name T815
Test name
Test status
Simulation time 6778674 ps
CPU time 1.44 seconds
Started Apr 15 12:37:01 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 235356 kb
Host smart-a6df2263-4b7e-40bf-9e64-0b6c2a689492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1602169672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1602169672
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1711150533
Short name T790
Test name
Test status
Simulation time 10906815 ps
CPU time 1.38 seconds
Started Apr 15 12:36:56 PM PDT 24
Finished Apr 15 12:36:58 PM PDT 24
Peak memory 234412 kb
Host smart-9980498d-5c46-4fcd-86ab-1a2520c7b88e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1711150533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1711150533
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3691726035
Short name T350
Test name
Test status
Simulation time 9304288 ps
CPU time 1.42 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 236336 kb
Host smart-d43e95be-4c57-473c-8eca-36c5ff30a30e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3691726035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3691726035
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3746588768
Short name T731
Test name
Test status
Simulation time 8460800 ps
CPU time 1.47 seconds
Started Apr 15 12:37:02 PM PDT 24
Finished Apr 15 12:37:05 PM PDT 24
Peak memory 235364 kb
Host smart-cc46da35-c1fe-466c-a937-272d36b4e08c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3746588768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3746588768
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3296302540
Short name T712
Test name
Test status
Simulation time 8872367 ps
CPU time 1.56 seconds
Started Apr 15 12:37:02 PM PDT 24
Finished Apr 15 12:37:05 PM PDT 24
Peak memory 235376 kb
Host smart-73c49ba9-b3c2-440c-a1e8-01bc3d7fa049
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3296302540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3296302540
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3390404532
Short name T762
Test name
Test status
Simulation time 10256146 ps
CPU time 1.52 seconds
Started Apr 15 12:37:07 PM PDT 24
Finished Apr 15 12:37:10 PM PDT 24
Peak memory 235304 kb
Host smart-d7142ac6-996a-4d5d-941f-ffd3b5ddb488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3390404532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3390404532
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.223188755
Short name T354
Test name
Test status
Simulation time 14946732 ps
CPU time 1.35 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:37:01 PM PDT 24
Peak memory 236240 kb
Host smart-74ef2009-9e7c-48e7-b1a1-0022f3bbc925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=223188755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.223188755
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1074828551
Short name T782
Test name
Test status
Simulation time 8339255 ps
CPU time 1.37 seconds
Started Apr 15 12:37:08 PM PDT 24
Finished Apr 15 12:37:11 PM PDT 24
Peak memory 236172 kb
Host smart-5867e3da-ba69-4bd7-9246-ef1a571b37b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1074828551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1074828551
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1891222967
Short name T761
Test name
Test status
Simulation time 10516797 ps
CPU time 1.25 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:37:01 PM PDT 24
Peak memory 235420 kb
Host smart-6e04c8f2-62e2-415f-ba95-38f76a056a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1891222967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1891222967
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.617175775
Short name T741
Test name
Test status
Simulation time 2555214452 ps
CPU time 144.32 seconds
Started Apr 15 12:36:50 PM PDT 24
Finished Apr 15 12:39:16 PM PDT 24
Peak memory 236284 kb
Host smart-7e8da482-c349-427c-a899-ef3d65a380ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=617175775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.617175775
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2290885740
Short name T775
Test name
Test status
Simulation time 1996018390 ps
CPU time 92.98 seconds
Started Apr 15 12:36:45 PM PDT 24
Finished Apr 15 12:38:20 PM PDT 24
Peak memory 239884 kb
Host smart-be0b07d4-5959-40e1-b9fb-91b8c76d5049
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2290885740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2290885740
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2281253094
Short name T793
Test name
Test status
Simulation time 139399913 ps
CPU time 6.38 seconds
Started Apr 15 12:36:54 PM PDT 24
Finished Apr 15 12:37:01 PM PDT 24
Peak memory 239848 kb
Host smart-a01d1f53-285f-4927-b8b1-e1a97d199e53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2281253094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2281253094
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.314569141
Short name T175
Test name
Test status
Simulation time 80827271 ps
CPU time 7.09 seconds
Started Apr 15 12:36:46 PM PDT 24
Finished Apr 15 12:36:56 PM PDT 24
Peak memory 240316 kb
Host smart-d8602863-956c-415c-99d2-c689fa2979f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314569141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.314569141
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3475690374
Short name T768
Test name
Test status
Simulation time 184043869 ps
CPU time 4.47 seconds
Started Apr 15 12:36:51 PM PDT 24
Finished Apr 15 12:36:56 PM PDT 24
Peak memory 235428 kb
Host smart-789efad1-29d4-42dc-b003-e1aaa173e6f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3475690374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3475690374
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2503933244
Short name T759
Test name
Test status
Simulation time 8307581 ps
CPU time 1.28 seconds
Started Apr 15 12:36:48 PM PDT 24
Finished Apr 15 12:36:51 PM PDT 24
Peak memory 236048 kb
Host smart-55349256-4e54-4b5a-bf4d-7a72cc729cfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2503933244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2503933244
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1796761496
Short name T826
Test name
Test status
Simulation time 1344609162 ps
CPU time 22.67 seconds
Started Apr 15 12:36:48 PM PDT 24
Finished Apr 15 12:37:12 PM PDT 24
Peak memory 244520 kb
Host smart-ffdb0677-c284-43c3-a6c9-c392fe7ea1c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1796761496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1796761496
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3544855387
Short name T146
Test name
Test status
Simulation time 16153383306 ps
CPU time 173.22 seconds
Started Apr 15 12:36:49 PM PDT 24
Finished Apr 15 12:39:44 PM PDT 24
Peak memory 264840 kb
Host smart-116428c0-8127-4bf3-853a-07feecce2630
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3544855387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3544855387
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.576181095
Short name T132
Test name
Test status
Simulation time 2633144433 ps
CPU time 282.19 seconds
Started Apr 15 12:36:54 PM PDT 24
Finished Apr 15 12:41:37 PM PDT 24
Peak memory 264952 kb
Host smart-e6a4e7b5-2a0e-46ce-8b76-7531a55b2ffa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576181095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.576181095
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2357674171
Short name T819
Test name
Test status
Simulation time 897814932 ps
CPU time 14.28 seconds
Started Apr 15 12:36:50 PM PDT 24
Finished Apr 15 12:37:06 PM PDT 24
Peak memory 248192 kb
Host smart-a3968b92-bfc0-4ca5-acf2-42216801d62d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2357674171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2357674171
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2369443897
Short name T729
Test name
Test status
Simulation time 10164621 ps
CPU time 1.63 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 236340 kb
Host smart-c460c852-bbfa-4291-8d81-85e59d283346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2369443897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2369443897
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2617797177
Short name T805
Test name
Test status
Simulation time 6734752 ps
CPU time 1.45 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 235456 kb
Host smart-dcc663c0-cc87-4089-8e93-ab21d2716f78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2617797177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2617797177
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.767602576
Short name T157
Test name
Test status
Simulation time 6623395 ps
CPU time 1.36 seconds
Started Apr 15 12:37:02 PM PDT 24
Finished Apr 15 12:37:04 PM PDT 24
Peak memory 236276 kb
Host smart-a7e23bb9-4591-4d0c-8eae-3548a0a14679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=767602576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.767602576
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2153893536
Short name T758
Test name
Test status
Simulation time 9971093 ps
CPU time 1.66 seconds
Started Apr 15 12:37:02 PM PDT 24
Finished Apr 15 12:37:05 PM PDT 24
Peak memory 235372 kb
Host smart-29538ee9-a462-480e-b20a-5a76ff43794e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2153893536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2153893536
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2366309870
Short name T745
Test name
Test status
Simulation time 15044353 ps
CPU time 1.43 seconds
Started Apr 15 12:37:03 PM PDT 24
Finished Apr 15 12:37:05 PM PDT 24
Peak memory 236244 kb
Host smart-8109da68-b84c-4671-8233-5a8c6a2e6521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2366309870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2366309870
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.276695265
Short name T155
Test name
Test status
Simulation time 12713565 ps
CPU time 1.61 seconds
Started Apr 15 12:36:58 PM PDT 24
Finished Apr 15 12:37:01 PM PDT 24
Peak memory 235420 kb
Host smart-444a56c1-b903-45e5-942c-cc235bba509f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=276695265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.276695265
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2948661101
Short name T156
Test name
Test status
Simulation time 20495914 ps
CPU time 1.41 seconds
Started Apr 15 12:37:21 PM PDT 24
Finished Apr 15 12:37:23 PM PDT 24
Peak memory 235292 kb
Host smart-3bae219e-dc73-47c5-beda-4fc03c641a9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2948661101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2948661101
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3504664081
Short name T785
Test name
Test status
Simulation time 6507688 ps
CPU time 1.5 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 236340 kb
Host smart-125e9316-44ba-4f14-9786-ed53b1a6f119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3504664081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3504664081
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1422249473
Short name T813
Test name
Test status
Simulation time 12548969 ps
CPU time 1.37 seconds
Started Apr 15 12:37:00 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 236336 kb
Host smart-ee8b9653-1994-489a-8123-4c0899e3eec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1422249473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1422249473
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3854683669
Short name T349
Test name
Test status
Simulation time 16368627 ps
CPU time 1.3 seconds
Started Apr 15 12:37:21 PM PDT 24
Finished Apr 15 12:37:22 PM PDT 24
Peak memory 235312 kb
Host smart-b6bb7c8c-3b91-4eb3-9bfe-85b963ef3b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3854683669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3854683669
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3220100641
Short name T780
Test name
Test status
Simulation time 270818761 ps
CPU time 5.39 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 240800 kb
Host smart-6481b810-c9a3-414f-9c5c-f6a02bfdf2d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220100641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3220100641
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4008858651
Short name T749
Test name
Test status
Simulation time 196011236 ps
CPU time 4.65 seconds
Started Apr 15 12:36:55 PM PDT 24
Finished Apr 15 12:37:01 PM PDT 24
Peak memory 235340 kb
Host smart-c3829d75-2612-4d0f-be77-afb33bf9bdc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4008858651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.4008858651
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3403918247
Short name T820
Test name
Test status
Simulation time 667532797 ps
CPU time 41.94 seconds
Started Apr 15 12:37:03 PM PDT 24
Finished Apr 15 12:37:46 PM PDT 24
Peak memory 247300 kb
Host smart-f10cbcb4-ac6f-4292-b36f-d2492cc5d6c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3403918247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3403918247
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2315460641
Short name T719
Test name
Test status
Simulation time 358758976 ps
CPU time 13.91 seconds
Started Apr 15 12:36:51 PM PDT 24
Finished Apr 15 12:37:06 PM PDT 24
Peak memory 248164 kb
Host smart-f417c7a5-3c1a-426b-8fdb-05d2fbd77c13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2315460641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2315460641
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.542654557
Short name T152
Test name
Test status
Simulation time 61376600 ps
CPU time 2.26 seconds
Started Apr 15 12:36:48 PM PDT 24
Finished Apr 15 12:36:52 PM PDT 24
Peak memory 236740 kb
Host smart-032f345a-44de-4e4c-9c74-c0d14eabb3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=542654557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.542654557
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4002676461
Short name T742
Test name
Test status
Simulation time 97059650 ps
CPU time 4.66 seconds
Started Apr 15 12:36:55 PM PDT 24
Finished Apr 15 12:37:01 PM PDT 24
Peak memory 236664 kb
Host smart-6778a14b-d60a-4f57-8562-4a331c8899af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002676461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.4002676461
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.203987004
Short name T816
Test name
Test status
Simulation time 575733076 ps
CPU time 8.29 seconds
Started Apr 15 12:36:53 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 235332 kb
Host smart-e4eb4eb3-881d-4220-8635-98d6b132a2c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=203987004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.203987004
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2934057152
Short name T822
Test name
Test status
Simulation time 6367993 ps
CPU time 1.41 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:36:59 PM PDT 24
Peak memory 236236 kb
Host smart-c485968e-bb6e-4fb3-9102-c2718b956363
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2934057152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2934057152
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2773773013
Short name T778
Test name
Test status
Simulation time 169477171 ps
CPU time 23.03 seconds
Started Apr 15 12:36:52 PM PDT 24
Finished Apr 15 12:37:16 PM PDT 24
Peak memory 244368 kb
Host smart-fd5b49c1-b3ab-436c-b6fa-f37968e59dec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2773773013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2773773013
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3823061232
Short name T725
Test name
Test status
Simulation time 193326652 ps
CPU time 13.16 seconds
Started Apr 15 12:37:01 PM PDT 24
Finished Apr 15 12:37:15 PM PDT 24
Peak memory 251500 kb
Host smart-f453c77d-91d8-4284-9ac9-7bdda881a8e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3823061232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3823061232
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.197029326
Short name T358
Test name
Test status
Simulation time 67580258 ps
CPU time 6.28 seconds
Started Apr 15 12:37:03 PM PDT 24
Finished Apr 15 12:37:10 PM PDT 24
Peak memory 248084 kb
Host smart-dc8a3bf8-3b47-4c5b-a88e-75c2a44faf32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197029326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.197029326
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1456551532
Short name T763
Test name
Test status
Simulation time 187325262 ps
CPU time 5.26 seconds
Started Apr 15 12:37:03 PM PDT 24
Finished Apr 15 12:37:09 PM PDT 24
Peak memory 236152 kb
Host smart-c5853bbf-9ea5-41ba-b1b0-85bdd7840d6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1456551532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1456551532
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3253177080
Short name T732
Test name
Test status
Simulation time 8388263 ps
CPU time 1.52 seconds
Started Apr 15 12:36:50 PM PDT 24
Finished Apr 15 12:36:53 PM PDT 24
Peak memory 236336 kb
Host smart-4ae133c3-a225-4da4-951b-1ade6e474d31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3253177080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3253177080
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.14861616
Short name T173
Test name
Test status
Simulation time 1718703815 ps
CPU time 41.31 seconds
Started Apr 15 12:36:52 PM PDT 24
Finished Apr 15 12:37:34 PM PDT 24
Peak memory 244492 kb
Host smart-dba4ad6b-1a8f-4b13-a8b0-9a1028edaee3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=14861616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outst
anding.14861616
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1425897133
Short name T141
Test name
Test status
Simulation time 11188719841 ps
CPU time 193.38 seconds
Started Apr 15 12:36:53 PM PDT 24
Finished Apr 15 12:40:08 PM PDT 24
Peak memory 264908 kb
Host smart-56587e25-cfb3-495d-a09e-beb27f6bd192
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1425897133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1425897133
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3893427185
Short name T139
Test name
Test status
Simulation time 7191719319 ps
CPU time 468.39 seconds
Started Apr 15 12:36:52 PM PDT 24
Finished Apr 15 12:44:42 PM PDT 24
Peak memory 268456 kb
Host smart-91b682ac-8ab0-4cad-84d0-191047c63982
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893427185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3893427185
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1162650981
Short name T720
Test name
Test status
Simulation time 124896889 ps
CPU time 7.98 seconds
Started Apr 15 12:36:50 PM PDT 24
Finished Apr 15 12:37:00 PM PDT 24
Peak memory 248160 kb
Host smart-583d3acb-d9dc-456f-9303-22a2363f9146
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1162650981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1162650981
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.513979409
Short name T733
Test name
Test status
Simulation time 479022834 ps
CPU time 12.16 seconds
Started Apr 15 12:37:03 PM PDT 24
Finished Apr 15 12:37:16 PM PDT 24
Peak memory 249868 kb
Host smart-ae6bd1e9-8eeb-43b2-8118-1805236d543b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513979409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.513979409
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2632892739
Short name T823
Test name
Test status
Simulation time 96657857 ps
CPU time 4.89 seconds
Started Apr 15 12:37:01 PM PDT 24
Finished Apr 15 12:37:07 PM PDT 24
Peak memory 239800 kb
Host smart-8e11ea60-1c72-4fcf-ba69-ae9dc3a93f78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2632892739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2632892739
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3722499488
Short name T789
Test name
Test status
Simulation time 13451929 ps
CPU time 1.65 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:37:00 PM PDT 24
Peak memory 235416 kb
Host smart-ba3e96d1-814e-45a9-95a4-25cbddc787fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3722499488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3722499488
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1497809672
Short name T807
Test name
Test status
Simulation time 1004486599 ps
CPU time 17.8 seconds
Started Apr 15 12:36:59 PM PDT 24
Finished Apr 15 12:37:18 PM PDT 24
Peak memory 239888 kb
Host smart-9eeb50d8-05bc-4c37-ac17-1f898db7c53e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1497809672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1497809672
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.878574936
Short name T136
Test name
Test status
Simulation time 2189364547 ps
CPU time 158.97 seconds
Started Apr 15 12:36:47 PM PDT 24
Finished Apr 15 12:39:29 PM PDT 24
Peak memory 256440 kb
Host smart-64cbedb4-fac8-43f5-9461-7bdafd35ce79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=878574936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.878574936
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.961553797
Short name T149
Test name
Test status
Simulation time 6944525301 ps
CPU time 484.44 seconds
Started Apr 15 12:36:52 PM PDT 24
Finished Apr 15 12:44:58 PM PDT 24
Peak memory 264804 kb
Host smart-d335a1f9-02c8-4f05-91e4-ad0eb55262df
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961553797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.961553797
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3372338576
Short name T717
Test name
Test status
Simulation time 235433169 ps
CPU time 7.75 seconds
Started Apr 15 12:36:49 PM PDT 24
Finished Apr 15 12:36:58 PM PDT 24
Peak memory 248064 kb
Host smart-3f7d3575-f407-497b-8e3d-c0faab8cf578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3372338576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3372338576
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1424730195
Short name T721
Test name
Test status
Simulation time 81276388 ps
CPU time 6.96 seconds
Started Apr 15 12:36:54 PM PDT 24
Finished Apr 15 12:37:02 PM PDT 24
Peak memory 240196 kb
Host smart-76e25310-5958-45c6-8b0a-847e416dd49a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424730195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1424730195
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.477026657
Short name T753
Test name
Test status
Simulation time 19666250 ps
CPU time 3.32 seconds
Started Apr 15 12:36:56 PM PDT 24
Finished Apr 15 12:37:00 PM PDT 24
Peak memory 235636 kb
Host smart-c6dae266-0cd9-4183-a69f-3ff0d6219c56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=477026657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.477026657
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.261410173
Short name T756
Test name
Test status
Simulation time 25256038 ps
CPU time 2.08 seconds
Started Apr 15 12:37:01 PM PDT 24
Finished Apr 15 12:37:04 PM PDT 24
Peak memory 234332 kb
Host smart-9d16bc15-de7a-4508-b61c-a81d3a6b2d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=261410173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.261410173
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2148436936
Short name T710
Test name
Test status
Simulation time 1996713648 ps
CPU time 36.01 seconds
Started Apr 15 12:36:57 PM PDT 24
Finished Apr 15 12:37:34 PM PDT 24
Peak memory 244416 kb
Host smart-ea77eb24-3292-4817-8fb8-39962f7076c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2148436936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2148436936
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.157515991
Short name T120
Test name
Test status
Simulation time 3879868637 ps
CPU time 300.34 seconds
Started Apr 15 12:36:55 PM PDT 24
Finished Apr 15 12:41:56 PM PDT 24
Peak memory 264824 kb
Host smart-a269d649-dc82-4b0b-93a4-6a3d0cef76e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=157515991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.157515991
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3795566971
Short name T713
Test name
Test status
Simulation time 278020472 ps
CPU time 9.43 seconds
Started Apr 15 12:36:53 PM PDT 24
Finished Apr 15 12:37:03 PM PDT 24
Peak memory 251076 kb
Host smart-c6eee3eb-3903-4cee-8f41-b342129fb0f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3795566971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3795566971
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.571608489
Short name T19
Test name
Test status
Simulation time 56870722737 ps
CPU time 2385.22 seconds
Started Apr 15 01:10:42 PM PDT 24
Finished Apr 15 01:50:29 PM PDT 24
Peak memory 284948 kb
Host smart-84b6c9b9-0d95-4fcd-b8d8-df7040adf1af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571608489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.571608489
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1519045858
Short name T494
Test name
Test status
Simulation time 948712123 ps
CPU time 22.29 seconds
Started Apr 15 01:10:45 PM PDT 24
Finished Apr 15 01:11:08 PM PDT 24
Peak memory 240836 kb
Host smart-9265dfb5-60ca-4b2c-90d2-847acfdc0d67
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1519045858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1519045858
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.689804949
Short name T490
Test name
Test status
Simulation time 448740513 ps
CPU time 13.79 seconds
Started Apr 15 01:10:57 PM PDT 24
Finished Apr 15 01:11:11 PM PDT 24
Peak memory 254064 kb
Host smart-3c795a35-7f43-4e42-b2be-201e32deabdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68980
4949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.689804949
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2902104454
Short name T511
Test name
Test status
Simulation time 8128395599 ps
CPU time 52.31 seconds
Started Apr 15 01:10:48 PM PDT 24
Finished Apr 15 01:11:41 PM PDT 24
Peak memory 255828 kb
Host smart-276548bb-7b4a-4810-9da5-571c1c1e5278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29021
04454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2902104454
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1125919882
Short name T104
Test name
Test status
Simulation time 62504176089 ps
CPU time 1759.1 seconds
Started Apr 15 01:10:53 PM PDT 24
Finished Apr 15 01:40:13 PM PDT 24
Peak memory 271848 kb
Host smart-ec1bca7a-d40a-469d-b2a3-0056645dda4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125919882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1125919882
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.358917573
Short name T389
Test name
Test status
Simulation time 65696130460 ps
CPU time 1027.08 seconds
Started Apr 15 01:10:48 PM PDT 24
Finished Apr 15 01:27:55 PM PDT 24
Peak memory 273400 kb
Host smart-e715171a-f794-4207-8efd-9c5f987f7a04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358917573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.358917573
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3944020071
Short name T598
Test name
Test status
Simulation time 25298668823 ps
CPU time 258.89 seconds
Started Apr 15 01:11:03 PM PDT 24
Finished Apr 15 01:15:23 PM PDT 24
Peak memory 247952 kb
Host smart-86888758-9a86-4798-b6a5-09b40b3c3dfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944020071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3944020071
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3216288662
Short name T671
Test name
Test status
Simulation time 3310043024 ps
CPU time 16.84 seconds
Started Apr 15 01:10:57 PM PDT 24
Finished Apr 15 01:11:15 PM PDT 24
Peak memory 249196 kb
Host smart-b4fa55c1-6f5e-4564-b72c-b9ad17a2cf59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32162
88662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3216288662
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2279738609
Short name T20
Test name
Test status
Simulation time 131452550 ps
CPU time 14.13 seconds
Started Apr 15 01:10:45 PM PDT 24
Finished Apr 15 01:11:00 PM PDT 24
Peak memory 247436 kb
Host smart-fa6963e6-bff0-4a7a-a5a8-88d59cd3147a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22797
38609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2279738609
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1468810907
Short name T60
Test name
Test status
Simulation time 101762040 ps
CPU time 8.34 seconds
Started Apr 15 01:10:56 PM PDT 24
Finished Apr 15 01:11:05 PM PDT 24
Peak memory 247596 kb
Host smart-fd7748cb-666c-4c7a-8ad6-25456e1f3f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14688
10907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1468810907
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.609200544
Short name T660
Test name
Test status
Simulation time 1606403579 ps
CPU time 33.82 seconds
Started Apr 15 01:10:52 PM PDT 24
Finished Apr 15 01:11:26 PM PDT 24
Peak memory 249316 kb
Host smart-42eda768-17a6-4ef9-9f26-40c6d5fe0bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60920
0544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.609200544
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.703075967
Short name T247
Test name
Test status
Simulation time 13548342290 ps
CPU time 988.52 seconds
Started Apr 15 01:11:09 PM PDT 24
Finished Apr 15 01:27:39 PM PDT 24
Peak memory 284868 kb
Host smart-d5cdd2f0-859f-41da-9739-ec337b5596b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703075967 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.703075967
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2348801030
Short name T462
Test name
Test status
Simulation time 1411185505 ps
CPU time 17.16 seconds
Started Apr 15 01:10:55 PM PDT 24
Finished Apr 15 01:11:13 PM PDT 24
Peak memory 240848 kb
Host smart-ca353a89-169d-453b-b595-f41620ed7401
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2348801030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2348801030
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.4000365377
Short name T364
Test name
Test status
Simulation time 5869345950 ps
CPU time 134.95 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 01:13:27 PM PDT 24
Peak memory 256816 kb
Host smart-b6eb3fb0-3814-4ac8-80ba-a996349f64a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40003
65377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.4000365377
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.480193563
Short name T576
Test name
Test status
Simulation time 882573629 ps
CPU time 44.41 seconds
Started Apr 15 01:10:51 PM PDT 24
Finished Apr 15 01:11:36 PM PDT 24
Peak memory 255388 kb
Host smart-ed81891e-0efc-4db1-879b-2df7d09af58f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48019
3563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.480193563
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3595350049
Short name T228
Test name
Test status
Simulation time 460514743866 ps
CPU time 1719.59 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:39:41 PM PDT 24
Peak memory 282552 kb
Host smart-d0f7f324-82a9-4c3a-8a39-1e30fc435ce7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595350049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3595350049
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1438003235
Short name T328
Test name
Test status
Simulation time 11564253348 ps
CPU time 463.52 seconds
Started Apr 15 01:11:06 PM PDT 24
Finished Apr 15 01:18:50 PM PDT 24
Peak memory 248548 kb
Host smart-54ebc129-05d3-4f07-9756-3d9cef5417f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438003235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1438003235
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1837813286
Short name T657
Test name
Test status
Simulation time 644166271 ps
CPU time 36.08 seconds
Started Apr 15 01:11:08 PM PDT 24
Finished Apr 15 01:11:45 PM PDT 24
Peak memory 256296 kb
Host smart-1cce5a20-3f33-471c-bed5-c5ff5f7a2435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18378
13286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1837813286
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2746696971
Short name T427
Test name
Test status
Simulation time 48125138 ps
CPU time 4.56 seconds
Started Apr 15 01:11:01 PM PDT 24
Finished Apr 15 01:11:07 PM PDT 24
Peak memory 240500 kb
Host smart-25ddc3da-ba9e-4e8b-b124-5d387a73f00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27466
96971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2746696971
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3691910963
Short name T32
Test name
Test status
Simulation time 911465950 ps
CPU time 14.56 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 01:11:27 PM PDT 24
Peak memory 265692 kb
Host smart-a333c282-b331-4a5b-b84b-7318c6585d59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3691910963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3691910963
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3337376168
Short name T434
Test name
Test status
Simulation time 638490386 ps
CPU time 17.09 seconds
Started Apr 15 01:10:56 PM PDT 24
Finished Apr 15 01:11:14 PM PDT 24
Peak memory 247372 kb
Host smart-4c6d81d0-6223-4dad-af05-e211d6333293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33373
76168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3337376168
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3716826183
Short name T514
Test name
Test status
Simulation time 1087885150 ps
CPU time 20.85 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:11:22 PM PDT 24
Peak memory 249072 kb
Host smart-53221dd8-d496-4288-b00e-8446242a1043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37168
26183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3716826183
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.219547293
Short name T201
Test name
Test status
Simulation time 61669910 ps
CPU time 2.82 seconds
Started Apr 15 01:11:17 PM PDT 24
Finished Apr 15 01:11:21 PM PDT 24
Peak memory 249224 kb
Host smart-2a623e9b-d7ff-4012-904d-64e5dcf444f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=219547293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.219547293
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3329961428
Short name T216
Test name
Test status
Simulation time 33769315047 ps
CPU time 1168.15 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 01:30:41 PM PDT 24
Peak memory 272352 kb
Host smart-1ecbcc79-aac1-430c-bf2b-2168e763559f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329961428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3329961428
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2382245121
Short name T577
Test name
Test status
Simulation time 1137803546 ps
CPU time 47.09 seconds
Started Apr 15 01:11:19 PM PDT 24
Finished Apr 15 01:12:07 PM PDT 24
Peak memory 240796 kb
Host smart-72480b14-f453-4a48-b97b-188c250fc6bb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2382245121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2382245121
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3418306126
Short name T291
Test name
Test status
Simulation time 12256451661 ps
CPU time 182.99 seconds
Started Apr 15 01:11:18 PM PDT 24
Finished Apr 15 01:14:22 PM PDT 24
Peak memory 257364 kb
Host smart-f2bf7ffe-22fd-484e-b0d1-8975ce2d675a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34183
06126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3418306126
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3691028544
Short name T73
Test name
Test status
Simulation time 2864023179 ps
CPU time 27.25 seconds
Started Apr 15 01:11:07 PM PDT 24
Finished Apr 15 01:11:36 PM PDT 24
Peak memory 255624 kb
Host smart-c063ee73-6b50-4cd0-9831-56b7fd1a93bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36910
28544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3691028544
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2685820010
Short name T107
Test name
Test status
Simulation time 26443167399 ps
CPU time 1387.75 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 01:34:20 PM PDT 24
Peak memory 265572 kb
Host smart-7ac8ddca-224b-483e-b5c2-2078c6231290
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685820010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2685820010
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1012290943
Short name T515
Test name
Test status
Simulation time 61963076460 ps
CPU time 1187.08 seconds
Started Apr 15 01:11:22 PM PDT 24
Finished Apr 15 01:31:10 PM PDT 24
Peak memory 289536 kb
Host smart-3d10da30-c858-4a0c-b19c-ddd2d1bc3d9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012290943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1012290943
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2804596891
Short name T327
Test name
Test status
Simulation time 38648974965 ps
CPU time 391.55 seconds
Started Apr 15 01:11:12 PM PDT 24
Finished Apr 15 01:17:44 PM PDT 24
Peak memory 256136 kb
Host smart-dba1d54b-a176-49dc-bdad-0b3669ca7476
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804596891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2804596891
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3848464313
Short name T386
Test name
Test status
Simulation time 226116629 ps
CPU time 4.38 seconds
Started Apr 15 01:11:17 PM PDT 24
Finished Apr 15 01:11:23 PM PDT 24
Peak memory 240844 kb
Host smart-ddcf3a25-d99f-4045-91da-09881a0a60f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38484
64313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3848464313
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.125386434
Short name T696
Test name
Test status
Simulation time 966250830 ps
CPU time 45.81 seconds
Started Apr 15 01:11:18 PM PDT 24
Finished Apr 15 01:12:05 PM PDT 24
Peak memory 247896 kb
Host smart-f1fa3a67-15da-4dc9-93b4-03ef63b542c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12538
6434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.125386434
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2787090614
Short name T684
Test name
Test status
Simulation time 73334703 ps
CPU time 7.76 seconds
Started Apr 15 01:11:20 PM PDT 24
Finished Apr 15 01:11:29 PM PDT 24
Peak memory 249076 kb
Host smart-45b151e9-e0d4-421c-9a95-b7ef33ec568f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27870
90614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2787090614
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1480064899
Short name T387
Test name
Test status
Simulation time 638777868 ps
CPU time 21.25 seconds
Started Apr 15 01:11:18 PM PDT 24
Finished Apr 15 01:11:40 PM PDT 24
Peak memory 248936 kb
Host smart-e9dd5e6e-c4c3-4e62-9306-851cef344ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14800
64899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1480064899
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.216964151
Short name T278
Test name
Test status
Simulation time 2305528083 ps
CPU time 39.37 seconds
Started Apr 15 01:11:20 PM PDT 24
Finished Apr 15 01:12:00 PM PDT 24
Peak memory 255296 kb
Host smart-8336c466-1ec7-4cc6-863e-f5d7c5a5137b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216964151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.216964151
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.507273937
Short name T203
Test name
Test status
Simulation time 63668020 ps
CPU time 2.99 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 01:11:15 PM PDT 24
Peak memory 249344 kb
Host smart-13b29a9c-243d-4135-8a61-64b3269d3208
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=507273937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.507273937
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.654384879
Short name T580
Test name
Test status
Simulation time 15951363419 ps
CPU time 989.72 seconds
Started Apr 15 01:11:10 PM PDT 24
Finished Apr 15 01:27:41 PM PDT 24
Peak memory 265568 kb
Host smart-76f94bb5-bb00-4b8c-a90d-aa9ebd3c6970
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654384879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.654384879
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.282449818
Short name T466
Test name
Test status
Simulation time 8823953525 ps
CPU time 57.33 seconds
Started Apr 15 01:11:22 PM PDT 24
Finished Apr 15 01:12:20 PM PDT 24
Peak memory 240924 kb
Host smart-ab6aeb56-5105-483a-9027-bc6141668492
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=282449818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.282449818
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1667437523
Short name T431
Test name
Test status
Simulation time 2741520118 ps
CPU time 49.13 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 01:12:01 PM PDT 24
Peak memory 257348 kb
Host smart-101d9c12-4aae-487a-b186-ac78649bbd5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16674
37523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1667437523
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3631438302
Short name T64
Test name
Test status
Simulation time 4385825182 ps
CPU time 67.62 seconds
Started Apr 15 01:11:16 PM PDT 24
Finished Apr 15 01:12:25 PM PDT 24
Peak memory 255268 kb
Host smart-2ed2a924-0f98-41f0-8f33-5bbb305d57c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36314
38302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3631438302
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3660697629
Short name T647
Test name
Test status
Simulation time 15978499764 ps
CPU time 1477.5 seconds
Started Apr 15 01:11:21 PM PDT 24
Finished Apr 15 01:36:00 PM PDT 24
Peak memory 287048 kb
Host smart-bfed541a-5689-4a4a-bc62-b1c7627fdac4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660697629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3660697629
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.886112189
Short name T275
Test name
Test status
Simulation time 23309181749 ps
CPU time 1439.48 seconds
Started Apr 15 01:11:16 PM PDT 24
Finished Apr 15 01:35:17 PM PDT 24
Peak memory 273676 kb
Host smart-667ce9ae-725c-45d7-bb31-fd85815ea4c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886112189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.886112189
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1052976614
Short name T187
Test name
Test status
Simulation time 47285687054 ps
CPU time 407.05 seconds
Started Apr 15 01:11:10 PM PDT 24
Finished Apr 15 01:17:58 PM PDT 24
Peak memory 248224 kb
Host smart-70fcc5d3-7da3-4823-8c2e-2c85c80128e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052976614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1052976614
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1099567061
Short name T608
Test name
Test status
Simulation time 62107987 ps
CPU time 4.86 seconds
Started Apr 15 01:11:09 PM PDT 24
Finished Apr 15 01:11:15 PM PDT 24
Peak memory 240808 kb
Host smart-1726146e-a24b-4e04-a8c1-8141e0f82862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10995
67061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1099567061
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3945389532
Short name T18
Test name
Test status
Simulation time 2428921381 ps
CPU time 69.37 seconds
Started Apr 15 01:11:05 PM PDT 24
Finished Apr 15 01:12:15 PM PDT 24
Peak memory 255304 kb
Host smart-1f88d876-c234-4313-9ab9-c5564f1cc7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39453
89532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3945389532
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.653342305
Short name T468
Test name
Test status
Simulation time 988377640 ps
CPU time 13.02 seconds
Started Apr 15 01:11:06 PM PDT 24
Finished Apr 15 01:11:20 PM PDT 24
Peak memory 247472 kb
Host smart-a902b40f-8a6c-452a-8600-019750a49a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65334
2305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.653342305
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.891702933
Short name T112
Test name
Test status
Simulation time 1268436680 ps
CPU time 20.18 seconds
Started Apr 15 01:11:16 PM PDT 24
Finished Apr 15 01:11:38 PM PDT 24
Peak memory 255704 kb
Host smart-c1937e65-e34e-46e7-adfd-354708fc0dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89170
2933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.891702933
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3003537370
Short name T84
Test name
Test status
Simulation time 105246433921 ps
CPU time 2858.98 seconds
Started Apr 15 01:11:04 PM PDT 24
Finished Apr 15 01:58:44 PM PDT 24
Peak memory 288548 kb
Host smart-a14515bd-36a6-4db4-821b-2e7175e61291
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003537370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3003537370
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.28443675
Short name T204
Test name
Test status
Simulation time 175731908 ps
CPU time 3.62 seconds
Started Apr 15 01:11:17 PM PDT 24
Finished Apr 15 01:11:22 PM PDT 24
Peak memory 249272 kb
Host smart-dd7b2006-caec-4684-bd1d-f60363165bd9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=28443675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.28443675
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3536091811
Short name T42
Test name
Test status
Simulation time 81191488646 ps
CPU time 1189.2 seconds
Started Apr 15 01:11:14 PM PDT 24
Finished Apr 15 01:31:05 PM PDT 24
Peak memory 273744 kb
Host smart-119fd5d4-ac2e-436e-9d25-92af4e8d63d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536091811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3536091811
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2056020001
Short name T501
Test name
Test status
Simulation time 124717025 ps
CPU time 8.38 seconds
Started Apr 15 01:11:16 PM PDT 24
Finished Apr 15 01:11:26 PM PDT 24
Peak memory 240740 kb
Host smart-700a630c-4f9f-43df-ab52-4e9403c01acb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2056020001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2056020001
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3414652584
Short name T664
Test name
Test status
Simulation time 577267351 ps
CPU time 35.45 seconds
Started Apr 15 01:11:21 PM PDT 24
Finished Apr 15 01:11:58 PM PDT 24
Peak memory 248672 kb
Host smart-ecb025e1-7a7b-496a-b992-a57e08a22237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34146
52584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3414652584
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.900199016
Short name T599
Test name
Test status
Simulation time 552864742 ps
CPU time 20.58 seconds
Started Apr 15 01:11:17 PM PDT 24
Finished Apr 15 01:11:39 PM PDT 24
Peak memory 255684 kb
Host smart-00db5c9f-87db-4384-a735-f0015b4439ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90019
9016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.900199016
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3697365180
Short name T699
Test name
Test status
Simulation time 52934648699 ps
CPU time 2766.48 seconds
Started Apr 15 01:11:12 PM PDT 24
Finished Apr 15 01:57:20 PM PDT 24
Peak memory 289300 kb
Host smart-0e01eed1-3f5c-4dfc-948f-0ccd5e166cbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697365180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3697365180
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3509480903
Short name T607
Test name
Test status
Simulation time 24487062255 ps
CPU time 1322.04 seconds
Started Apr 15 01:11:19 PM PDT 24
Finished Apr 15 01:33:23 PM PDT 24
Peak memory 286692 kb
Host smart-c97382de-3c72-4554-a838-374b15ce9790
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509480903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3509480903
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2837981596
Short name T652
Test name
Test status
Simulation time 63380017014 ps
CPU time 400.6 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:17:56 PM PDT 24
Peak memory 248400 kb
Host smart-528c1723-3983-4c15-8942-b593c3159a05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837981596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2837981596
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2788195191
Short name T381
Test name
Test status
Simulation time 1390092172 ps
CPU time 38.97 seconds
Started Apr 15 01:11:18 PM PDT 24
Finished Apr 15 01:11:59 PM PDT 24
Peak memory 255980 kb
Host smart-d2a51bca-e7fd-475f-98a5-cdb7bad15fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27881
95191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2788195191
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.716576597
Short name T551
Test name
Test status
Simulation time 330440331 ps
CPU time 36.71 seconds
Started Apr 15 01:11:16 PM PDT 24
Finished Apr 15 01:11:54 PM PDT 24
Peak memory 247956 kb
Host smart-2b6790b0-ea90-4916-ac49-e84dde647a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71657
6597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.716576597
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2485894445
Short name T621
Test name
Test status
Simulation time 599364843 ps
CPU time 31.33 seconds
Started Apr 15 01:11:23 PM PDT 24
Finished Apr 15 01:11:55 PM PDT 24
Peak memory 249060 kb
Host smart-b4be3e85-d655-49ee-bfb8-7e3ad112d6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24858
94445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2485894445
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3940574677
Short name T368
Test name
Test status
Simulation time 762790270 ps
CPU time 11.5 seconds
Started Apr 15 01:11:40 PM PDT 24
Finished Apr 15 01:11:53 PM PDT 24
Peak memory 257096 kb
Host smart-ac1fee20-911b-4426-94b6-0009e2bb4ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39405
74677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3940574677
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3583652569
Short name T179
Test name
Test status
Simulation time 20315437937 ps
CPU time 1952.58 seconds
Started Apr 15 01:11:21 PM PDT 24
Finished Apr 15 01:43:55 PM PDT 24
Peak memory 300176 kb
Host smart-2bc0b0e4-58b8-4dc2-acee-1440d47f0ca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583652569 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3583652569
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2036332063
Short name T213
Test name
Test status
Simulation time 114320341 ps
CPU time 3.42 seconds
Started Apr 15 01:11:35 PM PDT 24
Finished Apr 15 01:11:40 PM PDT 24
Peak memory 249332 kb
Host smart-d162f4fa-57bc-4ef1-bb54-692fd18547ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2036332063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2036332063
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3214853870
Short name T457
Test name
Test status
Simulation time 46517410272 ps
CPU time 2550.83 seconds
Started Apr 15 01:11:16 PM PDT 24
Finished Apr 15 01:53:48 PM PDT 24
Peak memory 289300 kb
Host smart-dbeca16c-0edb-4506-9c86-4715497750fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214853870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3214853870
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1495849091
Short name T575
Test name
Test status
Simulation time 1127762976 ps
CPU time 15.99 seconds
Started Apr 15 01:11:19 PM PDT 24
Finished Apr 15 01:11:37 PM PDT 24
Peak memory 240824 kb
Host smart-ff5cc2ad-2063-408f-a23c-01ef82249cbf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1495849091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1495849091
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3129723314
Short name T276
Test name
Test status
Simulation time 1167963025 ps
CPU time 93.24 seconds
Started Apr 15 01:11:24 PM PDT 24
Finished Apr 15 01:12:57 PM PDT 24
Peak memory 257352 kb
Host smart-1fa6bf3e-6688-43ba-a227-8de2779cfa5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31297
23314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3129723314
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.4241454054
Short name T70
Test name
Test status
Simulation time 1164235182 ps
CPU time 10.37 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:11:25 PM PDT 24
Peak memory 248656 kb
Host smart-6a1feadf-eee4-488a-98da-947cefcbb6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42414
54054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.4241454054
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.131916831
Short name T331
Test name
Test status
Simulation time 19603495462 ps
CPU time 1286.02 seconds
Started Apr 15 01:11:19 PM PDT 24
Finished Apr 15 01:32:46 PM PDT 24
Peak memory 265532 kb
Host smart-078afbc1-f7ed-4234-bb57-97b0ceabb794
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131916831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.131916831
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3233486927
Short name T5
Test name
Test status
Simulation time 146550299690 ps
CPU time 2072.55 seconds
Started Apr 15 01:11:20 PM PDT 24
Finished Apr 15 01:45:54 PM PDT 24
Peak memory 286300 kb
Host smart-d9c17f6e-33d7-4a4b-a089-00c5302299cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233486927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3233486927
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3897486867
Short name T627
Test name
Test status
Simulation time 1870924709 ps
CPU time 75.64 seconds
Started Apr 15 01:11:17 PM PDT 24
Finished Apr 15 01:12:34 PM PDT 24
Peak memory 248044 kb
Host smart-9f4aea15-d5de-4ece-b536-51e6a4231188
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897486867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3897486867
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1458297828
Short name T614
Test name
Test status
Simulation time 5824510338 ps
CPU time 55.96 seconds
Started Apr 15 01:11:18 PM PDT 24
Finished Apr 15 01:12:15 PM PDT 24
Peak memory 256408 kb
Host smart-75e62c4e-961a-4e2a-9768-798143904718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14582
97828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1458297828
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.330026645
Short name T418
Test name
Test status
Simulation time 1002818201 ps
CPU time 36.18 seconds
Started Apr 15 01:11:15 PM PDT 24
Finished Apr 15 01:11:53 PM PDT 24
Peak memory 247396 kb
Host smart-c3768cfa-db3d-4e19-9fdf-630182c4f680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33002
6645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.330026645
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1545401954
Short name T52
Test name
Test status
Simulation time 466722720 ps
CPU time 27.74 seconds
Started Apr 15 01:11:17 PM PDT 24
Finished Apr 15 01:11:46 PM PDT 24
Peak memory 255992 kb
Host smart-3b5c360f-d411-41ac-88de-614465f3de6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15454
01954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1545401954
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2937900644
Short name T590
Test name
Test status
Simulation time 431998343 ps
CPU time 21.43 seconds
Started Apr 15 01:11:24 PM PDT 24
Finished Apr 15 01:11:46 PM PDT 24
Peak memory 256084 kb
Host smart-2af4aab8-03c4-4b26-bed8-c40c267f51b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29379
00644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2937900644
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1237917999
Short name T250
Test name
Test status
Simulation time 169497626388 ps
CPU time 2707.83 seconds
Started Apr 15 01:11:16 PM PDT 24
Finished Apr 15 01:56:26 PM PDT 24
Peak memory 305704 kb
Host smart-04f54841-2c50-475d-ac8d-51e58328f672
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237917999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1237917999
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3293805998
Short name T685
Test name
Test status
Simulation time 32794604189 ps
CPU time 677.96 seconds
Started Apr 15 01:11:12 PM PDT 24
Finished Apr 15 01:22:31 PM PDT 24
Peak memory 286260 kb
Host smart-ef263c95-239b-43fd-a6d6-d601e83c333e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293805998 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3293805998
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1298189548
Short name T96
Test name
Test status
Simulation time 49268017440 ps
CPU time 797.88 seconds
Started Apr 15 01:11:19 PM PDT 24
Finished Apr 15 01:24:38 PM PDT 24
Peak memory 266576 kb
Host smart-e0e44601-ff3e-4e08-b9fe-8fea466cd0e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298189548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1298189548
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2089025281
Short name T377
Test name
Test status
Simulation time 6561431714 ps
CPU time 195.35 seconds
Started Apr 15 01:11:22 PM PDT 24
Finished Apr 15 01:14:38 PM PDT 24
Peak memory 250164 kb
Host smart-44386963-5407-43b3-83e4-e3e5654351de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20890
25281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2089025281
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3822970381
Short name T545
Test name
Test status
Simulation time 1305363230 ps
CPU time 27.58 seconds
Started Apr 15 01:11:14 PM PDT 24
Finished Apr 15 01:11:43 PM PDT 24
Peak memory 255680 kb
Host smart-d628fd1e-bc36-4f9c-a618-1ece4629d921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38229
70381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3822970381
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.404225582
Short name T318
Test name
Test status
Simulation time 35425280602 ps
CPU time 1517.17 seconds
Started Apr 15 01:11:18 PM PDT 24
Finished Apr 15 01:36:37 PM PDT 24
Peak memory 272788 kb
Host smart-ec3abbc9-6056-4eb1-be01-b6a0a6bc3899
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404225582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.404225582
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3848099618
Short name T464
Test name
Test status
Simulation time 10508698631 ps
CPU time 1149.68 seconds
Started Apr 15 01:11:20 PM PDT 24
Finished Apr 15 01:30:31 PM PDT 24
Peak memory 281856 kb
Host smart-89bfb104-b353-4633-aa69-c0be061b4789
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848099618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3848099618
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.4167533152
Short name T404
Test name
Test status
Simulation time 767573465 ps
CPU time 53.73 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:12:08 PM PDT 24
Peak memory 256256 kb
Host smart-5b8ed88f-0d40-4f63-9f7f-6af5c561fded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41675
33152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.4167533152
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2620873137
Short name T265
Test name
Test status
Simulation time 378532983 ps
CPU time 13.44 seconds
Started Apr 15 01:11:25 PM PDT 24
Finished Apr 15 01:11:41 PM PDT 24
Peak memory 248780 kb
Host smart-960d2a8b-4711-437d-a502-25872d95a1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26208
73137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2620873137
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2909738039
Short name T267
Test name
Test status
Simulation time 150089046 ps
CPU time 19.68 seconds
Started Apr 15 01:11:15 PM PDT 24
Finished Apr 15 01:11:36 PM PDT 24
Peak memory 248928 kb
Host smart-eb68552c-f725-4130-8f41-982e2d982491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29097
38039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2909738039
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.731025790
Short name T272
Test name
Test status
Simulation time 365804202 ps
CPU time 28.5 seconds
Started Apr 15 01:11:20 PM PDT 24
Finished Apr 15 01:11:49 PM PDT 24
Peak memory 256236 kb
Host smart-561de001-88f2-4dd4-9e7a-ff09bc8a3f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73102
5790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.731025790
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1216097528
Short name T212
Test name
Test status
Simulation time 32271724 ps
CPU time 3.37 seconds
Started Apr 15 01:11:20 PM PDT 24
Finished Apr 15 01:11:25 PM PDT 24
Peak memory 249356 kb
Host smart-b5233032-8d38-468d-a30b-c890b1772a34
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1216097528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1216097528
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.380627615
Short name T283
Test name
Test status
Simulation time 31244890238 ps
CPU time 1763.05 seconds
Started Apr 15 01:11:19 PM PDT 24
Finished Apr 15 01:40:43 PM PDT 24
Peak memory 273136 kb
Host smart-3784ddb5-58ac-4385-9b5b-eb91ebca5278
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380627615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.380627615
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.469008102
Short name T708
Test name
Test status
Simulation time 1677996799 ps
CPU time 19.71 seconds
Started Apr 15 01:11:34 PM PDT 24
Finished Apr 15 01:11:55 PM PDT 24
Peak memory 240712 kb
Host smart-4615b6e3-588e-43be-a9be-17fdde431a9e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=469008102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.469008102
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3779818481
Short name T537
Test name
Test status
Simulation time 2654450469 ps
CPU time 157.93 seconds
Started Apr 15 01:11:10 PM PDT 24
Finished Apr 15 01:13:49 PM PDT 24
Peak memory 257076 kb
Host smart-679661d4-6696-4646-b03e-76bd302e9eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37798
18481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3779818481
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2543959028
Short name T571
Test name
Test status
Simulation time 663602534 ps
CPU time 42.5 seconds
Started Apr 15 01:11:16 PM PDT 24
Finished Apr 15 01:12:00 PM PDT 24
Peak memory 256104 kb
Host smart-e0cecbdc-76de-47da-ad2d-eb2a08dc8aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25439
59028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2543959028
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3169799726
Short name T535
Test name
Test status
Simulation time 14825851294 ps
CPU time 1165.75 seconds
Started Apr 15 01:11:21 PM PDT 24
Finished Apr 15 01:30:48 PM PDT 24
Peak memory 289504 kb
Host smart-f7d2c6f1-5a33-4e50-8b2b-bc69bebf9059
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169799726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3169799726
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2635400231
Short name T4
Test name
Test status
Simulation time 20381824330 ps
CPU time 1301.38 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:32:56 PM PDT 24
Peak memory 285276 kb
Host smart-7375f3bd-1515-48fe-a59d-569dcfb17eff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635400231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2635400231
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3918880535
Short name T227
Test name
Test status
Simulation time 5654918015 ps
CPU time 248.23 seconds
Started Apr 15 01:11:19 PM PDT 24
Finished Apr 15 01:15:28 PM PDT 24
Peak memory 248236 kb
Host smart-72678e6a-894d-405d-a89c-b72170810628
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918880535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3918880535
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3523174662
Short name T15
Test name
Test status
Simulation time 502563077 ps
CPU time 26.73 seconds
Started Apr 15 01:11:23 PM PDT 24
Finished Apr 15 01:11:50 PM PDT 24
Peak memory 249240 kb
Host smart-b1cf37bb-0710-4714-9b6d-58ca47ed6908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35231
74662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3523174662
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2211024966
Short name T453
Test name
Test status
Simulation time 965605739 ps
CPU time 34.04 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 01:11:46 PM PDT 24
Peak memory 255748 kb
Host smart-faf39c79-1b3f-485a-bbe0-442fbb41113a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22110
24966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2211024966
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2260238021
Short name T367
Test name
Test status
Simulation time 83937082 ps
CPU time 8.81 seconds
Started Apr 15 01:11:34 PM PDT 24
Finished Apr 15 01:11:43 PM PDT 24
Peak memory 255372 kb
Host smart-e04b09a1-c0ab-463c-a0d2-524724217b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22602
38021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2260238021
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1579479386
Short name T700
Test name
Test status
Simulation time 12410567939 ps
CPU time 52.15 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:12:07 PM PDT 24
Peak memory 249192 kb
Host smart-e0b56781-9788-40a6-8551-6c2437153fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15794
79386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1579479386
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1742250830
Short name T674
Test name
Test status
Simulation time 166362638978 ps
CPU time 2008.46 seconds
Started Apr 15 01:11:15 PM PDT 24
Finished Apr 15 01:44:45 PM PDT 24
Peak memory 290104 kb
Host smart-dee418f5-5977-454f-be69-e31f0fe96c9a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742250830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1742250830
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3284251131
Short name T202
Test name
Test status
Simulation time 37196221 ps
CPU time 2.99 seconds
Started Apr 15 01:11:21 PM PDT 24
Finished Apr 15 01:11:25 PM PDT 24
Peak memory 249352 kb
Host smart-bd2a3c32-2308-4ef0-96c4-890d678e735b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3284251131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3284251131
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2802308567
Short name T424
Test name
Test status
Simulation time 11881630780 ps
CPU time 1175.4 seconds
Started Apr 15 01:11:23 PM PDT 24
Finished Apr 15 01:30:59 PM PDT 24
Peak memory 284960 kb
Host smart-ec71c7b9-8205-4318-827c-f5b31b4ca460
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802308567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2802308567
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.620935097
Short name T518
Test name
Test status
Simulation time 308885318 ps
CPU time 16.27 seconds
Started Apr 15 01:11:25 PM PDT 24
Finished Apr 15 01:11:44 PM PDT 24
Peak memory 249048 kb
Host smart-05071d81-cfba-4fbd-aa9f-d9680bfb0ae9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=620935097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.620935097
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.597976673
Short name T410
Test name
Test status
Simulation time 656994763 ps
CPU time 5.25 seconds
Started Apr 15 01:11:20 PM PDT 24
Finished Apr 15 01:11:27 PM PDT 24
Peak memory 250900 kb
Host smart-d2b3d19c-a197-41c6-9cc5-8b0600399792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59797
6673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.597976673
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1133167190
Short name T643
Test name
Test status
Simulation time 1220245953 ps
CPU time 33.53 seconds
Started Apr 15 01:11:25 PM PDT 24
Finished Apr 15 01:12:01 PM PDT 24
Peak memory 255732 kb
Host smart-b34e00bf-9a12-49fc-9708-9c37850b2af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11331
67190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1133167190
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.621349482
Short name T420
Test name
Test status
Simulation time 238804379158 ps
CPU time 3052.78 seconds
Started Apr 15 01:11:35 PM PDT 24
Finished Apr 15 02:02:30 PM PDT 24
Peak memory 288984 kb
Host smart-d12f9489-45ca-425b-ac10-9077bd8c7cde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621349482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.621349482
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.4006472903
Short name T646
Test name
Test status
Simulation time 192442235 ps
CPU time 4.66 seconds
Started Apr 15 01:11:21 PM PDT 24
Finished Apr 15 01:11:26 PM PDT 24
Peak memory 240748 kb
Host smart-544c0603-f7bb-4635-ae9b-b2f204b90fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40064
72903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.4006472903
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2931273032
Short name T477
Test name
Test status
Simulation time 246125554 ps
CPU time 19.18 seconds
Started Apr 15 01:11:46 PM PDT 24
Finished Apr 15 01:12:07 PM PDT 24
Peak memory 253804 kb
Host smart-e2a5e508-5e43-40a3-b4ec-9c5f490bceb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29312
73032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2931273032
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1440730364
Short name T679
Test name
Test status
Simulation time 248415926 ps
CPU time 12.13 seconds
Started Apr 15 01:11:22 PM PDT 24
Finished Apr 15 01:11:35 PM PDT 24
Peak memory 251936 kb
Host smart-4b7758db-8187-47c8-a3da-6d6d760ff137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14407
30364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1440730364
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1976309214
Short name T488
Test name
Test status
Simulation time 198484728 ps
CPU time 10.56 seconds
Started Apr 15 01:11:41 PM PDT 24
Finished Apr 15 01:11:53 PM PDT 24
Peak memory 254292 kb
Host smart-dee45785-b74c-4b6e-b4a9-121cd4747fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19763
09214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1976309214
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1129544653
Short name T44
Test name
Test status
Simulation time 21916043102 ps
CPU time 1173.81 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:30:49 PM PDT 24
Peak memory 284732 kb
Host smart-e40e3cd1-dade-4242-bd77-5e0cd16f9716
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129544653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1129544653
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.143206931
Short name T45
Test name
Test status
Simulation time 38094013583 ps
CPU time 3888.29 seconds
Started Apr 15 01:11:34 PM PDT 24
Finished Apr 15 02:16:24 PM PDT 24
Peak memory 339312 kb
Host smart-1f0c30d6-32f2-4e0c-bcb5-35e05fa0aab4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143206931 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.143206931
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.826341322
Short name T465
Test name
Test status
Simulation time 51609938570 ps
CPU time 2045.06 seconds
Started Apr 15 01:11:22 PM PDT 24
Finished Apr 15 01:45:29 PM PDT 24
Peak memory 288948 kb
Host smart-db25da93-f869-4cd8-a27f-c1b995b2436d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826341322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.826341322
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.4208086866
Short name T234
Test name
Test status
Simulation time 168916841 ps
CPU time 9.54 seconds
Started Apr 15 01:11:23 PM PDT 24
Finished Apr 15 01:11:33 PM PDT 24
Peak memory 240864 kb
Host smart-9b34940c-fd0e-4a5c-94af-8edcfd2ba69f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4208086866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.4208086866
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2450846096
Short name T536
Test name
Test status
Simulation time 14832413767 ps
CPU time 237.53 seconds
Started Apr 15 01:11:20 PM PDT 24
Finished Apr 15 01:15:19 PM PDT 24
Peak memory 257364 kb
Host smart-14f9bc46-04e4-47a6-9579-0888e04a8661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24508
46096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2450846096
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3043416103
Short name T520
Test name
Test status
Simulation time 484971187 ps
CPU time 13.64 seconds
Started Apr 15 01:11:21 PM PDT 24
Finished Apr 15 01:11:36 PM PDT 24
Peak memory 248900 kb
Host smart-c138b70e-8f8e-4db5-a0e5-bdbb019101cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30434
16103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3043416103
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.49907795
Short name T585
Test name
Test status
Simulation time 69980571034 ps
CPU time 1671.93 seconds
Started Apr 15 01:11:23 PM PDT 24
Finished Apr 15 01:39:16 PM PDT 24
Peak memory 289404 kb
Host smart-cec4dbdc-e9f9-46f9-822f-06ad2d836321
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49907795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.49907795
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1508367247
Short name T655
Test name
Test status
Simulation time 22822321137 ps
CPU time 495.81 seconds
Started Apr 15 01:11:22 PM PDT 24
Finished Apr 15 01:19:39 PM PDT 24
Peak memory 248236 kb
Host smart-61c37f73-2ab6-43b9-bc90-2ca1cf1ce64a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508367247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1508367247
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3105741226
Short name T491
Test name
Test status
Simulation time 1037081190 ps
CPU time 54.07 seconds
Started Apr 15 01:11:20 PM PDT 24
Finished Apr 15 01:12:15 PM PDT 24
Peak memory 249036 kb
Host smart-c44ad1a2-021e-4f44-93e2-6de5af4c9b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31057
41226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3105741226
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2525230992
Short name T661
Test name
Test status
Simulation time 241968628 ps
CPU time 13.83 seconds
Started Apr 15 01:11:17 PM PDT 24
Finished Apr 15 01:11:32 PM PDT 24
Peak memory 253120 kb
Host smart-6f618b4b-6816-4ea6-b28b-2f7ffb6edeee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25252
30992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2525230992
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2380466442
Short name T221
Test name
Test status
Simulation time 44565726 ps
CPU time 3.56 seconds
Started Apr 15 01:11:35 PM PDT 24
Finished Apr 15 01:11:40 PM PDT 24
Peak memory 239404 kb
Host smart-8ea99f04-9b82-4fe2-9fb8-d922cb3ede87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23804
66442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2380466442
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4065276335
Short name T553
Test name
Test status
Simulation time 609231692 ps
CPU time 9.49 seconds
Started Apr 15 01:11:26 PM PDT 24
Finished Apr 15 01:11:37 PM PDT 24
Peak memory 240576 kb
Host smart-a61a7bb0-fad8-4190-aa5b-b71f4569b3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40652
76335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4065276335
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1725601865
Short name T197
Test name
Test status
Simulation time 25353759 ps
CPU time 2.34 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:11:17 PM PDT 24
Peak memory 249368 kb
Host smart-75aa4298-1594-4c41-885c-e5ec653f80cd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1725601865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1725601865
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3265006508
Short name T287
Test name
Test status
Simulation time 145135167354 ps
CPU time 1995.45 seconds
Started Apr 15 01:11:18 PM PDT 24
Finished Apr 15 01:44:35 PM PDT 24
Peak memory 269728 kb
Host smart-f1fd47b4-d6ce-4f1f-9916-b053446acd52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265006508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3265006508
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.401732965
Short name T706
Test name
Test status
Simulation time 171666170 ps
CPU time 10.42 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:11:25 PM PDT 24
Peak memory 249028 kb
Host smart-5278604c-6212-409b-84a9-dd054e899887
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=401732965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.401732965
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2240628567
Short name T602
Test name
Test status
Simulation time 6465111082 ps
CPU time 97.82 seconds
Started Apr 15 01:11:16 PM PDT 24
Finished Apr 15 01:12:56 PM PDT 24
Peak memory 256936 kb
Host smart-7977e965-cdc6-4379-9230-32b587879b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22406
28567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2240628567
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1533273267
Short name T229
Test name
Test status
Simulation time 314854020 ps
CPU time 20.91 seconds
Started Apr 15 01:11:26 PM PDT 24
Finished Apr 15 01:11:49 PM PDT 24
Peak memory 256052 kb
Host smart-eaea96ca-1247-4f90-9f92-77103e5aead5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15332
73267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1533273267
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.4026970518
Short name T336
Test name
Test status
Simulation time 27452528087 ps
CPU time 1164.17 seconds
Started Apr 15 01:11:23 PM PDT 24
Finished Apr 15 01:30:48 PM PDT 24
Peak memory 265372 kb
Host smart-1cab17d6-373d-414f-a9ed-8a4d50c6bea0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026970518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4026970518
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2993610664
Short name T29
Test name
Test status
Simulation time 32118297068 ps
CPU time 2072.61 seconds
Started Apr 15 01:11:37 PM PDT 24
Finished Apr 15 01:46:11 PM PDT 24
Peak memory 288384 kb
Host smart-31237f8c-1dc6-43f7-93fe-ddd140c80b79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993610664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2993610664
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.69057093
Short name T321
Test name
Test status
Simulation time 6924022526 ps
CPU time 140.48 seconds
Started Apr 15 01:11:34 PM PDT 24
Finished Apr 15 01:13:56 PM PDT 24
Peak memory 253480 kb
Host smart-5b75b9fb-8820-4bf0-bbc7-0847c47270b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69057093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.69057093
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2944609461
Short name T268
Test name
Test status
Simulation time 156809460 ps
CPU time 7.12 seconds
Started Apr 15 01:11:45 PM PDT 24
Finished Apr 15 01:11:54 PM PDT 24
Peak memory 249076 kb
Host smart-c96fb8ca-67ec-4134-9de2-0c3e9894996e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29446
09461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2944609461
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1603067369
Short name T51
Test name
Test status
Simulation time 536306707 ps
CPU time 29.37 seconds
Started Apr 15 01:11:15 PM PDT 24
Finished Apr 15 01:11:46 PM PDT 24
Peak memory 249060 kb
Host smart-f9f35cb5-7c1e-4dee-91dd-d4cf31d3a200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16030
67369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1603067369
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1837300194
Short name T98
Test name
Test status
Simulation time 938992375 ps
CPU time 28.33 seconds
Started Apr 15 01:11:18 PM PDT 24
Finished Apr 15 01:11:48 PM PDT 24
Peak memory 249032 kb
Host smart-d71aae2f-12f4-4536-8c53-2f4d1ef67e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18373
00194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1837300194
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1524536667
Short name T415
Test name
Test status
Simulation time 893678278 ps
CPU time 19.24 seconds
Started Apr 15 01:11:20 PM PDT 24
Finished Apr 15 01:11:41 PM PDT 24
Peak memory 256216 kb
Host smart-03519564-4a95-48d4-ab71-75c3dc5b2413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15245
36667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1524536667
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2101995218
Short name T17
Test name
Test status
Simulation time 42486043367 ps
CPU time 2122.78 seconds
Started Apr 15 01:11:18 PM PDT 24
Finished Apr 15 01:46:42 PM PDT 24
Peak memory 289752 kb
Host smart-497563ce-78b6-4178-b4e5-701ffde8e954
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101995218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2101995218
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1271099279
Short name T111
Test name
Test status
Simulation time 27589209 ps
CPU time 2.51 seconds
Started Apr 15 01:11:26 PM PDT 24
Finished Apr 15 01:11:30 PM PDT 24
Peak memory 249336 kb
Host smart-af5ab1de-8feb-4c4b-9b9a-9a0b41a29db6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1271099279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1271099279
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3570444718
Short name T548
Test name
Test status
Simulation time 14800534546 ps
CPU time 1337.62 seconds
Started Apr 15 01:11:17 PM PDT 24
Finished Apr 15 01:33:36 PM PDT 24
Peak memory 281896 kb
Host smart-ba583e53-2b15-40ae-9aff-bc34df418811
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570444718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3570444718
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2276064624
Short name T540
Test name
Test status
Simulation time 276216948 ps
CPU time 14.63 seconds
Started Apr 15 01:11:22 PM PDT 24
Finished Apr 15 01:11:38 PM PDT 24
Peak memory 252764 kb
Host smart-e7c6c7dc-c654-44b3-927d-576a6eafcc67
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2276064624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2276064624
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.845585196
Short name T446
Test name
Test status
Simulation time 1647442944 ps
CPU time 93.63 seconds
Started Apr 15 01:11:25 PM PDT 24
Finished Apr 15 01:13:02 PM PDT 24
Peak memory 256916 kb
Host smart-a7402a15-969c-4dd2-8e30-29e0e8435430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84558
5196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.845585196
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2552435630
Short name T654
Test name
Test status
Simulation time 2460842550 ps
CPU time 48.74 seconds
Started Apr 15 01:11:35 PM PDT 24
Finished Apr 15 01:12:25 PM PDT 24
Peak memory 249116 kb
Host smart-5a5306f7-4010-4b8e-bc6e-53c47ebb22f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25524
35630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2552435630
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1285859321
Short name T617
Test name
Test status
Simulation time 49210002236 ps
CPU time 1075.54 seconds
Started Apr 15 01:11:15 PM PDT 24
Finished Apr 15 01:29:12 PM PDT 24
Peak memory 273028 kb
Host smart-5cc8178d-839b-492f-a7fd-441bf6e9213a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285859321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1285859321
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.644666159
Short name T324
Test name
Test status
Simulation time 21532344004 ps
CPU time 201.82 seconds
Started Apr 15 01:11:22 PM PDT 24
Finished Apr 15 01:14:45 PM PDT 24
Peak memory 248376 kb
Host smart-68ca8d66-5ddf-4297-998d-becebc0406f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644666159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.644666159
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.4207155686
Short name T642
Test name
Test status
Simulation time 7358312211 ps
CPU time 48.8 seconds
Started Apr 15 01:11:19 PM PDT 24
Finished Apr 15 01:12:09 PM PDT 24
Peak memory 256460 kb
Host smart-d06cda08-9ec3-4c59-a07d-c97ec25dd2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42071
55686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.4207155686
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1191543083
Short name T704
Test name
Test status
Simulation time 3454758443 ps
CPU time 56.85 seconds
Started Apr 15 01:11:24 PM PDT 24
Finished Apr 15 01:12:22 PM PDT 24
Peak memory 255244 kb
Host smart-74943252-1bd9-4dfc-b1f6-811ba6d2c962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11915
43083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1191543083
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2547943050
Short name T499
Test name
Test status
Simulation time 1196724035 ps
CPU time 20.02 seconds
Started Apr 15 01:11:25 PM PDT 24
Finished Apr 15 01:11:48 PM PDT 24
Peak memory 255028 kb
Host smart-fc219ea9-39f6-4ea7-be24-497e1b5d0839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25479
43050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2547943050
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.739751822
Short name T569
Test name
Test status
Simulation time 1545927597 ps
CPU time 30.93 seconds
Started Apr 15 01:11:19 PM PDT 24
Finished Apr 15 01:11:52 PM PDT 24
Peak memory 249044 kb
Host smart-34f2bc8b-cfe8-42a6-889e-12d75ef72180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73975
1822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.739751822
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1921761372
Short name T260
Test name
Test status
Simulation time 43779307153 ps
CPU time 2461.91 seconds
Started Apr 15 01:11:34 PM PDT 24
Finished Apr 15 01:52:37 PM PDT 24
Peak memory 289752 kb
Host smart-7a017bd4-e475-4710-9f25-1a2521c4dcef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921761372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1921761372
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.4116776031
Short name T199
Test name
Test status
Simulation time 529050139 ps
CPU time 3.87 seconds
Started Apr 15 01:10:57 PM PDT 24
Finished Apr 15 01:11:01 PM PDT 24
Peak memory 249292 kb
Host smart-7d7ca10c-b502-43ea-89ae-ca2030a33ad5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4116776031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.4116776031
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1946421966
Short name T538
Test name
Test status
Simulation time 531489204650 ps
CPU time 1675.71 seconds
Started Apr 15 01:10:59 PM PDT 24
Finished Apr 15 01:38:55 PM PDT 24
Peak memory 273728 kb
Host smart-720103a1-c89d-42db-8729-7500176fa6fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946421966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1946421966
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2126959296
Short name T425
Test name
Test status
Simulation time 487212790 ps
CPU time 24.27 seconds
Started Apr 15 01:10:56 PM PDT 24
Finished Apr 15 01:11:21 PM PDT 24
Peak memory 249020 kb
Host smart-35d9d4fa-2201-4a85-aa92-63bfb9fd7ae0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2126959296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2126959296
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.696315813
Short name T574
Test name
Test status
Simulation time 1733742118 ps
CPU time 127.06 seconds
Started Apr 15 01:11:04 PM PDT 24
Finished Apr 15 01:13:12 PM PDT 24
Peak memory 248708 kb
Host smart-1c48741c-6a0c-4b7b-bf34-3be8fa7fc59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69631
5813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.696315813
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2752007863
Short name T423
Test name
Test status
Simulation time 1179345436 ps
CPU time 37.27 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 01:11:49 PM PDT 24
Peak memory 255088 kb
Host smart-1ebb6073-a177-4fe2-bac3-f3509925937a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27520
07863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2752007863
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1686226618
Short name T54
Test name
Test status
Simulation time 1877530282 ps
CPU time 36.14 seconds
Started Apr 15 01:11:02 PM PDT 24
Finished Apr 15 01:11:40 PM PDT 24
Peak memory 256008 kb
Host smart-59d640b6-f2da-4178-9f85-1c469bc77d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16862
26618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1686226618
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1187243313
Short name T615
Test name
Test status
Simulation time 2152708956 ps
CPU time 33.34 seconds
Started Apr 15 01:10:59 PM PDT 24
Finished Apr 15 01:11:34 PM PDT 24
Peak memory 256252 kb
Host smart-fcf2e080-6e5b-418f-86ca-5413390e8855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11872
43313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1187243313
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3373752835
Short name T11
Test name
Test status
Simulation time 672196109 ps
CPU time 11.15 seconds
Started Apr 15 01:10:58 PM PDT 24
Finished Apr 15 01:11:10 PM PDT 24
Peak memory 265912 kb
Host smart-42689ac8-eeac-4d47-a1b3-cb764eb8b065
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3373752835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3373752835
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1417394981
Short name T665
Test name
Test status
Simulation time 2892806476 ps
CPU time 47.58 seconds
Started Apr 15 01:11:14 PM PDT 24
Finished Apr 15 01:12:03 PM PDT 24
Peak memory 256572 kb
Host smart-a1771acc-9e25-42c4-bc14-c087d247983d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14173
94981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1417394981
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2840065766
Short name T623
Test name
Test status
Simulation time 723044286 ps
CPU time 4.57 seconds
Started Apr 15 01:11:14 PM PDT 24
Finished Apr 15 01:11:20 PM PDT 24
Peak memory 240852 kb
Host smart-7b1ce932-5dc0-4683-af1c-23220fb1f5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28400
65766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2840065766
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.194769371
Short name T618
Test name
Test status
Simulation time 151642141 ps
CPU time 6.82 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 01:11:19 PM PDT 24
Peak memory 253092 kb
Host smart-34b76dc5-6a45-44c4-a8ca-fac3043d792d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194769371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.194769371
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3248201281
Short name T56
Test name
Test status
Simulation time 31325146505 ps
CPU time 915 seconds
Started Apr 15 01:11:26 PM PDT 24
Finished Apr 15 01:26:43 PM PDT 24
Peak memory 281928 kb
Host smart-e9c5d99a-6aab-45e8-a968-eb6b08c8116e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248201281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3248201281
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3685972980
Short name T549
Test name
Test status
Simulation time 663320815 ps
CPU time 40.71 seconds
Started Apr 15 01:11:36 PM PDT 24
Finished Apr 15 01:12:18 PM PDT 24
Peak memory 256332 kb
Host smart-ece76628-0698-4cfa-a231-feeaa3f2f02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859
72980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3685972980
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3536585954
Short name T297
Test name
Test status
Simulation time 552892528 ps
CPU time 43.7 seconds
Started Apr 15 01:11:18 PM PDT 24
Finished Apr 15 01:12:03 PM PDT 24
Peak memory 248020 kb
Host smart-24afdd33-f6b6-485a-af73-bdb200c525e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35365
85954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3536585954
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1147927595
Short name T344
Test name
Test status
Simulation time 58581325034 ps
CPU time 2902.95 seconds
Started Apr 15 01:11:44 PM PDT 24
Finished Apr 15 02:00:09 PM PDT 24
Peak memory 290120 kb
Host smart-ec7a7f52-4d64-4542-888a-3a08c5a3b4f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147927595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1147927595
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2218073486
Short name T688
Test name
Test status
Simulation time 127822388379 ps
CPU time 1844.83 seconds
Started Apr 15 01:11:24 PM PDT 24
Finished Apr 15 01:42:09 PM PDT 24
Peak memory 285508 kb
Host smart-b74e78e9-3563-4438-afe8-4f44742beba3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218073486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2218073486
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.62060866
Short name T307
Test name
Test status
Simulation time 20499685535 ps
CPU time 233.22 seconds
Started Apr 15 01:11:28 PM PDT 24
Finished Apr 15 01:15:22 PM PDT 24
Peak memory 247560 kb
Host smart-7301e629-87a5-4cfb-9ddd-15444c31ac5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62060866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.62060866
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.411466434
Short name T366
Test name
Test status
Simulation time 959026328 ps
CPU time 11.95 seconds
Started Apr 15 01:11:21 PM PDT 24
Finished Apr 15 01:11:34 PM PDT 24
Peak memory 249036 kb
Host smart-6d714dd7-5b7d-4e3b-aad1-c71beb47119f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41146
6434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.411466434
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1477295812
Short name T273
Test name
Test status
Simulation time 463484275 ps
CPU time 9.77 seconds
Started Apr 15 01:11:42 PM PDT 24
Finished Apr 15 01:11:54 PM PDT 24
Peak memory 252292 kb
Host smart-72aca17f-7f28-4ece-a810-2b5563b5988e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14772
95812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1477295812
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1155606565
Short name T185
Test name
Test status
Simulation time 1027251046 ps
CPU time 31.23 seconds
Started Apr 15 01:11:25 PM PDT 24
Finished Apr 15 01:11:58 PM PDT 24
Peak memory 256084 kb
Host smart-62bd4469-8e37-4e8f-bc3b-ae05c3d7a6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11556
06565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1155606565
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2727286829
Short name T467
Test name
Test status
Simulation time 1281401317 ps
CPU time 19.69 seconds
Started Apr 15 01:11:39 PM PDT 24
Finished Apr 15 01:12:00 PM PDT 24
Peak memory 249052 kb
Host smart-bc511cc8-788a-448e-86ca-57b12b52e3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27272
86829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2727286829
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.886235802
Short name T541
Test name
Test status
Simulation time 2672097488 ps
CPU time 75.1 seconds
Started Apr 15 01:11:26 PM PDT 24
Finished Apr 15 01:12:43 PM PDT 24
Peak memory 257364 kb
Host smart-6c341b54-1676-46e5-b621-1e20ebe9fee3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886235802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.886235802
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2742690279
Short name T401
Test name
Test status
Simulation time 1817502615 ps
CPU time 191.56 seconds
Started Apr 15 01:11:20 PM PDT 24
Finished Apr 15 01:14:33 PM PDT 24
Peak memory 256840 kb
Host smart-7ad2688c-db90-4009-a3b7-15596155feb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27426
90279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2742690279
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1624289247
Short name T606
Test name
Test status
Simulation time 616984094 ps
CPU time 40.43 seconds
Started Apr 15 01:11:26 PM PDT 24
Finished Apr 15 01:12:08 PM PDT 24
Peak memory 255492 kb
Host smart-2d93f64c-200d-4949-bf0f-11a4d42cb939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16242
89247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1624289247
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.684192339
Short name T332
Test name
Test status
Simulation time 15510652171 ps
CPU time 1064.42 seconds
Started Apr 15 01:11:42 PM PDT 24
Finished Apr 15 01:29:28 PM PDT 24
Peak memory 283288 kb
Host smart-f040dada-5d4e-4fe5-9129-cafdd5f4f7be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684192339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.684192339
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2045647189
Short name T649
Test name
Test status
Simulation time 5702676182 ps
CPU time 582.95 seconds
Started Apr 15 01:11:25 PM PDT 24
Finished Apr 15 01:21:11 PM PDT 24
Peak memory 272624 kb
Host smart-32f73c64-e88d-4187-8a88-bede48e65a7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045647189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2045647189
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2414309621
Short name T620
Test name
Test status
Simulation time 16465117331 ps
CPU time 642.97 seconds
Started Apr 15 01:11:17 PM PDT 24
Finished Apr 15 01:22:02 PM PDT 24
Peak memory 248300 kb
Host smart-e43005b0-1177-4d1b-94b0-c52cabb9ef7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414309621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2414309621
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3896417340
Short name T55
Test name
Test status
Simulation time 4570631728 ps
CPU time 32.34 seconds
Started Apr 15 01:11:31 PM PDT 24
Finished Apr 15 01:12:04 PM PDT 24
Peak memory 249036 kb
Host smart-e938bb42-c8b6-41d6-8291-c69e1767c400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38964
17340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3896417340
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2043818208
Short name T81
Test name
Test status
Simulation time 1003128390 ps
CPU time 14.85 seconds
Started Apr 15 01:11:29 PM PDT 24
Finished Apr 15 01:11:44 PM PDT 24
Peak memory 248692 kb
Host smart-759ec1f5-a4af-4f5b-9d29-c98eb304aaea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20438
18208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2043818208
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.114010762
Short name T305
Test name
Test status
Simulation time 2106537860 ps
CPU time 39.92 seconds
Started Apr 15 01:11:46 PM PDT 24
Finished Apr 15 01:12:28 PM PDT 24
Peak memory 255604 kb
Host smart-c5dfdb41-3d15-4803-858c-c320fc2e9c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11401
0762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.114010762
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.4255622078
Short name T71
Test name
Test status
Simulation time 484486178 ps
CPU time 30.19 seconds
Started Apr 15 01:11:36 PM PDT 24
Finished Apr 15 01:12:07 PM PDT 24
Peak memory 249012 kb
Host smart-a7d891fe-a87d-48b0-9cd8-f7d0e553709f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42556
22078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.4255622078
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.420418250
Short name T178
Test name
Test status
Simulation time 20056960636 ps
CPU time 649.81 seconds
Started Apr 15 01:11:32 PM PDT 24
Finished Apr 15 01:22:23 PM PDT 24
Peak memory 273816 kb
Host smart-c8fb0565-c14d-45ca-a418-7e4e62137503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420418250 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.420418250
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3314440728
Short name T452
Test name
Test status
Simulation time 162293178836 ps
CPU time 2313.42 seconds
Started Apr 15 01:11:24 PM PDT 24
Finished Apr 15 01:49:59 PM PDT 24
Peak memory 273708 kb
Host smart-da25e5bb-50ee-46b8-9ec8-ed15bc977391
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314440728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3314440728
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1425864647
Short name T496
Test name
Test status
Simulation time 1942884961 ps
CPU time 107.53 seconds
Started Apr 15 01:11:23 PM PDT 24
Finished Apr 15 01:13:12 PM PDT 24
Peak memory 256772 kb
Host smart-0d2077e4-f036-483f-a946-abe50b155cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14258
64647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1425864647
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3934158220
Short name T298
Test name
Test status
Simulation time 1012206733 ps
CPU time 12.01 seconds
Started Apr 15 01:11:25 PM PDT 24
Finished Apr 15 01:11:40 PM PDT 24
Peak memory 250948 kb
Host smart-9bac2bdf-e39e-4eef-8b61-fbfd20bb838e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39341
58220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3934158220
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2264669369
Short name T302
Test name
Test status
Simulation time 26982508298 ps
CPU time 1614.97 seconds
Started Apr 15 01:11:40 PM PDT 24
Finished Apr 15 01:38:37 PM PDT 24
Peak memory 272048 kb
Host smart-fe4e51c4-990c-40a3-b4b1-55ef8efd8f1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264669369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2264669369
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1042359371
Short name T479
Test name
Test status
Simulation time 16068534545 ps
CPU time 982.03 seconds
Started Apr 15 01:11:25 PM PDT 24
Finished Apr 15 01:27:50 PM PDT 24
Peak memory 273004 kb
Host smart-81e163f0-2922-41f0-9877-3af95f68930a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042359371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1042359371
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1138940836
Short name T303
Test name
Test status
Simulation time 27243558398 ps
CPU time 598.28 seconds
Started Apr 15 01:11:22 PM PDT 24
Finished Apr 15 01:21:21 PM PDT 24
Peak memory 254900 kb
Host smart-2f45e14f-9edb-4e05-ab12-0e26c29a5953
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138940836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1138940836
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.258581362
Short name T40
Test name
Test status
Simulation time 232402739 ps
CPU time 21.8 seconds
Started Apr 15 01:11:30 PM PDT 24
Finished Apr 15 01:11:53 PM PDT 24
Peak memory 249068 kb
Host smart-987bbcdf-b72d-4112-a692-4b964ca94aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25858
1362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.258581362
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3996625546
Short name T681
Test name
Test status
Simulation time 1191163020 ps
CPU time 28 seconds
Started Apr 15 01:11:34 PM PDT 24
Finished Apr 15 01:12:03 PM PDT 24
Peak memory 255780 kb
Host smart-64f3d698-1665-410c-a1df-3a03c1c68f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39966
25546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3996625546
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2448875712
Short name T379
Test name
Test status
Simulation time 294150407 ps
CPU time 5.86 seconds
Started Apr 15 01:11:34 PM PDT 24
Finished Apr 15 01:11:40 PM PDT 24
Peak memory 240736 kb
Host smart-dac663d9-eaa5-4c72-9378-d3b62dd53cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24488
75712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2448875712
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4008277366
Short name T533
Test name
Test status
Simulation time 5969178463 ps
CPU time 48.34 seconds
Started Apr 15 01:11:20 PM PDT 24
Finished Apr 15 01:12:10 PM PDT 24
Peak memory 249180 kb
Host smart-2758969d-431b-4979-847d-3078367321d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40082
77366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4008277366
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2987630186
Short name T682
Test name
Test status
Simulation time 186712508024 ps
CPU time 2730.76 seconds
Started Apr 15 01:11:38 PM PDT 24
Finished Apr 15 01:57:11 PM PDT 24
Peak memory 288384 kb
Host smart-5da3cd78-8f34-4ce3-b706-bdd80d9446f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987630186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2987630186
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2368299940
Short name T94
Test name
Test status
Simulation time 75539519267 ps
CPU time 983.11 seconds
Started Apr 15 01:11:39 PM PDT 24
Finished Apr 15 01:28:04 PM PDT 24
Peak memory 272364 kb
Host smart-6bbb30f8-69be-4ce3-b444-d53a94c9a175
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368299940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2368299940
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.121266274
Short name T505
Test name
Test status
Simulation time 1330378644 ps
CPU time 114.46 seconds
Started Apr 15 01:11:25 PM PDT 24
Finished Apr 15 01:13:22 PM PDT 24
Peak memory 256784 kb
Host smart-b0cc24c5-9a31-4d65-ac43-68a0c45736be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12126
6274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.121266274
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4245328779
Short name T644
Test name
Test status
Simulation time 1067460307 ps
CPU time 57.1 seconds
Started Apr 15 01:11:40 PM PDT 24
Finished Apr 15 01:12:39 PM PDT 24
Peak memory 255972 kb
Host smart-05c196e9-3a8e-4872-b334-4a49f8aef536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42453
28779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4245328779
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2604782358
Short name T38
Test name
Test status
Simulation time 164508125886 ps
CPU time 1805.13 seconds
Started Apr 15 01:11:38 PM PDT 24
Finished Apr 15 01:41:44 PM PDT 24
Peak memory 282140 kb
Host smart-d861283f-d8c3-43db-add4-1334bb4a8208
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604782358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2604782358
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3399915159
Short name T634
Test name
Test status
Simulation time 41603695947 ps
CPU time 2431.83 seconds
Started Apr 15 01:11:23 PM PDT 24
Finished Apr 15 01:51:56 PM PDT 24
Peak memory 290016 kb
Host smart-e461eae9-7488-4582-b956-9b4d327420c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399915159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3399915159
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1547578104
Short name T633
Test name
Test status
Simulation time 40316957608 ps
CPU time 299.75 seconds
Started Apr 15 01:11:39 PM PDT 24
Finished Apr 15 01:16:41 PM PDT 24
Peak memory 248076 kb
Host smart-621e1f27-14f2-4286-b60f-e5af62cdbf6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547578104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1547578104
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.110899365
Short name T640
Test name
Test status
Simulation time 877540498 ps
CPU time 19.82 seconds
Started Apr 15 01:11:27 PM PDT 24
Finished Apr 15 01:11:48 PM PDT 24
Peak memory 257396 kb
Host smart-c40fbecf-622e-4d25-88d9-c3bda7b54850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11089
9365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.110899365
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1034263390
Short name T567
Test name
Test status
Simulation time 126792573 ps
CPU time 8.74 seconds
Started Apr 15 01:11:43 PM PDT 24
Finished Apr 15 01:11:53 PM PDT 24
Peak memory 249792 kb
Host smart-802450bf-78f5-4a6d-9b74-05c2e5dd1cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10342
63390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1034263390
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2340469702
Short name T259
Test name
Test status
Simulation time 1046238821 ps
CPU time 21.71 seconds
Started Apr 15 01:11:38 PM PDT 24
Finished Apr 15 01:12:01 PM PDT 24
Peak memory 255632 kb
Host smart-5b65e524-33fa-4f27-b4ab-538f6d28115d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23404
69702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2340469702
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1000592246
Short name T563
Test name
Test status
Simulation time 274500307 ps
CPU time 29.3 seconds
Started Apr 15 01:11:43 PM PDT 24
Finished Apr 15 01:12:14 PM PDT 24
Peak memory 255764 kb
Host smart-7d24e275-6718-4275-b045-852f43179f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10005
92246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1000592246
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1000051998
Short name T255
Test name
Test status
Simulation time 196119770007 ps
CPU time 2521 seconds
Started Apr 15 01:11:43 PM PDT 24
Finished Apr 15 01:53:46 PM PDT 24
Peak memory 289732 kb
Host smart-d223374d-7163-48c5-a722-13d9a625c123
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000051998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1000051998
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1907476632
Short name T631
Test name
Test status
Simulation time 133049165926 ps
CPU time 2789.58 seconds
Started Apr 15 01:11:39 PM PDT 24
Finished Apr 15 01:58:11 PM PDT 24
Peak memory 281928 kb
Host smart-a0a93b44-3851-44b4-aa82-9694a3c54d1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907476632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1907476632
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.830156142
Short name T639
Test name
Test status
Simulation time 7889021016 ps
CPU time 227.94 seconds
Started Apr 15 01:11:39 PM PDT 24
Finished Apr 15 01:15:28 PM PDT 24
Peak memory 257364 kb
Host smart-dfbba367-cee5-4977-aae9-772ea4dcbe6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83015
6142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.830156142
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2780185814
Short name T578
Test name
Test status
Simulation time 262561408 ps
CPU time 22.49 seconds
Started Apr 15 01:11:22 PM PDT 24
Finished Apr 15 01:11:45 PM PDT 24
Peak memory 255976 kb
Host smart-7bb06ede-7413-4813-a2b3-99b2bbe9a557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27801
85814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2780185814
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.703355864
Short name T337
Test name
Test status
Simulation time 55776471866 ps
CPU time 2917.44 seconds
Started Apr 15 01:11:33 PM PDT 24
Finished Apr 15 02:00:12 PM PDT 24
Peak memory 281896 kb
Host smart-aee0e1ec-fb29-4b54-964b-b0ee251c3b79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703355864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.703355864
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.689247191
Short name T412
Test name
Test status
Simulation time 115962357814 ps
CPU time 1455.59 seconds
Started Apr 15 01:11:32 PM PDT 24
Finished Apr 15 01:35:49 PM PDT 24
Peak memory 270048 kb
Host smart-d5b8ff39-5adc-4fd7-8bc6-d0a8059f029e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689247191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.689247191
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1356265694
Short name T320
Test name
Test status
Simulation time 8954769034 ps
CPU time 89.05 seconds
Started Apr 15 01:11:42 PM PDT 24
Finished Apr 15 01:13:12 PM PDT 24
Peak memory 248540 kb
Host smart-bf68d515-2e49-44bd-869f-ad08e6529c66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356265694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1356265694
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.560566225
Short name T572
Test name
Test status
Simulation time 4633161682 ps
CPU time 44.29 seconds
Started Apr 15 01:11:26 PM PDT 24
Finished Apr 15 01:12:12 PM PDT 24
Peak memory 256312 kb
Host smart-f0d3ba6a-bbb6-4605-857c-e78f7e7f25e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56056
6225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.560566225
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.4131931762
Short name T476
Test name
Test status
Simulation time 916258009 ps
CPU time 26.6 seconds
Started Apr 15 01:11:38 PM PDT 24
Finished Apr 15 01:12:06 PM PDT 24
Peak memory 249052 kb
Host smart-6bd617b2-f75e-43b4-8a45-dc3145e01bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41319
31762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.4131931762
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.195835584
Short name T593
Test name
Test status
Simulation time 4789037510 ps
CPU time 73.86 seconds
Started Apr 15 01:11:36 PM PDT 24
Finished Apr 15 01:12:51 PM PDT 24
Peak memory 249472 kb
Host smart-2d46b4ff-2c08-455e-a693-e87b17377f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19583
5584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.195835584
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1541926243
Short name T58
Test name
Test status
Simulation time 30031600557 ps
CPU time 1948.01 seconds
Started Apr 15 01:11:44 PM PDT 24
Finished Apr 15 01:44:14 PM PDT 24
Peak memory 288192 kb
Host smart-73ca63e8-3333-4e2f-ac6e-fcb7670c78d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541926243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1541926243
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.374406516
Short name T605
Test name
Test status
Simulation time 41141651063 ps
CPU time 2553.17 seconds
Started Apr 15 01:11:30 PM PDT 24
Finished Apr 15 01:54:03 PM PDT 24
Peak memory 286584 kb
Host smart-5fc6ef3f-d7b3-42cc-8135-68f8adac4d61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374406516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.374406516
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2242265788
Short name T658
Test name
Test status
Simulation time 26924450784 ps
CPU time 134.29 seconds
Started Apr 15 01:11:45 PM PDT 24
Finished Apr 15 01:14:01 PM PDT 24
Peak memory 250204 kb
Host smart-dd7c66bd-76e5-457f-925f-a5d58de976e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22422
65788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2242265788
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.525089999
Short name T659
Test name
Test status
Simulation time 2098058347 ps
CPU time 30.44 seconds
Started Apr 15 01:11:38 PM PDT 24
Finished Apr 15 01:12:09 PM PDT 24
Peak memory 254908 kb
Host smart-7bcb9405-87b0-4769-861b-385fccc542af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52508
9999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.525089999
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1956024053
Short name T329
Test name
Test status
Simulation time 268749527373 ps
CPU time 1164.04 seconds
Started Apr 15 01:11:37 PM PDT 24
Finished Apr 15 01:31:02 PM PDT 24
Peak memory 265520 kb
Host smart-a2b74ed0-c684-48d2-ab8e-8847d0d55b6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956024053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1956024053
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1817699649
Short name T233
Test name
Test status
Simulation time 49892561678 ps
CPU time 3109.83 seconds
Started Apr 15 01:11:36 PM PDT 24
Finished Apr 15 02:03:27 PM PDT 24
Peak memory 289872 kb
Host smart-dc4bbab4-7e1d-4331-9de4-f358c9a1023c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817699649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1817699649
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1906285683
Short name T500
Test name
Test status
Simulation time 5890282381 ps
CPU time 245.99 seconds
Started Apr 15 01:11:44 PM PDT 24
Finished Apr 15 01:15:52 PM PDT 24
Peak memory 248076 kb
Host smart-42931ef5-af08-4775-9ee9-cc275d36d826
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906285683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1906285683
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2182133603
Short name T568
Test name
Test status
Simulation time 48088571 ps
CPU time 4.6 seconds
Started Apr 15 01:11:36 PM PDT 24
Finished Apr 15 01:11:42 PM PDT 24
Peak memory 240828 kb
Host smart-ba07f54d-7f0f-4dc6-86b6-8de2fc90b959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21821
33603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2182133603
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3851234547
Short name T483
Test name
Test status
Simulation time 931477764 ps
CPU time 16.87 seconds
Started Apr 15 01:11:27 PM PDT 24
Finished Apr 15 01:11:45 PM PDT 24
Peak memory 255088 kb
Host smart-af41833b-1eab-44b3-bc18-40ef5e326855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38512
34547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3851234547
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.795597892
Short name T99
Test name
Test status
Simulation time 3190811564 ps
CPU time 51.72 seconds
Started Apr 15 01:11:36 PM PDT 24
Finished Apr 15 01:12:29 PM PDT 24
Peak memory 249996 kb
Host smart-a86f59b0-998a-4f4f-b8c0-3162ab90dea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79559
7892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.795597892
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1571788949
Short name T34
Test name
Test status
Simulation time 234960989 ps
CPU time 14.48 seconds
Started Apr 15 01:11:31 PM PDT 24
Finished Apr 15 01:11:47 PM PDT 24
Peak memory 249060 kb
Host smart-d6224347-984d-4a77-88c2-a7ff1d5e964d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15717
88949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1571788949
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3281383898
Short name T616
Test name
Test status
Simulation time 216513732411 ps
CPU time 3380.19 seconds
Started Apr 15 01:11:43 PM PDT 24
Finished Apr 15 02:08:05 PM PDT 24
Peak memory 289876 kb
Host smart-d26f9dfc-8cf8-4556-9ba0-71a8edf0d30b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281383898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3281383898
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.4247079778
Short name T528
Test name
Test status
Simulation time 137820633951 ps
CPU time 2171.91 seconds
Started Apr 15 01:11:41 PM PDT 24
Finished Apr 15 01:47:54 PM PDT 24
Peak memory 286036 kb
Host smart-57e0b2d8-4eed-4500-add2-dd6e803749d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247079778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4247079778
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.776811878
Short name T439
Test name
Test status
Simulation time 2362861510 ps
CPU time 99.53 seconds
Started Apr 15 01:11:44 PM PDT 24
Finished Apr 15 01:13:25 PM PDT 24
Peak memory 250248 kb
Host smart-fa66b7be-1d3a-4a6d-8ff2-8d33b55ddf34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77681
1878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.776811878
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3465005229
Short name T609
Test name
Test status
Simulation time 925965312 ps
CPU time 50.28 seconds
Started Apr 15 01:11:33 PM PDT 24
Finished Apr 15 01:12:25 PM PDT 24
Peak memory 255792 kb
Host smart-73fc8ed4-1714-48b1-a53f-d315dd62debb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34650
05229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3465005229
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.135105668
Short name T564
Test name
Test status
Simulation time 11363905397 ps
CPU time 1018.44 seconds
Started Apr 15 01:11:50 PM PDT 24
Finished Apr 15 01:28:49 PM PDT 24
Peak memory 272856 kb
Host smart-dcb83afd-7589-4eca-85d2-e27fc3b4ef9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135105668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.135105668
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2668368440
Short name T463
Test name
Test status
Simulation time 104888463717 ps
CPU time 1351.77 seconds
Started Apr 15 01:11:48 PM PDT 24
Finished Apr 15 01:34:21 PM PDT 24
Peak memory 272368 kb
Host smart-3c47b1c2-8654-4b2d-9b26-f8c281f71594
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668368440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2668368440
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1807329889
Short name T589
Test name
Test status
Simulation time 241501207 ps
CPU time 10.38 seconds
Started Apr 15 01:11:41 PM PDT 24
Finished Apr 15 01:11:53 PM PDT 24
Peak memory 256220 kb
Host smart-27be7eed-5165-43f8-bf21-e87d6c946c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18073
29889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1807329889
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2129162112
Short name T105
Test name
Test status
Simulation time 1365298845 ps
CPU time 38.27 seconds
Started Apr 15 01:11:29 PM PDT 24
Finished Apr 15 01:12:08 PM PDT 24
Peak memory 256904 kb
Host smart-1143258b-cf30-44ad-9ac6-43371748ba01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21291
62112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2129162112
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3049730599
Short name T371
Test name
Test status
Simulation time 4390968566 ps
CPU time 70.54 seconds
Started Apr 15 01:11:46 PM PDT 24
Finished Apr 15 01:12:58 PM PDT 24
Peak memory 249216 kb
Host smart-099be5a6-54d8-48d4-8927-84cf9b210635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30497
30599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3049730599
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3785614280
Short name T264
Test name
Test status
Simulation time 57111387034 ps
CPU time 1239.61 seconds
Started Apr 15 01:11:49 PM PDT 24
Finished Apr 15 01:32:30 PM PDT 24
Peak memory 289268 kb
Host smart-e5c83dc2-6078-4ade-8780-5e0330027c04
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785614280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3785614280
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1149735943
Short name T375
Test name
Test status
Simulation time 39700761953 ps
CPU time 1974 seconds
Started Apr 15 01:11:46 PM PDT 24
Finished Apr 15 01:44:42 PM PDT 24
Peak memory 273704 kb
Host smart-bed67828-9e59-4991-aab7-2512e6440ade
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149735943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1149735943
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3974728762
Short name T677
Test name
Test status
Simulation time 13317162275 ps
CPU time 57.84 seconds
Started Apr 15 01:11:43 PM PDT 24
Finished Apr 15 01:12:43 PM PDT 24
Peak memory 248852 kb
Host smart-1b10186e-0a99-4dbd-ae4b-31a898ef29fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39747
28762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3974728762
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.4032359950
Short name T651
Test name
Test status
Simulation time 981834700 ps
CPU time 27.81 seconds
Started Apr 15 01:11:27 PM PDT 24
Finished Apr 15 01:11:56 PM PDT 24
Peak memory 255768 kb
Host smart-6d5e8eed-52f5-4e3f-92a3-47d0d0142d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40323
59950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.4032359950
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3697884298
Short name T666
Test name
Test status
Simulation time 62369320509 ps
CPU time 1105.37 seconds
Started Apr 15 01:11:47 PM PDT 24
Finished Apr 15 01:30:14 PM PDT 24
Peak memory 272792 kb
Host smart-0b8bd27b-45ca-4849-be3e-4de33d2a803f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697884298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3697884298
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2354377765
Short name T441
Test name
Test status
Simulation time 539523183122 ps
CPU time 2303.4 seconds
Started Apr 15 01:11:49 PM PDT 24
Finished Apr 15 01:50:14 PM PDT 24
Peak memory 283516 kb
Host smart-bba0dafe-5ae4-4fdb-8dbf-283fb5f997f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354377765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2354377765
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.141279808
Short name T236
Test name
Test status
Simulation time 53936797028 ps
CPU time 434.28 seconds
Started Apr 15 01:11:45 PM PDT 24
Finished Apr 15 01:19:01 PM PDT 24
Peak memory 247272 kb
Host smart-810d1bd1-a9ff-4678-8082-1917b87d555f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141279808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.141279808
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.4174688787
Short name T672
Test name
Test status
Simulation time 1326596323 ps
CPU time 46.42 seconds
Started Apr 15 01:11:36 PM PDT 24
Finished Apr 15 01:12:24 PM PDT 24
Peak memory 249140 kb
Host smart-7b559219-4d7d-498a-88c9-c024bdd9228d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41746
88787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.4174688787
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3535964277
Short name T695
Test name
Test status
Simulation time 2915966963 ps
CPU time 46.13 seconds
Started Apr 15 01:11:40 PM PDT 24
Finished Apr 15 01:12:27 PM PDT 24
Peak memory 256268 kb
Host smart-95207bbc-c8a4-4ea1-a4a2-41d3434ca79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35359
64277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3535964277
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3382776733
Short name T432
Test name
Test status
Simulation time 3745358607 ps
CPU time 57.06 seconds
Started Apr 15 01:11:45 PM PDT 24
Finished Apr 15 01:12:44 PM PDT 24
Peak memory 249124 kb
Host smart-c82c6923-108c-4ebe-9343-743dba5a1da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33827
76733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3382776733
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.375825751
Short name T613
Test name
Test status
Simulation time 2909821119 ps
CPU time 50.05 seconds
Started Apr 15 01:11:38 PM PDT 24
Finished Apr 15 01:12:29 PM PDT 24
Peak memory 249496 kb
Host smart-a96bef77-4742-4c80-af87-084b07fb7246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37582
5751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.375825751
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1753481392
Short name T49
Test name
Test status
Simulation time 40507953980 ps
CPU time 3286.25 seconds
Started Apr 15 01:11:38 PM PDT 24
Finished Apr 15 02:06:26 PM PDT 24
Peak memory 289412 kb
Host smart-f472bfd4-1969-42f0-bc2c-0033c99b1607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753481392 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1753481392
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.596248181
Short name T487
Test name
Test status
Simulation time 73862019145 ps
CPU time 1312.49 seconds
Started Apr 15 01:11:47 PM PDT 24
Finished Apr 15 01:33:41 PM PDT 24
Peak memory 285968 kb
Host smart-6326ed9a-9f3e-4a2f-8a01-af7543654d07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596248181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.596248181
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1521378964
Short name T705
Test name
Test status
Simulation time 15210977589 ps
CPU time 247.81 seconds
Started Apr 15 01:11:46 PM PDT 24
Finished Apr 15 01:15:56 PM PDT 24
Peak memory 250108 kb
Host smart-33cd1480-645a-418e-9338-af5da0c7b3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15213
78964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1521378964
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.574789878
Short name T405
Test name
Test status
Simulation time 1239489814 ps
CPU time 36.68 seconds
Started Apr 15 01:11:45 PM PDT 24
Finished Apr 15 01:12:24 PM PDT 24
Peak memory 248844 kb
Host smart-5b9ecd0a-ebce-4c29-a8a0-e36d4856c350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57478
9878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.574789878
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3042026580
Short name T341
Test name
Test status
Simulation time 22501653540 ps
CPU time 1257.68 seconds
Started Apr 15 01:11:46 PM PDT 24
Finished Apr 15 01:32:46 PM PDT 24
Peak memory 273568 kb
Host smart-86c297f5-5f9d-4db4-b759-bea3e985f8e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042026580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3042026580
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3317928162
Short name T416
Test name
Test status
Simulation time 69324957849 ps
CPU time 1226.94 seconds
Started Apr 15 01:11:43 PM PDT 24
Finished Apr 15 01:32:11 PM PDT 24
Peak memory 289296 kb
Host smart-d4f0e36e-28a2-46aa-affd-f4ce25e3b1f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317928162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3317928162
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3546921346
Short name T645
Test name
Test status
Simulation time 5650646794 ps
CPU time 221.51 seconds
Started Apr 15 01:11:47 PM PDT 24
Finished Apr 15 01:15:30 PM PDT 24
Peak memory 248072 kb
Host smart-6198ef34-ca47-4101-af4a-f00f764c4d47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546921346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3546921346
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2032912691
Short name T394
Test name
Test status
Simulation time 1904697122 ps
CPU time 14.48 seconds
Started Apr 15 01:11:49 PM PDT 24
Finished Apr 15 01:12:05 PM PDT 24
Peak memory 254788 kb
Host smart-eb6bccc0-f845-4680-accd-754196adb404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20329
12691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2032912691
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.760903400
Short name T689
Test name
Test status
Simulation time 2652796258 ps
CPU time 40.58 seconds
Started Apr 15 01:11:50 PM PDT 24
Finished Apr 15 01:12:31 PM PDT 24
Peak memory 255900 kb
Host smart-01a315a4-143a-4075-a706-7bbd065b9371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76090
3400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.760903400
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1424632741
Short name T472
Test name
Test status
Simulation time 960172411 ps
CPU time 15.57 seconds
Started Apr 15 01:11:47 PM PDT 24
Finished Apr 15 01:12:04 PM PDT 24
Peak memory 255504 kb
Host smart-dfb5689b-39d1-493c-9275-93aea923c7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14246
32741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1424632741
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1784194001
Short name T426
Test name
Test status
Simulation time 1148764664 ps
CPU time 69.75 seconds
Started Apr 15 01:11:45 PM PDT 24
Finished Apr 15 01:12:57 PM PDT 24
Peak memory 257188 kb
Host smart-70a3132c-a0f2-404c-b6f6-847e315cd04a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784194001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1784194001
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.319988893
Short name T68
Test name
Test status
Simulation time 5987857342 ps
CPU time 578.08 seconds
Started Apr 15 01:11:35 PM PDT 24
Finished Apr 15 01:21:14 PM PDT 24
Peak memory 273536 kb
Host smart-bfe7ca0e-78d4-4360-95aa-9516b487446b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319988893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.319988893
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1924795762
Short name T560
Test name
Test status
Simulation time 4679782409 ps
CPU time 238.96 seconds
Started Apr 15 01:11:43 PM PDT 24
Finished Apr 15 01:15:43 PM PDT 24
Peak memory 256856 kb
Host smart-1407caf6-41b0-414a-bc3e-ca1a70710a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19247
95762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1924795762
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2481597769
Short name T701
Test name
Test status
Simulation time 226726748 ps
CPU time 7.08 seconds
Started Apr 15 01:11:36 PM PDT 24
Finished Apr 15 01:11:44 PM PDT 24
Peak memory 253412 kb
Host smart-f51f4b76-5051-4bf3-93ed-87d0b2266f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24815
97769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2481597769
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.461089694
Short name T274
Test name
Test status
Simulation time 57595870686 ps
CPU time 1433.1 seconds
Started Apr 15 01:11:55 PM PDT 24
Finished Apr 15 01:35:49 PM PDT 24
Peak memory 290084 kb
Host smart-3bb86001-cb30-49ca-a8da-cbaa3707556c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461089694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.461089694
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.128638903
Short name T481
Test name
Test status
Simulation time 87893249488 ps
CPU time 1482.78 seconds
Started Apr 15 01:11:40 PM PDT 24
Finished Apr 15 01:36:25 PM PDT 24
Peak memory 272780 kb
Host smart-4c055a8b-6d27-436b-b771-f5a961c38f71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128638903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.128638903
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3449308584
Short name T310
Test name
Test status
Simulation time 23836438501 ps
CPU time 476.18 seconds
Started Apr 15 01:11:51 PM PDT 24
Finished Apr 15 01:19:48 PM PDT 24
Peak memory 247268 kb
Host smart-b04f2b60-1ea7-4f9c-b119-3bf11a5f3934
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449308584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3449308584
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1690677588
Short name T214
Test name
Test status
Simulation time 1016790975 ps
CPU time 36.86 seconds
Started Apr 15 01:11:47 PM PDT 24
Finished Apr 15 01:12:25 PM PDT 24
Peak memory 256220 kb
Host smart-6918d852-3755-4711-b9b0-b7e8dd4679f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16906
77588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1690677588
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1766331112
Short name T691
Test name
Test status
Simulation time 197293786 ps
CPU time 26.68 seconds
Started Apr 15 01:11:45 PM PDT 24
Finished Apr 15 01:12:13 PM PDT 24
Peak memory 256424 kb
Host smart-1ab6d7f9-eafc-4783-b9b5-0b7df4a36b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17663
31112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1766331112
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.4287838571
Short name T383
Test name
Test status
Simulation time 76848531 ps
CPU time 3.15 seconds
Started Apr 15 01:11:46 PM PDT 24
Finished Apr 15 01:11:51 PM PDT 24
Peak memory 239392 kb
Host smart-ebb35dc0-ed10-408a-b914-f86800b104ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42878
38571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.4287838571
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1391366593
Short name T498
Test name
Test status
Simulation time 264972615 ps
CPU time 6.06 seconds
Started Apr 15 01:11:52 PM PDT 24
Finished Apr 15 01:11:58 PM PDT 24
Peak memory 249140 kb
Host smart-c7455a92-3ebc-4dd5-8460-eab05b9375d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13913
66593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1391366593
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1972317786
Short name T558
Test name
Test status
Simulation time 31570866995 ps
CPU time 2030.37 seconds
Started Apr 15 01:11:46 PM PDT 24
Finished Apr 15 01:45:38 PM PDT 24
Peak memory 288704 kb
Host smart-d319a2fa-e16c-4b0f-adee-782306e53ee8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972317786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1972317786
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1231779789
Short name T207
Test name
Test status
Simulation time 20642887 ps
CPU time 2.86 seconds
Started Apr 15 01:11:07 PM PDT 24
Finished Apr 15 01:11:11 PM PDT 24
Peak memory 249300 kb
Host smart-a644b637-f720-4cbb-aa6c-002a5b986dbc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1231779789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1231779789
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2960732119
Short name T471
Test name
Test status
Simulation time 15713685513 ps
CPU time 811.63 seconds
Started Apr 15 01:10:55 PM PDT 24
Finished Apr 15 01:24:28 PM PDT 24
Peak memory 267592 kb
Host smart-d5f259a2-2ce6-4f0f-99d8-3ce8d44d5dcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960732119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2960732119
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3225913749
Short name T601
Test name
Test status
Simulation time 1187153524 ps
CPU time 25.33 seconds
Started Apr 15 01:11:07 PM PDT 24
Finished Apr 15 01:11:33 PM PDT 24
Peak memory 240856 kb
Host smart-1d152998-d4ee-4768-a3c0-729826a275ca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3225913749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3225913749
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3445193064
Short name T443
Test name
Test status
Simulation time 21141654715 ps
CPU time 118.14 seconds
Started Apr 15 01:11:01 PM PDT 24
Finished Apr 15 01:13:01 PM PDT 24
Peak memory 249156 kb
Host smart-6c1677de-f015-4042-babb-aadbb8cd4152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34451
93064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3445193064
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2075327600
Short name T256
Test name
Test status
Simulation time 599659867 ps
CPU time 18.76 seconds
Started Apr 15 01:10:58 PM PDT 24
Finished Apr 15 01:11:17 PM PDT 24
Peak memory 253592 kb
Host smart-a06575b6-ab39-44ae-87e0-7117f6933244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20753
27600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2075327600
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.544826738
Short name T299
Test name
Test status
Simulation time 14105826738 ps
CPU time 1391.57 seconds
Started Apr 15 01:10:59 PM PDT 24
Finished Apr 15 01:34:12 PM PDT 24
Peak memory 289264 kb
Host smart-c7fa0676-91cc-4406-a9a4-334eb71a4630
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544826738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.544826738
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2277884919
Short name T311
Test name
Test status
Simulation time 4732691712 ps
CPU time 194.19 seconds
Started Apr 15 01:10:59 PM PDT 24
Finished Apr 15 01:14:14 PM PDT 24
Peak memory 248048 kb
Host smart-4830ff05-49fd-45cf-9496-aafe229085ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277884919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2277884919
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1791473991
Short name T503
Test name
Test status
Simulation time 908298029 ps
CPU time 20.94 seconds
Started Apr 15 01:10:55 PM PDT 24
Finished Apr 15 01:11:17 PM PDT 24
Peak memory 249000 kb
Host smart-41d1a303-e099-4a96-9302-33e36e4d536a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17914
73991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1791473991
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3371357040
Short name T63
Test name
Test status
Simulation time 399343175 ps
CPU time 23.93 seconds
Started Apr 15 01:11:02 PM PDT 24
Finished Apr 15 01:11:27 PM PDT 24
Peak memory 247664 kb
Host smart-9589aa50-aaab-4bbc-b03d-9c69d661d394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713
57040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3371357040
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.586996723
Short name T10
Test name
Test status
Simulation time 176006403 ps
CPU time 11.48 seconds
Started Apr 15 01:11:01 PM PDT 24
Finished Apr 15 01:11:14 PM PDT 24
Peak memory 273408 kb
Host smart-f285077e-cfee-4d39-9fd2-ab1c089ea9fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=586996723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.586996723
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3728741995
Short name T385
Test name
Test status
Simulation time 517070233 ps
CPU time 9.74 seconds
Started Apr 15 01:10:55 PM PDT 24
Finished Apr 15 01:11:05 PM PDT 24
Peak memory 247448 kb
Host smart-b4aad952-99e5-4085-929f-6e89a49fd724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37287
41995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3728741995
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.516785236
Short name T180
Test name
Test status
Simulation time 8956170943 ps
CPU time 29.12 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:11:31 PM PDT 24
Peak memory 256352 kb
Host smart-8e67f089-3323-4177-bad1-0b9f9105c71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51678
5236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.516785236
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2755429295
Short name T25
Test name
Test status
Simulation time 6472077470 ps
CPU time 171.27 seconds
Started Apr 15 01:11:01 PM PDT 24
Finished Apr 15 01:13:54 PM PDT 24
Peak memory 255520 kb
Host smart-4896a876-0686-44f0-a3d1-42611059b7bc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755429295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2755429295
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3028541633
Short name T245
Test name
Test status
Simulation time 316109037448 ps
CPU time 3441.55 seconds
Started Apr 15 01:11:06 PM PDT 24
Finished Apr 15 02:08:28 PM PDT 24
Peak memory 331176 kb
Host smart-007f96d5-669e-41cd-ae49-d04cda7e6aa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028541633 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3028541633
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1466739716
Short name T519
Test name
Test status
Simulation time 63313984767 ps
CPU time 1574.11 seconds
Started Apr 15 01:11:50 PM PDT 24
Finished Apr 15 01:38:05 PM PDT 24
Peak memory 289268 kb
Host smart-8700ebfa-a101-41f1-9d7e-1b5369a7479c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466739716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1466739716
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3996285684
Short name T521
Test name
Test status
Simulation time 728949149 ps
CPU time 45.72 seconds
Started Apr 15 01:11:47 PM PDT 24
Finished Apr 15 01:12:34 PM PDT 24
Peak memory 256176 kb
Host smart-953b108f-b533-4cfa-9726-09f45fd5d5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39962
85684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3996285684
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1748191744
Short name T566
Test name
Test status
Simulation time 1067232821 ps
CPU time 38.99 seconds
Started Apr 15 01:11:46 PM PDT 24
Finished Apr 15 01:12:27 PM PDT 24
Peak memory 255688 kb
Host smart-0853c1a1-0111-4975-bfd5-73ec058f32fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17481
91744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1748191744
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1860360770
Short name T557
Test name
Test status
Simulation time 15292425312 ps
CPU time 802.87 seconds
Started Apr 15 01:11:51 PM PDT 24
Finished Apr 15 01:25:15 PM PDT 24
Peak memory 265548 kb
Host smart-ac97a3f0-414c-4111-a53f-6d47b7526692
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860360770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1860360770
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3281122342
Short name T470
Test name
Test status
Simulation time 19540099979 ps
CPU time 1267.59 seconds
Started Apr 15 01:11:58 PM PDT 24
Finished Apr 15 01:33:06 PM PDT 24
Peak memory 266588 kb
Host smart-a14bd4d9-1d7c-46b3-b87c-df8e1bef6020
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281122342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3281122342
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2474761268
Short name T8
Test name
Test status
Simulation time 7963977312 ps
CPU time 364.48 seconds
Started Apr 15 01:11:42 PM PDT 24
Finished Apr 15 01:17:48 PM PDT 24
Peak memory 248072 kb
Host smart-3f6c4e0c-8a0e-41e9-8535-0b06112dcb49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474761268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2474761268
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4168931486
Short name T428
Test name
Test status
Simulation time 785861661 ps
CPU time 13.49 seconds
Started Apr 15 01:11:46 PM PDT 24
Finished Apr 15 01:12:01 PM PDT 24
Peak memory 253216 kb
Host smart-f016d4fc-a0f6-4dbc-8883-229cda7e7786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41689
31486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4168931486
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3302032031
Short name T223
Test name
Test status
Simulation time 486544152 ps
CPU time 19.39 seconds
Started Apr 15 01:11:49 PM PDT 24
Finished Apr 15 01:12:09 PM PDT 24
Peak memory 249248 kb
Host smart-1b30fe56-5f19-45af-a2b0-77e5223d1275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33020
32031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3302032031
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2533989532
Short name T445
Test name
Test status
Simulation time 821702505 ps
CPU time 49.46 seconds
Started Apr 15 01:11:48 PM PDT 24
Finished Apr 15 01:12:39 PM PDT 24
Peak memory 249396 kb
Host smart-b0981028-1519-4769-9d6f-bf51afd52471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25339
89532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2533989532
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2919901066
Short name T449
Test name
Test status
Simulation time 68487602 ps
CPU time 5.24 seconds
Started Apr 15 01:11:44 PM PDT 24
Finished Apr 15 01:11:51 PM PDT 24
Peak memory 251164 kb
Host smart-3aca1e99-1f1a-464b-a7af-d2cc91359c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29199
01066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2919901066
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2841291006
Short name T284
Test name
Test status
Simulation time 9639030072 ps
CPU time 435.58 seconds
Started Apr 15 01:11:42 PM PDT 24
Finished Apr 15 01:18:59 PM PDT 24
Peak memory 267748 kb
Host smart-2a8491dc-17e3-46c0-8a71-e97d646976cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841291006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2841291006
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1759350238
Short name T80
Test name
Test status
Simulation time 380946915399 ps
CPU time 7833.06 seconds
Started Apr 15 01:11:49 PM PDT 24
Finished Apr 15 03:22:23 PM PDT 24
Peak memory 371264 kb
Host smart-609c7a2b-0d5e-48a0-8913-69f001e70cce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759350238 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1759350238
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3926669368
Short name T108
Test name
Test status
Simulation time 31538883978 ps
CPU time 1089.98 seconds
Started Apr 15 01:11:53 PM PDT 24
Finished Apr 15 01:30:04 PM PDT 24
Peak memory 265584 kb
Host smart-9e486696-4773-4cc0-ae8e-2a574cd38da3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926669368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3926669368
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1194752968
Short name T478
Test name
Test status
Simulation time 154497311 ps
CPU time 11.91 seconds
Started Apr 15 01:11:52 PM PDT 24
Finished Apr 15 01:12:05 PM PDT 24
Peak memory 254024 kb
Host smart-7b481d45-3969-4d5f-95d8-08fd5a21ed5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11947
52968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1194752968
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1547754467
Short name T552
Test name
Test status
Simulation time 131627286 ps
CPU time 10.18 seconds
Started Apr 15 01:11:50 PM PDT 24
Finished Apr 15 01:12:01 PM PDT 24
Peak memory 253252 kb
Host smart-9a0cba32-7ffc-442a-b8b0-4611a65a1e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15477
54467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1547754467
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1952322526
Short name T333
Test name
Test status
Simulation time 74043862430 ps
CPU time 1076.68 seconds
Started Apr 15 01:11:51 PM PDT 24
Finished Apr 15 01:29:49 PM PDT 24
Peak memory 289052 kb
Host smart-16e05307-2e6c-453c-9a66-472e8e453c32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952322526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1952322526
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3646490673
Short name T619
Test name
Test status
Simulation time 92865853958 ps
CPU time 1223.01 seconds
Started Apr 15 01:11:49 PM PDT 24
Finished Apr 15 01:32:13 PM PDT 24
Peak memory 282568 kb
Host smart-e31dd9d8-e231-40fe-b5da-dbb9c359fac9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646490673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3646490673
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.766418696
Short name T292
Test name
Test status
Simulation time 19048343193 ps
CPU time 387.18 seconds
Started Apr 15 01:11:57 PM PDT 24
Finished Apr 15 01:18:25 PM PDT 24
Peak memory 248296 kb
Host smart-144f2673-22b0-4c00-a484-39f7e024311e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766418696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.766418696
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1502825561
Short name T440
Test name
Test status
Simulation time 217836140 ps
CPU time 22.31 seconds
Started Apr 15 01:11:49 PM PDT 24
Finished Apr 15 01:12:13 PM PDT 24
Peak memory 249052 kb
Host smart-27b4f79e-a9d7-405c-afba-374e745cb9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15028
25561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1502825561
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.502121993
Short name T455
Test name
Test status
Simulation time 112647717 ps
CPU time 4.57 seconds
Started Apr 15 01:11:45 PM PDT 24
Finished Apr 15 01:11:52 PM PDT 24
Peak memory 252384 kb
Host smart-ef945b11-69c2-4de4-9a89-bc7a18aefd7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50212
1993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.502121993
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1180948374
Short name T16
Test name
Test status
Simulation time 336240006 ps
CPU time 17.85 seconds
Started Apr 15 01:11:48 PM PDT 24
Finished Apr 15 01:12:07 PM PDT 24
Peak memory 249028 kb
Host smart-48b75173-d3a4-4604-8343-5b6e4ccd4fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11809
48374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1180948374
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3698755037
Short name T525
Test name
Test status
Simulation time 79389235820 ps
CPU time 2025.58 seconds
Started Apr 15 01:11:51 PM PDT 24
Finished Apr 15 01:45:38 PM PDT 24
Peak memory 288284 kb
Host smart-489a6dab-b938-4c54-aba0-1d5c85c2aae5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698755037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3698755037
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2665791176
Short name T550
Test name
Test status
Simulation time 1457267291 ps
CPU time 25.79 seconds
Started Apr 15 01:11:54 PM PDT 24
Finished Apr 15 01:12:20 PM PDT 24
Peak memory 256264 kb
Host smart-4110c479-11db-4fa5-b7d4-1148edf8fbf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26657
91176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2665791176
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3307714485
Short name T512
Test name
Test status
Simulation time 780762350 ps
CPU time 19.72 seconds
Started Apr 15 01:11:51 PM PDT 24
Finished Apr 15 01:12:12 PM PDT 24
Peak memory 255800 kb
Host smart-1eab33ee-4b15-4a3b-856c-43934e15c6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33077
14485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3307714485
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1735149973
Short name T697
Test name
Test status
Simulation time 30733145476 ps
CPU time 1819.74 seconds
Started Apr 15 01:11:47 PM PDT 24
Finished Apr 15 01:42:09 PM PDT 24
Peak memory 285908 kb
Host smart-e5d50bd3-99f2-4d51-87cb-4d9dc1940315
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735149973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1735149973
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.52790507
Short name T692
Test name
Test status
Simulation time 106475714744 ps
CPU time 2993.73 seconds
Started Apr 15 01:11:52 PM PDT 24
Finished Apr 15 02:01:47 PM PDT 24
Peak memory 290056 kb
Host smart-c2a10af7-e74e-489c-8f6f-3e396bc970bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52790507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.52790507
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.400580282
Short name T532
Test name
Test status
Simulation time 21016762355 ps
CPU time 168.47 seconds
Started Apr 15 01:11:50 PM PDT 24
Finished Apr 15 01:14:39 PM PDT 24
Peak memory 253912 kb
Host smart-b6fb1693-f45a-4899-b824-235647360cb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400580282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.400580282
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.680805211
Short name T365
Test name
Test status
Simulation time 4823690537 ps
CPU time 28.43 seconds
Started Apr 15 01:11:43 PM PDT 24
Finished Apr 15 01:12:13 PM PDT 24
Peak memory 249164 kb
Host smart-e5d9fd07-9908-47a7-b6c5-996adf6e62de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68080
5211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.680805211
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1589668132
Short name T482
Test name
Test status
Simulation time 331948808 ps
CPU time 20.63 seconds
Started Apr 15 01:11:50 PM PDT 24
Finished Apr 15 01:12:11 PM PDT 24
Peak memory 255888 kb
Host smart-3eb4eecf-bda6-4b86-8356-c17c7b7b5ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15896
68132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1589668132
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3299796155
Short name T79
Test name
Test status
Simulation time 4913190755 ps
CPU time 77.7 seconds
Started Apr 15 01:11:50 PM PDT 24
Finished Apr 15 01:13:08 PM PDT 24
Peak memory 255784 kb
Host smart-0cc4b280-e985-4811-850e-634e35d28c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32997
96155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3299796155
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2848315130
Short name T650
Test name
Test status
Simulation time 52122037 ps
CPU time 2.82 seconds
Started Apr 15 01:11:56 PM PDT 24
Finished Apr 15 01:12:00 PM PDT 24
Peak memory 240860 kb
Host smart-bbd260eb-2082-4cc9-b4d8-8ab5b0ecec13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28483
15130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2848315130
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3866373268
Short name T638
Test name
Test status
Simulation time 95408767158 ps
CPU time 2139.35 seconds
Started Apr 15 01:11:53 PM PDT 24
Finished Apr 15 01:47:33 PM PDT 24
Peak memory 302656 kb
Host smart-4b90e292-afc7-4a41-9584-7b87b52f0abc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866373268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3866373268
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2247617380
Short name T559
Test name
Test status
Simulation time 103221305592 ps
CPU time 1448.22 seconds
Started Apr 15 01:11:50 PM PDT 24
Finished Apr 15 01:35:59 PM PDT 24
Peak memory 272084 kb
Host smart-90c0eb40-92e8-423c-b37a-35fe43682580
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247617380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2247617380
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.683706827
Short name T186
Test name
Test status
Simulation time 7519711658 ps
CPU time 103.99 seconds
Started Apr 15 01:11:50 PM PDT 24
Finished Apr 15 01:13:35 PM PDT 24
Peak memory 257088 kb
Host smart-047838af-0025-41e5-821e-2ce26e1cba9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68370
6827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.683706827
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1768471254
Short name T509
Test name
Test status
Simulation time 11022103300 ps
CPU time 74.82 seconds
Started Apr 15 01:11:53 PM PDT 24
Finished Apr 15 01:13:09 PM PDT 24
Peak memory 249156 kb
Host smart-a0bcb84f-4a09-4d51-a05d-c077c5d6f3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17684
71254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1768471254
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3322631885
Short name T597
Test name
Test status
Simulation time 22153980575 ps
CPU time 1260.66 seconds
Started Apr 15 01:11:53 PM PDT 24
Finished Apr 15 01:32:55 PM PDT 24
Peak memory 265488 kb
Host smart-22afaa6b-4995-421f-a942-7fa26fc32f67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322631885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3322631885
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1227367522
Short name T626
Test name
Test status
Simulation time 15784343944 ps
CPU time 789.9 seconds
Started Apr 15 01:11:53 PM PDT 24
Finished Apr 15 01:25:04 PM PDT 24
Peak memory 270776 kb
Host smart-86889368-4fae-4395-993c-4d8f56ecb566
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227367522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1227367522
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.605664526
Short name T306
Test name
Test status
Simulation time 24434781931 ps
CPU time 424.13 seconds
Started Apr 15 01:11:51 PM PDT 24
Finished Apr 15 01:18:56 PM PDT 24
Peak memory 254968 kb
Host smart-55dd6727-953e-43bf-9c42-e759bef00c1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605664526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.605664526
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3717468127
Short name T547
Test name
Test status
Simulation time 4988666044 ps
CPU time 26.09 seconds
Started Apr 15 01:11:53 PM PDT 24
Finished Apr 15 01:12:20 PM PDT 24
Peak memory 249096 kb
Host smart-b78b8aeb-2205-4d49-b628-148d5aef8d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37174
68127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3717468127
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3723874899
Short name T53
Test name
Test status
Simulation time 880877373 ps
CPU time 52.95 seconds
Started Apr 15 01:11:55 PM PDT 24
Finished Apr 15 01:12:49 PM PDT 24
Peak memory 254884 kb
Host smart-1b987c7e-f665-4bfc-9019-119b44bce0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37238
74899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3723874899
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2918881579
Short name T3
Test name
Test status
Simulation time 318546289 ps
CPU time 23.84 seconds
Started Apr 15 01:11:56 PM PDT 24
Finished Apr 15 01:12:21 PM PDT 24
Peak memory 247644 kb
Host smart-839f4ee1-eb72-4853-861c-53d524479507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29188
81579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2918881579
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4200875997
Short name T184
Test name
Test status
Simulation time 5233918642 ps
CPU time 69.51 seconds
Started Apr 15 01:11:49 PM PDT 24
Finished Apr 15 01:12:59 PM PDT 24
Peak memory 256456 kb
Host smart-3a698499-d9eb-4714-81fc-df3c14074159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42008
75997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4200875997
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.205967168
Short name T82
Test name
Test status
Simulation time 4901179950 ps
CPU time 78 seconds
Started Apr 15 01:11:58 PM PDT 24
Finished Apr 15 01:13:16 PM PDT 24
Peak memory 255324 kb
Host smart-f30b1dd1-4fbc-4e65-b108-b3bc601cf322
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205967168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.205967168
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2908683616
Short name T475
Test name
Test status
Simulation time 23284085705 ps
CPU time 724.6 seconds
Started Apr 15 01:11:56 PM PDT 24
Finished Apr 15 01:24:02 PM PDT 24
Peak memory 267600 kb
Host smart-eccf3a6b-243b-43ca-8c8c-0b719e8cc8ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908683616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2908683616
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2004092643
Short name T400
Test name
Test status
Simulation time 7062403643 ps
CPU time 127.7 seconds
Started Apr 15 01:11:57 PM PDT 24
Finished Apr 15 01:14:05 PM PDT 24
Peak memory 252232 kb
Host smart-78dbdc7c-d078-47c7-9214-92cc7d055094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20040
92643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2004092643
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2280025360
Short name T486
Test name
Test status
Simulation time 7409526704 ps
CPU time 48.42 seconds
Started Apr 15 01:11:51 PM PDT 24
Finished Apr 15 01:12:40 PM PDT 24
Peak memory 255488 kb
Host smart-95a736e6-9c63-4c5a-9ae9-3d5fec6ded43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22800
25360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2280025360
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1117136852
Short name T35
Test name
Test status
Simulation time 12233533822 ps
CPU time 1160.53 seconds
Started Apr 15 01:11:53 PM PDT 24
Finished Apr 15 01:31:15 PM PDT 24
Peak memory 286616 kb
Host smart-50cf784c-4012-4568-b8fb-4fee8577b06b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117136852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1117136852
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2302317320
Short name T280
Test name
Test status
Simulation time 147447410504 ps
CPU time 1904.73 seconds
Started Apr 15 01:11:52 PM PDT 24
Finished Apr 15 01:43:38 PM PDT 24
Peak memory 283924 kb
Host smart-2ff06139-b442-4e29-8e8f-0dbe8f6d0e5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302317320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2302317320
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.68494752
Short name T269
Test name
Test status
Simulation time 8452261173 ps
CPU time 358.44 seconds
Started Apr 15 01:11:58 PM PDT 24
Finished Apr 15 01:17:57 PM PDT 24
Peak memory 248316 kb
Host smart-8b02e9ae-8df9-4580-8900-8f846462418a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68494752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.68494752
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2561033420
Short name T181
Test name
Test status
Simulation time 2991637340 ps
CPU time 53.78 seconds
Started Apr 15 01:11:53 PM PDT 24
Finished Apr 15 01:12:48 PM PDT 24
Peak memory 249092 kb
Host smart-576c2020-9b42-4fa9-8a48-8123ce7b1557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25610
33420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2561033420
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3826283938
Short name T625
Test name
Test status
Simulation time 2822462369 ps
CPU time 13.13 seconds
Started Apr 15 01:11:54 PM PDT 24
Finished Apr 15 01:12:08 PM PDT 24
Peak memory 252816 kb
Host smart-d1716912-a8c0-4499-893b-c896a1ff81e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38262
83938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3826283938
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.288398908
Short name T65
Test name
Test status
Simulation time 643257688 ps
CPU time 41.17 seconds
Started Apr 15 01:11:54 PM PDT 24
Finished Apr 15 01:12:36 PM PDT 24
Peak memory 256168 kb
Host smart-bb0ead3b-09a4-4a21-874a-57ef218a3fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28839
8908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.288398908
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1121859021
Short name T603
Test name
Test status
Simulation time 644080587 ps
CPU time 36.83 seconds
Started Apr 15 01:11:52 PM PDT 24
Finished Apr 15 01:12:30 PM PDT 24
Peak memory 249076 kb
Host smart-4b10f695-1313-42db-afc1-569255afa80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11218
59021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1121859021
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3375406984
Short name T43
Test name
Test status
Simulation time 28291460312 ps
CPU time 1724.28 seconds
Started Apr 15 01:11:52 PM PDT 24
Finished Apr 15 01:40:38 PM PDT 24
Peak memory 273704 kb
Host smart-d32ab011-a29e-4eb0-bc15-940aa0337c21
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375406984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3375406984
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2645200261
Short name T110
Test name
Test status
Simulation time 363692211649 ps
CPU time 3823.86 seconds
Started Apr 15 01:11:56 PM PDT 24
Finished Apr 15 02:15:41 PM PDT 24
Peak memory 306560 kb
Host smart-9fee85f2-f5bc-412d-a67b-862e91545acf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645200261 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2645200261
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1570163557
Short name T395
Test name
Test status
Simulation time 10875236050 ps
CPU time 954.86 seconds
Started Apr 15 01:11:52 PM PDT 24
Finished Apr 15 01:27:47 PM PDT 24
Peak memory 273096 kb
Host smart-f9e94019-5a4b-482e-b087-23b4de2b0bda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570163557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1570163557
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3626587986
Short name T458
Test name
Test status
Simulation time 4528489828 ps
CPU time 67.51 seconds
Started Apr 15 01:11:52 PM PDT 24
Finished Apr 15 01:13:00 PM PDT 24
Peak memory 256388 kb
Host smart-1b296f3e-ed35-409d-a436-e4e8ceaf4c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36265
87986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3626587986
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3444360957
Short name T579
Test name
Test status
Simulation time 1574649428 ps
CPU time 22.13 seconds
Started Apr 15 01:11:57 PM PDT 24
Finished Apr 15 01:12:20 PM PDT 24
Peak memory 256100 kb
Host smart-5cdd2a60-3a33-43b1-bc20-da1937b22391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34443
60957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3444360957
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.411239315
Short name T555
Test name
Test status
Simulation time 99998665954 ps
CPU time 2101.38 seconds
Started Apr 15 01:11:58 PM PDT 24
Finished Apr 15 01:47:00 PM PDT 24
Peak memory 281656 kb
Host smart-24ea4455-4720-414c-8177-8e8096d33952
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411239315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.411239315
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3445010283
Short name T113
Test name
Test status
Simulation time 16604290210 ps
CPU time 1332.19 seconds
Started Apr 15 01:11:58 PM PDT 24
Finished Apr 15 01:34:11 PM PDT 24
Peak memory 281828 kb
Host smart-22ddaab2-a14f-4d30-806c-d1e62ecd8f5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445010283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3445010283
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.745490518
Short name T480
Test name
Test status
Simulation time 1831714192 ps
CPU time 27 seconds
Started Apr 15 01:11:53 PM PDT 24
Finished Apr 15 01:12:21 PM PDT 24
Peak memory 255020 kb
Host smart-ae6a9edb-1883-43bd-8385-b933a53247ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74549
0518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.745490518
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.4147274247
Short name T286
Test name
Test status
Simulation time 1126083094 ps
CPU time 43.32 seconds
Started Apr 15 01:11:56 PM PDT 24
Finished Apr 15 01:12:40 PM PDT 24
Peak memory 254968 kb
Host smart-04ddb414-6df7-4267-81e7-4701cc355d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41472
74247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.4147274247
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.674428392
Short name T37
Test name
Test status
Simulation time 205629628 ps
CPU time 11.72 seconds
Started Apr 15 01:11:59 PM PDT 24
Finished Apr 15 01:12:12 PM PDT 24
Peak memory 256200 kb
Host smart-d8355474-fd99-4bb5-8453-7dcea3bed052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67442
8392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.674428392
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1294882719
Short name T676
Test name
Test status
Simulation time 401370842 ps
CPU time 21.49 seconds
Started Apr 15 01:11:58 PM PDT 24
Finished Apr 15 01:12:20 PM PDT 24
Peak memory 256372 kb
Host smart-f1527583-6eb4-437f-a2ac-c17a046c5c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12948
82719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1294882719
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.44905786
Short name T380
Test name
Test status
Simulation time 16841970046 ps
CPU time 1325.19 seconds
Started Apr 15 01:11:55 PM PDT 24
Finished Apr 15 01:34:02 PM PDT 24
Peak memory 289680 kb
Host smart-1dd2b871-6b85-4802-9846-5da78b0ae1d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44905786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_hand
ler_stress_all.44905786
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1464869331
Short name T87
Test name
Test status
Simulation time 30438797325 ps
CPU time 1847.67 seconds
Started Apr 15 01:11:56 PM PDT 24
Finished Apr 15 01:42:45 PM PDT 24
Peak memory 290048 kb
Host smart-866b9935-87c8-4441-b3c1-fcf4adb0737b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464869331 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1464869331
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.568773873
Short name T293
Test name
Test status
Simulation time 3370182435 ps
CPU time 86.4 seconds
Started Apr 15 01:11:59 PM PDT 24
Finished Apr 15 01:13:26 PM PDT 24
Peak memory 256916 kb
Host smart-011df580-4c9d-4499-82ab-7c0ab9c93a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56877
3873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.568773873
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3959332978
Short name T687
Test name
Test status
Simulation time 396048004 ps
CPU time 28.69 seconds
Started Apr 15 01:12:04 PM PDT 24
Finished Apr 15 01:12:33 PM PDT 24
Peak memory 249376 kb
Host smart-1ce3d0b0-a121-4022-9e85-bf7b4be2cac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39593
32978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3959332978
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.222402098
Short name T39
Test name
Test status
Simulation time 16368085411 ps
CPU time 1042.97 seconds
Started Apr 15 01:12:02 PM PDT 24
Finished Apr 15 01:29:26 PM PDT 24
Peak memory 289108 kb
Host smart-5e70038b-245a-4a04-bd2b-e45b20ca3d68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222402098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.222402098
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.494086490
Short name T315
Test name
Test status
Simulation time 24100093329 ps
CPU time 239.62 seconds
Started Apr 15 01:11:59 PM PDT 24
Finished Apr 15 01:16:00 PM PDT 24
Peak memory 248372 kb
Host smart-13faac32-1b18-47de-a9fc-abbd85e590aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494086490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.494086490
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2267737544
Short name T484
Test name
Test status
Simulation time 1660517856 ps
CPU time 37.2 seconds
Started Apr 15 01:11:52 PM PDT 24
Finished Apr 15 01:12:30 PM PDT 24
Peak memory 256220 kb
Host smart-32cb02ea-456d-497f-bc37-11fbd4be1b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22677
37544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2267737544
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2784618165
Short name T226
Test name
Test status
Simulation time 4449036621 ps
CPU time 75.71 seconds
Started Apr 15 01:12:03 PM PDT 24
Finished Apr 15 01:13:19 PM PDT 24
Peak memory 249052 kb
Host smart-09219085-3895-4f82-9835-9c31bb9cd4a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27846
18165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2784618165
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3447157474
Short name T362
Test name
Test status
Simulation time 396594972 ps
CPU time 11.01 seconds
Started Apr 15 01:11:54 PM PDT 24
Finished Apr 15 01:12:05 PM PDT 24
Peak memory 249036 kb
Host smart-ed21edb7-c036-4055-ba5e-692043209b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34471
57474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3447157474
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.325477752
Short name T397
Test name
Test status
Simulation time 4459165243 ps
CPU time 256.14 seconds
Started Apr 15 01:12:03 PM PDT 24
Finished Apr 15 01:16:20 PM PDT 24
Peak memory 251344 kb
Host smart-cf7e1e79-34b0-475e-ae8a-2e0af639da0e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325477752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.325477752
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1244989077
Short name T237
Test name
Test status
Simulation time 66061270724 ps
CPU time 1989.63 seconds
Started Apr 15 01:11:57 PM PDT 24
Finished Apr 15 01:45:08 PM PDT 24
Peak memory 290048 kb
Host smart-9b948286-aa1e-4a99-b230-7efb019bd763
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244989077 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1244989077
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3569575266
Short name T230
Test name
Test status
Simulation time 61032238178 ps
CPU time 2027.8 seconds
Started Apr 15 01:11:56 PM PDT 24
Finished Apr 15 01:45:45 PM PDT 24
Peak memory 289068 kb
Host smart-e262fe0e-4d1a-48f1-8724-ecc4b14b7401
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569575266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3569575266
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3815974949
Short name T698
Test name
Test status
Simulation time 2786604313 ps
CPU time 92.53 seconds
Started Apr 15 01:12:00 PM PDT 24
Finished Apr 15 01:13:34 PM PDT 24
Peak memory 257372 kb
Host smart-a2455ced-96c7-4bed-ae88-7c6510c43425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38159
74949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3815974949
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.637864704
Short name T66
Test name
Test status
Simulation time 339655990 ps
CPU time 25.47 seconds
Started Apr 15 01:11:58 PM PDT 24
Finished Apr 15 01:12:24 PM PDT 24
Peak memory 249336 kb
Host smart-1742f625-3f6c-4b7d-a69c-4f6de1d31c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63786
4704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.637864704
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2132316439
Short name T338
Test name
Test status
Simulation time 21958358137 ps
CPU time 617.27 seconds
Started Apr 15 01:12:00 PM PDT 24
Finished Apr 15 01:22:18 PM PDT 24
Peak memory 265536 kb
Host smart-5ab51484-7ec8-4f70-a2cc-7b730ff94277
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132316439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2132316439
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1825167073
Short name T648
Test name
Test status
Simulation time 19024001141 ps
CPU time 1501.64 seconds
Started Apr 15 01:12:04 PM PDT 24
Finished Apr 15 01:37:06 PM PDT 24
Peak memory 289100 kb
Host smart-a740ddc0-4eb1-416d-9ded-d79cd1dddeaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825167073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1825167073
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2365702384
Short name T317
Test name
Test status
Simulation time 23346034860 ps
CPU time 286.48 seconds
Started Apr 15 01:11:59 PM PDT 24
Finished Apr 15 01:16:46 PM PDT 24
Peak memory 248328 kb
Host smart-63f8b3a9-7004-4352-b6d0-b437a1964f5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365702384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2365702384
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1056482499
Short name T373
Test name
Test status
Simulation time 603822681 ps
CPU time 14.13 seconds
Started Apr 15 01:11:59 PM PDT 24
Finished Apr 15 01:12:14 PM PDT 24
Peak memory 249072 kb
Host smart-b5330f70-1b2c-41a9-ae97-06517fd73367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10564
82499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1056482499
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.902693247
Short name T48
Test name
Test status
Simulation time 889583921 ps
CPU time 67.83 seconds
Started Apr 15 01:12:01 PM PDT 24
Finished Apr 15 01:13:10 PM PDT 24
Peak memory 256600 kb
Host smart-5d25f0d8-be11-4056-8814-5fb87d1d85e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90269
3247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.902693247
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1399943754
Short name T510
Test name
Test status
Simulation time 907295593 ps
CPU time 16.04 seconds
Started Apr 15 01:11:59 PM PDT 24
Finished Apr 15 01:12:16 PM PDT 24
Peak memory 249076 kb
Host smart-699aa238-48cb-403d-a999-e5f1aa37c9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13999
43754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1399943754
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.237238259
Short name T399
Test name
Test status
Simulation time 4895236889 ps
CPU time 79.48 seconds
Started Apr 15 01:12:03 PM PDT 24
Finished Apr 15 01:13:24 PM PDT 24
Peak memory 249116 kb
Host smart-58f543f2-54df-477d-8d87-27b3a20aec80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23723
8259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.237238259
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.4109109371
Short name T586
Test name
Test status
Simulation time 85613597451 ps
CPU time 1685.14 seconds
Started Apr 15 01:11:57 PM PDT 24
Finished Apr 15 01:40:04 PM PDT 24
Peak memory 300764 kb
Host smart-0c94ed51-a091-4080-b479-dcfd8dee2418
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109109371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.4109109371
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.348621044
Short name T238
Test name
Test status
Simulation time 100397093141 ps
CPU time 3078.21 seconds
Started Apr 15 01:11:58 PM PDT 24
Finished Apr 15 02:03:17 PM PDT 24
Peak memory 306228 kb
Host smart-89fc25c0-7990-40a7-986e-7cd9cd48a959
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348621044 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.348621044
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2977959378
Short name T393
Test name
Test status
Simulation time 138097844461 ps
CPU time 1864.87 seconds
Started Apr 15 01:12:01 PM PDT 24
Finished Apr 15 01:43:07 PM PDT 24
Peak memory 268648 kb
Host smart-1ed686b3-1ed5-4de3-a352-240301bb7a6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977959378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2977959378
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3389862426
Short name T83
Test name
Test status
Simulation time 7428489438 ps
CPU time 153.62 seconds
Started Apr 15 01:12:06 PM PDT 24
Finished Apr 15 01:14:40 PM PDT 24
Peak memory 252248 kb
Host smart-ed056767-e023-46cc-bbe9-523927dd25f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33898
62426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3389862426
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2827942182
Short name T534
Test name
Test status
Simulation time 640539600 ps
CPU time 32.98 seconds
Started Apr 15 01:12:03 PM PDT 24
Finished Apr 15 01:12:36 PM PDT 24
Peak memory 255780 kb
Host smart-42448cd2-fb04-41b2-b43a-e8c8251c19f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28279
42182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2827942182
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.537629184
Short name T539
Test name
Test status
Simulation time 65790911399 ps
CPU time 2050.85 seconds
Started Apr 15 01:12:01 PM PDT 24
Finished Apr 15 01:46:13 PM PDT 24
Peak memory 288808 kb
Host smart-7d0ea39d-43fd-42ba-b987-290a2ce2ecb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537629184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.537629184
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.4202452579
Short name T322
Test name
Test status
Simulation time 102234868777 ps
CPU time 565.04 seconds
Started Apr 15 01:12:02 PM PDT 24
Finished Apr 15 01:21:28 PM PDT 24
Peak memory 248040 kb
Host smart-16789d06-6fd2-4d9a-be4c-21509f277ece
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202452579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4202452579
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.770611688
Short name T376
Test name
Test status
Simulation time 3623272414 ps
CPU time 61.76 seconds
Started Apr 15 01:12:04 PM PDT 24
Finished Apr 15 01:13:06 PM PDT 24
Peak memory 249108 kb
Host smart-f70c8ae2-5c32-488a-a95d-17b395502dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77061
1688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.770611688
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.66612078
Short name T530
Test name
Test status
Simulation time 315260085 ps
CPU time 35.53 seconds
Started Apr 15 01:11:55 PM PDT 24
Finished Apr 15 01:12:32 PM PDT 24
Peak memory 248980 kb
Host smart-be7d8b15-b9f4-45d7-b963-c7a116f0ed92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66612
078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.66612078
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1976436653
Short name T460
Test name
Test status
Simulation time 74699359 ps
CPU time 8.93 seconds
Started Apr 15 01:12:00 PM PDT 24
Finished Apr 15 01:12:10 PM PDT 24
Peak memory 255256 kb
Host smart-ee39b312-9e68-4c7d-8f2d-98f02c57492a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19764
36653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1976436653
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2747692151
Short name T414
Test name
Test status
Simulation time 611469025 ps
CPU time 18.79 seconds
Started Apr 15 01:12:00 PM PDT 24
Finished Apr 15 01:12:20 PM PDT 24
Peak memory 257176 kb
Host smart-5c2239f7-37e5-4278-8b37-bb59d98b7c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27476
92151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2747692151
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.186023964
Short name T667
Test name
Test status
Simulation time 29455053099 ps
CPU time 1411.11 seconds
Started Apr 15 01:12:01 PM PDT 24
Finished Apr 15 01:35:33 PM PDT 24
Peak memory 288304 kb
Host smart-3b2ba6a9-3742-4877-b9c3-ab48914989b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186023964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.186023964
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.270432283
Short name T680
Test name
Test status
Simulation time 6983803817 ps
CPU time 657.28 seconds
Started Apr 15 01:12:03 PM PDT 24
Finished Apr 15 01:23:01 PM PDT 24
Peak memory 265520 kb
Host smart-e1e122ea-e41b-4bbc-864b-9624f5b79abc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270432283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.270432283
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2184121159
Short name T421
Test name
Test status
Simulation time 1198840180 ps
CPU time 36.09 seconds
Started Apr 15 01:12:05 PM PDT 24
Finished Apr 15 01:12:42 PM PDT 24
Peak memory 256956 kb
Host smart-e4dcb00c-c3a1-4f3f-890a-6836e4d72c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21841
21159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2184121159
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3870019672
Short name T662
Test name
Test status
Simulation time 171589147 ps
CPU time 8.68 seconds
Started Apr 15 01:12:00 PM PDT 24
Finished Apr 15 01:12:10 PM PDT 24
Peak memory 253088 kb
Host smart-366eeeeb-3c73-4f9b-bba1-a6bf49d75c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38700
19672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3870019672
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1923355147
Short name T343
Test name
Test status
Simulation time 28832328835 ps
CPU time 1847.83 seconds
Started Apr 15 01:12:02 PM PDT 24
Finished Apr 15 01:42:51 PM PDT 24
Peak memory 283048 kb
Host smart-3133e183-f84c-4114-bd46-f3c8ebe0c715
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923355147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1923355147
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.4111636045
Short name T430
Test name
Test status
Simulation time 10204537975 ps
CPU time 905.71 seconds
Started Apr 15 01:12:05 PM PDT 24
Finished Apr 15 01:27:11 PM PDT 24
Peak memory 273732 kb
Host smart-5b99a7c3-5cc3-4851-af28-5104901c8227
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111636045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.4111636045
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2178986322
Short name T565
Test name
Test status
Simulation time 568488488 ps
CPU time 28.1 seconds
Started Apr 15 01:11:59 PM PDT 24
Finished Apr 15 01:12:28 PM PDT 24
Peak memory 248940 kb
Host smart-25e2fd1d-5d75-4e88-999d-3c373f451cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21789
86322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2178986322
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2554671601
Short name T570
Test name
Test status
Simulation time 923953133 ps
CPU time 54.02 seconds
Started Apr 15 01:12:02 PM PDT 24
Finished Apr 15 01:12:56 PM PDT 24
Peak memory 256044 kb
Host smart-bc95332e-11eb-4d54-9a0f-0ac7f326275d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25546
71601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2554671601
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3996457354
Short name T46
Test name
Test status
Simulation time 314185063 ps
CPU time 21.95 seconds
Started Apr 15 01:12:03 PM PDT 24
Finished Apr 15 01:12:26 PM PDT 24
Peak memory 247564 kb
Host smart-71f61c7f-5354-4829-8474-7a0bd26b4b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39964
57354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3996457354
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3557354260
Short name T285
Test name
Test status
Simulation time 2485680544 ps
CPU time 76.3 seconds
Started Apr 15 01:11:59 PM PDT 24
Finished Apr 15 01:13:17 PM PDT 24
Peak memory 249112 kb
Host smart-a25ddaa1-cbeb-47ce-837b-eaf404d14eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35573
54260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3557354260
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2437020488
Short name T196
Test name
Test status
Simulation time 35113450 ps
CPU time 2.01 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:11:17 PM PDT 24
Peak memory 249312 kb
Host smart-1cacb7d2-c654-4f68-bce0-3bde8599d288
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2437020488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2437020488
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3637105731
Short name T294
Test name
Test status
Simulation time 246555082497 ps
CPU time 1442.9 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:35:05 PM PDT 24
Peak memory 289824 kb
Host smart-81867256-16ce-454a-a669-db926af08f03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637105731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3637105731
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2589057457
Short name T628
Test name
Test status
Simulation time 2337354113 ps
CPU time 17.31 seconds
Started Apr 15 01:11:01 PM PDT 24
Finished Apr 15 01:11:20 PM PDT 24
Peak memory 249156 kb
Host smart-a85b741b-7c55-4597-b07a-db201223e873
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2589057457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2589057457
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2422383562
Short name T454
Test name
Test status
Simulation time 135061130 ps
CPU time 9.96 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:11:11 PM PDT 24
Peak memory 253204 kb
Host smart-6eaf1e15-fdb7-4168-82cb-38af08094626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24223
83562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2422383562
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1243418068
Short name T261
Test name
Test status
Simulation time 224041581 ps
CPU time 13.47 seconds
Started Apr 15 01:10:59 PM PDT 24
Finished Apr 15 01:11:13 PM PDT 24
Peak memory 249240 kb
Host smart-09c4fc64-d6a5-47cf-8b99-3116a08184dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12434
18068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1243418068
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.572678729
Short name T435
Test name
Test status
Simulation time 16029552255 ps
CPU time 1344.36 seconds
Started Apr 15 01:11:06 PM PDT 24
Finished Apr 15 01:33:32 PM PDT 24
Peak memory 287404 kb
Host smart-96b11135-8ba5-48fb-9243-b332cec4bcf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572678729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.572678729
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3411859066
Short name T314
Test name
Test status
Simulation time 28933086568 ps
CPU time 281.38 seconds
Started Apr 15 01:11:02 PM PDT 24
Finished Apr 15 01:15:45 PM PDT 24
Peak memory 253744 kb
Host smart-8a51d752-9c58-461e-9064-b6e7fcd9c0ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411859066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3411859066
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.258835650
Short name T369
Test name
Test status
Simulation time 967349616 ps
CPU time 16.18 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:11:17 PM PDT 24
Peak memory 249060 kb
Host smart-92ffe0d8-69fd-4e6d-a7ef-669ee5047c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25883
5650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.258835650
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3890675695
Short name T398
Test name
Test status
Simulation time 352495155 ps
CPU time 10.95 seconds
Started Apr 15 01:11:01 PM PDT 24
Finished Apr 15 01:11:14 PM PDT 24
Peak memory 253060 kb
Host smart-76174f56-01ad-45a7-aa7c-aa78ec0f9efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38906
75695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3890675695
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3938161135
Short name T433
Test name
Test status
Simulation time 286197367 ps
CPU time 17.68 seconds
Started Apr 15 01:10:58 PM PDT 24
Finished Apr 15 01:11:17 PM PDT 24
Peak memory 254692 kb
Host smart-26c7b811-abea-4090-b4cc-1b1e2c55080d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39381
61135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3938161135
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3193876771
Short name T583
Test name
Test status
Simulation time 812207335 ps
CPU time 13.26 seconds
Started Apr 15 01:11:09 PM PDT 24
Finished Apr 15 01:11:24 PM PDT 24
Peak memory 249064 kb
Host smart-17b1c71c-abd0-4bbe-827c-77bf9eae459f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31938
76771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3193876771
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.4107359682
Short name T244
Test name
Test status
Simulation time 84115866590 ps
CPU time 1215.72 seconds
Started Apr 15 01:11:03 PM PDT 24
Finished Apr 15 01:31:20 PM PDT 24
Peak memory 289288 kb
Host smart-7945f8cd-fcb6-4ad8-b9da-e3f1ca604ab3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107359682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.4107359682
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2931806570
Short name T544
Test name
Test status
Simulation time 373689004 ps
CPU time 25.77 seconds
Started Apr 15 01:12:06 PM PDT 24
Finished Apr 15 01:12:32 PM PDT 24
Peak memory 256020 kb
Host smart-f32775be-209c-45da-b7ab-b17a07503594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318
06570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2931806570
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2181353065
Short name T396
Test name
Test status
Simulation time 222453963 ps
CPU time 19.32 seconds
Started Apr 15 01:12:02 PM PDT 24
Finished Apr 15 01:12:22 PM PDT 24
Peak memory 249048 kb
Host smart-c383d7fc-fce6-4785-b220-c24daab3f9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21813
53065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2181353065
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.248429868
Short name T345
Test name
Test status
Simulation time 59972198047 ps
CPU time 1949.87 seconds
Started Apr 15 01:12:06 PM PDT 24
Finished Apr 15 01:44:37 PM PDT 24
Peak memory 285008 kb
Host smart-560ba6b4-4425-481b-a41a-26c9e12900d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248429868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.248429868
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.834067397
Short name T516
Test name
Test status
Simulation time 117749137212 ps
CPU time 1910.52 seconds
Started Apr 15 01:12:09 PM PDT 24
Finished Apr 15 01:44:01 PM PDT 24
Peak memory 281872 kb
Host smart-2b6e343d-423c-4e6d-8005-ed8a53297a67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834067397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.834067397
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3285729985
Short name T232
Test name
Test status
Simulation time 6763401119 ps
CPU time 285.23 seconds
Started Apr 15 01:12:11 PM PDT 24
Finished Apr 15 01:16:57 PM PDT 24
Peak memory 248068 kb
Host smart-61dab26e-485a-4a64-a1b4-7ed42d348da4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285729985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3285729985
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.665848296
Short name T669
Test name
Test status
Simulation time 4928310489 ps
CPU time 60.32 seconds
Started Apr 15 01:12:05 PM PDT 24
Finished Apr 15 01:13:06 PM PDT 24
Peak memory 256552 kb
Host smart-39260811-d182-4944-b96e-76e8554857cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66584
8296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.665848296
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.862790796
Short name T474
Test name
Test status
Simulation time 1372162939 ps
CPU time 37.8 seconds
Started Apr 15 01:12:03 PM PDT 24
Finished Apr 15 01:12:41 PM PDT 24
Peak memory 256628 kb
Host smart-213dc479-c6f1-4a31-bc6c-a650ac3c9c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86279
0796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.862790796
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.83838649
Short name T263
Test name
Test status
Simulation time 499285210 ps
CPU time 33.45 seconds
Started Apr 15 01:12:10 PM PDT 24
Finished Apr 15 01:12:44 PM PDT 24
Peak memory 256256 kb
Host smart-e9982730-13a6-43c7-bce2-b345336a4623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83838
649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.83838649
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3419270866
Short name T507
Test name
Test status
Simulation time 353969704 ps
CPU time 38.31 seconds
Started Apr 15 01:12:05 PM PDT 24
Finished Apr 15 01:12:44 PM PDT 24
Peak memory 256168 kb
Host smart-35c694e7-e2e9-46a0-9ed2-640c9cbb9230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34192
70866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3419270866
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1076538832
Short name T93
Test name
Test status
Simulation time 4917981305 ps
CPU time 462.16 seconds
Started Apr 15 01:12:08 PM PDT 24
Finished Apr 15 01:19:51 PM PDT 24
Peak memory 265544 kb
Host smart-f87356d3-fbb0-411f-9750-c1a1dbea1794
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076538832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1076538832
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.295958004
Short name T14
Test name
Test status
Simulation time 32074170832 ps
CPU time 1952.4 seconds
Started Apr 15 01:12:10 PM PDT 24
Finished Apr 15 01:44:43 PM PDT 24
Peak memory 273768 kb
Host smart-8f6b4364-b085-4e76-9d00-af6409b4fed7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295958004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.295958004
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1942875858
Short name T506
Test name
Test status
Simulation time 811794751 ps
CPU time 81.07 seconds
Started Apr 15 01:12:11 PM PDT 24
Finished Apr 15 01:13:32 PM PDT 24
Peak memory 256716 kb
Host smart-ef30fd19-7382-4631-8f04-0a6fdb995743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19428
75858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1942875858
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1401808000
Short name T429
Test name
Test status
Simulation time 1101046451 ps
CPU time 28.03 seconds
Started Apr 15 01:12:08 PM PDT 24
Finished Apr 15 01:12:37 PM PDT 24
Peak memory 248960 kb
Host smart-6831faf0-b34f-496b-8870-e7d8f8b2d05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14018
08000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1401808000
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1517956151
Short name T339
Test name
Test status
Simulation time 7032734475 ps
CPU time 661.26 seconds
Started Apr 15 01:12:12 PM PDT 24
Finished Apr 15 01:23:14 PM PDT 24
Peak memory 265512 kb
Host smart-21eafaed-8ccd-4b04-9630-98b4127fba2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517956151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1517956151
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3652588617
Short name T388
Test name
Test status
Simulation time 46552633472 ps
CPU time 1498.65 seconds
Started Apr 15 01:12:14 PM PDT 24
Finished Apr 15 01:37:13 PM PDT 24
Peak memory 272876 kb
Host smart-1b43a292-c469-4f40-9532-1449105a4e12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652588617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3652588617
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3900172311
Short name T673
Test name
Test status
Simulation time 343820365 ps
CPU time 20.03 seconds
Started Apr 15 01:12:09 PM PDT 24
Finished Apr 15 01:12:29 PM PDT 24
Peak memory 255148 kb
Host smart-08f02747-0345-4d5a-bbb8-a7eef16a12e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39001
72311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3900172311
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.215672880
Short name T600
Test name
Test status
Simulation time 338061823 ps
CPU time 31.2 seconds
Started Apr 15 01:12:10 PM PDT 24
Finished Apr 15 01:12:42 PM PDT 24
Peak memory 249064 kb
Host smart-788c4532-3675-48ba-88ff-792e93fad65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21567
2880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.215672880
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3539055410
Short name T402
Test name
Test status
Simulation time 365006649 ps
CPU time 12.94 seconds
Started Apr 15 01:12:12 PM PDT 24
Finished Apr 15 01:12:25 PM PDT 24
Peak memory 247640 kb
Host smart-c45d9d98-285a-4447-9541-7a36c60c5528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35390
55410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3539055410
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1802656457
Short name T406
Test name
Test status
Simulation time 56426188 ps
CPU time 7 seconds
Started Apr 15 01:12:10 PM PDT 24
Finished Apr 15 01:12:17 PM PDT 24
Peak memory 249060 kb
Host smart-98c4826a-c868-4e6f-84e7-d197740d963b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18026
56457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1802656457
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3016288431
Short name T62
Test name
Test status
Simulation time 60241588941 ps
CPU time 1522.12 seconds
Started Apr 15 01:12:15 PM PDT 24
Finished Apr 15 01:37:37 PM PDT 24
Peak memory 289440 kb
Host smart-8f4cf86e-065f-44ba-acb0-b2865149dd39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016288431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3016288431
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1961271634
Short name T489
Test name
Test status
Simulation time 1459664019 ps
CPU time 77.08 seconds
Started Apr 15 01:12:13 PM PDT 24
Finished Apr 15 01:13:31 PM PDT 24
Peak memory 248860 kb
Host smart-6bccf3cd-61b5-499e-bd0d-dd7d840c6951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19612
71634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1961271634
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3236276500
Short name T417
Test name
Test status
Simulation time 1514139526 ps
CPU time 41.45 seconds
Started Apr 15 01:12:12 PM PDT 24
Finished Apr 15 01:12:55 PM PDT 24
Peak memory 255136 kb
Host smart-f60430d7-3ab8-475a-8880-82bbd583c1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32362
76500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3236276500
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.141183622
Short name T348
Test name
Test status
Simulation time 78596867153 ps
CPU time 1130.08 seconds
Started Apr 15 01:12:16 PM PDT 24
Finished Apr 15 01:31:07 PM PDT 24
Peak memory 266572 kb
Host smart-43c7f046-2aa2-4454-96ad-7c4a84537737
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141183622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.141183622
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.533895905
Short name T182
Test name
Test status
Simulation time 38915932569 ps
CPU time 2142.69 seconds
Started Apr 15 01:12:22 PM PDT 24
Finished Apr 15 01:48:06 PM PDT 24
Peak memory 281792 kb
Host smart-4e940a74-3639-486f-a224-b5d494b83fbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533895905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.533895905
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3330566093
Short name T407
Test name
Test status
Simulation time 2760903071 ps
CPU time 46.66 seconds
Started Apr 15 01:12:12 PM PDT 24
Finished Apr 15 01:12:59 PM PDT 24
Peak memory 256128 kb
Host smart-d37cee90-b44c-4fc7-ae55-5e48d67ac70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33305
66093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3330566093
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.202288712
Short name T611
Test name
Test status
Simulation time 192499160 ps
CPU time 8.85 seconds
Started Apr 15 01:12:13 PM PDT 24
Finished Apr 15 01:12:22 PM PDT 24
Peak memory 251996 kb
Host smart-484e6a37-ef75-4f02-a1a5-75d62cde31c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20228
8712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.202288712
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1940406059
Short name T702
Test name
Test status
Simulation time 353233056 ps
CPU time 20.9 seconds
Started Apr 15 01:12:14 PM PDT 24
Finished Apr 15 01:12:36 PM PDT 24
Peak memory 247640 kb
Host smart-8f43546b-08d5-4cef-8b26-798a06d71e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19404
06059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1940406059
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2553813515
Short name T374
Test name
Test status
Simulation time 168884669 ps
CPU time 6.2 seconds
Started Apr 15 01:12:12 PM PDT 24
Finished Apr 15 01:12:19 PM PDT 24
Peak memory 240868 kb
Host smart-845f3341-835f-428f-9aa7-8d5bebfed9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25538
13515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2553813515
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.499338742
Short name T90
Test name
Test status
Simulation time 55539527790 ps
CPU time 1771.96 seconds
Started Apr 15 01:12:14 PM PDT 24
Finished Apr 15 01:41:47 PM PDT 24
Peak memory 289452 kb
Host smart-e72b1107-a24a-4e2d-90c3-51e1936099df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499338742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.499338742
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3796847219
Short name T442
Test name
Test status
Simulation time 156298528052 ps
CPU time 3875.37 seconds
Started Apr 15 01:12:13 PM PDT 24
Finished Apr 15 02:16:49 PM PDT 24
Peak memory 322340 kb
Host smart-4cedfd89-e443-44e3-9f45-a394e016b651
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796847219 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3796847219
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.434708133
Short name T408
Test name
Test status
Simulation time 51706133965 ps
CPU time 1512.75 seconds
Started Apr 15 01:12:16 PM PDT 24
Finished Apr 15 01:37:29 PM PDT 24
Peak memory 289016 kb
Host smart-ad2843b3-a806-47e4-96c9-551d24253fab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434708133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.434708133
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.170705424
Short name T33
Test name
Test status
Simulation time 5017910717 ps
CPU time 84.89 seconds
Started Apr 15 01:12:18 PM PDT 24
Finished Apr 15 01:13:44 PM PDT 24
Peak memory 256996 kb
Host smart-6ea445a2-80f8-4553-b0e8-013ab80f0fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17070
5424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.170705424
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1788665298
Short name T584
Test name
Test status
Simulation time 27853833 ps
CPU time 3.6 seconds
Started Apr 15 01:12:21 PM PDT 24
Finished Apr 15 01:12:25 PM PDT 24
Peak memory 239220 kb
Host smart-6a4754ef-8011-4e87-9412-44288f3b3a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17886
65298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1788665298
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1310773590
Short name T330
Test name
Test status
Simulation time 18815884404 ps
CPU time 686.53 seconds
Started Apr 15 01:12:16 PM PDT 24
Finished Apr 15 01:23:43 PM PDT 24
Peak memory 265520 kb
Host smart-6245b417-24a1-4829-bf08-58c10faa24ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310773590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1310773590
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.872890385
Short name T24
Test name
Test status
Simulation time 51893810668 ps
CPU time 1355.04 seconds
Started Apr 15 01:12:15 PM PDT 24
Finished Apr 15 01:34:51 PM PDT 24
Peak memory 289388 kb
Host smart-36ecf1b0-4a19-4be3-a02e-8c2bf1464ecc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872890385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.872890385
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1171908033
Short name T309
Test name
Test status
Simulation time 88019998430 ps
CPU time 558.85 seconds
Started Apr 15 01:12:17 PM PDT 24
Finished Apr 15 01:21:37 PM PDT 24
Peak memory 247312 kb
Host smart-16c40d73-2660-4f5a-b51b-f573f28b469a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171908033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1171908033
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.338780169
Short name T370
Test name
Test status
Simulation time 474571207 ps
CPU time 26.69 seconds
Started Apr 15 01:12:17 PM PDT 24
Finished Apr 15 01:12:44 PM PDT 24
Peak memory 249072 kb
Host smart-85a0f580-8ab4-419b-99af-b7c6bddea2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33878
0169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.338780169
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3044261283
Short name T78
Test name
Test status
Simulation time 473422760 ps
CPU time 9.26 seconds
Started Apr 15 01:12:16 PM PDT 24
Finished Apr 15 01:12:26 PM PDT 24
Peak memory 247456 kb
Host smart-7f2df9dd-726f-4351-8878-df7126d9ddbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30442
61283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3044261283
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.358216502
Short name T36
Test name
Test status
Simulation time 1291200666 ps
CPU time 40.77 seconds
Started Apr 15 01:12:18 PM PDT 24
Finished Apr 15 01:12:59 PM PDT 24
Peak memory 256048 kb
Host smart-0f19f265-1756-4095-a051-4545c5168097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35821
6502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.358216502
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3125447617
Short name T456
Test name
Test status
Simulation time 1327724894 ps
CPU time 7.94 seconds
Started Apr 15 01:12:20 PM PDT 24
Finished Apr 15 01:12:29 PM PDT 24
Peak memory 251012 kb
Host smart-f92bd972-8210-4666-82ba-82a27567c95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31254
47617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3125447617
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3283200520
Short name T636
Test name
Test status
Simulation time 114702449700 ps
CPU time 1853.25 seconds
Started Apr 15 01:12:22 PM PDT 24
Finished Apr 15 01:43:17 PM PDT 24
Peak memory 285932 kb
Host smart-6d120a36-4b4d-4661-a6ed-cb5daea19f5f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283200520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3283200520
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.314085167
Short name T41
Test name
Test status
Simulation time 81440202821 ps
CPU time 4611.61 seconds
Started Apr 15 01:12:22 PM PDT 24
Finished Apr 15 02:29:15 PM PDT 24
Peak memory 306228 kb
Host smart-e2020fd2-574d-456a-95cc-d7e315d1e899
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314085167 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.314085167
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.593620023
Short name T678
Test name
Test status
Simulation time 43411601141 ps
CPU time 1066.3 seconds
Started Apr 15 01:12:20 PM PDT 24
Finished Apr 15 01:30:07 PM PDT 24
Peak memory 273696 kb
Host smart-22bc5922-4835-4f37-a8b1-b9d13899959f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593620023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.593620023
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3173754411
Short name T493
Test name
Test status
Simulation time 1298236610 ps
CPU time 72.84 seconds
Started Apr 15 01:12:19 PM PDT 24
Finished Apr 15 01:13:33 PM PDT 24
Peak memory 256800 kb
Host smart-bb97ca4d-9cf7-434f-9d4a-efff6cca9e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31737
54411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3173754411
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3742072554
Short name T663
Test name
Test status
Simulation time 76613062 ps
CPU time 8.37 seconds
Started Apr 15 01:12:22 PM PDT 24
Finished Apr 15 01:12:31 PM PDT 24
Peak memory 249516 kb
Host smart-4ccac136-7dfa-4c34-890d-86d314e5c4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37420
72554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3742072554
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2339848871
Short name T531
Test name
Test status
Simulation time 58743458805 ps
CPU time 819.41 seconds
Started Apr 15 01:12:21 PM PDT 24
Finished Apr 15 01:26:02 PM PDT 24
Peak memory 273096 kb
Host smart-6c94e10b-b2d1-40a3-8818-965135af4df7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339848871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2339848871
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.156104247
Short name T670
Test name
Test status
Simulation time 24303089373 ps
CPU time 1329.03 seconds
Started Apr 15 01:12:22 PM PDT 24
Finished Apr 15 01:34:32 PM PDT 24
Peak memory 273252 kb
Host smart-ad6c4ba1-b0df-4bd4-9395-b4b7d5e56215
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156104247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.156104247
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.685476420
Short name T313
Test name
Test status
Simulation time 5200523937 ps
CPU time 113.77 seconds
Started Apr 15 01:12:22 PM PDT 24
Finished Apr 15 01:14:17 PM PDT 24
Peak memory 248360 kb
Host smart-bba4c100-c11d-4d78-8406-b11d8c408e23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685476420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.685476420
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1131304161
Short name T612
Test name
Test status
Simulation time 237977273 ps
CPU time 24.16 seconds
Started Apr 15 01:12:20 PM PDT 24
Finished Apr 15 01:12:45 PM PDT 24
Peak memory 256208 kb
Host smart-3bb82909-2f0d-473a-b70d-95abd007c1fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11313
04161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1131304161
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2935498647
Short name T391
Test name
Test status
Simulation time 16647259730 ps
CPU time 60.2 seconds
Started Apr 15 01:12:19 PM PDT 24
Finished Apr 15 01:13:20 PM PDT 24
Peak memory 255608 kb
Host smart-33ff8987-11d2-4992-aa38-4e8f9cd0121b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29354
98647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2935498647
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1789027802
Short name T594
Test name
Test status
Simulation time 1790610569 ps
CPU time 24.5 seconds
Started Apr 15 01:12:22 PM PDT 24
Finished Apr 15 01:12:48 PM PDT 24
Peak memory 249056 kb
Host smart-14cf2021-5f51-4ce8-8284-4c9028684efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17890
27802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1789027802
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3234197858
Short name T629
Test name
Test status
Simulation time 54421171131 ps
CPU time 1273.95 seconds
Started Apr 15 01:12:22 PM PDT 24
Finished Apr 15 01:33:37 PM PDT 24
Peak memory 289240 kb
Host smart-2f84d74e-8bea-4c97-8f29-545b0b424b48
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234197858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3234197858
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2158314095
Short name T254
Test name
Test status
Simulation time 71040614399 ps
CPU time 1629.4 seconds
Started Apr 15 01:12:20 PM PDT 24
Finished Apr 15 01:39:31 PM PDT 24
Peak memory 298452 kb
Host smart-56d9e117-b0d8-49a5-b066-815966ec071e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158314095 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2158314095
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.886302996
Short name T413
Test name
Test status
Simulation time 113223568778 ps
CPU time 1747.67 seconds
Started Apr 15 01:12:26 PM PDT 24
Finished Apr 15 01:41:34 PM PDT 24
Peak memory 267872 kb
Host smart-6c7c111a-9553-4879-8dbb-516221d58b0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886302996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.886302996
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.847504763
Short name T217
Test name
Test status
Simulation time 95770307257 ps
CPU time 350.17 seconds
Started Apr 15 01:12:22 PM PDT 24
Finished Apr 15 01:18:13 PM PDT 24
Peak memory 255580 kb
Host smart-d27a3abf-b4ae-4c43-9233-ef70f742d385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84750
4763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.847504763
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.740967178
Short name T524
Test name
Test status
Simulation time 1091873652 ps
CPU time 30.43 seconds
Started Apr 15 01:12:22 PM PDT 24
Finished Apr 15 01:12:53 PM PDT 24
Peak memory 248980 kb
Host smart-8fdbeeb0-f197-4050-8a6a-7fdeb19b5a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74096
7178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.740967178
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3826581852
Short name T85
Test name
Test status
Simulation time 11635795892 ps
CPU time 749.12 seconds
Started Apr 15 01:12:25 PM PDT 24
Finished Apr 15 01:24:55 PM PDT 24
Peak memory 273068 kb
Host smart-f740fafd-48a2-4537-98dd-1e4a2807bd68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826581852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3826581852
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2124644835
Short name T437
Test name
Test status
Simulation time 4304676314 ps
CPU time 176.48 seconds
Started Apr 15 01:12:27 PM PDT 24
Finished Apr 15 01:15:25 PM PDT 24
Peak memory 248296 kb
Host smart-a03a8246-6777-4319-9f52-2c9f84449843
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124644835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2124644835
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1711087284
Short name T573
Test name
Test status
Simulation time 784412208 ps
CPU time 56.92 seconds
Started Apr 15 01:12:21 PM PDT 24
Finished Apr 15 01:13:19 PM PDT 24
Peak memory 249060 kb
Host smart-11aa23a4-8ff5-49e5-aa46-b77ca2e27d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17110
87284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1711087284
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.999963138
Short name T95
Test name
Test status
Simulation time 312156107 ps
CPU time 24.18 seconds
Started Apr 15 01:12:21 PM PDT 24
Finished Apr 15 01:12:46 PM PDT 24
Peak memory 254420 kb
Host smart-304103ea-7c82-4d61-931a-ad65ca5ced16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99996
3138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.999963138
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1306417417
Short name T438
Test name
Test status
Simulation time 577273893 ps
CPU time 40.73 seconds
Started Apr 15 01:12:30 PM PDT 24
Finished Apr 15 01:13:11 PM PDT 24
Peak memory 255632 kb
Host smart-d99e238e-434a-4319-aa7b-12bd808c37d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13064
17417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1306417417
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.4132853999
Short name T693
Test name
Test status
Simulation time 988639925 ps
CPU time 41.89 seconds
Started Apr 15 01:12:22 PM PDT 24
Finished Apr 15 01:13:05 PM PDT 24
Peak memory 255896 kb
Host smart-d2340d0a-ceb5-4b8a-a95e-34104ef46ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41328
53999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.4132853999
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1124768633
Short name T686
Test name
Test status
Simulation time 71841853274 ps
CPU time 3679.2 seconds
Started Apr 15 01:12:29 PM PDT 24
Finished Apr 15 02:13:49 PM PDT 24
Peak memory 306500 kb
Host smart-82552c28-2de1-4715-9937-572c94b39250
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124768633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1124768633
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2087343102
Short name T239
Test name
Test status
Simulation time 552430015636 ps
CPU time 8413.75 seconds
Started Apr 15 01:12:27 PM PDT 24
Finished Apr 15 03:32:43 PM PDT 24
Peak memory 338132 kb
Host smart-1834de1d-498d-486a-9026-487639306557
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087343102 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2087343102
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1020652809
Short name T13
Test name
Test status
Simulation time 26523759917 ps
CPU time 1164.65 seconds
Started Apr 15 01:12:26 PM PDT 24
Finished Apr 15 01:31:52 PM PDT 24
Peak memory 273128 kb
Host smart-a7bd74b9-2616-48eb-a0cc-bb988e721e9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020652809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1020652809
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3079081569
Short name T675
Test name
Test status
Simulation time 1822349214 ps
CPU time 71.22 seconds
Started Apr 15 01:12:27 PM PDT 24
Finished Apr 15 01:13:40 PM PDT 24
Peak memory 248840 kb
Host smart-dd32aa42-b12b-4132-b24c-a8dd1e896713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30790
81569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3079081569
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.347498469
Short name T450
Test name
Test status
Simulation time 58633391 ps
CPU time 5.86 seconds
Started Apr 15 01:12:27 PM PDT 24
Finished Apr 15 01:12:34 PM PDT 24
Peak memory 253004 kb
Host smart-73e19093-bc68-4c76-b7a2-a110cf7d32a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34749
8469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.347498469
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1060902984
Short name T502
Test name
Test status
Simulation time 56938147766 ps
CPU time 1104.49 seconds
Started Apr 15 01:12:26 PM PDT 24
Finished Apr 15 01:30:52 PM PDT 24
Peak memory 289584 kb
Host smart-bffc6606-e644-4f14-8565-896c0a91c9f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060902984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1060902984
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2536710688
Short name T554
Test name
Test status
Simulation time 7039263900 ps
CPU time 157.27 seconds
Started Apr 15 01:12:27 PM PDT 24
Finished Apr 15 01:15:06 PM PDT 24
Peak memory 248068 kb
Host smart-fbf1beb0-c206-4802-95f4-1db3bc206ccd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536710688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2536710688
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.352283333
Short name T419
Test name
Test status
Simulation time 1976169088 ps
CPU time 63.49 seconds
Started Apr 15 01:12:29 PM PDT 24
Finished Apr 15 01:13:33 PM PDT 24
Peak memory 256568 kb
Host smart-98c65aa5-d517-4bb6-857c-489cf45141db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35228
3333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.352283333
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.815197106
Short name T248
Test name
Test status
Simulation time 693108488 ps
CPU time 29.4 seconds
Started Apr 15 01:12:27 PM PDT 24
Finished Apr 15 01:12:58 PM PDT 24
Peak memory 256072 kb
Host smart-403613d2-9a5c-42f7-936c-58edcf701316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81519
7106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.815197106
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3444793955
Short name T59
Test name
Test status
Simulation time 756165789 ps
CPU time 44.82 seconds
Started Apr 15 01:12:30 PM PDT 24
Finished Apr 15 01:13:15 PM PDT 24
Peak memory 249184 kb
Host smart-0e0c4733-46f3-419f-8724-9b1616431a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34447
93955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3444793955
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.889089125
Short name T542
Test name
Test status
Simulation time 25017258051 ps
CPU time 1000.77 seconds
Started Apr 15 01:12:30 PM PDT 24
Finished Apr 15 01:29:12 PM PDT 24
Peak memory 287272 kb
Host smart-0bafa694-9e59-44e4-8cff-add6ea56dabe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889089125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.889089125
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.38225880
Short name T632
Test name
Test status
Simulation time 1795315330 ps
CPU time 48.33 seconds
Started Apr 15 01:12:31 PM PDT 24
Finished Apr 15 01:13:20 PM PDT 24
Peak memory 256936 kb
Host smart-47865ce2-48ef-4890-a92f-c2cedd7c3088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38225
880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.38225880
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2279462028
Short name T683
Test name
Test status
Simulation time 8706631575 ps
CPU time 53.67 seconds
Started Apr 15 01:12:34 PM PDT 24
Finished Apr 15 01:13:29 PM PDT 24
Peak memory 256264 kb
Host smart-2fee48d3-b4a8-4ddf-a3e1-072ccdee7be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22794
62028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2279462028
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.619023073
Short name T340
Test name
Test status
Simulation time 50570326811 ps
CPU time 2670.98 seconds
Started Apr 15 01:12:29 PM PDT 24
Finished Apr 15 01:57:01 PM PDT 24
Peak memory 288048 kb
Host smart-5b99c04c-4d0b-4efb-9749-7d7df531c957
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619023073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.619023073
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.160898338
Short name T409
Test name
Test status
Simulation time 24853012018 ps
CPU time 1666.15 seconds
Started Apr 15 01:12:29 PM PDT 24
Finished Apr 15 01:40:16 PM PDT 24
Peak memory 273196 kb
Host smart-356a1f44-0672-4609-8468-4420abcb3695
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160898338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.160898338
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2729373436
Short name T304
Test name
Test status
Simulation time 3458379201 ps
CPU time 131.87 seconds
Started Apr 15 01:12:32 PM PDT 24
Finished Apr 15 01:14:44 PM PDT 24
Peak memory 248224 kb
Host smart-09489162-94ab-4b77-8dcf-daf5eacd3cce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729373436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2729373436
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3391225680
Short name T363
Test name
Test status
Simulation time 605805293 ps
CPU time 44.18 seconds
Started Apr 15 01:12:34 PM PDT 24
Finished Apr 15 01:13:19 PM PDT 24
Peak memory 249080 kb
Host smart-7b1b2def-6931-41b6-848d-6d574bb00836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33912
25680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3391225680
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1780769780
Short name T504
Test name
Test status
Simulation time 1694581792 ps
CPU time 12.6 seconds
Started Apr 15 01:12:30 PM PDT 24
Finished Apr 15 01:12:43 PM PDT 24
Peak memory 252900 kb
Host smart-86493d44-4976-4d9c-a292-15f9f363c61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17807
69780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1780769780
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.4122193081
Short name T422
Test name
Test status
Simulation time 282624418 ps
CPU time 40.04 seconds
Started Apr 15 01:12:33 PM PDT 24
Finished Apr 15 01:13:13 PM PDT 24
Peak memory 256496 kb
Host smart-7e2dd3fc-86d7-4ee8-a3de-274e366ef2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41221
93081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.4122193081
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1628412596
Short name T622
Test name
Test status
Simulation time 72491983 ps
CPU time 3.88 seconds
Started Apr 15 01:12:30 PM PDT 24
Finished Apr 15 01:12:35 PM PDT 24
Peak memory 240832 kb
Host smart-f44608b2-0f5b-4d10-bbd2-261cb578f78f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16284
12596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1628412596
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3650550781
Short name T76
Test name
Test status
Simulation time 228255823809 ps
CPU time 1716.79 seconds
Started Apr 15 01:12:32 PM PDT 24
Finished Apr 15 01:41:09 PM PDT 24
Peak memory 304196 kb
Host smart-ced7081a-4378-40fd-a700-b9cf95d6062d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650550781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3650550781
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2057778956
Short name T57
Test name
Test status
Simulation time 96173938133 ps
CPU time 1540.26 seconds
Started Apr 15 01:12:29 PM PDT 24
Finished Apr 15 01:38:10 PM PDT 24
Peak memory 284112 kb
Host smart-1feb69f4-612d-4547-ab8f-be257228437f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057778956 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2057778956
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.4256103248
Short name T281
Test name
Test status
Simulation time 136814485479 ps
CPU time 1891.43 seconds
Started Apr 15 01:12:38 PM PDT 24
Finished Apr 15 01:44:11 PM PDT 24
Peak memory 281928 kb
Host smart-67cc456b-5d19-4571-a423-94f11ebbfc8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256103248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.4256103248
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.119092301
Short name T703
Test name
Test status
Simulation time 6011721967 ps
CPU time 168.19 seconds
Started Apr 15 01:12:38 PM PDT 24
Finished Apr 15 01:15:26 PM PDT 24
Peak memory 256872 kb
Host smart-b6bc7fe8-d87a-4855-8dfe-ea5251fa2aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11909
2301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.119092301
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.216634014
Short name T588
Test name
Test status
Simulation time 171875423 ps
CPU time 13.9 seconds
Started Apr 15 01:12:35 PM PDT 24
Finished Apr 15 01:12:50 PM PDT 24
Peak memory 253188 kb
Host smart-a07ffc0c-627e-43a4-9961-1aaf2f0b1b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21663
4014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.216634014
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1837925063
Short name T556
Test name
Test status
Simulation time 64990319541 ps
CPU time 1440.99 seconds
Started Apr 15 01:12:35 PM PDT 24
Finished Apr 15 01:36:37 PM PDT 24
Peak memory 289236 kb
Host smart-7eae59a9-35c1-47b5-b041-89c09556ec53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837925063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1837925063
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2053060375
Short name T88
Test name
Test status
Simulation time 39058958984 ps
CPU time 2280.24 seconds
Started Apr 15 01:12:34 PM PDT 24
Finished Apr 15 01:50:35 PM PDT 24
Peak memory 289560 kb
Host smart-720aa5d4-496a-41f5-8d88-e5e7d6dd294d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053060375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2053060375
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3277361863
Short name T188
Test name
Test status
Simulation time 9206083582 ps
CPU time 340.73 seconds
Started Apr 15 01:12:34 PM PDT 24
Finished Apr 15 01:18:15 PM PDT 24
Peak memory 248212 kb
Host smart-f7d1bad9-38d1-4a69-9f0c-3aa3eab5d1f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277361863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3277361863
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3627652231
Short name T561
Test name
Test status
Simulation time 64927325 ps
CPU time 3.6 seconds
Started Apr 15 01:12:31 PM PDT 24
Finished Apr 15 01:12:35 PM PDT 24
Peak memory 240816 kb
Host smart-1ff5aea7-d7f2-44d8-a56c-658495abd3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36276
52231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3627652231
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1363321364
Short name T92
Test name
Test status
Simulation time 477906247 ps
CPU time 18.13 seconds
Started Apr 15 01:12:30 PM PDT 24
Finished Apr 15 01:12:49 PM PDT 24
Peak memory 247548 kb
Host smart-b3e93d40-c5f6-40e8-b72c-3a34b5afb5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13633
21364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1363321364
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1597422547
Short name T637
Test name
Test status
Simulation time 1582442471 ps
CPU time 24 seconds
Started Apr 15 01:12:37 PM PDT 24
Finished Apr 15 01:13:02 PM PDT 24
Peak memory 255648 kb
Host smart-73b6913f-d985-41d8-8b38-88c00aa1d47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15974
22547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1597422547
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3563418355
Short name T378
Test name
Test status
Simulation time 272119259 ps
CPU time 14.79 seconds
Started Apr 15 01:12:29 PM PDT 24
Finished Apr 15 01:12:45 PM PDT 24
Peak memory 249068 kb
Host smart-a9be4ea7-4291-473a-8801-aa925a5cb388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35634
18355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3563418355
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2263950138
Short name T656
Test name
Test status
Simulation time 319889944448 ps
CPU time 1503.34 seconds
Started Apr 15 01:12:37 PM PDT 24
Finished Apr 15 01:37:41 PM PDT 24
Peak memory 290136 kb
Host smart-f73240fa-cf60-4601-95b6-42c3714be0ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263950138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2263950138
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.628717479
Short name T581
Test name
Test status
Simulation time 173976256595 ps
CPU time 1864.71 seconds
Started Apr 15 01:12:34 PM PDT 24
Finished Apr 15 01:43:40 PM PDT 24
Peak memory 281936 kb
Host smart-83452ecc-9be6-4c0b-b7bf-a10979eb69b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628717479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.628717479
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1798595968
Short name T289
Test name
Test status
Simulation time 1745493604 ps
CPU time 113.2 seconds
Started Apr 15 01:12:35 PM PDT 24
Finished Apr 15 01:14:29 PM PDT 24
Peak memory 256872 kb
Host smart-d1839992-e455-449e-ae6b-9e08ec380756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17985
95968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1798595968
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2257910999
Short name T444
Test name
Test status
Simulation time 624341993 ps
CPU time 3.88 seconds
Started Apr 15 01:12:34 PM PDT 24
Finished Apr 15 01:12:39 PM PDT 24
Peak memory 240880 kb
Host smart-65e8d6d9-a4ab-4891-9dd4-7a3dff75876d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22579
10999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2257910999
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2407846854
Short name T335
Test name
Test status
Simulation time 113079029052 ps
CPU time 2814.62 seconds
Started Apr 15 01:12:34 PM PDT 24
Finished Apr 15 01:59:30 PM PDT 24
Peak memory 287144 kb
Host smart-274b43eb-02df-49ce-9765-f928dc6b8861
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407846854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2407846854
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1418086920
Short name T26
Test name
Test status
Simulation time 14888766386 ps
CPU time 1195.78 seconds
Started Apr 15 01:12:39 PM PDT 24
Finished Apr 15 01:32:35 PM PDT 24
Peak memory 286812 kb
Host smart-e027610f-6194-4067-a0b7-ca15ce0439de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418086920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1418086920
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1758371030
Short name T325
Test name
Test status
Simulation time 12153708479 ps
CPU time 487.09 seconds
Started Apr 15 01:12:38 PM PDT 24
Finished Apr 15 01:20:45 PM PDT 24
Peak memory 247100 kb
Host smart-085f5eaa-92e9-4c2f-ae35-188638a5e882
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758371030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1758371030
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2028344840
Short name T411
Test name
Test status
Simulation time 1069553134 ps
CPU time 18.16 seconds
Started Apr 15 01:12:35 PM PDT 24
Finished Apr 15 01:12:54 PM PDT 24
Peak memory 249056 kb
Host smart-376e39f3-458c-4d12-9875-4dde2decadad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20283
44840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2028344840
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1427529134
Short name T523
Test name
Test status
Simulation time 117217581 ps
CPU time 11.77 seconds
Started Apr 15 01:12:35 PM PDT 24
Finished Apr 15 01:12:47 PM PDT 24
Peak memory 247388 kb
Host smart-f2bfc15e-a1e9-48a1-92ec-a1bffe5248c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14275
29134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1427529134
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3072711294
Short name T635
Test name
Test status
Simulation time 3840961022 ps
CPU time 149.46 seconds
Started Apr 15 01:12:35 PM PDT 24
Finished Apr 15 01:15:05 PM PDT 24
Peak memory 248988 kb
Host smart-e129bb93-798f-4faa-9725-4a4633ee665a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30727
11294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3072711294
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3003742626
Short name T384
Test name
Test status
Simulation time 450267863 ps
CPU time 28.22 seconds
Started Apr 15 01:12:33 PM PDT 24
Finished Apr 15 01:13:02 PM PDT 24
Peak memory 249056 kb
Host smart-220370a6-a3f0-43c5-a224-e7898e77a634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30037
42626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3003742626
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1924506647
Short name T75
Test name
Test status
Simulation time 12811949220 ps
CPU time 298.43 seconds
Started Apr 15 01:12:40 PM PDT 24
Finished Apr 15 01:17:39 PM PDT 24
Peak memory 257340 kb
Host smart-557fc0a7-42e6-4cdb-97f6-885c3e5ac7db
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924506647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1924506647
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1857275485
Short name T211
Test name
Test status
Simulation time 72894605 ps
CPU time 3.66 seconds
Started Apr 15 01:11:02 PM PDT 24
Finished Apr 15 01:11:07 PM PDT 24
Peak memory 249308 kb
Host smart-5b6f30e2-8d81-4c2e-aca7-f928bd8b1bfa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1857275485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1857275485
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.858491994
Short name T513
Test name
Test status
Simulation time 71587014372 ps
CPU time 2209.95 seconds
Started Apr 15 01:11:01 PM PDT 24
Finished Apr 15 01:47:52 PM PDT 24
Peak memory 273752 kb
Host smart-30a15483-bf7d-4686-b611-9366bbcb4876
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858491994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.858491994
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3261660385
Short name T582
Test name
Test status
Simulation time 805083012 ps
CPU time 19.16 seconds
Started Apr 15 01:11:03 PM PDT 24
Finished Apr 15 01:11:24 PM PDT 24
Peak memory 240852 kb
Host smart-7afab9f7-caa2-4e0d-950b-d7d2af5c3074
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3261660385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3261660385
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1313764394
Short name T546
Test name
Test status
Simulation time 3324414316 ps
CPU time 81.72 seconds
Started Apr 15 01:11:09 PM PDT 24
Finished Apr 15 01:12:32 PM PDT 24
Peak memory 257376 kb
Host smart-bda5c72a-8572-4d1b-bda3-ae877ab6ff60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13137
64394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1313764394
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.334117183
Short name T225
Test name
Test status
Simulation time 426183888 ps
CPU time 6.35 seconds
Started Apr 15 01:11:04 PM PDT 24
Finished Apr 15 01:11:11 PM PDT 24
Peak memory 240940 kb
Host smart-f86a38c7-fab7-416b-9145-c55afd2c7522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33411
7183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.334117183
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.439402854
Short name T301
Test name
Test status
Simulation time 52334046449 ps
CPU time 1261.36 seconds
Started Apr 15 01:11:09 PM PDT 24
Finished Apr 15 01:32:11 PM PDT 24
Peak memory 281944 kb
Host smart-266016fb-f30e-4edb-96da-ddee80192936
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439402854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.439402854
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.715907627
Short name T279
Test name
Test status
Simulation time 42084501016 ps
CPU time 1088.38 seconds
Started Apr 15 01:11:01 PM PDT 24
Finished Apr 15 01:29:11 PM PDT 24
Peak memory 281940 kb
Host smart-5e4808cf-3473-47a8-81c7-f6afe8281cde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715907627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.715907627
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2858556457
Short name T392
Test name
Test status
Simulation time 949380752 ps
CPU time 53.49 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:11:55 PM PDT 24
Peak memory 249072 kb
Host smart-38876a72-f126-45f8-b7c9-a751509b4fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28585
56457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2858556457
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3833146065
Short name T495
Test name
Test status
Simulation time 738943137 ps
CPU time 20.85 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 01:11:33 PM PDT 24
Peak memory 255236 kb
Host smart-b8638ab8-9417-4b8d-b154-031149c95b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38331
46065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3833146065
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.561356455
Short name T624
Test name
Test status
Simulation time 473035068 ps
CPU time 7.94 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:11:23 PM PDT 24
Peak memory 240844 kb
Host smart-4224474c-4523-46a4-aee8-2b8d029e1f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56135
6455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.561356455
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2387712987
Short name T517
Test name
Test status
Simulation time 2380283339 ps
CPU time 43.97 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:11:46 PM PDT 24
Peak memory 256376 kb
Host smart-361eda34-ce30-41e4-bb54-a64161446b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23877
12987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2387712987
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2707806013
Short name T690
Test name
Test status
Simulation time 94013675845 ps
CPU time 1298.44 seconds
Started Apr 15 01:10:58 PM PDT 24
Finished Apr 15 01:32:37 PM PDT 24
Peak memory 289216 kb
Host smart-bf74831c-292b-4fc0-b83b-34853839b1f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707806013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2707806013
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.133715227
Short name T246
Test name
Test status
Simulation time 12171537194 ps
CPU time 1198.44 seconds
Started Apr 15 01:11:03 PM PDT 24
Finished Apr 15 01:31:03 PM PDT 24
Peak memory 289452 kb
Host smart-93daf04a-b8bc-48d3-801a-fe9607dda368
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133715227 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.133715227
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3712168625
Short name T200
Test name
Test status
Simulation time 50779894 ps
CPU time 4.32 seconds
Started Apr 15 01:11:04 PM PDT 24
Finished Apr 15 01:11:10 PM PDT 24
Peak memory 249332 kb
Host smart-1bd668c7-c905-48e9-923b-7018829cb793
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3712168625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3712168625
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2633520154
Short name T473
Test name
Test status
Simulation time 213487285575 ps
CPU time 2327.02 seconds
Started Apr 15 01:10:55 PM PDT 24
Finished Apr 15 01:49:43 PM PDT 24
Peak memory 281900 kb
Host smart-fe066575-fd1f-4784-ad10-351a51fb7cad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633520154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2633520154
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.173680541
Short name T526
Test name
Test status
Simulation time 349503305 ps
CPU time 6.24 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:11:08 PM PDT 24
Peak memory 240840 kb
Host smart-94a9aa5f-94cd-48c0-b2e1-55fb87d897cb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=173680541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.173680541
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1769449197
Short name T610
Test name
Test status
Simulation time 534818746 ps
CPU time 38.57 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:11:53 PM PDT 24
Peak memory 248868 kb
Host smart-7db5cf40-e8fd-497b-b607-8af5cfc778b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17694
49197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1769449197
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3000632729
Short name T67
Test name
Test status
Simulation time 815955103 ps
CPU time 46.18 seconds
Started Apr 15 01:11:03 PM PDT 24
Finished Apr 15 01:11:51 PM PDT 24
Peak memory 249016 kb
Host smart-8b9f8d26-68ee-4a36-9c00-549120fe65b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30006
32729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3000632729
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2539789031
Short name T641
Test name
Test status
Simulation time 141972039584 ps
CPU time 1373.21 seconds
Started Apr 15 01:11:21 PM PDT 24
Finished Apr 15 01:34:15 PM PDT 24
Peak memory 272948 kb
Host smart-6ccc60a4-452c-49df-a044-17b7fe038744
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539789031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2539789031
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.698066712
Short name T436
Test name
Test status
Simulation time 11641637590 ps
CPU time 975.1 seconds
Started Apr 15 01:11:09 PM PDT 24
Finished Apr 15 01:27:25 PM PDT 24
Peak memory 283232 kb
Host smart-cc605df1-8752-4e83-b339-22be7588b3d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698066712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.698066712
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3725489808
Short name T529
Test name
Test status
Simulation time 45863119933 ps
CPU time 469.15 seconds
Started Apr 15 01:11:01 PM PDT 24
Finished Apr 15 01:18:52 PM PDT 24
Peak memory 254652 kb
Host smart-53e35709-0ba0-4821-a6f7-80bcb921ddf0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725489808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3725489808
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.864662511
Short name T215
Test name
Test status
Simulation time 1406940706 ps
CPU time 46.12 seconds
Started Apr 15 01:11:07 PM PDT 24
Finished Apr 15 01:11:55 PM PDT 24
Peak memory 249016 kb
Host smart-d3396dcf-1c46-41d2-9220-9de3a9cddf2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86466
2511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.864662511
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1450758109
Short name T497
Test name
Test status
Simulation time 527408727 ps
CPU time 31.2 seconds
Started Apr 15 01:11:07 PM PDT 24
Finished Apr 15 01:11:39 PM PDT 24
Peak memory 256764 kb
Host smart-48929e96-b9ee-4c7c-8dd5-8dcb74f81d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14507
58109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1450758109
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.665969351
Short name T258
Test name
Test status
Simulation time 1152479661 ps
CPU time 45.68 seconds
Started Apr 15 01:10:58 PM PDT 24
Finished Apr 15 01:11:44 PM PDT 24
Peak memory 254988 kb
Host smart-83e58337-ca04-46bd-b9a3-7bf31ee8dba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66596
9351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.665969351
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.153221209
Short name T522
Test name
Test status
Simulation time 358858405 ps
CPU time 12.39 seconds
Started Apr 15 01:10:59 PM PDT 24
Finished Apr 15 01:11:12 PM PDT 24
Peak memory 249048 kb
Host smart-7c9a13ae-9181-4c68-8d13-45527059acc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15322
1209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.153221209
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2151605376
Short name T403
Test name
Test status
Simulation time 491984189 ps
CPU time 9.52 seconds
Started Apr 15 01:11:10 PM PDT 24
Finished Apr 15 01:11:20 PM PDT 24
Peak memory 252628 kb
Host smart-3ce74496-7364-4078-bfd5-a036c90fc6ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151605376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2151605376
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3034131602
Short name T102
Test name
Test status
Simulation time 176677690509 ps
CPU time 5444.86 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 02:41:58 PM PDT 24
Peak memory 322300 kb
Host smart-b26ff77e-e065-47cd-9132-1bd4d5e5c1ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034131602 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3034131602
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2338765575
Short name T198
Test name
Test status
Simulation time 229737766 ps
CPU time 2.8 seconds
Started Apr 15 01:11:03 PM PDT 24
Finished Apr 15 01:11:07 PM PDT 24
Peak memory 249300 kb
Host smart-855d1c53-5875-412e-b4e0-78279bb1c6fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2338765575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2338765575
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2303312716
Short name T447
Test name
Test status
Simulation time 37944006304 ps
CPU time 2405.76 seconds
Started Apr 15 01:11:12 PM PDT 24
Finished Apr 15 01:51:19 PM PDT 24
Peak memory 289728 kb
Host smart-d937eff3-482f-4fa3-bcc9-f74fc2314ecf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303312716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2303312716
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1376412206
Short name T218
Test name
Test status
Simulation time 921001677 ps
CPU time 12.28 seconds
Started Apr 15 01:10:58 PM PDT 24
Finished Apr 15 01:11:12 PM PDT 24
Peak memory 240852 kb
Host smart-fb761e73-8d5d-497d-bce2-b902e1cd2408
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1376412206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1376412206
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.510840246
Short name T295
Test name
Test status
Simulation time 2171431408 ps
CPU time 139.25 seconds
Started Apr 15 01:11:04 PM PDT 24
Finished Apr 15 01:13:24 PM PDT 24
Peak memory 256880 kb
Host smart-28937806-f4e4-411e-8599-8e2573931904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51084
0246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.510840246
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.192034392
Short name T448
Test name
Test status
Simulation time 1882010545 ps
CPU time 43.77 seconds
Started Apr 15 01:11:22 PM PDT 24
Finished Apr 15 01:12:07 PM PDT 24
Peak memory 255640 kb
Host smart-babbb344-9c4c-4525-b88e-37324d031671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19203
4392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.192034392
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1762188602
Short name T461
Test name
Test status
Simulation time 210546486253 ps
CPU time 3123.61 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 02:03:18 PM PDT 24
Peak memory 281896 kb
Host smart-3a834991-9406-446e-af32-c2f1a4faed91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762188602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1762188602
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1123111583
Short name T323
Test name
Test status
Simulation time 49366608435 ps
CPU time 518.92 seconds
Started Apr 15 01:11:07 PM PDT 24
Finished Apr 15 01:19:47 PM PDT 24
Peak memory 248080 kb
Host smart-21275f22-4cde-4944-a3b1-d71503a19f27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123111583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1123111583
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3223873132
Short name T527
Test name
Test status
Simulation time 874989324 ps
CPU time 19.83 seconds
Started Apr 15 01:11:18 PM PDT 24
Finished Apr 15 01:11:39 PM PDT 24
Peak memory 249032 kb
Host smart-f0aa26ff-ff4b-4749-a4cb-5f36b2e007e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32238
73132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3223873132
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4203810542
Short name T390
Test name
Test status
Simulation time 1789282259 ps
CPU time 22.18 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:11:24 PM PDT 24
Peak memory 254476 kb
Host smart-546afec7-3794-47cc-b5b3-ea68a3696c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42038
10542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4203810542
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1292323083
Short name T74
Test name
Test status
Simulation time 412950824 ps
CPU time 22.13 seconds
Started Apr 15 01:11:14 PM PDT 24
Finished Apr 15 01:11:37 PM PDT 24
Peak memory 247532 kb
Host smart-b17affc7-886e-49ab-bb18-bc0a1c42df38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12923
23083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1292323083
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.637671560
Short name T372
Test name
Test status
Simulation time 473279763 ps
CPU time 34.55 seconds
Started Apr 15 01:11:01 PM PDT 24
Finished Apr 15 01:11:37 PM PDT 24
Peak memory 249000 kb
Host smart-68468099-0f39-409d-b300-e94304300656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63767
1560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.637671560
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2604131087
Short name T591
Test name
Test status
Simulation time 191171809573 ps
CPU time 1641.49 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:38:23 PM PDT 24
Peak memory 290100 kb
Host smart-3622ba71-a7f5-4e15-a1ea-7176edf43d0e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604131087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2604131087
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3731671737
Short name T210
Test name
Test status
Simulation time 30055922 ps
CPU time 2.66 seconds
Started Apr 15 01:11:08 PM PDT 24
Finished Apr 15 01:11:12 PM PDT 24
Peak memory 249220 kb
Host smart-b23d4747-fa1a-4f99-bd94-47d73937c5a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3731671737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3731671737
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1384601767
Short name T485
Test name
Test status
Simulation time 60321372927 ps
CPU time 1275.61 seconds
Started Apr 15 01:11:02 PM PDT 24
Finished Apr 15 01:32:19 PM PDT 24
Peak memory 289700 kb
Host smart-ac169bb3-73db-41c1-9005-f74bdcf381ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384601767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1384601767
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.432894497
Short name T668
Test name
Test status
Simulation time 307460374 ps
CPU time 14.46 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 01:11:27 PM PDT 24
Peak memory 249000 kb
Host smart-ee9ff6ee-4f9e-4363-83f6-2416bd1b53fc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=432894497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.432894497
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2094858208
Short name T382
Test name
Test status
Simulation time 28929621207 ps
CPU time 211.95 seconds
Started Apr 15 01:11:03 PM PDT 24
Finished Apr 15 01:14:37 PM PDT 24
Peak memory 257112 kb
Host smart-4ebefe33-1360-4854-a4fc-136374b18468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20948
58208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2094858208
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2749496788
Short name T469
Test name
Test status
Simulation time 1273483043 ps
CPU time 19.11 seconds
Started Apr 15 01:11:15 PM PDT 24
Finished Apr 15 01:11:36 PM PDT 24
Peak memory 255940 kb
Host smart-31234965-a34e-4f55-8125-c09c5fbac513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27494
96788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2749496788
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1271722047
Short name T89
Test name
Test status
Simulation time 33203135597 ps
CPU time 1850.41 seconds
Started Apr 15 01:11:01 PM PDT 24
Finished Apr 15 01:41:53 PM PDT 24
Peak memory 285420 kb
Host smart-13b4f32d-4026-45f0-9abd-bc0786219756
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271722047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1271722047
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1174907655
Short name T277
Test name
Test status
Simulation time 158950691007 ps
CPU time 2518.2 seconds
Started Apr 15 01:11:00 PM PDT 24
Finished Apr 15 01:53:00 PM PDT 24
Peak memory 288536 kb
Host smart-b05c1514-1e59-430f-9f8d-a240adbae2d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174907655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1174907655
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1667049728
Short name T308
Test name
Test status
Simulation time 11759788811 ps
CPU time 457.38 seconds
Started Apr 15 01:11:11 PM PDT 24
Finished Apr 15 01:18:50 PM PDT 24
Peak memory 248352 kb
Host smart-9792084a-5e13-4afb-bacb-bb8e89221f51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667049728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1667049728
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3243384313
Short name T543
Test name
Test status
Simulation time 1448873917 ps
CPU time 35.01 seconds
Started Apr 15 01:11:12 PM PDT 24
Finished Apr 15 01:11:48 PM PDT 24
Peak memory 249040 kb
Host smart-3e594705-458e-4d35-8883-ffc0bf9c4c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32433
84313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3243384313
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3410385099
Short name T224
Test name
Test status
Simulation time 132166375 ps
CPU time 8.39 seconds
Started Apr 15 01:11:05 PM PDT 24
Finished Apr 15 01:11:14 PM PDT 24
Peak memory 252388 kb
Host smart-b19799de-8b2c-4ab9-b37b-e6546afaca35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34103
85099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3410385099
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.923913556
Short name T562
Test name
Test status
Simulation time 195753909 ps
CPU time 10.19 seconds
Started Apr 15 01:11:10 PM PDT 24
Finished Apr 15 01:11:21 PM PDT 24
Peak memory 248996 kb
Host smart-e02d6175-abef-4205-bf28-3391050cad7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92391
3556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.923913556
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2801219165
Short name T492
Test name
Test status
Simulation time 268095839 ps
CPU time 5.1 seconds
Started Apr 15 01:11:12 PM PDT 24
Finished Apr 15 01:11:19 PM PDT 24
Peak memory 240872 kb
Host smart-8f959a3b-3ac7-46d7-bbb2-05ba99d80b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28012
19165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2801219165
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1159971114
Short name T47
Test name
Test status
Simulation time 13410639851 ps
CPU time 1338.37 seconds
Started Apr 15 01:11:08 PM PDT 24
Finished Apr 15 01:33:27 PM PDT 24
Peak memory 290048 kb
Host smart-7a6952bb-bc0c-4f9b-a115-a3adb6b170e2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159971114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1159971114
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2574016570
Short name T595
Test name
Test status
Simulation time 41371425102 ps
CPU time 3711.07 seconds
Started Apr 15 01:11:10 PM PDT 24
Finished Apr 15 02:13:03 PM PDT 24
Peak memory 314508 kb
Host smart-bcef95ba-923d-4d29-aaa5-f695bb23e940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574016570 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2574016570
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.461172680
Short name T205
Test name
Test status
Simulation time 33113267 ps
CPU time 3.15 seconds
Started Apr 15 01:11:04 PM PDT 24
Finished Apr 15 01:11:08 PM PDT 24
Peak memory 249348 kb
Host smart-02255c1b-4877-44b2-9d43-d14140aee146
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=461172680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.461172680
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3188106435
Short name T346
Test name
Test status
Simulation time 76188786305 ps
CPU time 2232 seconds
Started Apr 15 01:11:22 PM PDT 24
Finished Apr 15 01:48:36 PM PDT 24
Peak memory 286504 kb
Host smart-1af0f30b-b115-4883-abf9-98e915f35abd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188106435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3188106435
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.318440628
Short name T592
Test name
Test status
Simulation time 205171049 ps
CPU time 12.01 seconds
Started Apr 15 01:11:09 PM PDT 24
Finished Apr 15 01:11:22 PM PDT 24
Peak memory 252668 kb
Host smart-0b317388-5bea-4ab7-b4cf-f7c2b49eaca9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=318440628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.318440628
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3433135764
Short name T630
Test name
Test status
Simulation time 3356534509 ps
CPU time 189.01 seconds
Started Apr 15 01:11:01 PM PDT 24
Finished Apr 15 01:14:12 PM PDT 24
Peak memory 257068 kb
Host smart-b4c82346-1cbf-41e1-8f70-5d39dbcd1831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34331
35764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3433135764
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1243045040
Short name T459
Test name
Test status
Simulation time 173728767 ps
CPU time 12.58 seconds
Started Apr 15 01:11:03 PM PDT 24
Finished Apr 15 01:11:17 PM PDT 24
Peak memory 252212 kb
Host smart-75d023b2-3436-4b40-8ca6-33ece21ce5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12430
45040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1243045040
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.692377733
Short name T604
Test name
Test status
Simulation time 85556185486 ps
CPU time 1230.78 seconds
Started Apr 15 01:11:13 PM PDT 24
Finished Apr 15 01:31:46 PM PDT 24
Peak memory 272788 kb
Host smart-0db36894-f368-4385-9f21-d6316dd624ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692377733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.692377733
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1110911730
Short name T312
Test name
Test status
Simulation time 59574128160 ps
CPU time 598.74 seconds
Started Apr 15 01:11:29 PM PDT 24
Finished Apr 15 01:21:28 PM PDT 24
Peak memory 248296 kb
Host smart-3a104a56-8270-413f-80db-08475e68d525
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110911730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1110911730
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.4053530877
Short name T451
Test name
Test status
Simulation time 97663851 ps
CPU time 4.81 seconds
Started Apr 15 01:11:15 PM PDT 24
Finished Apr 15 01:11:21 PM PDT 24
Peak memory 240832 kb
Host smart-01a7a558-5ebd-42c3-8daf-36ca2802a56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40535
30877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.4053530877
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.4247559803
Short name T30
Test name
Test status
Simulation time 566088975 ps
CPU time 35.03 seconds
Started Apr 15 01:11:04 PM PDT 24
Finished Apr 15 01:11:40 PM PDT 24
Peak memory 255576 kb
Host smart-ef272e05-577b-4e41-b60d-3580c0896b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42475
59803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.4247559803
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2155442068
Short name T508
Test name
Test status
Simulation time 48794740 ps
CPU time 7.24 seconds
Started Apr 15 01:11:17 PM PDT 24
Finished Apr 15 01:11:26 PM PDT 24
Peak memory 247408 kb
Host smart-3d222f41-ccd4-47dd-9e73-d4388b1608cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21554
42068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2155442068
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1685065332
Short name T596
Test name
Test status
Simulation time 1827461758 ps
CPU time 54.62 seconds
Started Apr 15 01:11:03 PM PDT 24
Finished Apr 15 01:11:59 PM PDT 24
Peak memory 249084 kb
Host smart-1e823c51-f1d1-4b63-97d5-d98d9b7f0aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16850
65332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1685065332
Directory /workspace/9.alert_handler_smoke/latest
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