Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	67839	1			T4	2		T8	7		T14	1650
class_i[0x1]	50561	1			T2	540		T4	7		T9	2
class_i[0x2]	60827	1			T2	5		T4	1		T8	9
class_i[0x3]	68210	1			T3	4928		T4	11		T5	2790

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	62696	1			T2	2		T3	1226		T4	7
alert[0x1]	61957	1			T2	9		T3	1273		T4	6
alert[0x2]	60131	1			T2	9		T3	1263		T4	6
alert[0x3]	62653	1			T2	525		T3	1166		T4	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

247159

1

T2

545

T3

4928

T4

11

esc_ping_fail

278

1

T4

10

T9

7

T10

9

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	62614	1			T2	2		T3	1226		T4	4
esc_integrity_fail	alert[0x1]	61882	1			T2	9		T3	1273		T4	4
esc_integrity_fail	alert[0x2]	60069	1			T2	9		T3	1263		T4	3
esc_integrity_fail	alert[0x3]	62594	1			T2	525		T3	1166		T5	779
esc_ping_fail	alert[0x0]	82	1			T4	3		T9	3		T10	1
esc_ping_fail	alert[0x1]	75	1			T4	2		T9	2		T10	2
esc_ping_fail	alert[0x2]	62	1			T4	3		T9	1		T10	2
esc_ping_fail	alert[0x3]	59	1			T4	2		T9	1		T10	4

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	67762	1			T8	7		T14	1650		T42	80
esc_integrity_fail	class_i[0x1]	50527	1			T2	540		T4	7		T9	2
esc_integrity_fail	class_i[0x2]	60775	1			T2	5		T8	9		T41	9
esc_integrity_fail	class_i[0x3]	68095	1			T3	4928		T4	4		T5	2790
esc_ping_fail	class_i[0x0]	77	1			T4	2		T10	1		T238	2
esc_ping_fail	class_i[0x1]	34	1			T238	1		T315	2		T314	1
esc_ping_fail	class_i[0x2]	52	1			T4	1		T10	1		T238	1
esc_ping_fail	class_i[0x3]	115	1			T4	7		T9	7		T10	7