Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	646783603	0	0	625
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	646783603	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	646783603	646645797	0	0
tb.dut.CheckAccuCntDw	0	0	625	625	0	0
tb.dut.CheckEscCntDw	0	0	625	625	0	0
tb.dut.CheckNAlerts	0	0	625	625	0	0
tb.dut.CheckNClasses	0	0	625	625	0	0
tb.dut.CheckNEscSev	0	0	625	625	0	0
tb.dut.CrashdumpKnownO_A	0	0	646783603	646645797	0	0
tb.dut.EdnKnownO_A	0	0	646783603	646645797	0	0
tb.dut.EscPKnownO_A	0	0	646783603	646645797	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	646783603	50	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	646783603	50	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	646783603	50	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	646783603	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	646783603	50	0	0
tb.dut.IrqAKnownO_A	0	0	646783603	646645797	0	0
tb.dut.IrqBKnownO_A	0	0	646783603	646645797	0	0
tb.dut.IrqCKnownO_A	0	0	646783603	646645797	0	0
tb.dut.IrqDKnownO_A	0	0	646783603	646645797	0	0
tb.dut.TlAReadyKnownO_A	0	0	646783603	646645797	0	0
tb.dut.TlDValidKnownO_A	0	0	646783603	646645797	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	670649307	2948473	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	670649307	12047	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	670649307	12181	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	670649307	13225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	670649307	12898	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	670649307	14286	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	670649307	10583	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	670649307	14515	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	670649307	11674	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	670649307	11753	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	670649307	11794	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	670649307	11752	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	670649307	10697	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	670649307	13199	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	670649307	10563	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	670649307	11900	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	670649307	12013	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	670649307	13031	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	670649307	11708	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	670649307	12108	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	670649307	11853	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	670649307	11043	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	670649307	11816	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	670649307	10693	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	670649307	13177	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	670649307	12848	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	670649307	13230	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	670649307	12137	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	670649307	11796	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	670649307	10640	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	670649307	13216	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	670649307	10753	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	670649307	12243	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	670649307	13966	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	670649307	10709	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	670649307	12192	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	670649307	10644	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	670649307	11768	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	670649307	10644	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	670649307	10723	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	670649307	11075	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	670649307	13139	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	670649307	13092	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	670649307	11701	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	670649307	10770	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	670649307	10742	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	670649307	11849	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	670649307	10438	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	670649307	11806	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	670649307	13101	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	670649307	13354	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	670649307	13175	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	670649307	14162	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	670649307	12911	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	670649307	12139	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	670649307	12787	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	670649307	12668	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	670649307	11924	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	670649307	10524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	670649307	10762	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	670649307	12310	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	670649307	10520	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	670649307	10675	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	670649307	10730	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	670649307	10909	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	670649307	11791	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	670649307	10624	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	670649307	14235	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	670649307	12032	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	670649307	10891	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	670649307	26071	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	670649307	10858	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	670649307	11018	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	670649307	11862	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	670649307	10222	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	670649307	12263	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	670649307	13198	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	670649307	12965	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	670649307	10771	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	646783603	50	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	646783603	50	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	646783603	50	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	646783603	2380	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	646783603	225611	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	646783603	298994037	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	646783603	141	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	646783603	897	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	646783603	44	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	646783603	456	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	646651613	224139543	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	646783603	1006	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	646783603	982	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	646783603	953	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	646783603	935	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	646783603	1472	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	646783603	132797	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	646783603	1343	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	646783603	84	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	646783603	904	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	646783603	754	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	646783603	646645797	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	646783603	50	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	646783603	50	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	646783603	50	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	646783603	4682	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	646783603	200706	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	646783603	340218696	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	646783603	182	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	646783603	547	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	646783603	25	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	646783603	276	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	646651613	261588802	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	646783603	630	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	646783603	605	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	646783603	584	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	646783603	573	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	646783603	1444	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	646783603	134620	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	646783603	1352	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	646783603	65	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	646783603	902	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	646783603	752	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	646783603	646645797	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	646783603	50	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	646783603	50	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	646783603	50	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	646783603	4875	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	646783603	200085	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	646783603	348666344	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	646783603	169	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	646783603	494	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	646783603	16	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	646783603	215	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	646651613	257984250	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	646783603	566	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	646783603	556	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	646783603	544	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	646783603	536	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	646783603	1553	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	646783603	151909	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	646783603	1466	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	646783603	70	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	646783603	909	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	646783603	759	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	646783603	646645797	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	646783603	50	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	646783603	50	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	646783603	50	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	646783603	1637	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	646783603	184123	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	646783603	390351565	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	646783603	169	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	646783603	473	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	646783603	28	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	646783603	203	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	646651613	295803653	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	646783603	558	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	646783603	547	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	646783603	540	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	646783603	532	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	646783603	1258	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	646783603	104771	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	646783603	1166	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	646783603	64	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	646783603	903	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	646783603	753	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	646783603	646645797	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	670649307	131691179	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	670649307	670002589	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	670649307	670002589	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	670649307	181904004	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	670649307	670002589	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	670649307	670002589	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
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tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
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tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0

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