Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	172	1			T2	1		T4	1		T20	3
index[0x1]	184	1			T20	4		T21	1		T22	1
index[0x2]	199	1			T2	2		T3	1		T4	1
index[0x3]	166	1			T5	1		T19	1		T14	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	242	1			T2	1		T4	2		T21	1
lens_less_than_1000[1]	144	1			T20	7		T22	1		T8	1
lens_less_than_1000[2]	84	1			T2	1		T3	1		T5	1
lens_less_than_1000[3]	73	1			T23	1		T42	2		T64	1
lens_less_than_1000[4]	59	1			T14	2		T47	1		T94	1
lens_less_than_1000[5]	46	1			T2	1		T19	1		T14	2
lens_less_than_1000[6]	29	1			T70	1		T94	1		T241	1
lens_less_than_1000[7]	23	1			T268	1		T39	1		T254	1
lens_less_than_1000[8]	7	1			T84	1		T269	3		T235	1
lens_less_than_1000[9]	6	1			T56	1		T269	1		T163	1
len_2	8	1			T270	3		T228	1		T51	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0] , index[0x1]]	[lens_less_than_1000[8]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	57	1			T2	1		T4	1		T8	1
index[0x0]	lens_less_than_1000[1]	32	1			T20	3		T57	1		T63	3
index[0x0]	lens_less_than_1000[2]	24	1			T14	1		T55	1		T27	4
index[0x0]	lens_less_than_1000[3]	15	1			T49	1		T85	1		T271	1
index[0x0]	lens_less_than_1000[4]	20	1			T14	1		T49	1		T74	1
index[0x0]	lens_less_than_1000[5]	9	1			T14	1		T47	1		T76	1
index[0x0]	lens_less_than_1000[6]	3	1			T70	1		T272	1		T273	1
index[0x0]	lens_less_than_1000[7]	7	1			T268	1		T39	1		T248	1
index[0x0]	lens_less_than_1000[9]	3	1			T56	1		T269	1		T274	1
index[0x0]	len_2	2	1			T228	1		T275	1		-	-
index[0x1]	lens_less_than_1000[0]	72	1			T21	1		T7	1		T41	2
index[0x1]	lens_less_than_1000[1]	39	1			T20	4		T22	1		T207	1
index[0x1]	lens_less_than_1000[2]	16	1			T61	2		T84	1		T269	1
index[0x1]	lens_less_than_1000[3]	17	1			T42	1		T66	1		T70	1
index[0x1]	lens_less_than_1000[4]	9	1			T14	1		T268	1		T276	1
index[0x1]	lens_less_than_1000[5]	10	1			T85	3		T161	1		T248	1
index[0x1]	lens_less_than_1000[6]	14	1			T241	1		T98	3		T277	1
index[0x1]	lens_less_than_1000[7]	5	1			T254	1		T273	1		T278	1
index[0x1]	lens_less_than_1000[9]	1	1			T163	1		-	-		-	-
index[0x1]	len_2	1	1			T279	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	67	1			T4	1		T57	1		T46	1
index[0x2]	lens_less_than_1000[1]	38	1			T8	1		T41	1		T70	1
index[0x2]	lens_less_than_1000[2]	23	1			T2	1		T3	1		T76	1
index[0x2]	lens_less_than_1000[3]	26	1			T23	1		T42	1		T64	1
index[0x2]	lens_less_than_1000[4]	15	1			T47	1		T76	1		T280	1
index[0x2]	lens_less_than_1000[5]	10	1			T2	1		T14	1		T47	1
index[0x2]	lens_less_than_1000[6]	4	1			T281	1		T282	2		T283	1
index[0x2]	lens_less_than_1000[7]	9	1			T246	1		T284	6		T265	1
index[0x2]	lens_less_than_1000[8]	5	1			T269	3		T235	1		T285	1
index[0x2]	lens_less_than_1000[9]	1	1			T286	1		-	-		-	-
index[0x2]	len_2	1	1			T279	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	46	1			T14	1		T7	1		T287	1
index[0x3]	lens_less_than_1000[1]	35	1			T58	1		T47	1		T68	1
index[0x3]	lens_less_than_1000[2]	21	1			T5	1		T56	1		T24	1
index[0x3]	lens_less_than_1000[3]	15	1			T288	1		T254	1		T161	1
index[0x3]	lens_less_than_1000[4]	15	1			T94	1		T73	1		T38	1
index[0x3]	lens_less_than_1000[5]	17	1			T19	1		T41	1		T47	2
index[0x3]	lens_less_than_1000[6]	8	1			T94	1		T219	1		T289	1
index[0x3]	lens_less_than_1000[7]	2	1			T224	1		T90	1		-	-
index[0x3]	lens_less_than_1000[8]	2	1			T84	1		T290	1		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T291	1		-	-		-	-
index[0x3]	len_2	4	1			T270	3		T51	1		-	-