Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	84	1			T8	1		T14	1		T41	2
class_index[0x1]	65	1			T41	1		T47	1		T70	1
class_index[0x2]	70	1			T28	1		T60	1		T42	1
class_index[0x3]	64	1			T1	1		T5	2		T42	3

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	113	1			T5	2		T8	1		T28	1
intr_timeout_cnt[1]	64	1			T1	1		T41	2		T66	1
intr_timeout_cnt[2]	31	1			T47	1		T68	1		T71	3
intr_timeout_cnt[3]	14	1			T60	1		T68	1		T239	1
intr_timeout_cnt[4]	8	1			T68	1		T73	3		T240	1
intr_timeout_cnt[5]	15	1			T42	1		T49	1		T73	3
intr_timeout_cnt[6]	10	1			T42	2		T49	1		T73	1
intr_timeout_cnt[7]	9	1			T42	1		T241	1		T242	1
intr_timeout_cnt[8]	16	1			T49	4		T77	1		T33	1
intr_timeout_cnt[9]	3	1			T73	1		T243	1		T244	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	36	1			T8	1		T14	1		T41	1
class_index[0x0]	intr_timeout_cnt[1]	19	1			T41	1		T66	1		T76	1
class_index[0x0]	intr_timeout_cnt[2]	8	1			T47	1		T68	1		T75	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T68	1		T245	1		T246	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T73	3		T247	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	6	1			T49	1		T248	2		T237	2
class_index[0x0]	intr_timeout_cnt[7]	2	1			T42	1		T249	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	4	1			T49	1		T161	1		T250	1
class_index[0x0]	intr_timeout_cnt[9]	1	1			T243	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	29	1			T47	1		T70	1		T49	2
class_index[0x1]	intr_timeout_cnt[1]	17	1			T41	1		T72	1		T74	1
class_index[0x1]	intr_timeout_cnt[2]	9	1			T71	3		T49	1		T76	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T248	1		T251	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	2	1			T68	1		T242	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T49	1		T237	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T252	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T49	1		T253	2		-	-
class_index[0x2]	intr_timeout_cnt[0]	19	1			T28	1		T47	1		T76	2
class_index[0x2]	intr_timeout_cnt[1]	18	1			T70	1		T49	1		T75	1
class_index[0x2]	intr_timeout_cnt[2]	8	1			T254	1		T255	1		T256	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T60	1		T257	1		T258	1
class_index[0x2]	intr_timeout_cnt[4]	1	1			T240	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	7	1			T42	1		T73	3		T259	3
class_index[0x2]	intr_timeout_cnt[6]	2	1			T75	1		T248	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	4	1			T241	1		T242	1		T260	1
class_index[0x2]	intr_timeout_cnt[8]	5	1			T49	1		T77	1		T250	1
class_index[0x2]	intr_timeout_cnt[9]	2	1			T73	1		T244	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	29	1			T5	2		T42	1		T47	1
class_index[0x3]	intr_timeout_cnt[1]	10	1			T1	1		T50	1		T241	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T49	2		T221	1		T256	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T239	1		T254	1		T162	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T261	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	2	1			T262	1		T263	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	6	1			T42	2		T73	1		T264	1
class_index[0x3]	intr_timeout_cnt[7]	2	1			T265	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	4	1			T49	1		T33	1		T243	1