Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	346955	1			T1	39		T2	2152		T3	1897
all_values[1]	346955	1			T1	39		T2	2152		T3	1897
all_values[2]	346955	1			T1	39		T2	2152		T3	1897
all_values[3]	346955	1			T1	39		T2	2152		T3	1897

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

690074

1

T1

75

T2

4361

T3

3785

auto[1]

697746

1

T1

81

T2

4247

T3

3803

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

835151

1

T1

80

T2

6319

T3

3836

auto[1]

552669

1

T1

76

T2

2289

T3

3752

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98195	1			T1	10		T2	718		T3	493
all_values[0]	auto[0]	auto[1]	74433	1			T1	10		T2	408		T3	484
all_values[0]	auto[1]	auto[0]	99648	1			T1	10		T2	647		T3	464
all_values[0]	auto[1]	auto[1]	74679	1			T1	9		T2	379		T3	456
all_values[1]	auto[0]	auto[0]	104524	1			T1	10		T2	860		T3	457
all_values[1]	auto[0]	auto[1]	67956	1			T1	9		T2	274		T3	453
all_values[1]	auto[1]	auto[0]	106492	1			T1	10		T2	777		T3	499
all_values[1]	auto[1]	auto[1]	67983	1			T1	10		T2	241		T3	488
all_values[2]	auto[0]	auto[0]	106399	1			T1	10		T2	884		T3	487
all_values[2]	auto[0]	auto[1]	66266	1			T1	10		T2	167		T3	458
all_values[2]	auto[1]	auto[0]	107624	1			T1	10		T2	942		T3	486
all_values[2]	auto[1]	auto[1]	66666	1			T1	9		T2	159		T3	466
all_values[3]	auto[0]	auto[0]	105219	1			T1	8		T2	736		T3	477
all_values[3]	auto[0]	auto[1]	67082	1			T1	8		T2	314		T3	476
all_values[3]	auto[1]	auto[0]	107050	1			T1	12		T2	755		T3	473
all_values[3]	auto[1]	auto[1]	67604	1			T1	11		T2	347		T3	471