Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	346955	1			T1	39		T2	2152		T3	1897
all_pins[1]	346955	1			T1	39		T2	2152		T3	1897
all_pins[2]	346955	1			T1	39		T2	2152		T3	1897
all_pins[3]	346955	1			T1	39		T2	2152		T3	1897

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1110888	1			T1	117		T2	7482		T3	5707
values[0x1]	276932	1			T1	39		T2	1126		T3	1881
transitions[0x0=>0x1]	184404	1			T1	25		T2	932		T3	1167
transitions[0x1=>0x0]	184641	1			T1	25		T2	932		T3	1167

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	272276	1			T1	30		T2	1773		T3	1441
all_pins[0]	values[0x1]	74679	1			T1	9		T2	379		T3	456
all_pins[0]	transitions[0x0=>0x1]	74079	1			T1	9		T2	377		T3	456
all_pins[0]	transitions[0x1=>0x0]	67241	1			T1	11		T2	345		T3	471
all_pins[1]	values[0x0]	278972	1			T1	29		T2	1911		T3	1409
all_pins[1]	values[0x1]	67983	1			T1	10		T2	241		T3	488
all_pins[1]	transitions[0x0=>0x1]	36956	1			T1	7		T2	148		T3	263
all_pins[1]	transitions[0x1=>0x0]	43652	1			T1	6		T2	286		T3	231
all_pins[2]	values[0x0]	280289	1			T1	30		T2	1993		T3	1431
all_pins[2]	values[0x1]	66666	1			T1	9		T2	159		T3	466
all_pins[2]	transitions[0x0=>0x1]	36215	1			T1	5		T2	110		T3	209
all_pins[2]	transitions[0x1=>0x0]	37532	1			T1	6		T2	192		T3	231
all_pins[3]	values[0x0]	279351	1			T1	28		T2	1805		T3	1426
all_pins[3]	values[0x1]	67604	1			T1	11		T2	347		T3	471
all_pins[3]	transitions[0x0=>0x1]	37154	1			T1	4		T2	297		T3	239
all_pins[3]	transitions[0x1=>0x0]	36216	1			T1	2		T2	109		T3	234