Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	257	1			T140	7		T141	7		T142	7
all_values[1]	257	1			T140	7		T141	7		T142	7
all_values[2]	257	1			T140	7		T141	7		T142	7
all_values[3]	257	1			T140	7		T141	7		T142	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

581

1

T140

22

T141

16

T142

12

auto[1]

447

1

T140

6

T141

12

T142

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

404

1

T140

13

T141

10

T142

14

auto[1]

624

1

T140

15

T141

18

T142

14

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

623

1

T140

17

T141

15

T142

18

auto[1]

405

1

T140

11

T141

13

T142

10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

73

1

T140

4

T141

3

T142

2

all_values[0]

auto[0]

auto[0]

auto[1]

26

1

T350

1

T351

2

T352

3

all_values[0]

auto[0]

auto[1]

auto[0]

39

1

T140

1

T142

2

T353

1

all_values[0]

auto[0]

auto[1]

auto[1]

26

1

T141

1

T142

1

T354

2

all_values[0]

auto[1]

auto[0]

auto[1]

61

1

T140

1

T141

2

T350

1

all_values[0]

auto[1]

auto[1]

auto[1]

32

1

T140

1

T141

1

T142

2

all_values[1]

auto[0]

auto[0]

auto[0]

67

1

T140

3

T141

2

T142

1

all_values[1]

auto[0]

auto[0]

auto[1]

23

1

T140

1

T142

1

T350

2

all_values[1]

auto[0]

auto[1]

auto[0]

40

1

T140

1

T142

1

T355

1

all_values[1]

auto[0]

auto[1]

auto[1]

27

1

T141

2

T142

1

T353

2

all_values[1]

auto[1]

auto[0]

auto[1]

57

1

T140

1

T141

2

T142

1

all_values[1]

auto[1]

auto[1]

auto[1]

43

1

T140

1

T141

1

T142

2

all_values[2]

auto[0]

auto[0]

auto[0]

54

1

T140

1

T141

3

T142

2

all_values[2]

auto[0]

auto[0]

auto[1]

24

1

T140

2

T355

1

T352

1

all_values[2]

auto[0]

auto[1]

auto[0]

40

1

T141

1

T142

3

T350

1

all_values[2]

auto[0]

auto[1]

auto[1]

32

1

T350

1

T353

1

T351

2

all_values[2]

auto[1]

auto[0]

auto[1]

62

1

T140

2

T142

2

T355

1

all_values[2]

auto[1]

auto[1]

auto[1]

45

1

T140

2

T141

3

T350

1

all_values[3]

auto[0]

auto[0]

auto[0]

49

1

T140

3

T141

1

T142

1

all_values[3]

auto[0]

auto[0]

auto[1]

29

1

T140

1

T141

2

T350

1

all_values[3]

auto[0]

auto[1]

auto[0]

42

1

T142

2

T353

2

T351

1

all_values[3]

auto[0]

auto[1]

auto[1]

32

1

T142

1

T353

1

T356

1

all_values[3]

auto[1]

auto[0]

auto[1]

56

1

T140

3

T141

1

T142

2

all_values[3]

auto[1]

auto[1]

auto[1]

49

1

T141

3

T142

1

T354

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal