Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	86395	1			T3	1504		T5	378		T8	1284
accum_cnt_1000	231575	1			T2	1215		T3	1456		T5	787
accum_cnt_100	27714	1			T2	144		T3	82		T5	99
accum_cnt_50	71016	1			T1	28		T2	128		T3	71
accum_cnt_10	188211	1			T1	44		T2	120		T3	21
accum_cnt_0	376446	1			T1	80		T2	4869		T3	1446

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	256155	1			T1	38		T2	1619		T3	1441
class_index[0x1]	256155	1			T1	38		T2	1619		T3	1441
class_index[0x2]	256155	1			T1	38		T2	1619		T3	1441
class_index[0x3]	256155	1			T1	38		T2	1619		T3	1441

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24452	1			T5	164		T8	603		T14	57
class_index[0x0]	accum_cnt_1000	67130	1			T5	571		T19	36		T21	22
class_index[0x0]	accum_cnt_100	9969	1			T5	64		T19	31		T20	3
class_index[0x0]	accum_cnt_50	15254	1			T5	47		T18	1		T19	27
class_index[0x0]	accum_cnt_10	50772	1			T2	92		T4	47		T5	11
class_index[0x0]	accum_cnt_0	77653	1			T1	38		T2	1527		T3	1441
class_index[0x1]	accum_cnt_2000	22954	1			T3	616		T8	65		T14	61
class_index[0x1]	accum_cnt_1000	64144	1			T2	1215		T3	547		T19	53
class_index[0x1]	accum_cnt_100	5777	1			T2	144		T3	30		T19	22
class_index[0x1]	accum_cnt_50	16934	1			T2	124		T3	29		T5	55
class_index[0x1]	accum_cnt_10	38529	1			T1	38		T2	19		T3	6
class_index[0x1]	accum_cnt_0	98927	1			T2	117		T4	47		T5	801
class_index[0x2]	accum_cnt_2000	20851	1			T3	664		T8	616		T27	100
class_index[0x2]	accum_cnt_1000	51854	1			T3	694		T5	5		T19	61
class_index[0x2]	accum_cnt_100	5711	1			T3	35		T5	26		T19	20
class_index[0x2]	accum_cnt_50	16130	1			T3	34		T4	20		T5	13
class_index[0x2]	accum_cnt_10	52747	1			T2	4		T3	12		T4	21
class_index[0x2]	accum_cnt_0	97413	1			T1	38		T2	1615		T3	2
class_index[0x3]	accum_cnt_2000	18138	1			T3	224		T5	214		T7	452
class_index[0x3]	accum_cnt_1000	48447	1			T3	215		T5	211		T21	15
class_index[0x3]	accum_cnt_100	6257	1			T3	17		T5	9		T21	13
class_index[0x3]	accum_cnt_50	22698	1			T1	28		T2	4		T3	8
class_index[0x3]	accum_cnt_10	46163	1			T1	6		T2	5		T3	3
class_index[0x3]	accum_cnt_0	102453	1			T1	4		T2	1610		T3	3