Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	8578	1			T28	4		T9	1		T44	2
alert[0x1]	5234	1			T5	7		T22	1		T14	229
alert[0x2]	1582	1			T22	13		T8	197		T14	3
alert[0x3]	1940	1			T8	148		T28	6		T60	2
alert[0x4]	13033	1			T4	1		T8	8856		T9	1
alert[0x5]	2391	1			T14	17		T300	6		T63	643
alert[0x6]	4740	1			T14	234		T24	1		T70	45
alert[0x7]	5177	1			T28	1		T9	1		T14	80
alert[0x8]	9307	1			T4	1		T22	6		T8	70
alert[0x9]	4261	1			T14	1		T220	1		T63	8
alert[0xa]	8528	1			T14	13		T42	4		T10	1
alert[0xb]	5509	1			T22	1		T8	142		T28	96
alert[0xc]	7053	1			T8	397		T28	786		T9	1
alert[0xd]	2839	1			T28	6		T41	16		T47	106
alert[0xe]	1840	1			T4	2		T14	11		T42	2
alert[0xf]	4076	1			T8	1938		T28	8		T14	37
alert[0x10]	5822	1			T8	2403		T9	1		T63	630
alert[0x11]	3960	1			T9	1		T14	220		T63	498
alert[0x12]	16493	1			T2	6369		T8	31		T28	3
alert[0x13]	8017	1			T4	1		T14	454		T63	29
alert[0x14]	10768	1			T2	62		T8	52		T28	61
alert[0x15]	4716	1			T4	1		T8	498		T9	1
alert[0x16]	3739	1			T3	6		T4	1		T28	13
alert[0x17]	6225	1			T8	333		T28	45		T68	37
alert[0x18]	2834	1			T2	77		T9	1		T14	31
alert[0x19]	4433	1			T22	23		T8	6		T28	50
alert[0x1a]	3716	1			T4	1		T14	57		T10	1
alert[0x1b]	3323	1			T2	2		T28	3		T14	59
alert[0x1c]	3551	1			T2	2		T8	81		T70	40
alert[0x1d]	3328	1			T4	1		T8	46		T28	71
alert[0x1e]	4492	1			T8	202		T14	20		T63	19
alert[0x1f]	10371	1			T8	23		T28	12		T63	77
alert[0x20]	5129	1			T4	1		T5	1		T22	26
alert[0x21]	3988	1			T22	2		T9	1		T14	20
alert[0x22]	1818	1			T42	11		T44	3		T220	14
alert[0x23]	10473	1			T8	127		T24	2		T70	33
alert[0x24]	2755	1			T22	1		T9	1		T14	574
alert[0x25]	5340	1			T4	1		T8	2307		T28	17
alert[0x26]	5464	1			T3	6		T8	45		T28	49
alert[0x27]	4796	1			T4	1		T5	3		T8	37
alert[0x28]	6708	1			T5	4		T8	95		T9	1
alert[0x29]	5999	1			T4	1		T10	1		T63	60
alert[0x2a]	11822	1			T8	318		T28	21		T63	589
alert[0x2b]	3660	1			T4	1		T28	154		T9	1
alert[0x2c]	13783	1			T8	121		T64	11		T70	373
alert[0x2d]	3577	1			T8	140		T28	101		T14	63
alert[0x2e]	6016	1			T8	351		T9	1		T42	4
alert[0x2f]	9727	1			T8	488		T10	1		T220	3
alert[0x30]	5737	1			T4	1		T5	7		T8	36
alert[0x31]	7112	1			T3	1		T14	3		T63	8
alert[0x32]	8108	1			T2	2		T14	33		T41	2
alert[0x33]	6085	1			T47	1817		T70	121		T238	1
alert[0x34]	7705	1			T4	1		T22	1		T28	29
alert[0x35]	5925	1			T14	187		T44	2		T301	153
alert[0x36]	7038	1			T28	3		T14	340		T63	512
alert[0x37]	4653	1			T5	6		T63	32		T70	6
alert[0x38]	8620	1			T2	2890		T5	5		T41	5
alert[0x39]	7362	1			T3	1		T8	657		T14	36
alert[0x3a]	10654	1			T4	1		T22	1		T8	4210
alert[0x3b]	4102	1			T5	5		T70	38		T73	204
alert[0x3c]	5193	1			T4	1		T8	202		T14	100
alert[0x3d]	6966	1			T4	1		T5	2		T220	3
alert[0x3e]	6496	1			T14	3336		T47	26		T70	234
alert[0x3f]	7743	1			T8	227		T76	1		T301	3959
alert[0x40]	1523	1			T8	19		T14	226		T70	39

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	72352	1			T2	9382		T5	22		T28	1539
class_i[0x1]	106313	1			T2	6		T5	5		T8	24803
class_i[0x2]	115128	1			T3	14		T4	18		T5	7
class_i[0x3]	100160	1			T2	16		T4	1		T5	6

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

393304

1

T2

9404

T3

14

T5

40

alert_ping_fail

649

1

T4

19

T9

18

T16

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	8572	1			T28	4		T44	2		T63	84
alert_integrity_fail	alert[0x1]	5227	1			T5	7		T22	1		T14	229
alert_integrity_fail	alert[0x2]	1574	1			T22	13		T8	197		T14	3
alert_integrity_fail	alert[0x3]	1934	1			T8	148		T28	6		T60	2
alert_integrity_fail	alert[0x4]	13028	1			T8	8856		T47	198		T24	3
alert_integrity_fail	alert[0x5]	2379	1			T14	17		T300	6		T63	643
alert_integrity_fail	alert[0x6]	4724	1			T14	234		T24	1		T70	45
alert_integrity_fail	alert[0x7]	5163	1			T28	1		T14	80		T300	6
alert_integrity_fail	alert[0x8]	9297	1			T22	6		T8	70		T73	1018
alert_integrity_fail	alert[0x9]	4251	1			T14	1		T220	1		T63	8
alert_integrity_fail	alert[0xa]	8515	1			T14	13		T42	4		T63	140
alert_integrity_fail	alert[0xb]	5500	1			T22	1		T8	142		T28	96
alert_integrity_fail	alert[0xc]	7042	1			T8	397		T28	786		T44	2
alert_integrity_fail	alert[0xd]	2829	1			T28	6		T41	16		T47	106
alert_integrity_fail	alert[0xe]	1827	1			T14	11		T42	2		T68	4
alert_integrity_fail	alert[0xf]	4069	1			T8	1938		T28	8		T14	37
alert_integrity_fail	alert[0x10]	5810	1			T8	2403		T63	630		T47	170
alert_integrity_fail	alert[0x11]	3954	1			T14	220		T63	498		T47	52
alert_integrity_fail	alert[0x12]	16478	1			T2	6369		T8	31		T28	3
alert_integrity_fail	alert[0x13]	8004	1			T14	454		T63	29		T68	273
alert_integrity_fail	alert[0x14]	10757	1			T2	62		T8	52		T28	61
alert_integrity_fail	alert[0x15]	4703	1			T8	498		T63	169		T64	59
alert_integrity_fail	alert[0x16]	3725	1			T3	6		T28	13		T14	27
alert_integrity_fail	alert[0x17]	6216	1			T8	333		T28	45		T68	37
alert_integrity_fail	alert[0x18]	2829	1			T2	77		T14	31		T24	1
alert_integrity_fail	alert[0x19]	4419	1			T22	23		T8	6		T28	50
alert_integrity_fail	alert[0x1a]	3710	1			T14	57		T63	924		T47	47
alert_integrity_fail	alert[0x1b]	3319	1			T2	2		T28	3		T14	59
alert_integrity_fail	alert[0x1c]	3539	1			T2	2		T8	81		T70	40
alert_integrity_fail	alert[0x1d]	3320	1			T8	46		T28	71		T24	21
alert_integrity_fail	alert[0x1e]	4482	1			T8	202		T14	20		T63	19
alert_integrity_fail	alert[0x1f]	10358	1			T8	23		T28	12		T63	77
alert_integrity_fail	alert[0x20]	5117	1			T5	1		T22	26		T14	52
alert_integrity_fail	alert[0x21]	3978	1			T22	2		T14	20		T70	2
alert_integrity_fail	alert[0x22]	1809	1			T42	11		T44	3		T220	14
alert_integrity_fail	alert[0x23]	10459	1			T8	127		T24	2		T70	33
alert_integrity_fail	alert[0x24]	2748	1			T22	1		T14	574		T42	2
alert_integrity_fail	alert[0x25]	5337	1			T8	2307		T28	17		T14	4
alert_integrity_fail	alert[0x26]	5450	1			T3	6		T8	45		T28	49
alert_integrity_fail	alert[0x27]	4785	1			T5	3		T8	37		T14	85
alert_integrity_fail	alert[0x28]	6696	1			T5	4		T8	95		T44	1
alert_integrity_fail	alert[0x29]	5990	1			T63	60		T64	3		T47	225
alert_integrity_fail	alert[0x2a]	11812	1			T8	318		T28	21		T63	589
alert_integrity_fail	alert[0x2b]	3651	1			T28	154		T63	222		T70	24
alert_integrity_fail	alert[0x2c]	13767	1			T8	121		T64	11		T70	373
alert_integrity_fail	alert[0x2d]	3559	1			T8	140		T28	101		T14	63
alert_integrity_fail	alert[0x2e]	6005	1			T8	351		T42	4		T70	9
alert_integrity_fail	alert[0x2f]	9707	1			T8	488		T220	3		T47	4797
alert_integrity_fail	alert[0x30]	5726	1			T5	7		T8	36		T47	98
alert_integrity_fail	alert[0x31]	7102	1			T3	1		T14	3		T63	8
alert_integrity_fail	alert[0x32]	8101	1			T2	2		T14	33		T41	2
alert_integrity_fail	alert[0x33]	6079	1			T47	1817		T70	121		T76	5
alert_integrity_fail	alert[0x34]	7696	1			T22	1		T28	29		T63	350
alert_integrity_fail	alert[0x35]	5916	1			T14	187		T44	2		T301	153
alert_integrity_fail	alert[0x36]	7026	1			T28	3		T14	340		T63	512
alert_integrity_fail	alert[0x37]	4644	1			T5	6		T63	32		T70	6
alert_integrity_fail	alert[0x38]	8612	1			T2	2890		T5	5		T41	5
alert_integrity_fail	alert[0x39]	7357	1			T3	1		T8	657		T14	36
alert_integrity_fail	alert[0x3a]	10642	1			T22	1		T8	4210		T64	1
alert_integrity_fail	alert[0x3b]	4094	1			T5	5		T70	38		T73	204
alert_integrity_fail	alert[0x3c]	5183	1			T8	202		T14	100		T63	85
alert_integrity_fail	alert[0x3d]	6958	1			T5	2		T220	3		T63	1332
alert_integrity_fail	alert[0x3e]	6488	1			T14	3336		T47	26		T70	234
alert_integrity_fail	alert[0x3f]	7739	1			T8	227		T76	1		T301	3959
alert_integrity_fail	alert[0x40]	1517	1			T8	19		T14	226		T70	39
alert_ping_fail	alert[0x0]	6	1			T9	1		T302	1		T303	1
alert_ping_fail	alert[0x1]	7	1			T10	1		T238	1		T304	1
alert_ping_fail	alert[0x2]	8	1			T305	1		T306	1		T302	1
alert_ping_fail	alert[0x3]	6	1			T307	1		T308	1		T303	1
alert_ping_fail	alert[0x4]	5	1			T4	1		T9	1		T304	1
alert_ping_fail	alert[0x5]	12	1			T216	1		T309	1		T310	1
alert_ping_fail	alert[0x6]	16	1			T305	1		T311	1		T95	1
alert_ping_fail	alert[0x7]	14	1			T9	1		T10	1		T298	1
alert_ping_fail	alert[0x8]	10	1			T4	1		T312	1		T313	1
alert_ping_fail	alert[0x9]	10	1			T305	1		T307	1		T306	2
alert_ping_fail	alert[0xa]	13	1			T10	1		T298	1		T216	1
alert_ping_fail	alert[0xb]	9	1			T10	1		T311	1		T314	1
alert_ping_fail	alert[0xc]	11	1			T9	1		T95	1		T306	1
alert_ping_fail	alert[0xd]	10	1			T307	1		T315	1		T306	1
alert_ping_fail	alert[0xe]	13	1			T4	2		T304	1		T316	1
alert_ping_fail	alert[0xf]	7	1			T10	2		T317	1		T303	1
alert_ping_fail	alert[0x10]	12	1			T9	1		T95	1		T307	1
alert_ping_fail	alert[0x11]	6	1			T9	1		T308	1		T318	1
alert_ping_fail	alert[0x12]	15	1			T10	1		T233	1		T312	1
alert_ping_fail	alert[0x13]	13	1			T4	1		T95	1		T319	1
alert_ping_fail	alert[0x14]	11	1			T9	1		T307	1		T319	1
alert_ping_fail	alert[0x15]	13	1			T4	1		T9	1		T10	1
alert_ping_fail	alert[0x16]	14	1			T4	1		T10	1		T319	1
alert_ping_fail	alert[0x17]	9	1			T238	1		T95	1		T307	1
alert_ping_fail	alert[0x18]	5	1			T9	1		T304	3		T320	1
alert_ping_fail	alert[0x19]	14	1			T311	1		T312	1		T304	1
alert_ping_fail	alert[0x1a]	6	1			T4	1		T10	1		T311	1
alert_ping_fail	alert[0x1b]	4	1			T10	1		T305	1		T311	1
alert_ping_fail	alert[0x1c]	12	1			T238	1		T305	1		T312	1
alert_ping_fail	alert[0x1d]	8	1			T4	1		T10	1		T302	1
alert_ping_fail	alert[0x1e]	10	1			T304	2		T317	1		T316	1
alert_ping_fail	alert[0x1f]	13	1			T307	1		T312	1		T321	1
alert_ping_fail	alert[0x20]	12	1			T4	1		T9	2		T16	1
alert_ping_fail	alert[0x21]	10	1			T9	1		T311	1		T312	1
alert_ping_fail	alert[0x22]	9	1			T322	1		T310	1		T323	1
alert_ping_fail	alert[0x23]	14	1			T233	1		T95	1		T307	1
alert_ping_fail	alert[0x24]	7	1			T9	1		T238	1		T321	1
alert_ping_fail	alert[0x25]	3	1			T4	1		T233	1		T324	1
alert_ping_fail	alert[0x26]	14	1			T233	1		T312	1		T325	3
alert_ping_fail	alert[0x27]	11	1			T4	1		T10	1		T305	1
alert_ping_fail	alert[0x28]	12	1			T9	1		T326	1		T281	1
alert_ping_fail	alert[0x29]	9	1			T4	1		T10	1		T238	1
alert_ping_fail	alert[0x2a]	10	1			T95	1		T327	1		T328	1
alert_ping_fail	alert[0x2b]	9	1			T4	1		T9	1		T10	1
alert_ping_fail	alert[0x2c]	16	1			T311	1		T95	1		T319	3
alert_ping_fail	alert[0x2d]	18	1			T10	1		T305	2		T312	1
alert_ping_fail	alert[0x2e]	11	1			T9	1		T281	1		T307	1
alert_ping_fail	alert[0x2f]	20	1			T10	1		T305	1		T95	2
alert_ping_fail	alert[0x30]	11	1			T4	1		T95	1		T321	1
alert_ping_fail	alert[0x31]	10	1			T307	1		T315	1		T329	1
alert_ping_fail	alert[0x32]	7	1			T10	1		T306	1		T321	1
alert_ping_fail	alert[0x33]	6	1			T238	1		T323	1		T330	1
alert_ping_fail	alert[0x34]	9	1			T4	1		T10	1		T95	1
alert_ping_fail	alert[0x35]	9	1			T308	1		T303	1		T331	1
alert_ping_fail	alert[0x36]	12	1			T312	1		T306	1		T304	3
alert_ping_fail	alert[0x37]	9	1			T311	2		T315	1		T306	1
alert_ping_fail	alert[0x38]	8	1			T95	1		T317	1		T303	1
alert_ping_fail	alert[0x39]	5	1			T95	1		T307	1		T331	1
alert_ping_fail	alert[0x3a]	12	1			T4	1		T9	2		T10	1
alert_ping_fail	alert[0x3b]	8	1			T306	1		T304	1		T328	1
alert_ping_fail	alert[0x3c]	10	1			T4	1		T315	1		T317	1
alert_ping_fail	alert[0x3d]	8	1			T4	1		T306	1		T316	1
alert_ping_fail	alert[0x3e]	8	1			T321	1		T323	1		T290	1
alert_ping_fail	alert[0x3f]	4	1			T95	1		T329	1		T332	1
alert_ping_fail	alert[0x40]	6	1			T238	1		T233	1		T306	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	72224	1			T2	9382		T5	22		T28	1539
alert_integrity_fail	class_i[0x1]	106127	1			T2	6		T5	5		T8	24803
alert_integrity_fail	class_i[0x2]	114983	1			T3	14		T5	7		T22	75
alert_integrity_fail	class_i[0x3]	99970	1			T2	16		T5	6		T14	560
alert_ping_fail	class_i[0x0]	128	1			T10	3		T238	1		T305	3
alert_ping_fail	class_i[0x1]	186	1			T10	2		T238	4		T311	1
alert_ping_fail	class_i[0x2]	145	1			T4	18		T9	1		T16	1
alert_ping_fail	class_i[0x3]	190	1			T4	1		T9	17		T10	13