Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.75 100.00 100.00 100.00 99.38 99.56


Total test records in report: 830
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T776 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.711776845 Apr 16 01:06:18 PM PDT 24 Apr 16 01:06:39 PM PDT 24 256569329 ps
T777 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3601405899 Apr 16 01:06:01 PM PDT 24 Apr 16 01:06:06 PM PDT 24 110067534 ps
T778 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2812440992 Apr 16 01:06:06 PM PDT 24 Apr 16 01:06:08 PM PDT 24 26775669 ps
T779 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3513535059 Apr 16 01:05:54 PM PDT 24 Apr 16 01:06:42 PM PDT 24 2703962242 ps
T780 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1883250655 Apr 16 01:05:55 PM PDT 24 Apr 16 01:06:01 PM PDT 24 62712667 ps
T781 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1870264156 Apr 16 01:06:11 PM PDT 24 Apr 16 01:06:30 PM PDT 24 258002499 ps
T782 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.449000062 Apr 16 01:06:08 PM PDT 24 Apr 16 01:06:41 PM PDT 24 1915312801 ps
T110 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2309688713 Apr 16 01:06:18 PM PDT 24 Apr 16 01:14:24 PM PDT 24 12296873863 ps
T783 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4042813093 Apr 16 01:05:58 PM PDT 24 Apr 16 01:06:08 PM PDT 24 396260712 ps
T784 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3705982734 Apr 16 01:06:18 PM PDT 24 Apr 16 01:06:21 PM PDT 24 10866761 ps
T785 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.4089200805 Apr 16 01:05:59 PM PDT 24 Apr 16 01:06:06 PM PDT 24 112719361 ps
T786 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2671506409 Apr 16 01:06:13 PM PDT 24 Apr 16 01:06:15 PM PDT 24 9760380 ps
T787 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4245263207 Apr 16 01:05:56 PM PDT 24 Apr 16 01:05:59 PM PDT 24 9290506 ps
T788 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1281825813 Apr 16 01:05:53 PM PDT 24 Apr 16 01:06:03 PM PDT 24 125106573 ps
T789 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.4288661064 Apr 16 01:06:07 PM PDT 24 Apr 16 01:06:14 PM PDT 24 349216155 ps
T790 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3032595000 Apr 16 01:05:50 PM PDT 24 Apr 16 01:09:15 PM PDT 24 1687172375 ps
T124 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.797513226 Apr 16 01:06:01 PM PDT 24 Apr 16 01:21:28 PM PDT 24 12109980936 ps
T791 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2477826008 Apr 16 01:06:02 PM PDT 24 Apr 16 01:06:11 PM PDT 24 104234960 ps
T121 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2834095639 Apr 16 01:06:01 PM PDT 24 Apr 16 01:08:06 PM PDT 24 902249350 ps
T129 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2181385961 Apr 16 01:05:57 PM PDT 24 Apr 16 01:13:40 PM PDT 24 7300365986 ps
T153 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4140594938 Apr 16 01:06:03 PM PDT 24 Apr 16 01:06:07 PM PDT 24 78959466 ps
T792 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4167224711 Apr 16 01:06:14 PM PDT 24 Apr 16 01:06:49 PM PDT 24 1221701275 ps
T122 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3686067564 Apr 16 01:05:53 PM PDT 24 Apr 16 01:14:10 PM PDT 24 7016810952 ps
T793 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2208513539 Apr 16 01:05:45 PM PDT 24 Apr 16 01:05:59 PM PDT 24 735004632 ps
T794 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1326881523 Apr 16 01:06:14 PM PDT 24 Apr 16 01:06:16 PM PDT 24 10765885 ps
T795 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3186861862 Apr 16 01:05:55 PM PDT 24 Apr 16 01:06:05 PM PDT 24 136403032 ps
T123 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3316766341 Apr 16 01:05:58 PM PDT 24 Apr 16 01:07:41 PM PDT 24 1002575054 ps
T131 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3010242779 Apr 16 01:06:09 PM PDT 24 Apr 16 01:13:12 PM PDT 24 23317518917 ps
T149 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.666646420 Apr 16 01:05:54 PM PDT 24 Apr 16 01:06:33 PM PDT 24 590572279 ps
T796 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3612906053 Apr 16 01:05:57 PM PDT 24 Apr 16 01:06:00 PM PDT 24 10735389 ps
T797 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3169307495 Apr 16 01:06:21 PM PDT 24 Apr 16 01:06:24 PM PDT 24 10328503 ps
T798 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4102551856 Apr 16 01:06:16 PM PDT 24 Apr 16 01:06:22 PM PDT 24 70070262 ps
T799 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2084075190 Apr 16 01:06:07 PM PDT 24 Apr 16 01:06:14 PM PDT 24 69036502 ps
T800 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3848947794 Apr 16 01:06:12 PM PDT 24 Apr 16 01:06:23 PM PDT 24 677241775 ps
T133 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1957504705 Apr 16 01:05:48 PM PDT 24 Apr 16 01:16:27 PM PDT 24 8491445246 ps
T801 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3367540778 Apr 16 01:05:55 PM PDT 24 Apr 16 01:07:12 PM PDT 24 2251152624 ps
T126 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2393729610 Apr 16 01:06:08 PM PDT 24 Apr 16 01:09:06 PM PDT 24 6600083738 ps
T125 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1476401710 Apr 16 01:06:00 PM PDT 24 Apr 16 01:09:23 PM PDT 24 3145952603 ps
T802 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4002324753 Apr 16 01:06:00 PM PDT 24 Apr 16 01:06:03 PM PDT 24 8584333 ps
T803 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3631913620 Apr 16 01:05:47 PM PDT 24 Apr 16 01:05:53 PM PDT 24 32632692 ps
T804 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2075018641 Apr 16 01:06:09 PM PDT 24 Apr 16 01:06:47 PM PDT 24 1980187023 ps
T805 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3879253972 Apr 16 01:05:44 PM PDT 24 Apr 16 01:05:55 PM PDT 24 241005937 ps
T806 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1684839194 Apr 16 01:06:06 PM PDT 24 Apr 16 01:06:12 PM PDT 24 52738356 ps
T807 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4242881983 Apr 16 01:06:18 PM PDT 24 Apr 16 01:06:25 PM PDT 24 30262882 ps
T127 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.981730713 Apr 16 01:06:04 PM PDT 24 Apr 16 01:09:17 PM PDT 24 11813304120 ps
T132 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3820943185 Apr 16 01:05:48 PM PDT 24 Apr 16 01:10:36 PM PDT 24 3843418569 ps
T130 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3641243519 Apr 16 01:05:51 PM PDT 24 Apr 16 01:09:34 PM PDT 24 34016822591 ps
T808 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3643194738 Apr 16 01:06:12 PM PDT 24 Apr 16 01:06:15 PM PDT 24 24185547 ps
T146 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1529064261 Apr 16 01:06:13 PM PDT 24 Apr 16 01:06:55 PM PDT 24 651514320 ps
T809 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2496778882 Apr 16 01:06:22 PM PDT 24 Apr 16 01:06:26 PM PDT 24 28716904 ps
T810 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2068417704 Apr 16 01:06:17 PM PDT 24 Apr 16 01:06:20 PM PDT 24 7998154 ps
T811 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1330112568 Apr 16 01:05:49 PM PDT 24 Apr 16 01:05:56 PM PDT 24 50987427 ps
T812 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1551642983 Apr 16 01:05:55 PM PDT 24 Apr 16 01:06:00 PM PDT 24 104056414 ps
T813 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4151098650 Apr 16 01:05:50 PM PDT 24 Apr 16 01:07:42 PM PDT 24 823192115 ps
T147 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3100995276 Apr 16 01:06:14 PM PDT 24 Apr 16 01:06:52 PM PDT 24 307060804 ps
T357 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.759507868 Apr 16 01:06:14 PM PDT 24 Apr 16 01:11:23 PM PDT 24 8309968627 ps
T358 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3519820198 Apr 16 01:06:07 PM PDT 24 Apr 16 01:21:33 PM PDT 24 57820500731 ps
T134 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3091711362 Apr 16 01:05:47 PM PDT 24 Apr 16 01:10:37 PM PDT 24 4013632634 ps
T814 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.45142963 Apr 16 01:05:58 PM PDT 24 Apr 16 01:06:01 PM PDT 24 18447470 ps
T815 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1403049750 Apr 16 01:06:17 PM PDT 24 Apr 16 01:06:19 PM PDT 24 12083884 ps
T816 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1190904817 Apr 16 01:06:13 PM PDT 24 Apr 16 01:06:15 PM PDT 24 16421198 ps
T817 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3709855067 Apr 16 01:06:18 PM PDT 24 Apr 16 01:06:25 PM PDT 24 158703933 ps
T818 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.550709008 Apr 16 01:06:04 PM PDT 24 Apr 16 01:06:13 PM PDT 24 186848398 ps
T819 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1491833298 Apr 16 01:06:01 PM PDT 24 Apr 16 01:06:08 PM PDT 24 33361960 ps
T820 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3935641621 Apr 16 01:06:08 PM PDT 24 Apr 16 01:06:24 PM PDT 24 1087326480 ps
T821 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2083272746 Apr 16 01:05:48 PM PDT 24 Apr 16 01:05:53 PM PDT 24 22622776 ps
T822 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3823824322 Apr 16 01:06:16 PM PDT 24 Apr 16 01:06:18 PM PDT 24 14137835 ps
T267 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3674303357 Apr 16 01:05:54 PM PDT 24 Apr 16 01:05:57 PM PDT 24 93649204 ps
T823 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.137864354 Apr 16 01:06:11 PM PDT 24 Apr 16 01:06:58 PM PDT 24 2604531552 ps
T136 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3466439802 Apr 16 01:06:17 PM PDT 24 Apr 16 01:09:45 PM PDT 24 2021338913 ps
T359 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4214471119 Apr 16 01:05:52 PM PDT 24 Apr 16 01:13:51 PM PDT 24 65645116316 ps
T824 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3355400853 Apr 16 01:06:00 PM PDT 24 Apr 16 01:06:21 PM PDT 24 1098498543 ps
T825 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2285272939 Apr 16 01:06:19 PM PDT 24 Apr 16 01:06:22 PM PDT 24 9476833 ps
T135 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.470734686 Apr 16 01:05:48 PM PDT 24 Apr 16 01:25:37 PM PDT 24 17192646452 ps
T152 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.99937747 Apr 16 01:05:47 PM PDT 24 Apr 16 01:05:51 PM PDT 24 89845083 ps
T826 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1872237409 Apr 16 01:06:11 PM PDT 24 Apr 16 01:06:14 PM PDT 24 9849225 ps
T827 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.695626784 Apr 16 01:05:59 PM PDT 24 Apr 16 01:06:08 PM PDT 24 180912047 ps
T828 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1064363002 Apr 16 01:05:49 PM PDT 24 Apr 16 01:06:02 PM PDT 24 95814519 ps
T829 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.998908056 Apr 16 01:06:09 PM PDT 24 Apr 16 01:06:16 PM PDT 24 57818716 ps
T830 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3524647866 Apr 16 01:06:00 PM PDT 24 Apr 16 01:06:53 PM PDT 24 711138798 ps

Test location /workspace/coverage/default/29.alert_handler_stress_all.3728100343
Short name T5
Test name
Test status
Simulation time 42449161273 ps
CPU time 835.28 seconds
Started Apr 16 02:57:16 PM PDT 24
Finished Apr 16 03:11:12 PM PDT 24
Peak memory 271912 kb
Host smart-dad303c8-87db-4436-baa6-802250126b4f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728100343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3728100343
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3150144449
Short name T14
Test name
Test status
Simulation time 128409848737 ps
CPU time 3323.98 seconds
Started Apr 16 02:54:47 PM PDT 24
Finished Apr 16 03:50:13 PM PDT 24
Peak memory 338636 kb
Host smart-025a6dbf-5863-4484-90e7-35550a47e002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150144449 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3150144449
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3588635183
Short name T11
Test name
Test status
Simulation time 422047679 ps
CPU time 13.05 seconds
Started Apr 16 02:54:47 PM PDT 24
Finished Apr 16 02:55:01 PM PDT 24
Peak memory 265660 kb
Host smart-48f78824-9af2-4162-b15b-5833975f11a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3588635183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3588635183
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4252381919
Short name T138
Test name
Test status
Simulation time 1418459811 ps
CPU time 85.2 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:07:36 PM PDT 24
Peak memory 236688 kb
Host smart-a5daa6fb-910c-4e51-aea1-9462d1c73eeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4252381919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4252381919
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3917726822
Short name T41
Test name
Test status
Simulation time 149022129679 ps
CPU time 4204.4 seconds
Started Apr 16 02:54:50 PM PDT 24
Finished Apr 16 04:04:56 PM PDT 24
Peak memory 306520 kb
Host smart-5be315e7-43db-484a-ae24-86acc10d6b38
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917726822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3917726822
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2757473152
Short name T47
Test name
Test status
Simulation time 65489076792 ps
CPU time 1934.87 seconds
Started Apr 16 02:58:42 PM PDT 24
Finished Apr 16 03:30:58 PM PDT 24
Peak memory 289344 kb
Host smart-d2aae533-a197-4018-8f5e-b213115d4f69
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757473152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2757473152
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.84421639
Short name T101
Test name
Test status
Simulation time 12264467722 ps
CPU time 222.11 seconds
Started Apr 16 01:06:08 PM PDT 24
Finished Apr 16 01:09:51 PM PDT 24
Peak memory 273168 kb
Host smart-1b9e42a9-7568-44d4-bcbb-48298338193f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=84421639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_error
s.84421639
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2811758238
Short name T27
Test name
Test status
Simulation time 21754713845 ps
CPU time 558.19 seconds
Started Apr 16 02:56:35 PM PDT 24
Finished Apr 16 03:05:54 PM PDT 24
Peak memory 265688 kb
Host smart-1b12c9ea-6cc2-4293-a7a9-8ccef15efc38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811758238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2811758238
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2925567325
Short name T42
Test name
Test status
Simulation time 93851990131 ps
CPU time 3002.28 seconds
Started Apr 16 03:00:05 PM PDT 24
Finished Apr 16 03:50:08 PM PDT 24
Peak memory 289480 kb
Host smart-6ad72313-0409-48e0-bc45-838cc6fd274b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925567325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2925567325
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3885228375
Short name T295
Test name
Test status
Simulation time 175152098624 ps
CPU time 2240.29 seconds
Started Apr 16 02:55:50 PM PDT 24
Finished Apr 16 03:33:11 PM PDT 24
Peak memory 289020 kb
Host smart-b4e459ab-ff19-4af1-8982-6b1d60df0444
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885228375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3885228375
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3576047860
Short name T56
Test name
Test status
Simulation time 19220612688 ps
CPU time 969.26 seconds
Started Apr 16 02:55:01 PM PDT 24
Finished Apr 16 03:11:12 PM PDT 24
Peak memory 283960 kb
Host smart-6cebee78-ab5f-4f5b-bb5e-3d11e17f5917
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576047860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3576047860
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.684668856
Short name T105
Test name
Test status
Simulation time 17575440656 ps
CPU time 542.64 seconds
Started Apr 16 01:06:06 PM PDT 24
Finished Apr 16 01:15:10 PM PDT 24
Peak memory 271564 kb
Host smart-3d363044-55c8-476b-b771-e8f8536e48fb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684668856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.684668856
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2061249967
Short name T95
Test name
Test status
Simulation time 22261379958 ps
CPU time 444.57 seconds
Started Apr 16 02:56:49 PM PDT 24
Finished Apr 16 03:04:15 PM PDT 24
Peak memory 247056 kb
Host smart-f2481297-95f4-4e47-a601-599dc54f6f1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061249967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2061249967
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3245643069
Short name T106
Test name
Test status
Simulation time 4843764925 ps
CPU time 655.16 seconds
Started Apr 16 01:06:08 PM PDT 24
Finished Apr 16 01:17:04 PM PDT 24
Peak memory 273024 kb
Host smart-1c795774-5cf0-48c4-8aa0-8636725e7ea7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245643069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3245643069
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.284139018
Short name T33
Test name
Test status
Simulation time 116230858746 ps
CPU time 3112.85 seconds
Started Apr 16 02:54:47 PM PDT 24
Finished Apr 16 03:46:41 PM PDT 24
Peak memory 305276 kb
Host smart-fa0ab0a1-b8f3-41a5-aa95-e50d307a34ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284139018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.284139018
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3820943185
Short name T132
Test name
Test status
Simulation time 3843418569 ps
CPU time 286.85 seconds
Started Apr 16 01:05:48 PM PDT 24
Finished Apr 16 01:10:36 PM PDT 24
Peak memory 270620 kb
Host smart-5b9a9f64-78cf-428a-8e9f-f9556f2aa2b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3820943185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3820943185
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.4104431562
Short name T16
Test name
Test status
Simulation time 361144051577 ps
CPU time 1875.63 seconds
Started Apr 16 02:58:29 PM PDT 24
Finished Apr 16 03:29:45 PM PDT 24
Peak memory 284036 kb
Host smart-9c0299ba-22f3-4185-9266-4416dbecabe7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104431562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.4104431562
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2075749055
Short name T142
Test name
Test status
Simulation time 12048186 ps
CPU time 1.32 seconds
Started Apr 16 01:06:10 PM PDT 24
Finished Apr 16 01:06:13 PM PDT 24
Peak memory 235540 kb
Host smart-d6f30f2b-46da-458e-834e-2a5a8027a0c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2075749055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2075749055
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.112623462
Short name T118
Test name
Test status
Simulation time 49094419313 ps
CPU time 954.47 seconds
Started Apr 16 01:06:01 PM PDT 24
Finished Apr 16 01:21:57 PM PDT 24
Peak memory 265056 kb
Host smart-9e90c2a4-8794-4b38-bf74-9e367d4206a3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112623462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.112623462
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1479294413
Short name T8
Test name
Test status
Simulation time 200309912524 ps
CPU time 2027.43 seconds
Started Apr 16 02:58:03 PM PDT 24
Finished Apr 16 03:31:51 PM PDT 24
Peak memory 286748 kb
Host smart-885958b4-6805-4191-9121-515da4289707
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479294413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1479294413
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.645343066
Short name T10
Test name
Test status
Simulation time 14728714282 ps
CPU time 587.43 seconds
Started Apr 16 02:55:35 PM PDT 24
Finished Apr 16 03:05:23 PM PDT 24
Peak memory 248376 kb
Host smart-519cf4fb-8010-4576-a456-ad7ce0ac7101
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645343066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.645343066
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1786690057
Short name T319
Test name
Test status
Simulation time 158286184236 ps
CPU time 2151.11 seconds
Started Apr 16 02:56:46 PM PDT 24
Finished Apr 16 03:32:38 PM PDT 24
Peak memory 271888 kb
Host smart-93340b37-44db-4309-96d1-faa03a0d3bc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786690057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1786690057
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4058909561
Short name T109
Test name
Test status
Simulation time 8870047370 ps
CPU time 289.8 seconds
Started Apr 16 01:06:20 PM PDT 24
Finished Apr 16 01:11:11 PM PDT 24
Peak memory 272188 kb
Host smart-09512be3-5716-4516-bd01-89a8f871b104
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4058909561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.4058909561
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3466439802
Short name T136
Test name
Test status
Simulation time 2021338913 ps
CPU time 206.91 seconds
Started Apr 16 01:06:17 PM PDT 24
Finished Apr 16 01:09:45 PM PDT 24
Peak memory 264880 kb
Host smart-0d6bb308-be03-42de-b1cc-8585cac97180
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3466439802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3466439802
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.584524426
Short name T288
Test name
Test status
Simulation time 41305699129 ps
CPU time 1276.77 seconds
Started Apr 16 02:56:01 PM PDT 24
Finished Apr 16 03:17:19 PM PDT 24
Peak memory 265536 kb
Host smart-82586e40-dd98-474e-8004-4c371d3c4376
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584524426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.584524426
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.470734686
Short name T135
Test name
Test status
Simulation time 17192646452 ps
CPU time 1188.5 seconds
Started Apr 16 01:05:48 PM PDT 24
Finished Apr 16 01:25:37 PM PDT 24
Peak memory 265000 kb
Host smart-67b1d944-e4a7-475e-bded-a05c331dbbcc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470734686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.470734686
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3470979758
Short name T348
Test name
Test status
Simulation time 124324133968 ps
CPU time 3216.33 seconds
Started Apr 16 02:59:28 PM PDT 24
Finished Apr 16 03:53:05 PM PDT 24
Peak memory 289172 kb
Host smart-268fdc2e-64cc-4aa4-bed7-9cb923e127ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470979758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3470979758
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1202231563
Short name T9
Test name
Test status
Simulation time 20978756857 ps
CPU time 444.21 seconds
Started Apr 16 02:59:31 PM PDT 24
Finished Apr 16 03:06:56 PM PDT 24
Peak memory 247172 kb
Host smart-86e012f8-2bdf-42a5-a0ea-34bbeb53a0af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202231563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1202231563
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1711076611
Short name T49
Test name
Test status
Simulation time 296946075831 ps
CPU time 2276.13 seconds
Started Apr 16 02:57:33 PM PDT 24
Finished Apr 16 03:35:30 PM PDT 24
Peak memory 281432 kb
Host smart-c51baf09-608d-4ffc-bb7c-ae6dd66a888e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711076611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1711076611
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1979207975
Short name T306
Test name
Test status
Simulation time 9756339872 ps
CPU time 407.99 seconds
Started Apr 16 02:58:53 PM PDT 24
Finished Apr 16 03:05:43 PM PDT 24
Peak memory 248036 kb
Host smart-365b631f-06be-4965-a719-42a629d5f20d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979207975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1979207975
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2491292048
Short name T73
Test name
Test status
Simulation time 432898356883 ps
CPU time 2005.48 seconds
Started Apr 16 02:56:52 PM PDT 24
Finished Apr 16 03:30:18 PM PDT 24
Peak memory 285248 kb
Host smart-921c093e-0ac3-41c4-9655-ace3bc8be812
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491292048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2491292048
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2331989884
Short name T108
Test name
Test status
Simulation time 15171478014 ps
CPU time 1053.16 seconds
Started Apr 16 01:05:59 PM PDT 24
Finished Apr 16 01:23:33 PM PDT 24
Peak memory 264928 kb
Host smart-ced8b164-e48a-4dfc-85b7-265484013481
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331989884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2331989884
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1643472597
Short name T248
Test name
Test status
Simulation time 192011833649 ps
CPU time 3046.66 seconds
Started Apr 16 02:59:33 PM PDT 24
Finished Apr 16 03:50:20 PM PDT 24
Peak memory 297848 kb
Host smart-f45d107b-17fa-4fef-a577-ab426a9fe9d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643472597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1643472597
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1337538095
Short name T340
Test name
Test status
Simulation time 18899868156 ps
CPU time 1144.24 seconds
Started Apr 16 02:55:04 PM PDT 24
Finished Apr 16 03:14:09 PM PDT 24
Peak memory 265516 kb
Host smart-4d5501fe-a6ea-4f7d-b7fb-6c1b21a08fb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337538095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1337538095
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1440279672
Short name T350
Test name
Test status
Simulation time 14325309 ps
CPU time 1.24 seconds
Started Apr 16 01:06:12 PM PDT 24
Finished Apr 16 01:06:14 PM PDT 24
Peak memory 236360 kb
Host smart-8d805a77-e47a-4db9-9e9b-f6b125ba0470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1440279672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1440279672
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3577456634
Short name T290
Test name
Test status
Simulation time 17101991336 ps
CPU time 161.65 seconds
Started Apr 16 02:56:11 PM PDT 24
Finished Apr 16 02:58:54 PM PDT 24
Peak memory 248308 kb
Host smart-5a616c91-d06e-46dc-8081-88a96840fc26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577456634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3577456634
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.550778977
Short name T296
Test name
Test status
Simulation time 172522669702 ps
CPU time 2303.31 seconds
Started Apr 16 02:56:40 PM PDT 24
Finished Apr 16 03:35:05 PM PDT 24
Peak memory 271696 kb
Host smart-c84e39f1-ec8c-41d2-8d9a-f052494b6e72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550778977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.550778977
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1642321384
Short name T324
Test name
Test status
Simulation time 13892798823 ps
CPU time 605.34 seconds
Started Apr 16 02:57:24 PM PDT 24
Finished Apr 16 03:07:30 PM PDT 24
Peak memory 248076 kb
Host smart-f5fdca04-c3b1-4d70-ac21-a263460fdd4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642321384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1642321384
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1663326088
Short name T265
Test name
Test status
Simulation time 40019917263 ps
CPU time 803.27 seconds
Started Apr 16 02:56:40 PM PDT 24
Finished Apr 16 03:10:04 PM PDT 24
Peak memory 268244 kb
Host smart-0555b1b8-64f2-4c29-b5f4-72048ca455d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663326088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1663326088
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2423208480
Short name T308
Test name
Test status
Simulation time 15619384993 ps
CPU time 450.83 seconds
Started Apr 16 02:55:14 PM PDT 24
Finished Apr 16 03:02:47 PM PDT 24
Peak memory 249148 kb
Host smart-9c820643-1af9-432a-9448-4e2cbeff875a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423208480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2423208480
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1698023528
Short name T113
Test name
Test status
Simulation time 2507884689 ps
CPU time 155.48 seconds
Started Apr 16 01:06:01 PM PDT 24
Finished Apr 16 01:08:38 PM PDT 24
Peak memory 264960 kb
Host smart-e81915de-e11e-415e-8448-e4bd0e795c76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1698023528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1698023528
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.761602564
Short name T254
Test name
Test status
Simulation time 73593187704 ps
CPU time 1488.93 seconds
Started Apr 16 02:55:25 PM PDT 24
Finished Apr 16 03:20:17 PM PDT 24
Peak memory 306332 kb
Host smart-877d9e36-c5aa-4df4-93fd-28889232b7d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761602564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.761602564
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3652727081
Short name T289
Test name
Test status
Simulation time 623028190 ps
CPU time 26.05 seconds
Started Apr 16 02:58:32 PM PDT 24
Finished Apr 16 02:58:59 PM PDT 24
Peak memory 249040 kb
Host smart-a2fd157f-e299-4360-b910-6c98046892dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36527
27081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3652727081
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2255574577
Short name T279
Test name
Test status
Simulation time 46758450440 ps
CPU time 1198.06 seconds
Started Apr 16 02:55:17 PM PDT 24
Finished Apr 16 03:15:17 PM PDT 24
Peak memory 289552 kb
Host smart-4c6bf2d6-4b0d-4f57-90bf-dd1c62fa6ca2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255574577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2255574577
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3519820198
Short name T358
Test name
Test status
Simulation time 57820500731 ps
CPU time 924.9 seconds
Started Apr 16 01:06:07 PM PDT 24
Finished Apr 16 01:21:33 PM PDT 24
Peak memory 265084 kb
Host smart-a5810f5f-0cf1-4785-95ea-2a51457c170b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519820198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3519820198
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1195608365
Short name T151
Test name
Test status
Simulation time 211517396 ps
CPU time 4.39 seconds
Started Apr 16 01:06:10 PM PDT 24
Finished Apr 16 01:06:16 PM PDT 24
Peak memory 236344 kb
Host smart-6190cc10-decc-49a6-993c-18f6c57f08eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1195608365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1195608365
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.592595134
Short name T139
Test name
Test status
Simulation time 2150392159 ps
CPU time 21.66 seconds
Started Apr 16 01:05:52 PM PDT 24
Finished Apr 16 01:06:15 PM PDT 24
Peak memory 239116 kb
Host smart-3e7a5d0b-43a6-409b-bf8b-3be23ff85970
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=592595134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.592595134
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1072465334
Short name T199
Test name
Test status
Simulation time 42153019 ps
CPU time 3.13 seconds
Started Apr 16 02:54:45 PM PDT 24
Finished Apr 16 02:54:48 PM PDT 24
Peak memory 249368 kb
Host smart-003a32a8-b9b7-4d55-8ec3-24ef2d32a4d2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1072465334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1072465334
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1578986616
Short name T193
Test name
Test status
Simulation time 166658864 ps
CPU time 3.37 seconds
Started Apr 16 02:54:46 PM PDT 24
Finished Apr 16 02:54:50 PM PDT 24
Peak memory 249288 kb
Host smart-a6141f85-dd6b-4f36-ac97-459289d30feb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1578986616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1578986616
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1915557424
Short name T197
Test name
Test status
Simulation time 72730352 ps
CPU time 3.67 seconds
Started Apr 16 02:55:16 PM PDT 24
Finished Apr 16 02:55:22 PM PDT 24
Peak memory 249360 kb
Host smart-c978f7bd-2d4a-4e2e-9407-84398a56fc00
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1915557424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1915557424
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2318415539
Short name T202
Test name
Test status
Simulation time 119028152 ps
CPU time 2.77 seconds
Started Apr 16 02:55:19 PM PDT 24
Finished Apr 16 02:55:24 PM PDT 24
Peak memory 249356 kb
Host smart-9ebeeaeb-a8b2-4a06-8536-421827c4f691
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2318415539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2318415539
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1116931454
Short name T104
Test name
Test status
Simulation time 31544020846 ps
CPU time 484.49 seconds
Started Apr 16 01:05:46 PM PDT 24
Finished Apr 16 01:13:51 PM PDT 24
Peak memory 264884 kb
Host smart-7ddee132-a9cd-41ec-a5c2-1b2a3cd0ba19
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116931454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1116931454
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3977088402
Short name T334
Test name
Test status
Simulation time 25935759649 ps
CPU time 1432.59 seconds
Started Apr 16 02:55:27 PM PDT 24
Finished Apr 16 03:19:22 PM PDT 24
Peak memory 273680 kb
Host smart-cd447c7e-b51e-4af6-aefb-651a45629fb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977088402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3977088402
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.867596159
Short name T246
Test name
Test status
Simulation time 199048498433 ps
CPU time 5250.55 seconds
Started Apr 16 02:55:51 PM PDT 24
Finished Apr 16 04:23:23 PM PDT 24
Peak memory 363776 kb
Host smart-b4757791-3d7c-48c5-b4a3-1ca3e529e416
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867596159 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.867596159
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.729759236
Short name T329
Test name
Test status
Simulation time 8438434915 ps
CPU time 335.06 seconds
Started Apr 16 02:57:12 PM PDT 24
Finished Apr 16 03:02:48 PM PDT 24
Peak memory 247356 kb
Host smart-d3c4da44-5ca9-4a76-bafa-e07321b2e7dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729759236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.729759236
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1091462049
Short name T269
Test name
Test status
Simulation time 24669725275 ps
CPU time 1695.04 seconds
Started Apr 16 02:58:28 PM PDT 24
Finished Apr 16 03:26:44 PM PDT 24
Peak memory 283000 kb
Host smart-540abdd6-7ea9-4d30-97ec-ca65ba718389
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091462049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1091462049
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.981730713
Short name T127
Test name
Test status
Simulation time 11813304120 ps
CPU time 192.6 seconds
Started Apr 16 01:06:04 PM PDT 24
Finished Apr 16 01:09:17 PM PDT 24
Peak memory 264548 kb
Host smart-09010512-115b-45c5-a7c7-cf800db3c946
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=981730713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.981730713
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.165602910
Short name T120
Test name
Test status
Simulation time 7207553317 ps
CPU time 251.13 seconds
Started Apr 16 01:06:18 PM PDT 24
Finished Apr 16 01:10:31 PM PDT 24
Peak memory 264964 kb
Host smart-a7ea9044-3ca5-43d5-89ec-b82d8b0335d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=165602910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.165602910
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1974819102
Short name T756
Test name
Test status
Simulation time 18856783 ps
CPU time 1.4 seconds
Started Apr 16 01:06:08 PM PDT 24
Finished Apr 16 01:06:11 PM PDT 24
Peak memory 235480 kb
Host smart-1c9f90f8-46ec-4443-b0dd-0b98a2b2370d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1974819102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1974819102
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2378285773
Short name T228
Test name
Test status
Simulation time 716498862 ps
CPU time 44.56 seconds
Started Apr 16 02:55:30 PM PDT 24
Finished Apr 16 02:56:16 PM PDT 24
Peak memory 256048 kb
Host smart-9ce5b109-a958-48a1-aeb4-1981fb39e8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23782
85773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2378285773
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2144697566
Short name T283
Test name
Test status
Simulation time 757652224009 ps
CPU time 2629.93 seconds
Started Apr 16 02:55:43 PM PDT 24
Finished Apr 16 03:39:34 PM PDT 24
Peak memory 289732 kb
Host smart-22d4adee-8860-41b1-91f7-9fe747a37478
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144697566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2144697566
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.667102496
Short name T261
Test name
Test status
Simulation time 356124312 ps
CPU time 24.02 seconds
Started Apr 16 02:55:55 PM PDT 24
Finished Apr 16 02:56:20 PM PDT 24
Peak memory 249040 kb
Host smart-265df15e-d175-40db-8d5d-562606a1ee73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66710
2496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.667102496
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3204708529
Short name T263
Test name
Test status
Simulation time 66574183032 ps
CPU time 3806.89 seconds
Started Apr 16 02:56:04 PM PDT 24
Finished Apr 16 03:59:32 PM PDT 24
Peak memory 289424 kb
Host smart-c70fceb2-f685-4ac5-bc28-163a783240e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204708529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3204708529
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1110107138
Short name T291
Test name
Test status
Simulation time 166320336666 ps
CPU time 2764.68 seconds
Started Apr 16 02:56:19 PM PDT 24
Finished Apr 16 03:42:26 PM PDT 24
Peak memory 290108 kb
Host smart-2e4b3409-68ab-45fa-8bd7-51fb0e186e27
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110107138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1110107138
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1827182135
Short name T90
Test name
Test status
Simulation time 23162159919 ps
CPU time 1183.38 seconds
Started Apr 16 02:56:23 PM PDT 24
Finished Apr 16 03:16:08 PM PDT 24
Peak memory 287132 kb
Host smart-581166ef-ce69-408f-ba47-0f261f971f14
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827182135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1827182135
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1152779528
Short name T272
Test name
Test status
Simulation time 6449891204 ps
CPU time 384.86 seconds
Started Apr 16 02:56:30 PM PDT 24
Finished Apr 16 03:02:56 PM PDT 24
Peak memory 257348 kb
Host smart-6aff1744-0f0c-472b-9eb4-6c3d544ec94f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152779528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1152779528
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.632764532
Short name T242
Test name
Test status
Simulation time 1266184176 ps
CPU time 39.15 seconds
Started Apr 16 02:56:40 PM PDT 24
Finished Apr 16 02:57:20 PM PDT 24
Peak memory 249056 kb
Host smart-ff3f491a-732c-4ad7-aeb1-f2c9f9024764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63276
4532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.632764532
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2886722060
Short name T243
Test name
Test status
Simulation time 537934464 ps
CPU time 18.95 seconds
Started Apr 16 02:57:30 PM PDT 24
Finished Apr 16 02:57:49 PM PDT 24
Peak memory 255012 kb
Host smart-c1d0bc13-dd58-4b74-9029-2c765eebb7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28867
22060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2886722060
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.1125420996
Short name T163
Test name
Test status
Simulation time 26143797742 ps
CPU time 3265.87 seconds
Started Apr 16 02:57:43 PM PDT 24
Finished Apr 16 03:52:10 PM PDT 24
Peak memory 322936 kb
Host smart-c42640e8-9e61-4f31-8ffc-5579eb377b3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125420996 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.1125420996
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3180238966
Short name T240
Test name
Test status
Simulation time 263988741 ps
CPU time 33.4 seconds
Started Apr 16 02:58:23 PM PDT 24
Finished Apr 16 02:58:57 PM PDT 24
Peak memory 247988 kb
Host smart-2aeb3acd-0d94-498b-a7f4-a780a2f73842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31802
38966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3180238966
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3781807455
Short name T252
Test name
Test status
Simulation time 7817540107 ps
CPU time 44.54 seconds
Started Apr 16 02:59:04 PM PDT 24
Finished Apr 16 02:59:49 PM PDT 24
Peak memory 249184 kb
Host smart-b2c4a156-cbd5-4ab6-9746-efe489cdae0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37818
07455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3781807455
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2488955815
Short name T51
Test name
Test status
Simulation time 81596472824 ps
CPU time 1210.6 seconds
Started Apr 16 02:59:15 PM PDT 24
Finished Apr 16 03:19:27 PM PDT 24
Peak memory 273092 kb
Host smart-a90c5d24-3182-4e1f-84b4-4828c69964af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488955815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2488955815
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.17167782
Short name T339
Test name
Test status
Simulation time 51871489695 ps
CPU time 2827.14 seconds
Started Apr 16 02:59:41 PM PDT 24
Finished Apr 16 03:46:49 PM PDT 24
Peak memory 289192 kb
Host smart-6454fd69-612b-4809-ac2f-e22e7adbb7f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17167782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.17167782
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.399625434
Short name T286
Test name
Test status
Simulation time 341825845 ps
CPU time 30.8 seconds
Started Apr 16 03:00:10 PM PDT 24
Finished Apr 16 03:00:42 PM PDT 24
Peak memory 249052 kb
Host smart-c1af77f6-89b9-40a6-acfe-72513b02aa05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39962
5434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.399625434
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3091711362
Short name T134
Test name
Test status
Simulation time 4013632634 ps
CPU time 288.8 seconds
Started Apr 16 01:05:47 PM PDT 24
Finished Apr 16 01:10:37 PM PDT 24
Peak memory 264984 kb
Host smart-cc46db99-ee38-4023-92e9-51015fa91ff7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3091711362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3091711362
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1399928451
Short name T148
Test name
Test status
Simulation time 2170803198 ps
CPU time 80.57 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:07:11 PM PDT 24
Peak memory 236752 kb
Host smart-a73c723e-afc7-47c5-b145-a93fb35b901f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1399928451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1399928451
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1105606499
Short name T143
Test name
Test status
Simulation time 1840114609 ps
CPU time 71.44 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:07:22 PM PDT 24
Peak memory 239968 kb
Host smart-2a995339-bbeb-49ac-bcb3-36b08e01622f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1105606499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1105606499
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.598741656
Short name T137
Test name
Test status
Simulation time 96410987 ps
CPU time 5.13 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:06:15 PM PDT 24
Peak memory 236620 kb
Host smart-4c1da361-aba8-4d56-b675-dbdc6eca2326
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=598741656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.598741656
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2834095639
Short name T121
Test name
Test status
Simulation time 902249350 ps
CPU time 124.14 seconds
Started Apr 16 01:06:01 PM PDT 24
Finished Apr 16 01:08:06 PM PDT 24
Peak memory 264864 kb
Host smart-54ac0955-64f3-403f-a52d-c4abed705954
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2834095639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2834095639
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2696975097
Short name T150
Test name
Test status
Simulation time 3698696492 ps
CPU time 68.04 seconds
Started Apr 16 01:05:58 PM PDT 24
Finished Apr 16 01:07:08 PM PDT 24
Peak memory 245128 kb
Host smart-f8d90e9b-ce41-4e59-84d1-87280a75729d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2696975097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2696975097
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1529064261
Short name T146
Test name
Test status
Simulation time 651514320 ps
CPU time 41.12 seconds
Started Apr 16 01:06:13 PM PDT 24
Finished Apr 16 01:06:55 PM PDT 24
Peak memory 244640 kb
Host smart-3383a5ee-323e-4c92-aa76-a5f96776a7cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1529064261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1529064261
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.99937747
Short name T152
Test name
Test status
Simulation time 89845083 ps
CPU time 3.56 seconds
Started Apr 16 01:05:47 PM PDT 24
Finished Apr 16 01:05:51 PM PDT 24
Peak memory 235452 kb
Host smart-576056b4-65cb-4d55-8bd1-b1a17d3b3714
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=99937747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.99937747
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2927039069
Short name T154
Test name
Test status
Simulation time 179527648 ps
CPU time 3.62 seconds
Started Apr 16 01:05:54 PM PDT 24
Finished Apr 16 01:05:58 PM PDT 24
Peak memory 236352 kb
Host smart-fc56671e-2f19-4813-b1e4-274f09b4cd9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2927039069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2927039069
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2941168564
Short name T159
Test name
Test status
Simulation time 607740793 ps
CPU time 22.28 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:06:12 PM PDT 24
Peak memory 239912 kb
Host smart-2ac44021-000d-48a6-9504-5c77fedec915
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2941168564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2941168564
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3742908295
Short name T111
Test name
Test status
Simulation time 1684735505 ps
CPU time 225.96 seconds
Started Apr 16 01:06:10 PM PDT 24
Finished Apr 16 01:09:57 PM PDT 24
Peak memory 264944 kb
Host smart-cc308a25-e736-414b-bec2-342632d9064d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3742908295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3742908295
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3100995276
Short name T147
Test name
Test status
Simulation time 307060804 ps
CPU time 37.12 seconds
Started Apr 16 01:06:14 PM PDT 24
Finished Apr 16 01:06:52 PM PDT 24
Peak memory 236592 kb
Host smart-505169d7-5135-467e-9b0b-0aa025cab2d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3100995276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3100995276
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.665147387
Short name T157
Test name
Test status
Simulation time 41585707 ps
CPU time 3.87 seconds
Started Apr 16 01:06:06 PM PDT 24
Finished Apr 16 01:06:10 PM PDT 24
Peak memory 236296 kb
Host smart-d4d2d7fe-3d94-4e01-814a-7fe7c7aa5658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=665147387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.665147387
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.41796895
Short name T155
Test name
Test status
Simulation time 1211722191 ps
CPU time 46.59 seconds
Started Apr 16 01:06:10 PM PDT 24
Finished Apr 16 01:06:58 PM PDT 24
Peak memory 239224 kb
Host smart-ea6d72d5-92d9-49cb-946e-a66a2598585f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=41796895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.41796895
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4140594938
Short name T153
Test name
Test status
Simulation time 78959466 ps
CPU time 2.6 seconds
Started Apr 16 01:06:03 PM PDT 24
Finished Apr 16 01:06:07 PM PDT 24
Peak memory 236300 kb
Host smart-46ce75ab-644b-466d-9e54-072acedbf2cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4140594938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.4140594938
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1079279565
Short name T144
Test name
Test status
Simulation time 32672298 ps
CPU time 2 seconds
Started Apr 16 01:06:07 PM PDT 24
Finished Apr 16 01:06:10 PM PDT 24
Peak memory 236364 kb
Host smart-ed59adc2-a5e4-494b-8d41-9a873a97a58e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1079279565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1079279565
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.666646420
Short name T149
Test name
Test status
Simulation time 590572279 ps
CPU time 37.68 seconds
Started Apr 16 01:05:54 PM PDT 24
Finished Apr 16 01:06:33 PM PDT 24
Peak memory 236608 kb
Host smart-59face53-2627-4f48-8bbb-e5ee6269a45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=666646420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.666646420
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3946547652
Short name T145
Test name
Test status
Simulation time 43060428 ps
CPU time 3.29 seconds
Started Apr 16 01:05:59 PM PDT 24
Finished Apr 16 01:06:04 PM PDT 24
Peak memory 236340 kb
Host smart-7b386877-d44e-4827-a044-3ba196af0b06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3946547652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3946547652
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.4077020813
Short name T24
Test name
Test status
Simulation time 2799198975 ps
CPU time 43.39 seconds
Started Apr 16 02:55:05 PM PDT 24
Finished Apr 16 02:55:49 PM PDT 24
Peak memory 255768 kb
Host smart-8a31f984-9c3b-4607-a7a2-67d516e107f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40770
20813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.4077020813
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1301660202
Short name T723
Test name
Test status
Simulation time 1419975218 ps
CPU time 150.33 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:08:21 PM PDT 24
Peak memory 239916 kb
Host smart-4e892db8-c4b4-4b21-90ac-9bf776382677
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1301660202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1301660202
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.49867939
Short name T765
Test name
Test status
Simulation time 7774376132 ps
CPU time 205.3 seconds
Started Apr 16 01:05:45 PM PDT 24
Finished Apr 16 01:09:11 PM PDT 24
Peak memory 236424 kb
Host smart-f96af92e-4f94-4fe0-a652-54c35b0887a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=49867939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.49867939
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3879253972
Short name T805
Test name
Test status
Simulation time 241005937 ps
CPU time 9.48 seconds
Started Apr 16 01:05:44 PM PDT 24
Finished Apr 16 01:05:55 PM PDT 24
Peak memory 240000 kb
Host smart-97ecaf45-0491-4a73-aaeb-44c712a20169
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3879253972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3879253972
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.399844003
Short name T732
Test name
Test status
Simulation time 245334240 ps
CPU time 9.15 seconds
Started Apr 16 01:05:47 PM PDT 24
Finished Apr 16 01:05:57 PM PDT 24
Peak memory 253344 kb
Host smart-8da2a3d7-9a84-42b0-b885-9d9f0efef57b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399844003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.399844003
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1294191960
Short name T179
Test name
Test status
Simulation time 130172716 ps
CPU time 9.4 seconds
Started Apr 16 01:05:42 PM PDT 24
Finished Apr 16 01:05:52 PM PDT 24
Peak memory 240028 kb
Host smart-3adfe833-e9a9-4156-a6f0-0e20b1179ae7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1294191960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1294191960
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3255768226
Short name T721
Test name
Test status
Simulation time 7695326 ps
CPU time 1.46 seconds
Started Apr 16 01:05:48 PM PDT 24
Finished Apr 16 01:05:50 PM PDT 24
Peak memory 235452 kb
Host smart-60288423-a5f0-458f-bf8d-dfc5940698d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3255768226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3255768226
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.328683481
Short name T736
Test name
Test status
Simulation time 1129173260 ps
CPU time 18.23 seconds
Started Apr 16 01:05:42 PM PDT 24
Finished Apr 16 01:06:01 PM PDT 24
Peak memory 248216 kb
Host smart-fd6361fa-2eda-4644-8571-85099a3ee787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=328683481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.328683481
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1406799075
Short name T107
Test name
Test status
Simulation time 3282138576 ps
CPU time 104.58 seconds
Started Apr 16 01:05:51 PM PDT 24
Finished Apr 16 01:07:36 PM PDT 24
Peak memory 264884 kb
Host smart-58315148-eded-4ed0-8265-48485d0ec75c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1406799075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1406799075
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2208513539
Short name T793
Test name
Test status
Simulation time 735004632 ps
CPU time 12.86 seconds
Started Apr 16 01:05:45 PM PDT 24
Finished Apr 16 01:05:59 PM PDT 24
Peak memory 248432 kb
Host smart-fb75976e-3638-41f5-9945-163f2b818011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2208513539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2208513539
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.318679503
Short name T175
Test name
Test status
Simulation time 1734406964 ps
CPU time 113.15 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:07:43 PM PDT 24
Peak memory 239928 kb
Host smart-02f2073f-7f3f-4fd9-a7dc-dcb35f8be387
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=318679503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.318679503
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.4038810853
Short name T718
Test name
Test status
Simulation time 12560379653 ps
CPU time 238.46 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:09:48 PM PDT 24
Peak memory 236380 kb
Host smart-e9daa71b-f808-403b-af98-c4cb9da10c18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4038810853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.4038810853
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.282473998
Short name T178
Test name
Test status
Simulation time 79425174 ps
CPU time 6.46 seconds
Started Apr 16 01:05:55 PM PDT 24
Finished Apr 16 01:06:03 PM PDT 24
Peak memory 240028 kb
Host smart-2ac7cdc6-9381-410a-98b5-1aa106fe0be7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=282473998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.282473998
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2939388626
Short name T730
Test name
Test status
Simulation time 56002811 ps
CPU time 8.38 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:05:59 PM PDT 24
Peak memory 251668 kb
Host smart-6b9c4cea-0107-4daf-ab16-3ce376ce8d37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939388626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2939388626
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3695335433
Short name T755
Test name
Test status
Simulation time 122041822 ps
CPU time 5.28 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:05:55 PM PDT 24
Peak memory 236328 kb
Host smart-298f122a-1b40-4c6d-bfc2-acb1c1e78659
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3695335433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3695335433
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.682173708
Short name T771
Test name
Test status
Simulation time 9867053 ps
CPU time 1.22 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:05:51 PM PDT 24
Peak memory 235496 kb
Host smart-1ca0f7a7-2100-46f4-8dc7-c05c1823baf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=682173708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.682173708
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3516485643
Short name T739
Test name
Test status
Simulation time 400955777 ps
CPU time 11.05 seconds
Started Apr 16 01:05:52 PM PDT 24
Finished Apr 16 01:06:04 PM PDT 24
Peak memory 240008 kb
Host smart-80e59222-595c-44bc-bdb9-5ee1a072cdd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3516485643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3516485643
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1484898945
Short name T116
Test name
Test status
Simulation time 2148168708 ps
CPU time 158.24 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:08:28 PM PDT 24
Peak memory 265532 kb
Host smart-cac2f756-29f7-464f-a7cb-b5edd953800c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1484898945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1484898945
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4214471119
Short name T359
Test name
Test status
Simulation time 65645116316 ps
CPU time 478.79 seconds
Started Apr 16 01:05:52 PM PDT 24
Finished Apr 16 01:13:51 PM PDT 24
Peak memory 264896 kb
Host smart-377e6613-f4d1-45d3-b89e-c34b1509edbc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214471119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.4214471119
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1064363002
Short name T828
Test name
Test status
Simulation time 95814519 ps
CPU time 11.72 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:06:02 PM PDT 24
Peak memory 248288 kb
Host smart-6e883539-6f0d-4db5-8304-a3ef4ed0647b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1064363002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1064363002
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3601405899
Short name T777
Test name
Test status
Simulation time 110067534 ps
CPU time 4.07 seconds
Started Apr 16 01:06:01 PM PDT 24
Finished Apr 16 01:06:06 PM PDT 24
Peak memory 238752 kb
Host smart-6387af3d-057a-4982-a770-806d6b333034
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601405899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3601405899
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1491833298
Short name T819
Test name
Test status
Simulation time 33361960 ps
CPU time 5.22 seconds
Started Apr 16 01:06:01 PM PDT 24
Finished Apr 16 01:06:08 PM PDT 24
Peak memory 236344 kb
Host smart-bdc984b4-7b77-4b60-9b9e-483d25322d74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1491833298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1491833298
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4002324753
Short name T802
Test name
Test status
Simulation time 8584333 ps
CPU time 1.61 seconds
Started Apr 16 01:06:00 PM PDT 24
Finished Apr 16 01:06:03 PM PDT 24
Peak memory 236380 kb
Host smart-daeac132-e65a-40a6-98b3-0404253bf125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4002324753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4002324753
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1870264156
Short name T781
Test name
Test status
Simulation time 258002499 ps
CPU time 18.28 seconds
Started Apr 16 01:06:11 PM PDT 24
Finished Apr 16 01:06:30 PM PDT 24
Peak memory 244528 kb
Host smart-efe66f68-d661-450f-bd67-b0435b3d0360
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1870264156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1870264156
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.999004186
Short name T112
Test name
Test status
Simulation time 3377143854 ps
CPU time 162.4 seconds
Started Apr 16 01:05:58 PM PDT 24
Finished Apr 16 01:08:42 PM PDT 24
Peak memory 271288 kb
Host smart-84b7f0be-71e3-4821-9771-6a8c7f4cc10b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=999004186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.999004186
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3546784022
Short name T709
Test name
Test status
Simulation time 914359070 ps
CPU time 16.93 seconds
Started Apr 16 01:06:08 PM PDT 24
Finished Apr 16 01:06:26 PM PDT 24
Peak memory 249280 kb
Host smart-14352fc8-e464-4ec9-85d8-903fbbeb3bd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3546784022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3546784022
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.550709008
Short name T818
Test name
Test status
Simulation time 186848398 ps
CPU time 8.2 seconds
Started Apr 16 01:06:04 PM PDT 24
Finished Apr 16 01:06:13 PM PDT 24
Peak memory 247820 kb
Host smart-61180e96-7b4e-4168-bb4d-d002611cf6f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550709008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.550709008
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1684839194
Short name T806
Test name
Test status
Simulation time 52738356 ps
CPU time 5.05 seconds
Started Apr 16 01:06:06 PM PDT 24
Finished Apr 16 01:06:12 PM PDT 24
Peak memory 236268 kb
Host smart-cec07c0c-874a-4e4f-ad41-4450137e600f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1684839194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1684839194
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2812440992
Short name T778
Test name
Test status
Simulation time 26775669 ps
CPU time 2.14 seconds
Started Apr 16 01:06:06 PM PDT 24
Finished Apr 16 01:06:08 PM PDT 24
Peak memory 236268 kb
Host smart-7eb90a18-87cf-402f-b6c7-1d9a25e03524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2812440992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2812440992
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2613047955
Short name T176
Test name
Test status
Simulation time 1348358245 ps
CPU time 42.95 seconds
Started Apr 16 01:06:11 PM PDT 24
Finished Apr 16 01:06:55 PM PDT 24
Peak memory 244528 kb
Host smart-13564cee-f9f3-49d2-9808-333fe210ba63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2613047955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2613047955
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.4288661064
Short name T789
Test name
Test status
Simulation time 349216155 ps
CPU time 6.43 seconds
Started Apr 16 01:06:07 PM PDT 24
Finished Apr 16 01:06:14 PM PDT 24
Peak memory 249684 kb
Host smart-a8a42852-bf24-4b65-8388-217e1876b86e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4288661064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.4288661064
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2785624465
Short name T743
Test name
Test status
Simulation time 117858953 ps
CPU time 10.68 seconds
Started Apr 16 01:06:18 PM PDT 24
Finished Apr 16 01:06:30 PM PDT 24
Peak memory 251144 kb
Host smart-4dada461-e0ef-4782-a3a1-b3b05817da78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785624465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2785624465
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2935856933
Short name T772
Test name
Test status
Simulation time 151969026 ps
CPU time 8.25 seconds
Started Apr 16 01:06:10 PM PDT 24
Finished Apr 16 01:06:20 PM PDT 24
Peak memory 235484 kb
Host smart-28e8300f-d0fe-4097-9b4f-c023bdfc1a88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2935856933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2935856933
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3097078746
Short name T717
Test name
Test status
Simulation time 8176697 ps
CPU time 1.59 seconds
Started Apr 16 01:06:06 PM PDT 24
Finished Apr 16 01:06:09 PM PDT 24
Peak memory 236348 kb
Host smart-73a47e1d-2a69-4cfd-a419-c3bf3ab9562d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3097078746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3097078746
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3522447194
Short name T753
Test name
Test status
Simulation time 656401729 ps
CPU time 44.13 seconds
Started Apr 16 01:06:11 PM PDT 24
Finished Apr 16 01:06:56 PM PDT 24
Peak memory 244548 kb
Host smart-9b72ca25-fe42-457a-bf87-4c249ec4ba0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3522447194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3522447194
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.152994442
Short name T741
Test name
Test status
Simulation time 679878544 ps
CPU time 5.93 seconds
Started Apr 16 01:06:05 PM PDT 24
Finished Apr 16 01:06:11 PM PDT 24
Peak memory 247380 kb
Host smart-5e92554b-1f9e-45e5-9067-cb7e9884237e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=152994442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.152994442
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3790472850
Short name T266
Test name
Test status
Simulation time 571338222 ps
CPU time 34.86 seconds
Started Apr 16 01:06:04 PM PDT 24
Finished Apr 16 01:06:40 PM PDT 24
Peak memory 236528 kb
Host smart-495d0418-1aaf-4b6e-b97c-a37baa78be03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3790472850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3790472850
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2084075190
Short name T799
Test name
Test status
Simulation time 69036502 ps
CPU time 5.57 seconds
Started Apr 16 01:06:07 PM PDT 24
Finished Apr 16 01:06:14 PM PDT 24
Peak memory 252000 kb
Host smart-3077b85f-b9e5-4f47-8992-de3828a5000e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084075190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2084075190
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3206227317
Short name T752
Test name
Test status
Simulation time 327367642 ps
CPU time 5.19 seconds
Started Apr 16 01:06:19 PM PDT 24
Finished Apr 16 01:06:25 PM PDT 24
Peak memory 236352 kb
Host smart-14b5f710-a422-4839-afa3-f87f72df4c90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3206227317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3206227317
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.693604695
Short name T731
Test name
Test status
Simulation time 6518909 ps
CPU time 1.48 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:06:11 PM PDT 24
Peak memory 236376 kb
Host smart-ad8d9d69-41b7-4736-8630-e1dda05d4910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=693604695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.693604695
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2075018641
Short name T804
Test name
Test status
Simulation time 1980187023 ps
CPU time 37.25 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:06:47 PM PDT 24
Peak memory 248120 kb
Host smart-7f343d13-3d78-4c68-ad28-60b05e8abbd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2075018641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2075018641
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2393729610
Short name T126
Test name
Test status
Simulation time 6600083738 ps
CPU time 177.67 seconds
Started Apr 16 01:06:08 PM PDT 24
Finished Apr 16 01:09:06 PM PDT 24
Peak memory 264972 kb
Host smart-377053b8-ab52-48eb-8156-04405ba5f678
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2393729610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2393729610
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3010242779
Short name T131
Test name
Test status
Simulation time 23317518917 ps
CPU time 422.3 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:13:12 PM PDT 24
Peak memory 264668 kb
Host smart-748e208f-c995-4bfe-bb2c-38e71fd9398a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010242779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3010242779
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3412077174
Short name T760
Test name
Test status
Simulation time 97166676 ps
CPU time 10.21 seconds
Started Apr 16 01:06:07 PM PDT 24
Finished Apr 16 01:06:18 PM PDT 24
Peak memory 248312 kb
Host smart-26f78306-dc2e-44a8-af8e-2eac0f460125
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3412077174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3412077174
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.998908056
Short name T829
Test name
Test status
Simulation time 57818716 ps
CPU time 6.22 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:06:16 PM PDT 24
Peak memory 242500 kb
Host smart-0adb81cd-2f39-4561-9137-48dba37ee10e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998908056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.998908056
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2674888307
Short name T716
Test name
Test status
Simulation time 64940888 ps
CPU time 3.24 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:06:13 PM PDT 24
Peak memory 239948 kb
Host smart-8c5c867e-7647-46f5-92b5-f652dc90e981
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2674888307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2674888307
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.449000062
Short name T782
Test name
Test status
Simulation time 1915312801 ps
CPU time 32.09 seconds
Started Apr 16 01:06:08 PM PDT 24
Finished Apr 16 01:06:41 PM PDT 24
Peak memory 248192 kb
Host smart-8b98a976-fe79-49f5-b36d-4e100d2d4f77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=449000062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.449000062
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3778247590
Short name T102
Test name
Test status
Simulation time 12791985286 ps
CPU time 883.56 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:20:53 PM PDT 24
Peak memory 264896 kb
Host smart-23d5ce32-7609-40fc-93e8-d955d641b4a1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778247590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3778247590
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3935641621
Short name T820
Test name
Test status
Simulation time 1087326480 ps
CPU time 14.85 seconds
Started Apr 16 01:06:08 PM PDT 24
Finished Apr 16 01:06:24 PM PDT 24
Peak memory 248144 kb
Host smart-992606c3-17a7-42ba-8420-2891648a78d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3935641621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3935641621
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4162672765
Short name T710
Test name
Test status
Simulation time 77428509 ps
CPU time 5.42 seconds
Started Apr 16 01:06:10 PM PDT 24
Finished Apr 16 01:06:17 PM PDT 24
Peak memory 237432 kb
Host smart-bbcc1618-5fd2-403b-84d3-a871bd31891e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162672765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.4162672765
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1600227347
Short name T750
Test name
Test status
Simulation time 54011822 ps
CPU time 4.53 seconds
Started Apr 16 01:06:06 PM PDT 24
Finished Apr 16 01:06:11 PM PDT 24
Peak memory 236228 kb
Host smart-6ddda06b-28d3-4ac1-8fb9-88ff868cdcea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1600227347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1600227347
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.386740780
Short name T759
Test name
Test status
Simulation time 20731497 ps
CPU time 1.29 seconds
Started Apr 16 01:06:10 PM PDT 24
Finished Apr 16 01:06:13 PM PDT 24
Peak memory 234424 kb
Host smart-eaac3664-2044-4021-bac1-3fae086591b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=386740780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.386740780
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.711776845
Short name T776
Test name
Test status
Simulation time 256569329 ps
CPU time 19.24 seconds
Started Apr 16 01:06:18 PM PDT 24
Finished Apr 16 01:06:39 PM PDT 24
Peak memory 239964 kb
Host smart-650aaed3-a3d1-4bf9-9fd6-ef4ea2fc2265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=711776845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.711776845
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.723759598
Short name T234
Test name
Test status
Simulation time 949810843 ps
CPU time 19.75 seconds
Started Apr 16 01:06:11 PM PDT 24
Finished Apr 16 01:06:32 PM PDT 24
Peak memory 253600 kb
Host smart-f2c394f3-bfab-4ad0-8d0e-b2baead59fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=723759598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.723759598
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2771829733
Short name T746
Test name
Test status
Simulation time 322515468 ps
CPU time 11.66 seconds
Started Apr 16 01:06:10 PM PDT 24
Finished Apr 16 01:06:23 PM PDT 24
Peak memory 249280 kb
Host smart-9bf7906c-74b1-43d9-bee3-6b59ffaa3f0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771829733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2771829733
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2404332548
Short name T174
Test name
Test status
Simulation time 120718713 ps
CPU time 5.52 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:06:15 PM PDT 24
Peak memory 236228 kb
Host smart-3358ab3e-7c3e-4d3d-90f2-7bb7637c7b6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2404332548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2404332548
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.496850402
Short name T354
Test name
Test status
Simulation time 7613828 ps
CPU time 1.44 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:06:12 PM PDT 24
Peak memory 234472 kb
Host smart-e3fe190e-79ca-40ce-b3f7-979b18d6cbf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=496850402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.496850402
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.137864354
Short name T823
Test name
Test status
Simulation time 2604531552 ps
CPU time 45.14 seconds
Started Apr 16 01:06:11 PM PDT 24
Finished Apr 16 01:06:58 PM PDT 24
Peak memory 244632 kb
Host smart-ee48f638-2867-4e3f-943c-6ea8b1e19670
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=137864354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.137864354
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.750504995
Short name T115
Test name
Test status
Simulation time 3421150998 ps
CPU time 102.78 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:07:53 PM PDT 24
Peak memory 256708 kb
Host smart-5ecf8061-01e8-46b1-9ad9-5ae1aa35c935
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=750504995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.750504995
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3531172437
Short name T749
Test name
Test status
Simulation time 139274334 ps
CPU time 4.58 seconds
Started Apr 16 01:06:09 PM PDT 24
Finished Apr 16 01:06:14 PM PDT 24
Peak memory 248012 kb
Host smart-6d6f8f12-c63a-45bf-9b1a-af43b1d245bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3531172437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3531172437
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3649197230
Short name T735
Test name
Test status
Simulation time 82477811 ps
CPU time 6.9 seconds
Started Apr 16 01:06:10 PM PDT 24
Finished Apr 16 01:06:18 PM PDT 24
Peak memory 239728 kb
Host smart-945dec33-d88f-4bc3-8be5-a26274e9f413
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649197230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3649197230
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3709855067
Short name T817
Test name
Test status
Simulation time 158703933 ps
CPU time 5.02 seconds
Started Apr 16 01:06:18 PM PDT 24
Finished Apr 16 01:06:25 PM PDT 24
Peak memory 239180 kb
Host smart-eddb286d-9c02-49c9-8e2a-a47898411e0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3709855067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3709855067
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1004468524
Short name T724
Test name
Test status
Simulation time 511118263 ps
CPU time 18.23 seconds
Started Apr 16 01:06:07 PM PDT 24
Finished Apr 16 01:06:26 PM PDT 24
Peak memory 243672 kb
Host smart-a1ea24c2-d3f6-40a9-843d-474a4a13cfe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1004468524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1004468524
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2309688713
Short name T110
Test name
Test status
Simulation time 12296873863 ps
CPU time 484.36 seconds
Started Apr 16 01:06:18 PM PDT 24
Finished Apr 16 01:14:24 PM PDT 24
Peak memory 264944 kb
Host smart-2e683658-2ebe-4f4e-9f22-e3b94cfaa360
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309688713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2309688713
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.249139120
Short name T713
Test name
Test status
Simulation time 597315729 ps
CPU time 12.02 seconds
Started Apr 16 01:06:18 PM PDT 24
Finished Apr 16 01:06:32 PM PDT 24
Peak memory 247836 kb
Host smart-cdfea2eb-3a54-45b7-8792-eeecc53ca620
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=249139120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.249139120
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4242881983
Short name T807
Test name
Test status
Simulation time 30262882 ps
CPU time 5.5 seconds
Started Apr 16 01:06:18 PM PDT 24
Finished Apr 16 01:06:25 PM PDT 24
Peak memory 248212 kb
Host smart-8a31d441-9364-4ef1-93f2-d87678a1a197
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242881983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4242881983
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3852193923
Short name T764
Test name
Test status
Simulation time 49973194 ps
CPU time 5.07 seconds
Started Apr 16 01:06:12 PM PDT 24
Finished Apr 16 01:06:18 PM PDT 24
Peak memory 236360 kb
Host smart-cc3681f2-e542-45e8-a7f9-88c59fb3b97f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3852193923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3852193923
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.502181842
Short name T711
Test name
Test status
Simulation time 8285900 ps
CPU time 1.43 seconds
Started Apr 16 01:06:12 PM PDT 24
Finished Apr 16 01:06:14 PM PDT 24
Peak memory 236380 kb
Host smart-61b15043-d92b-4561-b71d-6f8df8bc2728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=502181842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.502181842
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1293731275
Short name T177
Test name
Test status
Simulation time 1388988570 ps
CPU time 19.81 seconds
Started Apr 16 01:06:16 PM PDT 24
Finished Apr 16 01:06:36 PM PDT 24
Peak memory 243672 kb
Host smart-a2ad3cb0-2250-4d20-a325-ea076cdeada7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1293731275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1293731275
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1994703236
Short name T100
Test name
Test status
Simulation time 3234002718 ps
CPU time 295.14 seconds
Started Apr 16 01:06:14 PM PDT 24
Finished Apr 16 01:11:10 PM PDT 24
Peak memory 264952 kb
Host smart-633781f8-57db-40bd-9dba-36dfbca837a0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994703236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1994703236
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3848947794
Short name T800
Test name
Test status
Simulation time 677241775 ps
CPU time 10.22 seconds
Started Apr 16 01:06:12 PM PDT 24
Finished Apr 16 01:06:23 PM PDT 24
Peak memory 248196 kb
Host smart-69904492-758d-49ef-83a8-f2afffc48703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3848947794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3848947794
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.4071157589
Short name T774
Test name
Test status
Simulation time 42100559 ps
CPU time 4.81 seconds
Started Apr 16 01:06:14 PM PDT 24
Finished Apr 16 01:06:20 PM PDT 24
Peak memory 239012 kb
Host smart-24a74378-42a9-4904-8eb2-6c24c19e482c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071157589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.4071157589
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4102551856
Short name T798
Test name
Test status
Simulation time 70070262 ps
CPU time 5.66 seconds
Started Apr 16 01:06:16 PM PDT 24
Finished Apr 16 01:06:22 PM PDT 24
Peak memory 240012 kb
Host smart-459549e3-ee3c-46e4-81a8-808702f8e7e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4102551856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.4102551856
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2777792685
Short name T351
Test name
Test status
Simulation time 6417512 ps
CPU time 1.43 seconds
Started Apr 16 01:06:11 PM PDT 24
Finished Apr 16 01:06:14 PM PDT 24
Peak memory 235536 kb
Host smart-b13c44ac-ac24-4293-b6f9-c501a31d6b48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2777792685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2777792685
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4167224711
Short name T792
Test name
Test status
Simulation time 1221701275 ps
CPU time 34.18 seconds
Started Apr 16 01:06:14 PM PDT 24
Finished Apr 16 01:06:49 PM PDT 24
Peak memory 248172 kb
Host smart-a30b5257-f8a4-4961-a0cd-36ccebf09e59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4167224711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.4167224711
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.759507868
Short name T357
Test name
Test status
Simulation time 8309968627 ps
CPU time 307.36 seconds
Started Apr 16 01:06:14 PM PDT 24
Finished Apr 16 01:11:23 PM PDT 24
Peak memory 264976 kb
Host smart-334300b5-8fc1-446f-b423-9fa8fd225df0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759507868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.759507868
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.903905802
Short name T766
Test name
Test status
Simulation time 444409213 ps
CPU time 15.28 seconds
Started Apr 16 01:06:20 PM PDT 24
Finished Apr 16 01:06:36 PM PDT 24
Peak memory 248232 kb
Host smart-b3131d15-bb13-48b1-9ab9-4f8182133f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=903905802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.903905802
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1346472943
Short name T748
Test name
Test status
Simulation time 16641388348 ps
CPU time 276.9 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:10:27 PM PDT 24
Peak memory 239380 kb
Host smart-d95f92bc-252f-4997-b8c2-fad059a98255
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1346472943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1346472943
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4151098650
Short name T813
Test name
Test status
Simulation time 823192115 ps
CPU time 110.44 seconds
Started Apr 16 01:05:50 PM PDT 24
Finished Apr 16 01:07:42 PM PDT 24
Peak memory 236556 kb
Host smart-3b9f4077-dc30-4afe-93fc-429dae3b8a78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4151098650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.4151098650
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1929528216
Short name T727
Test name
Test status
Simulation time 103703398 ps
CPU time 4.81 seconds
Started Apr 16 01:05:51 PM PDT 24
Finished Apr 16 01:05:57 PM PDT 24
Peak memory 239972 kb
Host smart-e99c5137-f058-41a5-87a1-9d6ab1fae21e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1929528216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1929528216
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3631913620
Short name T803
Test name
Test status
Simulation time 32632692 ps
CPU time 5.13 seconds
Started Apr 16 01:05:47 PM PDT 24
Finished Apr 16 01:05:53 PM PDT 24
Peak memory 240956 kb
Host smart-45e7c17d-2f29-424c-9aac-068f5cdf7f11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631913620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3631913620
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1330112568
Short name T811
Test name
Test status
Simulation time 50987427 ps
CPU time 5.3 seconds
Started Apr 16 01:05:49 PM PDT 24
Finished Apr 16 01:05:56 PM PDT 24
Peak memory 239940 kb
Host smart-cea0c90c-1308-4d4b-b134-415b30ebecf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1330112568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1330112568
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.556446021
Short name T738
Test name
Test status
Simulation time 8345622 ps
CPU time 1.4 seconds
Started Apr 16 01:05:51 PM PDT 24
Finished Apr 16 01:05:54 PM PDT 24
Peak memory 235416 kb
Host smart-c210a374-49fa-4327-a1a7-da718d5febde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=556446021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.556446021
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3091531274
Short name T715
Test name
Test status
Simulation time 340386936 ps
CPU time 23.82 seconds
Started Apr 16 01:05:52 PM PDT 24
Finished Apr 16 01:06:16 PM PDT 24
Peak memory 248136 kb
Host smart-0cda1f1f-228f-4c2d-83c5-af6f3828c05d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3091531274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3091531274
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1957504705
Short name T133
Test name
Test status
Simulation time 8491445246 ps
CPU time 638.11 seconds
Started Apr 16 01:05:48 PM PDT 24
Finished Apr 16 01:16:27 PM PDT 24
Peak memory 265012 kb
Host smart-f97ba997-811a-4eac-a0b6-e67c71312ada
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957504705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1957504705
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2097823096
Short name T707
Test name
Test status
Simulation time 32816682 ps
CPU time 4.74 seconds
Started Apr 16 01:05:48 PM PDT 24
Finished Apr 16 01:05:53 PM PDT 24
Peak memory 248240 kb
Host smart-4b06bd39-7856-4a50-9458-73d74ad2c506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2097823096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2097823096
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2641472955
Short name T737
Test name
Test status
Simulation time 12166356 ps
CPU time 1.77 seconds
Started Apr 16 01:06:20 PM PDT 24
Finished Apr 16 01:06:23 PM PDT 24
Peak memory 236336 kb
Host smart-15e6fc16-8927-467a-9602-2892adc0796d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2641472955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2641472955
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3721571185
Short name T754
Test name
Test status
Simulation time 16017356 ps
CPU time 1.69 seconds
Started Apr 16 01:06:16 PM PDT 24
Finished Apr 16 01:06:19 PM PDT 24
Peak memory 236360 kb
Host smart-d1afc18f-b9dc-4482-9351-ceebd7f39320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3721571185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3721571185
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3790348597
Short name T744
Test name
Test status
Simulation time 6449280 ps
CPU time 1.39 seconds
Started Apr 16 01:06:20 PM PDT 24
Finished Apr 16 01:06:22 PM PDT 24
Peak memory 236352 kb
Host smart-aaa88677-b728-414b-aa3c-9d7130363244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3790348597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3790348597
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1872237409
Short name T826
Test name
Test status
Simulation time 9849225 ps
CPU time 1.35 seconds
Started Apr 16 01:06:11 PM PDT 24
Finished Apr 16 01:06:14 PM PDT 24
Peak memory 234476 kb
Host smart-640a7e47-8383-4e5d-ba59-ddf291f757f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1872237409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1872237409
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1319474291
Short name T745
Test name
Test status
Simulation time 12540105 ps
CPU time 1.62 seconds
Started Apr 16 01:06:12 PM PDT 24
Finished Apr 16 01:06:14 PM PDT 24
Peak memory 236336 kb
Host smart-846fd5d5-6962-4c61-9823-34d516c42c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1319474291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1319474291
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3823824322
Short name T822
Test name
Test status
Simulation time 14137835 ps
CPU time 1.3 seconds
Started Apr 16 01:06:16 PM PDT 24
Finished Apr 16 01:06:18 PM PDT 24
Peak memory 236384 kb
Host smart-60a2b4f6-24c5-4c59-ac7a-2103a291cb65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3823824322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3823824322
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3705982734
Short name T784
Test name
Test status
Simulation time 10866761 ps
CPU time 1.66 seconds
Started Apr 16 01:06:18 PM PDT 24
Finished Apr 16 01:06:21 PM PDT 24
Peak memory 235448 kb
Host smart-e2d3a448-2823-4ec5-a09f-f7b5a7959431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3705982734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3705982734
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3643194738
Short name T808
Test name
Test status
Simulation time 24185547 ps
CPU time 1.43 seconds
Started Apr 16 01:06:12 PM PDT 24
Finished Apr 16 01:06:15 PM PDT 24
Peak memory 235452 kb
Host smart-276300b4-6460-435b-a260-6cbee841194f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3643194738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3643194738
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1190904817
Short name T816
Test name
Test status
Simulation time 16421198 ps
CPU time 1.32 seconds
Started Apr 16 01:06:13 PM PDT 24
Finished Apr 16 01:06:15 PM PDT 24
Peak memory 234348 kb
Host smart-3fce1bed-9c2a-4d17-8593-dcea65d4faca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1190904817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1190904817
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1563147944
Short name T356
Test name
Test status
Simulation time 7697984 ps
CPU time 1.5 seconds
Started Apr 16 01:06:17 PM PDT 24
Finished Apr 16 01:06:19 PM PDT 24
Peak memory 234488 kb
Host smart-d18be95b-65e1-41e3-a92d-b036d3dde66d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1563147944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1563147944
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3367540778
Short name T801
Test name
Test status
Simulation time 2251152624 ps
CPU time 75.9 seconds
Started Apr 16 01:05:55 PM PDT 24
Finished Apr 16 01:07:12 PM PDT 24
Peak memory 236428 kb
Host smart-0accaeb2-2d31-41e2-a79e-fdbf17ef5670
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3367540778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3367540778
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3032595000
Short name T790
Test name
Test status
Simulation time 1687172375 ps
CPU time 204.4 seconds
Started Apr 16 01:05:50 PM PDT 24
Finished Apr 16 01:09:15 PM PDT 24
Peak memory 236324 kb
Host smart-8d2baec3-bf54-47d9-b098-14baf7265d6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3032595000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3032595000
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2348605830
Short name T733
Test name
Test status
Simulation time 78153455 ps
CPU time 3.88 seconds
Started Apr 16 01:05:48 PM PDT 24
Finished Apr 16 01:05:53 PM PDT 24
Peak memory 240020 kb
Host smart-70d47128-3279-4c92-8927-0e7b014aeb1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2348605830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2348605830
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1584611689
Short name T712
Test name
Test status
Simulation time 61845096 ps
CPU time 7.92 seconds
Started Apr 16 01:05:50 PM PDT 24
Finished Apr 16 01:05:59 PM PDT 24
Peak memory 256396 kb
Host smart-2e4ac43d-3568-4515-a45e-2b2284956187
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584611689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1584611689
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2083272746
Short name T821
Test name
Test status
Simulation time 22622776 ps
CPU time 4.14 seconds
Started Apr 16 01:05:48 PM PDT 24
Finished Apr 16 01:05:53 PM PDT 24
Peak memory 236312 kb
Host smart-37ee8b8d-cf9c-45cb-85f1-3e514c8d7a3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2083272746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2083272746
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1203295679
Short name T726
Test name
Test status
Simulation time 7616515 ps
CPU time 1.34 seconds
Started Apr 16 01:05:53 PM PDT 24
Finished Apr 16 01:05:56 PM PDT 24
Peak memory 236388 kb
Host smart-aae18d3c-08d0-4f00-868e-7014ab75cf13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1203295679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1203295679
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3513535059
Short name T779
Test name
Test status
Simulation time 2703962242 ps
CPU time 46.65 seconds
Started Apr 16 01:05:54 PM PDT 24
Finished Apr 16 01:06:42 PM PDT 24
Peak memory 244632 kb
Host smart-3b878d78-566c-4c7a-a469-d9eb0729d4bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3513535059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3513535059
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3908263650
Short name T740
Test name
Test status
Simulation time 906858634 ps
CPU time 15.34 seconds
Started Apr 16 01:05:50 PM PDT 24
Finished Apr 16 01:06:06 PM PDT 24
Peak memory 246568 kb
Host smart-c2fb0630-d2bb-4f46-b2e6-707cc4a485e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3908263650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3908263650
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2671506409
Short name T786
Test name
Test status
Simulation time 9760380 ps
CPU time 1.58 seconds
Started Apr 16 01:06:13 PM PDT 24
Finished Apr 16 01:06:15 PM PDT 24
Peak memory 236272 kb
Host smart-f4db0b49-d7c7-4b6b-ae77-7f31dad6aa10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2671506409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2671506409
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1326881523
Short name T794
Test name
Test status
Simulation time 10765885 ps
CPU time 1.6 seconds
Started Apr 16 01:06:14 PM PDT 24
Finished Apr 16 01:06:16 PM PDT 24
Peak memory 236344 kb
Host smart-7ae3f4e3-66fb-4d5d-a3eb-85f0e965c9b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1326881523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1326881523
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.712255636
Short name T141
Test name
Test status
Simulation time 11437997 ps
CPU time 1.24 seconds
Started Apr 16 01:06:16 PM PDT 24
Finished Apr 16 01:06:18 PM PDT 24
Peak memory 235496 kb
Host smart-b3d9bd24-5d6d-4cd8-adee-233cbeac162b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=712255636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.712255636
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.4241297528
Short name T355
Test name
Test status
Simulation time 10704045 ps
CPU time 1.32 seconds
Started Apr 16 01:06:13 PM PDT 24
Finished Apr 16 01:06:15 PM PDT 24
Peak memory 236240 kb
Host smart-7b0ee886-5cab-4ded-8958-fdce6c67b137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4241297528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.4241297528
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3189135720
Short name T722
Test name
Test status
Simulation time 7600068 ps
CPU time 1.37 seconds
Started Apr 16 01:06:14 PM PDT 24
Finished Apr 16 01:06:16 PM PDT 24
Peak memory 236360 kb
Host smart-784bc48e-4489-4b91-bc38-f60d9103b135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3189135720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3189135720
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1403049750
Short name T815
Test name
Test status
Simulation time 12083884 ps
CPU time 1.3 seconds
Started Apr 16 01:06:17 PM PDT 24
Finished Apr 16 01:06:19 PM PDT 24
Peak memory 235492 kb
Host smart-5e62bca6-a0c2-4725-94d6-7a53832e8f8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1403049750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1403049750
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.867731350
Short name T770
Test name
Test status
Simulation time 44122505 ps
CPU time 2.66 seconds
Started Apr 16 01:06:19 PM PDT 24
Finished Apr 16 01:06:23 PM PDT 24
Peak memory 236352 kb
Host smart-3854b80e-7d11-4e41-9fb6-422746594562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=867731350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.867731350
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.763328431
Short name T353
Test name
Test status
Simulation time 12836176 ps
CPU time 1.8 seconds
Started Apr 16 01:06:25 PM PDT 24
Finished Apr 16 01:06:29 PM PDT 24
Peak memory 236284 kb
Host smart-0dbf7495-5908-400b-9019-64e0113ce757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=763328431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.763328431
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3829421837
Short name T728
Test name
Test status
Simulation time 10501811 ps
CPU time 1.55 seconds
Started Apr 16 01:06:19 PM PDT 24
Finished Apr 16 01:06:22 PM PDT 24
Peak memory 235488 kb
Host smart-b6d8a06a-eeb1-40db-8268-d0f2cc8f8f51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3829421837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3829421837
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4290014640
Short name T767
Test name
Test status
Simulation time 4600127095 ps
CPU time 287.14 seconds
Started Apr 16 01:05:53 PM PDT 24
Finished Apr 16 01:10:42 PM PDT 24
Peak memory 238232 kb
Host smart-47df9927-ea6e-4926-b7ed-50851476f380
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4290014640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4290014640
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.901343900
Short name T734
Test name
Test status
Simulation time 13520773288 ps
CPU time 181.27 seconds
Started Apr 16 01:05:58 PM PDT 24
Finished Apr 16 01:09:01 PM PDT 24
Peak memory 235512 kb
Host smart-4f330973-bec9-469c-ab2c-f3a38b8e6235
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=901343900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.901343900
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3538536087
Short name T762
Test name
Test status
Simulation time 204539302 ps
CPU time 4.87 seconds
Started Apr 16 01:05:56 PM PDT 24
Finished Apr 16 01:06:02 PM PDT 24
Peak memory 240048 kb
Host smart-12d4ac37-8f66-4201-9f16-0d85f19fe0c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3538536087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3538536087
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4216286006
Short name T751
Test name
Test status
Simulation time 666982821 ps
CPU time 6.81 seconds
Started Apr 16 01:05:56 PM PDT 24
Finished Apr 16 01:06:03 PM PDT 24
Peak memory 239908 kb
Host smart-40dc43c3-0c62-4640-bdb9-6b5b909fd1f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216286006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.4216286006
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1551642983
Short name T812
Test name
Test status
Simulation time 104056414 ps
CPU time 3.55 seconds
Started Apr 16 01:05:55 PM PDT 24
Finished Apr 16 01:06:00 PM PDT 24
Peak memory 236280 kb
Host smart-732c3a20-ca1b-4569-bf43-58fea84b5068
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1551642983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1551642983
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3612906053
Short name T796
Test name
Test status
Simulation time 10735389 ps
CPU time 1.39 seconds
Started Apr 16 01:05:57 PM PDT 24
Finished Apr 16 01:06:00 PM PDT 24
Peak memory 236572 kb
Host smart-c56b4b36-cf64-436f-8f45-30f58c5754a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3612906053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3612906053
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3524647866
Short name T830
Test name
Test status
Simulation time 711138798 ps
CPU time 51.48 seconds
Started Apr 16 01:06:00 PM PDT 24
Finished Apr 16 01:06:53 PM PDT 24
Peak memory 248412 kb
Host smart-fa6c6e8e-2d72-4b29-bb00-22fc9234d103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3524647866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3524647866
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3641243519
Short name T130
Test name
Test status
Simulation time 34016822591 ps
CPU time 221.4 seconds
Started Apr 16 01:05:51 PM PDT 24
Finished Apr 16 01:09:34 PM PDT 24
Peak memory 264936 kb
Host smart-6e13f15d-8065-4eda-a188-c20083bf1c7e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3641243519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3641243519
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2181385961
Short name T129
Test name
Test status
Simulation time 7300365986 ps
CPU time 462.49 seconds
Started Apr 16 01:05:57 PM PDT 24
Finished Apr 16 01:13:40 PM PDT 24
Peak memory 264992 kb
Host smart-39e861e7-9358-4e4a-afe3-49949485f787
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181385961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2181385961
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3239799429
Short name T729
Test name
Test status
Simulation time 374302383 ps
CPU time 12.63 seconds
Started Apr 16 01:06:02 PM PDT 24
Finished Apr 16 01:06:16 PM PDT 24
Peak memory 251872 kb
Host smart-ba292797-a9c4-4ec8-96a0-865cac5e1884
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3239799429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3239799429
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.416287643
Short name T352
Test name
Test status
Simulation time 29704755 ps
CPU time 2.24 seconds
Started Apr 16 01:06:17 PM PDT 24
Finished Apr 16 01:06:20 PM PDT 24
Peak memory 236268 kb
Host smart-7b1dad9e-a1e2-4ea2-b2c0-3593390e8937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=416287643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.416287643
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2310190664
Short name T768
Test name
Test status
Simulation time 18264692 ps
CPU time 1.33 seconds
Started Apr 16 01:06:20 PM PDT 24
Finished Apr 16 01:06:23 PM PDT 24
Peak memory 236344 kb
Host smart-71cdff62-5a08-45ac-a502-393dea57afc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2310190664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2310190664
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3181839432
Short name T763
Test name
Test status
Simulation time 6594232 ps
CPU time 1.46 seconds
Started Apr 16 01:06:16 PM PDT 24
Finished Apr 16 01:06:18 PM PDT 24
Peak memory 236344 kb
Host smart-d8eb03bf-7241-41d4-92ab-93708297974d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3181839432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3181839432
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3169307495
Short name T797
Test name
Test status
Simulation time 10328503 ps
CPU time 1.7 seconds
Started Apr 16 01:06:21 PM PDT 24
Finished Apr 16 01:06:24 PM PDT 24
Peak memory 236352 kb
Host smart-ab6530a8-2031-4006-9a21-5c9ff60fbdbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3169307495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3169307495
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2496778882
Short name T809
Test name
Test status
Simulation time 28716904 ps
CPU time 1.47 seconds
Started Apr 16 01:06:22 PM PDT 24
Finished Apr 16 01:06:26 PM PDT 24
Peak memory 235408 kb
Host smart-daa7f813-621e-4daa-9e3b-17e37ed8bfba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2496778882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2496778882
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1048724207
Short name T747
Test name
Test status
Simulation time 12584786 ps
CPU time 1.39 seconds
Started Apr 16 01:06:20 PM PDT 24
Finished Apr 16 01:06:22 PM PDT 24
Peak memory 235404 kb
Host smart-4b7cf3dd-1d64-4ed2-ac25-c7b804ff6fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1048724207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1048724207
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.346241122
Short name T761
Test name
Test status
Simulation time 7610578 ps
CPU time 1.37 seconds
Started Apr 16 01:06:19 PM PDT 24
Finished Apr 16 01:06:22 PM PDT 24
Peak memory 235516 kb
Host smart-b167f88b-99be-4387-8c58-c7b25b9ff679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=346241122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.346241122
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2068417704
Short name T810
Test name
Test status
Simulation time 7998154 ps
CPU time 1.46 seconds
Started Apr 16 01:06:17 PM PDT 24
Finished Apr 16 01:06:20 PM PDT 24
Peak memory 235472 kb
Host smart-9cef8555-2f81-4faf-8c7a-7be6272739ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2068417704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2068417704
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2673696064
Short name T775
Test name
Test status
Simulation time 11448215 ps
CPU time 1.71 seconds
Started Apr 16 01:06:26 PM PDT 24
Finished Apr 16 01:06:29 PM PDT 24
Peak memory 235436 kb
Host smart-1339e707-22d4-4627-aa2f-0b1c923fdf9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2673696064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2673696064
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2285272939
Short name T825
Test name
Test status
Simulation time 9476833 ps
CPU time 1.27 seconds
Started Apr 16 01:06:19 PM PDT 24
Finished Apr 16 01:06:22 PM PDT 24
Peak memory 236356 kb
Host smart-de8da0b6-b1dd-43ab-b885-9897e91ffd2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2285272939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2285272939
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4042813093
Short name T783
Test name
Test status
Simulation time 396260712 ps
CPU time 7.71 seconds
Started Apr 16 01:05:58 PM PDT 24
Finished Apr 16 01:06:08 PM PDT 24
Peak memory 238960 kb
Host smart-393b50ad-5eb0-4629-a661-d373a95d8061
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042813093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.4042813093
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.695626784
Short name T827
Test name
Test status
Simulation time 180912047 ps
CPU time 7.67 seconds
Started Apr 16 01:05:59 PM PDT 24
Finished Apr 16 01:06:08 PM PDT 24
Peak memory 235448 kb
Host smart-baf8d1ba-6268-42bb-8e2e-882f8251276e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=695626784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.695626784
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4245263207
Short name T787
Test name
Test status
Simulation time 9290506 ps
CPU time 1.56 seconds
Started Apr 16 01:05:56 PM PDT 24
Finished Apr 16 01:05:59 PM PDT 24
Peak memory 236236 kb
Host smart-16d42afb-6caf-4178-b6fe-ed72ace7e84d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4245263207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4245263207
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3005786219
Short name T719
Test name
Test status
Simulation time 314354074 ps
CPU time 22.3 seconds
Started Apr 16 01:05:52 PM PDT 24
Finished Apr 16 01:06:15 PM PDT 24
Peak memory 248228 kb
Host smart-49bb86b7-aedb-49c4-8ada-52572d7ef29a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3005786219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3005786219
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.233806911
Short name T128
Test name
Test status
Simulation time 2265193841 ps
CPU time 278.79 seconds
Started Apr 16 01:05:51 PM PDT 24
Finished Apr 16 01:10:31 PM PDT 24
Peak memory 264908 kb
Host smart-2e90421a-0bff-4bd5-b2d3-dc5cb7258fd6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233806911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.233806911
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3186008832
Short name T708
Test name
Test status
Simulation time 32363993 ps
CPU time 4.59 seconds
Started Apr 16 01:05:54 PM PDT 24
Finished Apr 16 01:06:00 PM PDT 24
Peak memory 250600 kb
Host smart-15cbf584-5a07-4962-9bfb-47f630ef4a97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3186008832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3186008832
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1883250655
Short name T780
Test name
Test status
Simulation time 62712667 ps
CPU time 5.24 seconds
Started Apr 16 01:05:55 PM PDT 24
Finished Apr 16 01:06:01 PM PDT 24
Peak memory 240936 kb
Host smart-84ffca82-5694-4ffd-8cc4-2bd918e0fee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883250655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1883250655
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1281825813
Short name T788
Test name
Test status
Simulation time 125106573 ps
CPU time 9.41 seconds
Started Apr 16 01:05:53 PM PDT 24
Finished Apr 16 01:06:03 PM PDT 24
Peak memory 236324 kb
Host smart-012b9808-4690-4da4-94c3-df46825c979f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1281825813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1281825813
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1199658880
Short name T720
Test name
Test status
Simulation time 12312786 ps
CPU time 1.37 seconds
Started Apr 16 01:05:55 PM PDT 24
Finished Apr 16 01:05:57 PM PDT 24
Peak memory 234476 kb
Host smart-f6d3df93-5893-4748-bc78-6dbcaa6ee65b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1199658880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1199658880
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2309339619
Short name T769
Test name
Test status
Simulation time 1229137622 ps
CPU time 21.78 seconds
Started Apr 16 01:05:55 PM PDT 24
Finished Apr 16 01:06:17 PM PDT 24
Peak memory 248228 kb
Host smart-5835f890-a379-4384-8bd7-f5415821e725
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2309339619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2309339619
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1476401710
Short name T125
Test name
Test status
Simulation time 3145952603 ps
CPU time 201.44 seconds
Started Apr 16 01:06:00 PM PDT 24
Finished Apr 16 01:09:23 PM PDT 24
Peak memory 264936 kb
Host smart-da73afd6-fa34-4529-a007-bbf469638f2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1476401710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1476401710
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3686067564
Short name T122
Test name
Test status
Simulation time 7016810952 ps
CPU time 496.39 seconds
Started Apr 16 01:05:53 PM PDT 24
Finished Apr 16 01:14:10 PM PDT 24
Peak memory 264996 kb
Host smart-5a3d0aa0-e7ba-49eb-b7ca-cbca2f58fa97
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686067564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3686067564
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1339173302
Short name T758
Test name
Test status
Simulation time 1693418222 ps
CPU time 31.37 seconds
Started Apr 16 01:05:51 PM PDT 24
Finished Apr 16 01:06:23 PM PDT 24
Peak memory 248276 kb
Host smart-47fb4ee7-fe1c-448c-ad06-97e067b4aa99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1339173302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1339173302
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3674303357
Short name T267
Test name
Test status
Simulation time 93649204 ps
CPU time 2.02 seconds
Started Apr 16 01:05:54 PM PDT 24
Finished Apr 16 01:05:57 PM PDT 24
Peak memory 236336 kb
Host smart-c718a7ce-0f67-4d56-884f-1afd810e5a76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3674303357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3674303357
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3186861862
Short name T795
Test name
Test status
Simulation time 136403032 ps
CPU time 9.62 seconds
Started Apr 16 01:05:55 PM PDT 24
Finished Apr 16 01:06:05 PM PDT 24
Peak memory 238624 kb
Host smart-50e90e1d-a440-43a8-b77d-5713af4454fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186861862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3186861862
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4074433892
Short name T725
Test name
Test status
Simulation time 159977068 ps
CPU time 4.31 seconds
Started Apr 16 01:06:02 PM PDT 24
Finished Apr 16 01:06:07 PM PDT 24
Peak memory 236296 kb
Host smart-7a5b0759-1a27-425e-87b7-34a560f5c17d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4074433892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4074433892
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.45142963
Short name T814
Test name
Test status
Simulation time 18447470 ps
CPU time 1.36 seconds
Started Apr 16 01:05:58 PM PDT 24
Finished Apr 16 01:06:01 PM PDT 24
Peak memory 234408 kb
Host smart-46b4f766-26db-44fd-801a-9fc5bd3dd8cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=45142963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.45142963
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1567310811
Short name T714
Test name
Test status
Simulation time 1008914578 ps
CPU time 20.01 seconds
Started Apr 16 01:05:58 PM PDT 24
Finished Apr 16 01:06:19 PM PDT 24
Peak memory 248112 kb
Host smart-d8598e43-18ff-4b82-a06e-4cc015c08aa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1567310811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1567310811
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3316766341
Short name T123
Test name
Test status
Simulation time 1002575054 ps
CPU time 101.39 seconds
Started Apr 16 01:05:58 PM PDT 24
Finished Apr 16 01:07:41 PM PDT 24
Peak memory 256616 kb
Host smart-30df00cd-bf1b-4673-bd44-879fa6ef5232
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3316766341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3316766341
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1918440129
Short name T114
Test name
Test status
Simulation time 86087237829 ps
CPU time 434.04 seconds
Started Apr 16 01:05:56 PM PDT 24
Finished Apr 16 01:13:11 PM PDT 24
Peak memory 264948 kb
Host smart-f4870d1a-a9ca-4016-a1a1-64ad291d0fa4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918440129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1918440129
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3612957233
Short name T773
Test name
Test status
Simulation time 121343235 ps
CPU time 5.37 seconds
Started Apr 16 01:05:56 PM PDT 24
Finished Apr 16 01:06:03 PM PDT 24
Peak memory 248300 kb
Host smart-be039cf6-fef1-43d3-b8af-1b103cacba80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3612957233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3612957233
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2477826008
Short name T791
Test name
Test status
Simulation time 104234960 ps
CPU time 8.3 seconds
Started Apr 16 01:06:02 PM PDT 24
Finished Apr 16 01:06:11 PM PDT 24
Peak memory 240012 kb
Host smart-9acf3975-e93a-47ac-906b-5eb69651f3db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477826008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2477826008
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.93774748
Short name T156
Test name
Test status
Simulation time 104849259 ps
CPU time 5.94 seconds
Started Apr 16 01:05:56 PM PDT 24
Finished Apr 16 01:06:03 PM PDT 24
Peak memory 236352 kb
Host smart-2ae37b3c-0bce-49d3-af96-d9dc2443223a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=93774748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.93774748
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2027885602
Short name T140
Test name
Test status
Simulation time 8691842 ps
CPU time 1.56 seconds
Started Apr 16 01:05:59 PM PDT 24
Finished Apr 16 01:06:02 PM PDT 24
Peak memory 236200 kb
Host smart-aedd9721-622d-4a34-b0a3-81b98da7db30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2027885602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2027885602
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.362635422
Short name T181
Test name
Test status
Simulation time 345942697 ps
CPU time 21.97 seconds
Started Apr 16 01:05:59 PM PDT 24
Finished Apr 16 01:06:23 PM PDT 24
Peak memory 248220 kb
Host smart-b66c5364-1c01-4a07-aab2-144d600615cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=362635422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.362635422
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3153341911
Short name T119
Test name
Test status
Simulation time 3462761085 ps
CPU time 170.64 seconds
Started Apr 16 01:06:00 PM PDT 24
Finished Apr 16 01:08:52 PM PDT 24
Peak memory 265936 kb
Host smart-61fe5792-2055-4810-b16a-f186388dff6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3153341911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3153341911
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.450286882
Short name T103
Test name
Test status
Simulation time 29568322237 ps
CPU time 538.74 seconds
Started Apr 16 01:06:11 PM PDT 24
Finished Apr 16 01:15:11 PM PDT 24
Peak memory 264956 kb
Host smart-c4077135-0bcd-4b8e-8262-ec7b11e17f43
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450286882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.450286882
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3355400853
Short name T824
Test name
Test status
Simulation time 1098498543 ps
CPU time 19.9 seconds
Started Apr 16 01:06:00 PM PDT 24
Finished Apr 16 01:06:21 PM PDT 24
Peak memory 248144 kb
Host smart-0c51a742-ed31-45a2-be8d-063462032252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3355400853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3355400853
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2775396454
Short name T158
Test name
Test status
Simulation time 501442226 ps
CPU time 8.51 seconds
Started Apr 16 01:06:06 PM PDT 24
Finished Apr 16 01:06:15 PM PDT 24
Peak memory 237568 kb
Host smart-f8d9c19b-6be9-4829-8299-5e4c317c0f54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775396454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2775396454
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.4089200805
Short name T785
Test name
Test status
Simulation time 112719361 ps
CPU time 5.47 seconds
Started Apr 16 01:05:59 PM PDT 24
Finished Apr 16 01:06:06 PM PDT 24
Peak memory 236332 kb
Host smart-87796255-52d3-4318-b058-669203efcf3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4089200805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.4089200805
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2873592859
Short name T742
Test name
Test status
Simulation time 17061402 ps
CPU time 1.36 seconds
Started Apr 16 01:06:01 PM PDT 24
Finished Apr 16 01:06:04 PM PDT 24
Peak memory 235472 kb
Host smart-0cc70d95-6bc5-4542-9789-22a95bc482fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2873592859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2873592859
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1691126956
Short name T180
Test name
Test status
Simulation time 1005746560 ps
CPU time 20 seconds
Started Apr 16 01:06:06 PM PDT 24
Finished Apr 16 01:06:27 PM PDT 24
Peak memory 244456 kb
Host smart-db51b38a-e7a7-491a-b2c2-5ae63a182012
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1691126956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1691126956
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4095669764
Short name T117
Test name
Test status
Simulation time 2992230136 ps
CPU time 107.65 seconds
Started Apr 16 01:05:57 PM PDT 24
Finished Apr 16 01:07:47 PM PDT 24
Peak memory 267424 kb
Host smart-55df6b73-9a1b-4283-956a-4d5788b5db78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4095669764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.4095669764
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.797513226
Short name T124
Test name
Test status
Simulation time 12109980936 ps
CPU time 925.89 seconds
Started Apr 16 01:06:01 PM PDT 24
Finished Apr 16 01:21:28 PM PDT 24
Peak memory 264964 kb
Host smart-ff33ca4d-eaeb-40e7-86be-a8ca88182497
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797513226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.797513226
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4210614633
Short name T757
Test name
Test status
Simulation time 628204253 ps
CPU time 9.46 seconds
Started Apr 16 01:06:08 PM PDT 24
Finished Apr 16 01:06:19 PM PDT 24
Peak memory 248232 kb
Host smart-dfd3f7c6-16d2-4209-b6b6-c26550f74a30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4210614633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4210614633
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1127160767
Short name T588
Test name
Test status
Simulation time 6650538920 ps
CPU time 560.66 seconds
Started Apr 16 02:54:47 PM PDT 24
Finished Apr 16 03:04:08 PM PDT 24
Peak memory 265552 kb
Host smart-90fac3ad-88fe-4ffd-b530-08d046d087f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127160767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1127160767
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1124838050
Short name T380
Test name
Test status
Simulation time 387205433 ps
CPU time 10.78 seconds
Started Apr 16 02:54:48 PM PDT 24
Finished Apr 16 02:54:59 PM PDT 24
Peak memory 240812 kb
Host smart-a66b5cc5-da3d-4af0-a785-c884f4f095bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1124838050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1124838050
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1138493060
Short name T484
Test name
Test status
Simulation time 4841459542 ps
CPU time 98.41 seconds
Started Apr 16 02:54:41 PM PDT 24
Finished Apr 16 02:56:21 PM PDT 24
Peak memory 250104 kb
Host smart-660171f6-a2a9-42f5-8df9-2fb0ecba11b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11384
93060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1138493060
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.896509969
Short name T518
Test name
Test status
Simulation time 760481620 ps
CPU time 40.57 seconds
Started Apr 16 02:54:41 PM PDT 24
Finished Apr 16 02:55:23 PM PDT 24
Peak memory 255484 kb
Host smart-daf53b7f-2c00-4c2c-8fd6-0f04a1378ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89650
9969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.896509969
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.668734453
Short name T669
Test name
Test status
Simulation time 32943225367 ps
CPU time 1842.62 seconds
Started Apr 16 02:54:45 PM PDT 24
Finished Apr 16 03:25:29 PM PDT 24
Peak memory 284920 kb
Host smart-bb22d89c-cf70-48e8-8896-39452cff3db5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668734453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.668734453
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3306435426
Short name T677
Test name
Test status
Simulation time 17151065745 ps
CPU time 974.77 seconds
Started Apr 16 02:54:48 PM PDT 24
Finished Apr 16 03:11:04 PM PDT 24
Peak memory 271424 kb
Host smart-29d710eb-cd05-4210-acc5-37eeb93b8f51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306435426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3306435426
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3169327491
Short name T171
Test name
Test status
Simulation time 53580658920 ps
CPU time 520.03 seconds
Started Apr 16 02:54:45 PM PDT 24
Finished Apr 16 03:03:26 PM PDT 24
Peak memory 248232 kb
Host smart-1ee94d2a-1e95-483e-947a-07b5fd368397
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169327491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3169327491
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3319583992
Short name T80
Test name
Test status
Simulation time 960153405 ps
CPU time 28.07 seconds
Started Apr 16 02:54:49 PM PDT 24
Finished Apr 16 02:55:19 PM PDT 24
Peak memory 256232 kb
Host smart-28dbf7b3-efab-4e6a-90f1-77330233311e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33195
83992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3319583992
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.462519755
Short name T61
Test name
Test status
Simulation time 1260680596 ps
CPU time 41.91 seconds
Started Apr 16 02:54:49 PM PDT 24
Finished Apr 16 02:55:32 PM PDT 24
Peak memory 255756 kb
Host smart-a3b13a5c-ae9f-424d-987f-08d877f9935b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46251
9755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.462519755
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1920127082
Short name T249
Test name
Test status
Simulation time 410382994 ps
CPU time 26.54 seconds
Started Apr 16 02:54:45 PM PDT 24
Finished Apr 16 02:55:12 PM PDT 24
Peak memory 247572 kb
Host smart-794ace79-095f-4c63-83c8-90c586240afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19201
27082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1920127082
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1878039429
Short name T539
Test name
Test status
Simulation time 781357739 ps
CPU time 38.76 seconds
Started Apr 16 02:54:40 PM PDT 24
Finished Apr 16 02:55:19 PM PDT 24
Peak memory 249036 kb
Host smart-6e5a3dcd-e5eb-4bf0-8b5a-52851dd1844d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18780
39429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1878039429
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1899795069
Short name T63
Test name
Test status
Simulation time 11276183135 ps
CPU time 1149.9 seconds
Started Apr 16 02:54:46 PM PDT 24
Finished Apr 16 03:13:57 PM PDT 24
Peak memory 290084 kb
Host smart-7b306d1c-6156-4519-b742-eb522450a0dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899795069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1899795069
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1360830041
Short name T99
Test name
Test status
Simulation time 313520048 ps
CPU time 15.58 seconds
Started Apr 16 02:54:44 PM PDT 24
Finished Apr 16 02:55:01 PM PDT 24
Peak memory 240824 kb
Host smart-c5a6e630-1caf-4ff8-a552-9ffb89dcce40
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1360830041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1360830041
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.306609983
Short name T425
Test name
Test status
Simulation time 19968346045 ps
CPU time 76.84 seconds
Started Apr 16 02:54:44 PM PDT 24
Finished Apr 16 02:56:02 PM PDT 24
Peak memory 257088 kb
Host smart-593bbed3-b75e-4b22-9a06-43e633b82b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30660
9983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.306609983
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.296122318
Short name T515
Test name
Test status
Simulation time 410131661 ps
CPU time 31.11 seconds
Started Apr 16 02:54:51 PM PDT 24
Finished Apr 16 02:55:24 PM PDT 24
Peak memory 255964 kb
Host smart-00f6e9c0-ed36-46ac-9a11-345e55e21e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29612
2318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.296122318
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.481578459
Short name T297
Test name
Test status
Simulation time 128263625177 ps
CPU time 1677.83 seconds
Started Apr 16 02:54:47 PM PDT 24
Finished Apr 16 03:22:46 PM PDT 24
Peak memory 272608 kb
Host smart-e6f5154c-0f9a-455a-b180-05d19124049e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481578459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.481578459
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1380733211
Short name T388
Test name
Test status
Simulation time 178630741607 ps
CPU time 1112.15 seconds
Started Apr 16 02:54:48 PM PDT 24
Finished Apr 16 03:13:21 PM PDT 24
Peak memory 273692 kb
Host smart-80c6f6bc-b41d-4751-81f5-061af360fbd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380733211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1380733211
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2158014369
Short name T316
Test name
Test status
Simulation time 6002026436 ps
CPU time 125.08 seconds
Started Apr 16 02:54:47 PM PDT 24
Finished Apr 16 02:56:52 PM PDT 24
Peak memory 248364 kb
Host smart-5942d573-7589-4cfb-b00a-cbd2d8437be5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158014369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2158014369
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2657239447
Short name T361
Test name
Test status
Simulation time 882323111 ps
CPU time 49.78 seconds
Started Apr 16 02:54:48 PM PDT 24
Finished Apr 16 02:55:39 PM PDT 24
Peak memory 256088 kb
Host smart-dc156338-fdfc-41e4-aa73-9ef6f0a53fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26572
39447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2657239447
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2752823851
Short name T284
Test name
Test status
Simulation time 897345700 ps
CPU time 38.76 seconds
Started Apr 16 02:54:46 PM PDT 24
Finished Apr 16 02:55:26 PM PDT 24
Peak memory 249048 kb
Host smart-e841ccc4-8e35-467c-895a-dece1902820d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27528
23851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2752823851
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1549845400
Short name T29
Test name
Test status
Simulation time 698272476 ps
CPU time 12.35 seconds
Started Apr 16 02:54:44 PM PDT 24
Finished Apr 16 02:54:57 PM PDT 24
Peak memory 273836 kb
Host smart-f5d19c79-e706-45f6-9e09-0f6f1f414ed5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1549845400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1549845400
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2606558565
Short name T486
Test name
Test status
Simulation time 119126173 ps
CPU time 11.04 seconds
Started Apr 16 02:54:51 PM PDT 24
Finished Apr 16 02:55:03 PM PDT 24
Peak memory 255028 kb
Host smart-d5003768-97f9-4728-bcbd-788d43779e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26065
58565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2606558565
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2298465005
Short name T706
Test name
Test status
Simulation time 107514342 ps
CPU time 3.4 seconds
Started Apr 16 02:54:48 PM PDT 24
Finished Apr 16 02:54:53 PM PDT 24
Peak memory 240808 kb
Host smart-e993d006-bd5f-4f89-869f-b9030dcc312b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22984
65005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2298465005
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.4247679926
Short name T530
Test name
Test status
Simulation time 1467503147 ps
CPU time 71.65 seconds
Started Apr 16 02:54:46 PM PDT 24
Finished Apr 16 02:55:59 PM PDT 24
Peak memory 257232 kb
Host smart-d055177c-2d2a-4061-99d8-0714746a9c26
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247679926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.4247679926
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.591135577
Short name T694
Test name
Test status
Simulation time 379904068941 ps
CPU time 9682.75 seconds
Started Apr 16 02:54:44 PM PDT 24
Finished Apr 16 05:36:09 PM PDT 24
Peak memory 371300 kb
Host smart-c8653b53-eb47-4e87-a742-80a421b9a2bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591135577 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.591135577
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1065251312
Short name T387
Test name
Test status
Simulation time 41652268921 ps
CPU time 2181.35 seconds
Started Apr 16 02:55:14 PM PDT 24
Finished Apr 16 03:31:37 PM PDT 24
Peak memory 282256 kb
Host smart-6b631c90-3d1c-43da-9836-50fd596ed579
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065251312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1065251312
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2802769378
Short name T639
Test name
Test status
Simulation time 825185388 ps
CPU time 10.76 seconds
Started Apr 16 02:55:13 PM PDT 24
Finished Apr 16 02:55:26 PM PDT 24
Peak memory 240820 kb
Host smart-2cd2518e-8540-46c2-8dde-d93e84b157b4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2802769378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2802769378
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3057909206
Short name T529
Test name
Test status
Simulation time 3932206913 ps
CPU time 39.96 seconds
Started Apr 16 02:55:19 PM PDT 24
Finished Apr 16 02:56:01 PM PDT 24
Peak memory 248824 kb
Host smart-63a24278-b80d-4dd3-90d5-307fb571f647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30579
09206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3057909206
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2356282451
Short name T697
Test name
Test status
Simulation time 446498389 ps
CPU time 37.09 seconds
Started Apr 16 02:55:17 PM PDT 24
Finished Apr 16 02:55:56 PM PDT 24
Peak memory 255764 kb
Host smart-b0640286-af67-48b6-a1ab-e6921e2d9942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23562
82451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2356282451
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.938988435
Short name T293
Test name
Test status
Simulation time 44197237569 ps
CPU time 886.24 seconds
Started Apr 16 02:55:19 PM PDT 24
Finished Apr 16 03:10:07 PM PDT 24
Peak memory 282436 kb
Host smart-edd6c6d1-691d-47e5-bdff-8bedff354ed0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938988435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.938988435
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2886992313
Short name T81
Test name
Test status
Simulation time 520004748599 ps
CPU time 1820.87 seconds
Started Apr 16 02:55:16 PM PDT 24
Finished Apr 16 03:25:39 PM PDT 24
Peak memory 281896 kb
Host smart-abd5a200-07b2-4f3b-a7b2-7c2b87f2dee9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886992313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2886992313
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.4238466109
Short name T544
Test name
Test status
Simulation time 12011418321 ps
CPU time 127.11 seconds
Started Apr 16 02:55:16 PM PDT 24
Finished Apr 16 02:57:26 PM PDT 24
Peak memory 248484 kb
Host smart-bd2eaf51-ab7d-4bb8-8ade-48480c98cf6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238466109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.4238466109
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2049520798
Short name T169
Test name
Test status
Simulation time 859704104 ps
CPU time 21.42 seconds
Started Apr 16 02:55:16 PM PDT 24
Finished Apr 16 02:55:39 PM PDT 24
Peak memory 249068 kb
Host smart-1ab86b75-5bd1-4159-aae0-04259669be3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20495
20798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2049520798
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.754546466
Short name T386
Test name
Test status
Simulation time 582011722 ps
CPU time 12.21 seconds
Started Apr 16 02:55:16 PM PDT 24
Finished Apr 16 02:55:31 PM PDT 24
Peak memory 253364 kb
Host smart-a41a8078-9d49-403b-ac28-d3463e790958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75454
6466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.754546466
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.662634298
Short name T597
Test name
Test status
Simulation time 178807975 ps
CPU time 11.19 seconds
Started Apr 16 02:55:13 PM PDT 24
Finished Apr 16 02:55:25 PM PDT 24
Peak memory 254164 kb
Host smart-14ce50f9-e754-47ba-b21d-845801e10170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66263
4298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.662634298
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.795743903
Short name T271
Test name
Test status
Simulation time 656288776 ps
CPU time 35.72 seconds
Started Apr 16 02:55:17 PM PDT 24
Finished Apr 16 02:55:55 PM PDT 24
Peak memory 249072 kb
Host smart-81056e77-25ab-45cb-b787-e70b3ea227fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79574
3903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.795743903
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3836139503
Short name T257
Test name
Test status
Simulation time 21407509570 ps
CPU time 440.09 seconds
Started Apr 16 02:55:16 PM PDT 24
Finished Apr 16 03:02:39 PM PDT 24
Peak memory 265456 kb
Host smart-a5d00ed4-5ebb-4744-8620-b416c5284056
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836139503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3836139503
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3771112887
Short name T500
Test name
Test status
Simulation time 23409582386 ps
CPU time 1731.96 seconds
Started Apr 16 02:55:19 PM PDT 24
Finished Apr 16 03:24:13 PM PDT 24
Peak memory 272092 kb
Host smart-54a1b61e-0245-4332-8079-3b00b1055535
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771112887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3771112887
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.179940494
Short name T429
Test name
Test status
Simulation time 1189246523 ps
CPU time 27.24 seconds
Started Apr 16 02:55:18 PM PDT 24
Finished Apr 16 02:55:48 PM PDT 24
Peak memory 240824 kb
Host smart-ac3517a2-2766-4195-b573-1b2f198851d6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=179940494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.179940494
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2913469747
Short name T207
Test name
Test status
Simulation time 920500617 ps
CPU time 14.45 seconds
Started Apr 16 02:55:22 PM PDT 24
Finished Apr 16 02:55:38 PM PDT 24
Peak memory 248760 kb
Host smart-c38a3b5c-0d9d-421e-b5b6-9a28ff71117d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29134
69747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2913469747
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2298033355
Short name T412
Test name
Test status
Simulation time 176813989 ps
CPU time 3.53 seconds
Started Apr 16 02:55:13 PM PDT 24
Finished Apr 16 02:55:18 PM PDT 24
Peak memory 240832 kb
Host smart-72ee9488-04cc-44b9-b93d-c55d3d95e2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22980
33355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2298033355
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1099393240
Short name T592
Test name
Test status
Simulation time 72520038741 ps
CPU time 1099.8 seconds
Started Apr 16 02:55:21 PM PDT 24
Finished Apr 16 03:13:42 PM PDT 24
Peak memory 265544 kb
Host smart-97f05195-5eee-4527-b25d-5414c6873518
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099393240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1099393240
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.4182778087
Short name T506
Test name
Test status
Simulation time 52865081586 ps
CPU time 3058.52 seconds
Started Apr 16 02:55:19 PM PDT 24
Finished Apr 16 03:46:20 PM PDT 24
Peak memory 289572 kb
Host smart-aa6ebe30-9f7f-46fa-a54d-452e67e05c70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182778087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.4182778087
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2165953712
Short name T233
Test name
Test status
Simulation time 80081263295 ps
CPU time 183.37 seconds
Started Apr 16 02:55:22 PM PDT 24
Finished Apr 16 02:58:27 PM PDT 24
Peak memory 247920 kb
Host smart-66668f23-4cb7-4118-88a8-c6e5730c9d2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165953712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2165953712
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1545348180
Short name T477
Test name
Test status
Simulation time 361468267 ps
CPU time 25.22 seconds
Started Apr 16 02:55:16 PM PDT 24
Finished Apr 16 02:55:44 PM PDT 24
Peak memory 255912 kb
Host smart-9fd77e27-6f1f-4fd0-aff1-a06f853ddaaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15453
48180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1545348180
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.356431901
Short name T504
Test name
Test status
Simulation time 357907361 ps
CPU time 30.95 seconds
Started Apr 16 02:55:15 PM PDT 24
Finished Apr 16 02:55:48 PM PDT 24
Peak memory 256104 kb
Host smart-288d88cd-fda4-49be-971d-743dbfcf6177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35643
1901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.356431901
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2405072192
Short name T239
Test name
Test status
Simulation time 483276187 ps
CPU time 28.64 seconds
Started Apr 16 02:55:20 PM PDT 24
Finished Apr 16 02:55:50 PM PDT 24
Peak memory 247736 kb
Host smart-348ac26c-f555-4305-ae13-d0656d0cc739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24050
72192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2405072192
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2945607212
Short name T647
Test name
Test status
Simulation time 99611165 ps
CPU time 3.11 seconds
Started Apr 16 02:55:16 PM PDT 24
Finished Apr 16 02:55:22 PM PDT 24
Peak memory 240868 kb
Host smart-4379fdd8-e60c-4f87-8268-1d98d9209a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29456
07212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2945607212
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2958482619
Short name T606
Test name
Test status
Simulation time 88140872108 ps
CPU time 1260.05 seconds
Started Apr 16 02:55:22 PM PDT 24
Finished Apr 16 03:16:24 PM PDT 24
Peak memory 273456 kb
Host smart-a14f4e1a-6dcb-44ff-a38a-0faa4394233f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958482619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2958482619
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3727580498
Short name T226
Test name
Test status
Simulation time 100577852118 ps
CPU time 2837.91 seconds
Started Apr 16 02:55:23 PM PDT 24
Finished Apr 16 03:42:42 PM PDT 24
Peak memory 298720 kb
Host smart-f250397e-f434-4631-bcf0-aaeb42d18383
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727580498 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3727580498
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1397814361
Short name T191
Test name
Test status
Simulation time 59743304 ps
CPU time 3.84 seconds
Started Apr 16 02:55:24 PM PDT 24
Finished Apr 16 02:55:29 PM PDT 24
Peak memory 249324 kb
Host smart-70af61ca-49f3-49a5-9600-591527d53218
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1397814361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1397814361
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.4208744615
Short name T514
Test name
Test status
Simulation time 31011034657 ps
CPU time 930.26 seconds
Started Apr 16 02:55:23 PM PDT 24
Finished Apr 16 03:10:55 PM PDT 24
Peak memory 271468 kb
Host smart-f48c8e64-d8f0-494a-92b1-b02b322f1d70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208744615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.4208744615
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3427721672
Short name T424
Test name
Test status
Simulation time 1151696037 ps
CPU time 9.75 seconds
Started Apr 16 02:55:26 PM PDT 24
Finished Apr 16 02:55:38 PM PDT 24
Peak memory 240844 kb
Host smart-cb20ca97-f718-47fa-8c24-e2c0864621b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3427721672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3427721672
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2660520999
Short name T536
Test name
Test status
Simulation time 5011891106 ps
CPU time 79.59 seconds
Started Apr 16 02:55:24 PM PDT 24
Finished Apr 16 02:56:45 PM PDT 24
Peak memory 257272 kb
Host smart-e32e1a91-0b4d-4c1e-8a03-4c9b12835f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26605
20999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2660520999
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2017302219
Short name T399
Test name
Test status
Simulation time 3155978424 ps
CPU time 45.58 seconds
Started Apr 16 02:55:26 PM PDT 24
Finished Apr 16 02:56:13 PM PDT 24
Peak memory 255360 kb
Host smart-3b046fa8-ae54-463d-ae93-2b6942f8359a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20173
02219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2017302219
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.561014723
Short name T492
Test name
Test status
Simulation time 24222097208 ps
CPU time 1207.02 seconds
Started Apr 16 02:55:27 PM PDT 24
Finished Apr 16 03:15:36 PM PDT 24
Peak memory 289064 kb
Host smart-433f290c-07f6-467d-a334-483226b770f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561014723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.561014723
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.432910385
Short name T314
Test name
Test status
Simulation time 1778392602 ps
CPU time 72.42 seconds
Started Apr 16 02:55:25 PM PDT 24
Finished Apr 16 02:56:40 PM PDT 24
Peak memory 248080 kb
Host smart-65c5b2cc-5f5f-4a46-a40a-ac50b199ead6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432910385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.432910385
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2955038492
Short name T363
Test name
Test status
Simulation time 1119055582 ps
CPU time 35.15 seconds
Started Apr 16 02:55:19 PM PDT 24
Finished Apr 16 02:55:57 PM PDT 24
Peak memory 249216 kb
Host smart-f35a2dca-a9fd-4291-8725-fbe7b9aff4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29550
38492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2955038492
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3467533248
Short name T287
Test name
Test status
Simulation time 1206420765 ps
CPU time 19 seconds
Started Apr 16 02:55:26 PM PDT 24
Finished Apr 16 02:55:47 PM PDT 24
Peak memory 255532 kb
Host smart-1ae4d7a4-6f65-4344-ba78-e74a2d9f4c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34675
33248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3467533248
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.447582313
Short name T557
Test name
Test status
Simulation time 155211265 ps
CPU time 8.91 seconds
Started Apr 16 02:55:27 PM PDT 24
Finished Apr 16 02:55:37 PM PDT 24
Peak memory 249068 kb
Host smart-9b0d4d10-2947-41ff-a337-7aa793276ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44758
2313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.447582313
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2336923945
Short name T65
Test name
Test status
Simulation time 4597116194 ps
CPU time 60.23 seconds
Started Apr 16 02:55:21 PM PDT 24
Finished Apr 16 02:56:23 PM PDT 24
Peak memory 256392 kb
Host smart-771af874-c5cb-4b36-8f67-97ab557e772a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23369
23945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2336923945
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3807147257
Short name T204
Test name
Test status
Simulation time 31041930 ps
CPU time 3.08 seconds
Started Apr 16 02:55:30 PM PDT 24
Finished Apr 16 02:55:35 PM PDT 24
Peak memory 249308 kb
Host smart-a20f0406-a226-4328-a843-0c99a25c8b60
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3807147257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3807147257
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2328122401
Short name T405
Test name
Test status
Simulation time 25719594229 ps
CPU time 688.16 seconds
Started Apr 16 02:55:31 PM PDT 24
Finished Apr 16 03:07:01 PM PDT 24
Peak memory 273188 kb
Host smart-a26a61a9-6a45-487e-8f23-ed26fd24bb51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328122401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2328122401
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.706790331
Short name T434
Test name
Test status
Simulation time 262142169 ps
CPU time 7.76 seconds
Started Apr 16 02:55:28 PM PDT 24
Finished Apr 16 02:55:37 PM PDT 24
Peak memory 240860 kb
Host smart-832ab0b3-a541-46c1-94a6-3e2218ec4443
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=706790331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.706790331
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1811649792
Short name T208
Test name
Test status
Simulation time 12029961970 ps
CPU time 156.86 seconds
Started Apr 16 02:55:32 PM PDT 24
Finished Apr 16 02:58:10 PM PDT 24
Peak memory 257152 kb
Host smart-a8a34171-f1a1-4d66-866c-354b42c43fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18116
49792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1811649792
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2354213772
Short name T617
Test name
Test status
Simulation time 970581091 ps
CPU time 27.32 seconds
Started Apr 16 02:55:31 PM PDT 24
Finished Apr 16 02:56:00 PM PDT 24
Peak memory 248532 kb
Host smart-65046523-e544-49a0-90ca-03c40aa9dc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23542
13772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2354213772
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1343505298
Short name T523
Test name
Test status
Simulation time 50461522747 ps
CPU time 2781.72 seconds
Started Apr 16 02:55:30 PM PDT 24
Finished Apr 16 03:41:54 PM PDT 24
Peak memory 287664 kb
Host smart-c963cc84-0aff-4686-bf33-f225cb2151b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343505298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1343505298
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.725556278
Short name T692
Test name
Test status
Simulation time 14169623383 ps
CPU time 723.09 seconds
Started Apr 16 02:55:29 PM PDT 24
Finished Apr 16 03:07:33 PM PDT 24
Peak memory 273048 kb
Host smart-e0103e09-f075-4a46-a348-16b4e05dff91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725556278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.725556278
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1252913467
Short name T238
Test name
Test status
Simulation time 20825524126 ps
CPU time 202.09 seconds
Started Apr 16 02:55:29 PM PDT 24
Finished Apr 16 02:58:52 PM PDT 24
Peak memory 247900 kb
Host smart-ce4f1648-a696-4a4f-8171-c1202eabea3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252913467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1252913467
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2270933
Short name T483
Test name
Test status
Simulation time 293003753 ps
CPU time 25.43 seconds
Started Apr 16 02:55:23 PM PDT 24
Finished Apr 16 02:55:50 PM PDT 24
Peak memory 248984 kb
Host smart-7164f6b5-1b18-49e1-ac46-5817a2076ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22709
33 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2270933
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.323835227
Short name T660
Test name
Test status
Simulation time 293825114 ps
CPU time 18.41 seconds
Started Apr 16 02:55:30 PM PDT 24
Finished Apr 16 02:55:50 PM PDT 24
Peak memory 255528 kb
Host smart-04e46562-87ad-445c-b83b-8eac025a464a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32383
5227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.323835227
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3808759960
Short name T395
Test name
Test status
Simulation time 46169446 ps
CPU time 4.47 seconds
Started Apr 16 02:55:26 PM PDT 24
Finished Apr 16 02:55:33 PM PDT 24
Peak memory 251084 kb
Host smart-db86f979-7330-49ea-8b01-c07d2c7b8c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38087
59960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3808759960
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1797796577
Short name T88
Test name
Test status
Simulation time 11827248089 ps
CPU time 1103.74 seconds
Started Apr 16 02:55:28 PM PDT 24
Finished Apr 16 03:13:53 PM PDT 24
Peak memory 290056 kb
Host smart-b45e6911-b6bb-48ab-b79e-54fe1e233a49
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797796577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1797796577
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2490664985
Short name T196
Test name
Test status
Simulation time 41489057 ps
CPU time 3.17 seconds
Started Apr 16 02:55:35 PM PDT 24
Finished Apr 16 02:55:40 PM PDT 24
Peak memory 249244 kb
Host smart-cebb351f-2023-4f6d-bb7c-fcfec739b6c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2490664985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2490664985
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.603439432
Short name T442
Test name
Test status
Simulation time 23757569182 ps
CPU time 1401.08 seconds
Started Apr 16 02:55:35 PM PDT 24
Finished Apr 16 03:18:58 PM PDT 24
Peak memory 272700 kb
Host smart-9bbce336-fdc1-4b32-b6a3-693a15d95c00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603439432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.603439432
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3630738749
Short name T362
Test name
Test status
Simulation time 2766605287 ps
CPU time 13.54 seconds
Started Apr 16 02:55:37 PM PDT 24
Finished Apr 16 02:55:52 PM PDT 24
Peak memory 252216 kb
Host smart-2abf6755-ef5b-4083-b805-38bc06c64c83
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3630738749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3630738749
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.4015225222
Short name T496
Test name
Test status
Simulation time 94240573 ps
CPU time 9.81 seconds
Started Apr 16 02:55:35 PM PDT 24
Finished Apr 16 02:55:46 PM PDT 24
Peak memory 255240 kb
Host smart-e2e26102-1061-47fd-b278-0c5caf1e7392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40152
25222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.4015225222
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.238049151
Short name T541
Test name
Test status
Simulation time 896996168 ps
CPU time 38.51 seconds
Started Apr 16 02:55:36 PM PDT 24
Finished Apr 16 02:56:16 PM PDT 24
Peak memory 256148 kb
Host smart-78975d77-da29-43b6-84b0-22d1b25dce1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23804
9151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.238049151
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3864398903
Short name T507
Test name
Test status
Simulation time 50576820117 ps
CPU time 1130.51 seconds
Started Apr 16 02:55:35 PM PDT 24
Finished Apr 16 03:14:28 PM PDT 24
Peak memory 269568 kb
Host smart-eeb620eb-0a2e-40ce-a016-fab938b9fe48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864398903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3864398903
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1402542161
Short name T420
Test name
Test status
Simulation time 55958322317 ps
CPU time 1671.9 seconds
Started Apr 16 02:55:38 PM PDT 24
Finished Apr 16 03:23:31 PM PDT 24
Peak memory 283376 kb
Host smart-58cf3b4a-313f-4469-84d8-024a46a9a898
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402542161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1402542161
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2011346881
Short name T209
Test name
Test status
Simulation time 222990451 ps
CPU time 15.31 seconds
Started Apr 16 02:55:34 PM PDT 24
Finished Apr 16 02:55:50 PM PDT 24
Peak memory 255152 kb
Host smart-8895e3b1-6cae-48ae-b50d-14bb326e5838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20113
46881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2011346881
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3161776460
Short name T673
Test name
Test status
Simulation time 66462848 ps
CPU time 5.28 seconds
Started Apr 16 02:55:33 PM PDT 24
Finished Apr 16 02:55:39 PM PDT 24
Peak memory 239364 kb
Host smart-07a66cf6-b584-447d-91c0-7cbed6120179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31617
76460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3161776460
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3246869057
Short name T60
Test name
Test status
Simulation time 92270033 ps
CPU time 7.51 seconds
Started Apr 16 02:55:34 PM PDT 24
Finished Apr 16 02:55:43 PM PDT 24
Peak memory 251612 kb
Host smart-d39390d3-1da9-49ce-97b4-286ba23e06be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32468
69057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3246869057
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1111613275
Short name T681
Test name
Test status
Simulation time 2171614772 ps
CPU time 28.81 seconds
Started Apr 16 02:55:35 PM PDT 24
Finished Apr 16 02:56:06 PM PDT 24
Peak memory 248992 kb
Host smart-ad549b3e-c583-4a6e-97de-8c437de83919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11116
13275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1111613275
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.846282835
Short name T460
Test name
Test status
Simulation time 7718204522 ps
CPU time 446.74 seconds
Started Apr 16 02:55:35 PM PDT 24
Finished Apr 16 03:03:03 PM PDT 24
Peak memory 254636 kb
Host smart-fa6a9e80-35d8-40f3-a112-a3f65e2dea0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846282835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.846282835
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.398102760
Short name T648
Test name
Test status
Simulation time 322000379359 ps
CPU time 7858.3 seconds
Started Apr 16 02:55:36 PM PDT 24
Finished Apr 16 05:06:37 PM PDT 24
Peak memory 372128 kb
Host smart-f4e49684-82a8-40db-b50d-7d25adcd9f1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398102760 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.398102760
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2527578674
Short name T190
Test name
Test status
Simulation time 34132862 ps
CPU time 2.94 seconds
Started Apr 16 02:55:43 PM PDT 24
Finished Apr 16 02:55:47 PM PDT 24
Peak memory 249280 kb
Host smart-b5bb8c1e-a7dd-4165-9bff-c45295f92cdd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2527578674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2527578674
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1128156535
Short name T390
Test name
Test status
Simulation time 33713662343 ps
CPU time 831.91 seconds
Started Apr 16 02:55:41 PM PDT 24
Finished Apr 16 03:09:34 PM PDT 24
Peak memory 271708 kb
Host smart-c3e0a06d-2236-44ba-b25d-7363347b13c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128156535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1128156535
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3402502113
Short name T497
Test name
Test status
Simulation time 181350301 ps
CPU time 9.71 seconds
Started Apr 16 02:55:40 PM PDT 24
Finished Apr 16 02:55:50 PM PDT 24
Peak memory 240792 kb
Host smart-40fb1db3-4885-4f0e-94e1-a25af31dafa8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3402502113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3402502113
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.609491469
Short name T447
Test name
Test status
Simulation time 9268738953 ps
CPU time 115.64 seconds
Started Apr 16 02:55:42 PM PDT 24
Finished Apr 16 02:57:38 PM PDT 24
Peak memory 250172 kb
Host smart-e478b1e9-34bd-436d-b2be-ea0d15040e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60949
1469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.609491469
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.4287442625
Short name T649
Test name
Test status
Simulation time 4142817312 ps
CPU time 57.29 seconds
Started Apr 16 02:55:41 PM PDT 24
Finished Apr 16 02:56:39 PM PDT 24
Peak memory 249480 kb
Host smart-d14d98aa-7202-4956-b03f-16c012f8f89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42874
42625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.4287442625
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3376351468
Short name T341
Test name
Test status
Simulation time 39288329814 ps
CPU time 1121.71 seconds
Started Apr 16 02:55:37 PM PDT 24
Finished Apr 16 03:14:20 PM PDT 24
Peak memory 265500 kb
Host smart-17ec8295-e05f-4dd9-97ef-52d50bdc9468
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376351468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3376351468
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1411991665
Short name T654
Test name
Test status
Simulation time 34301427159 ps
CPU time 375.74 seconds
Started Apr 16 02:55:44 PM PDT 24
Finished Apr 16 03:02:01 PM PDT 24
Peak memory 248332 kb
Host smart-d2e3794b-3833-4fd0-b5f4-2c68c5fbaeb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411991665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1411991665
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3886166487
Short name T188
Test name
Test status
Simulation time 308638736 ps
CPU time 16.02 seconds
Started Apr 16 02:55:41 PM PDT 24
Finished Apr 16 02:55:57 PM PDT 24
Peak memory 254172 kb
Host smart-fa55e844-3ee6-4749-b388-9991c9efcc2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38861
66487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3886166487
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2550602562
Short name T451
Test name
Test status
Simulation time 2049607734 ps
CPU time 28.75 seconds
Started Apr 16 02:55:40 PM PDT 24
Finished Apr 16 02:56:10 PM PDT 24
Peak memory 255048 kb
Host smart-3dbf4aa6-189c-43e1-acdb-02d924f00033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25506
02562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2550602562
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1813824277
Short name T568
Test name
Test status
Simulation time 197640616 ps
CPU time 12.58 seconds
Started Apr 16 02:55:44 PM PDT 24
Finished Apr 16 02:55:57 PM PDT 24
Peak memory 253244 kb
Host smart-451060e0-dcb8-4669-a573-ab821c023709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18138
24277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1813824277
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1240019202
Short name T579
Test name
Test status
Simulation time 1924571114 ps
CPU time 55.36 seconds
Started Apr 16 02:55:39 PM PDT 24
Finished Apr 16 02:56:35 PM PDT 24
Peak memory 256200 kb
Host smart-4fe37639-87e3-4154-b055-766ff5c61ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12400
19202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1240019202
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.4207888289
Short name T255
Test name
Test status
Simulation time 185119820 ps
CPU time 20.58 seconds
Started Apr 16 02:55:44 PM PDT 24
Finished Apr 16 02:56:05 PM PDT 24
Peak memory 256200 kb
Host smart-bbb4ede9-38b5-4cc1-91e3-29e647f3f96e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207888289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.4207888289
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3248493757
Short name T251
Test name
Test status
Simulation time 112841825505 ps
CPU time 3113.16 seconds
Started Apr 16 02:55:44 PM PDT 24
Finished Apr 16 03:47:39 PM PDT 24
Peak memory 338972 kb
Host smart-029a9c90-b6d0-42dc-898a-a1b9ada9d370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248493757 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3248493757
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2810654642
Short name T184
Test name
Test status
Simulation time 41402583 ps
CPU time 3.31 seconds
Started Apr 16 02:55:51 PM PDT 24
Finished Apr 16 02:55:55 PM PDT 24
Peak memory 249312 kb
Host smart-9818c14b-e1dd-458d-be38-ac94eebfbe70
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2810654642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2810654642
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3712170104
Short name T409
Test name
Test status
Simulation time 88717325847 ps
CPU time 2096.8 seconds
Started Apr 16 02:55:53 PM PDT 24
Finished Apr 16 03:30:51 PM PDT 24
Peak memory 287076 kb
Host smart-421a264e-2218-4f05-b3e8-8c881940d9a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712170104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3712170104
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.4077483614
Short name T6
Test name
Test status
Simulation time 1042620098 ps
CPU time 13.09 seconds
Started Apr 16 02:55:54 PM PDT 24
Finished Apr 16 02:56:08 PM PDT 24
Peak memory 248980 kb
Host smart-f00d0e9c-e072-4492-85a5-5b1f00f56dc1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4077483614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.4077483614
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3571376919
Short name T21
Test name
Test status
Simulation time 26229049543 ps
CPU time 117.59 seconds
Started Apr 16 02:55:51 PM PDT 24
Finished Apr 16 02:57:50 PM PDT 24
Peak memory 248844 kb
Host smart-46cadfda-4bbd-41c3-acb9-8c93562b4292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35713
76919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3571376919
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1317304708
Short name T454
Test name
Test status
Simulation time 2011851734 ps
CPU time 30.31 seconds
Started Apr 16 02:55:49 PM PDT 24
Finished Apr 16 02:56:20 PM PDT 24
Peak memory 255760 kb
Host smart-b1ec0193-f8c1-416c-83a1-4b7b5817caaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13173
04708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1317304708
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3696291712
Short name T15
Test name
Test status
Simulation time 95196780703 ps
CPU time 1365.15 seconds
Started Apr 16 02:55:51 PM PDT 24
Finished Apr 16 03:18:37 PM PDT 24
Peak memory 271400 kb
Host smart-1511a426-560a-4509-b4d5-b6ec0c412501
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696291712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3696291712
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2382777324
Short name T323
Test name
Test status
Simulation time 58557986317 ps
CPU time 221.97 seconds
Started Apr 16 02:55:48 PM PDT 24
Finished Apr 16 02:59:31 PM PDT 24
Peak memory 248456 kb
Host smart-d4b44c64-416b-4a35-bc63-d0604e40c124
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382777324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2382777324
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1765139293
Short name T393
Test name
Test status
Simulation time 1573603679 ps
CPU time 43.79 seconds
Started Apr 16 02:55:46 PM PDT 24
Finished Apr 16 02:56:31 PM PDT 24
Peak memory 256436 kb
Host smart-940e8dec-b0eb-40ff-beac-a12c2b0f4909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17651
39293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1765139293
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1660217697
Short name T633
Test name
Test status
Simulation time 190775686 ps
CPU time 11.71 seconds
Started Apr 16 02:55:45 PM PDT 24
Finished Apr 16 02:55:58 PM PDT 24
Peak memory 249036 kb
Host smart-9966e449-c80f-46a3-8730-146ebfaca23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16602
17697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1660217697
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2220717078
Short name T22
Test name
Test status
Simulation time 794519903 ps
CPU time 42.67 seconds
Started Apr 16 02:55:50 PM PDT 24
Finished Apr 16 02:56:33 PM PDT 24
Peak memory 255420 kb
Host smart-ad7dbc0b-e323-4a8e-ab6f-5112d170f5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22207
17078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2220717078
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.672109175
Short name T456
Test name
Test status
Simulation time 1114383353 ps
CPU time 24.63 seconds
Started Apr 16 02:55:43 PM PDT 24
Finished Apr 16 02:56:09 PM PDT 24
Peak memory 256524 kb
Host smart-76add5f1-2fac-4e6f-9bf8-da2dc119cf39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67210
9175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.672109175
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1752763717
Short name T250
Test name
Test status
Simulation time 151257196812 ps
CPU time 2366.26 seconds
Started Apr 16 02:55:51 PM PDT 24
Finished Apr 16 03:35:18 PM PDT 24
Peak memory 290052 kb
Host smart-a97a7b30-f094-427f-905b-aba2e54c0c83
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752763717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1752763717
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.438250725
Short name T565
Test name
Test status
Simulation time 62174115111 ps
CPU time 1595.13 seconds
Started Apr 16 02:55:50 PM PDT 24
Finished Apr 16 03:22:26 PM PDT 24
Peak memory 306256 kb
Host smart-ec6e458a-7148-4355-9871-35472d24f464
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438250725 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.438250725
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1802370392
Short name T35
Test name
Test status
Simulation time 127968659 ps
CPU time 3.81 seconds
Started Apr 16 02:55:55 PM PDT 24
Finished Apr 16 02:56:00 PM PDT 24
Peak memory 249344 kb
Host smart-1fa545f0-5cb5-4318-966c-0c2ea20394c1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1802370392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1802370392
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3933500956
Short name T172
Test name
Test status
Simulation time 7220900392 ps
CPU time 668.95 seconds
Started Apr 16 02:55:54 PM PDT 24
Finished Apr 16 03:07:04 PM PDT 24
Peak memory 265632 kb
Host smart-bb998acb-9dc5-4cb7-b20b-c1fdd05a5eb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933500956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3933500956
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.763475055
Short name T34
Test name
Test status
Simulation time 504306796 ps
CPU time 8.02 seconds
Started Apr 16 02:55:57 PM PDT 24
Finished Apr 16 02:56:06 PM PDT 24
Peak memory 240856 kb
Host smart-5dbb448d-0337-4c11-81a1-40bc2cbbf54e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=763475055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.763475055
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3669830110
Short name T186
Test name
Test status
Simulation time 3549499490 ps
CPU time 118.81 seconds
Started Apr 16 02:55:55 PM PDT 24
Finished Apr 16 02:57:55 PM PDT 24
Peak memory 257324 kb
Host smart-8eccf6c1-74ea-428a-a367-5b5d4c97763d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36698
30110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3669830110
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2437158664
Short name T551
Test name
Test status
Simulation time 44352599 ps
CPU time 3.94 seconds
Started Apr 16 02:55:57 PM PDT 24
Finished Apr 16 02:56:02 PM PDT 24
Peak memory 240872 kb
Host smart-3fdd993d-4a2d-4151-9de5-b94bbff94d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24371
58664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2437158664
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.167619993
Short name T337
Test name
Test status
Simulation time 28131967013 ps
CPU time 1082.81 seconds
Started Apr 16 02:55:55 PM PDT 24
Finished Apr 16 03:13:59 PM PDT 24
Peak memory 290136 kb
Host smart-cc4a93f4-acde-44af-b8bb-951f1a622337
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167619993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.167619993
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1610394038
Short name T444
Test name
Test status
Simulation time 56182673677 ps
CPU time 3231.33 seconds
Started Apr 16 02:55:54 PM PDT 24
Finished Apr 16 03:49:47 PM PDT 24
Peak memory 289568 kb
Host smart-9d4897e4-ed1c-4f2d-a94a-3564d3dcb6a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610394038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1610394038
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.273073412
Short name T307
Test name
Test status
Simulation time 53689435187 ps
CPU time 467.96 seconds
Started Apr 16 02:55:55 PM PDT 24
Finished Apr 16 03:03:44 PM PDT 24
Peak memory 248300 kb
Host smart-98f03045-ad22-49dc-bde1-e99534fa5ec1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273073412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.273073412
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3331836949
Short name T455
Test name
Test status
Simulation time 285224096 ps
CPU time 17.61 seconds
Started Apr 16 02:55:56 PM PDT 24
Finished Apr 16 02:56:15 PM PDT 24
Peak memory 249184 kb
Host smart-053d9e55-6b2c-4563-8373-efb175404d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33318
36949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3331836949
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3242769732
Short name T285
Test name
Test status
Simulation time 6355758774 ps
CPU time 48.89 seconds
Started Apr 16 02:55:54 PM PDT 24
Finished Apr 16 02:56:44 PM PDT 24
Peak memory 254764 kb
Host smart-6f9163de-208f-48be-bf18-212bbb1daeac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32427
69732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3242769732
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3677765541
Short name T625
Test name
Test status
Simulation time 752914139 ps
CPU time 14.88 seconds
Started Apr 16 02:55:58 PM PDT 24
Finished Apr 16 02:56:14 PM PDT 24
Peak memory 257244 kb
Host smart-375243fd-8dfc-4777-946e-d6410626a674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36777
65541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3677765541
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2485299691
Short name T84
Test name
Test status
Simulation time 19917893286 ps
CPU time 427.17 seconds
Started Apr 16 02:55:57 PM PDT 24
Finished Apr 16 03:03:05 PM PDT 24
Peak memory 265536 kb
Host smart-fc534657-6e79-4560-bb65-3fae7344b019
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485299691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2485299691
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2257478620
Short name T203
Test name
Test status
Simulation time 44897882 ps
CPU time 3.5 seconds
Started Apr 16 02:56:05 PM PDT 24
Finished Apr 16 02:56:09 PM PDT 24
Peak memory 249328 kb
Host smart-e0cc4a13-4d92-4afe-b3c8-12fce9fd40df
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2257478620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2257478620
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2295594095
Short name T406
Test name
Test status
Simulation time 147329690799 ps
CPU time 2083.28 seconds
Started Apr 16 02:56:00 PM PDT 24
Finished Apr 16 03:30:44 PM PDT 24
Peak memory 281940 kb
Host smart-3879a2af-a208-4f9c-a934-220d5fec12ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295594095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2295594095
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2153944469
Short name T211
Test name
Test status
Simulation time 892582399 ps
CPU time 38.31 seconds
Started Apr 16 02:56:01 PM PDT 24
Finished Apr 16 02:56:40 PM PDT 24
Peak memory 251656 kb
Host smart-773446cc-0439-4e4c-ab94-7f7dd6302182
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2153944469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2153944469
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1304424325
Short name T684
Test name
Test status
Simulation time 296535431 ps
CPU time 4.14 seconds
Started Apr 16 02:56:00 PM PDT 24
Finished Apr 16 02:56:05 PM PDT 24
Peak memory 239408 kb
Host smart-bc60a44f-ad45-4e8d-8b71-b8b789184a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13044
24325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1304424325
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2244910858
Short name T585
Test name
Test status
Simulation time 848459857 ps
CPU time 14.3 seconds
Started Apr 16 02:55:59 PM PDT 24
Finished Apr 16 02:56:14 PM PDT 24
Peak memory 252084 kb
Host smart-dea663d2-e3dd-4e85-abfa-19693c7e3f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22449
10858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2244910858
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2081273982
Short name T281
Test name
Test status
Simulation time 8905944698 ps
CPU time 649.53 seconds
Started Apr 16 02:56:01 PM PDT 24
Finished Apr 16 03:06:51 PM PDT 24
Peak memory 265772 kb
Host smart-b1a99cfe-2051-425f-948f-6a8870ed2502
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081273982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2081273982
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1401724673
Short name T703
Test name
Test status
Simulation time 51798105831 ps
CPU time 1093.26 seconds
Started Apr 16 02:55:59 PM PDT 24
Finished Apr 16 03:14:13 PM PDT 24
Peak memory 281860 kb
Host smart-60e88187-f928-4c78-be01-9e841c80df9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401724673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1401724673
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.367444554
Short name T680
Test name
Test status
Simulation time 8858217081 ps
CPU time 348.01 seconds
Started Apr 16 02:55:59 PM PDT 24
Finished Apr 16 03:01:48 PM PDT 24
Peak memory 248296 kb
Host smart-f64057be-313b-46fd-853f-534c86822ea5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367444554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.367444554
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1517315737
Short name T508
Test name
Test status
Simulation time 515675145 ps
CPU time 36.82 seconds
Started Apr 16 02:55:58 PM PDT 24
Finished Apr 16 02:56:35 PM PDT 24
Peak memory 256356 kb
Host smart-e96c1916-8736-44e2-9c01-3341f7e2ad91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15173
15737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1517315737
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3637215752
Short name T441
Test name
Test status
Simulation time 295005360 ps
CPU time 6.65 seconds
Started Apr 16 02:55:59 PM PDT 24
Finished Apr 16 02:56:06 PM PDT 24
Peak memory 254260 kb
Host smart-a68b36c0-6610-4abb-af96-bad7e0efa87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36372
15752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3637215752
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1964519644
Short name T452
Test name
Test status
Simulation time 1168182308 ps
CPU time 61.81 seconds
Started Apr 16 02:55:58 PM PDT 24
Finished Apr 16 02:57:00 PM PDT 24
Peak memory 255700 kb
Host smart-4f60c542-c56d-4f78-a0ca-0aa42e833fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19645
19644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1964519644
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.4054926057
Short name T612
Test name
Test status
Simulation time 448041940 ps
CPU time 16.14 seconds
Started Apr 16 02:56:00 PM PDT 24
Finished Apr 16 02:56:16 PM PDT 24
Peak memory 248984 kb
Host smart-c61158b5-d4b2-4d4b-b00e-46b37a0dcaa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40549
26057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.4054926057
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2117316718
Short name T79
Test name
Test status
Simulation time 160450929 ps
CPU time 3.49 seconds
Started Apr 16 02:56:09 PM PDT 24
Finished Apr 16 02:56:13 PM PDT 24
Peak memory 249324 kb
Host smart-1bc5a725-51e7-488a-9b8c-d6673b4e3457
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2117316718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2117316718
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1646172109
Short name T670
Test name
Test status
Simulation time 12901228204 ps
CPU time 569.07 seconds
Started Apr 16 02:56:04 PM PDT 24
Finished Apr 16 03:05:34 PM PDT 24
Peak memory 273532 kb
Host smart-7fa5504d-82ca-479c-8ef2-e54fa10b4e5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646172109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1646172109
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.970830041
Short name T214
Test name
Test status
Simulation time 2237036210 ps
CPU time 23.89 seconds
Started Apr 16 02:56:06 PM PDT 24
Finished Apr 16 02:56:31 PM PDT 24
Peak memory 240936 kb
Host smart-9fab4161-1220-49e5-9dd7-d44cd83205e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=970830041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.970830041
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1278148159
Short name T537
Test name
Test status
Simulation time 16315057972 ps
CPU time 208.59 seconds
Started Apr 16 02:56:03 PM PDT 24
Finished Apr 16 02:59:32 PM PDT 24
Peak memory 257032 kb
Host smart-9598dae3-58d7-4dfe-8cc1-3fcefa145d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12781
48159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1278148159
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2757631766
Short name T71
Test name
Test status
Simulation time 787072972 ps
CPU time 26.16 seconds
Started Apr 16 02:56:03 PM PDT 24
Finished Apr 16 02:56:29 PM PDT 24
Peak memory 255760 kb
Host smart-4c279c46-8aa5-483c-8058-3cb3da4deffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27576
31766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2757631766
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2064952599
Short name T552
Test name
Test status
Simulation time 29098205162 ps
CPU time 1687.44 seconds
Started Apr 16 02:56:06 PM PDT 24
Finished Apr 16 03:24:15 PM PDT 24
Peak memory 273732 kb
Host smart-926e524f-5e29-434a-a6d6-f3bd90b00157
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064952599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2064952599
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3817921117
Short name T531
Test name
Test status
Simulation time 10379426094 ps
CPU time 111.68 seconds
Started Apr 16 02:56:03 PM PDT 24
Finished Apr 16 02:57:55 PM PDT 24
Peak memory 248336 kb
Host smart-048c1df6-744e-4892-b3d2-38fad5cfba26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817921117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3817921117
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.4139652902
Short name T404
Test name
Test status
Simulation time 350471285 ps
CPU time 7.33 seconds
Started Apr 16 02:56:03 PM PDT 24
Finished Apr 16 02:56:11 PM PDT 24
Peak memory 249044 kb
Host smart-e0c9933a-9faf-4091-965f-24d77b70c450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41396
52902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.4139652902
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2736546042
Short name T92
Test name
Test status
Simulation time 4845461544 ps
CPU time 33.41 seconds
Started Apr 16 02:56:05 PM PDT 24
Finished Apr 16 02:56:39 PM PDT 24
Peak memory 249000 kb
Host smart-b82e35eb-d7ad-425c-9928-30357a47f52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27365
46042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2736546042
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3300591444
Short name T527
Test name
Test status
Simulation time 109435690 ps
CPU time 8.29 seconds
Started Apr 16 02:56:06 PM PDT 24
Finished Apr 16 02:56:15 PM PDT 24
Peak memory 247552 kb
Host smart-0b52c5f6-a222-4778-966b-27150301d2fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33005
91444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3300591444
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1306065675
Short name T509
Test name
Test status
Simulation time 6956325984 ps
CPU time 49.13 seconds
Started Apr 16 02:56:03 PM PDT 24
Finished Apr 16 02:56:53 PM PDT 24
Peak memory 249176 kb
Host smart-cf10f25c-2ddc-49cd-8fb1-ca60902792ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13060
65675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1306065675
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2528330314
Short name T528
Test name
Test status
Simulation time 90176881388 ps
CPU time 1284.93 seconds
Started Apr 16 02:56:09 PM PDT 24
Finished Apr 16 03:17:35 PM PDT 24
Peak memory 273256 kb
Host smart-d6187149-8c51-49a9-951c-322b8892ade7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528330314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2528330314
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1693271791
Short name T40
Test name
Test status
Simulation time 184481781 ps
CPU time 3.91 seconds
Started Apr 16 02:54:50 PM PDT 24
Finished Apr 16 02:54:56 PM PDT 24
Peak memory 249308 kb
Host smart-df3429e5-a392-406d-a3a2-97bc2153582f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1693271791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1693271791
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2231233028
Short name T89
Test name
Test status
Simulation time 16149836011 ps
CPU time 832.12 seconds
Started Apr 16 02:54:51 PM PDT 24
Finished Apr 16 03:08:45 PM PDT 24
Peak memory 272888 kb
Host smart-7d17ac7c-fdbc-42ad-91b5-385a5e205143
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231233028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2231233028
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.239919268
Short name T392
Test name
Test status
Simulation time 200087256 ps
CPU time 10.86 seconds
Started Apr 16 02:54:50 PM PDT 24
Finished Apr 16 02:55:02 PM PDT 24
Peak memory 249080 kb
Host smart-d85c33a1-6da8-4033-9f5c-586f4027265c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=239919268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.239919268
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3058142326
Short name T55
Test name
Test status
Simulation time 8934549563 ps
CPU time 156.44 seconds
Started Apr 16 02:54:53 PM PDT 24
Finished Apr 16 02:57:31 PM PDT 24
Peak memory 251304 kb
Host smart-c543b290-442d-424d-880a-3ad6f9463964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30581
42326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3058142326
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3434568849
Short name T696
Test name
Test status
Simulation time 4873713176 ps
CPU time 66.45 seconds
Started Apr 16 02:54:50 PM PDT 24
Finished Apr 16 02:55:58 PM PDT 24
Peak memory 255280 kb
Host smart-9c83dcae-8b0f-4310-ae14-89666d726d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34345
68849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3434568849
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.251059194
Short name T672
Test name
Test status
Simulation time 37654500816 ps
CPU time 693.26 seconds
Started Apr 16 02:54:52 PM PDT 24
Finished Apr 16 03:06:27 PM PDT 24
Peak memory 271680 kb
Host smart-ca30d07e-8c5b-431d-9a89-9a531ca166ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251059194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.251059194
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3516076405
Short name T379
Test name
Test status
Simulation time 55425390734 ps
CPU time 3154.49 seconds
Started Apr 16 02:54:51 PM PDT 24
Finished Apr 16 03:47:27 PM PDT 24
Peak memory 289612 kb
Host smart-270c2891-b84a-43e6-97e2-1f8cffe0f1a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516076405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3516076405
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3982155983
Short name T542
Test name
Test status
Simulation time 17085649845 ps
CPU time 174.83 seconds
Started Apr 16 02:54:52 PM PDT 24
Finished Apr 16 02:57:49 PM PDT 24
Peak memory 248384 kb
Host smart-46225b2e-7414-4d1a-bcda-10f7e327911f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982155983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3982155983
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1598972967
Short name T360
Test name
Test status
Simulation time 2699079704 ps
CPU time 17.4 seconds
Started Apr 16 02:54:45 PM PDT 24
Finished Apr 16 02:55:03 PM PDT 24
Peak memory 249176 kb
Host smart-24ac78e2-43d5-4a25-b562-d979c9b66421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15989
72967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1598972967
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.4205983224
Short name T559
Test name
Test status
Simulation time 843403415 ps
CPU time 49.64 seconds
Started Apr 16 02:54:46 PM PDT 24
Finished Apr 16 02:55:37 PM PDT 24
Peak memory 247724 kb
Host smart-ac5ad7d5-1429-4d19-bf64-a2e2b7957b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42059
83224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.4205983224
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2205785225
Short name T30
Test name
Test status
Simulation time 539122728 ps
CPU time 23.05 seconds
Started Apr 16 02:54:50 PM PDT 24
Finished Apr 16 02:55:15 PM PDT 24
Peak memory 265592 kb
Host smart-f1116de3-da6f-4629-9820-9f1fcaf456c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2205785225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2205785225
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1634458284
Short name T421
Test name
Test status
Simulation time 55582638 ps
CPU time 5.9 seconds
Started Apr 16 02:54:48 PM PDT 24
Finished Apr 16 02:54:55 PM PDT 24
Peak memory 251912 kb
Host smart-5b52ec19-5036-40b4-b2e3-c8a489b589e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16344
58284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1634458284
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1969887497
Short name T634
Test name
Test status
Simulation time 917618761 ps
CPU time 49.71 seconds
Started Apr 16 02:54:45 PM PDT 24
Finished Apr 16 02:55:36 PM PDT 24
Peak memory 249048 kb
Host smart-ab3e9e1c-100e-4127-8e08-ebefe1e63868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19698
87497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1969887497
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.656393947
Short name T558
Test name
Test status
Simulation time 17810390360 ps
CPU time 682.99 seconds
Started Apr 16 02:56:12 PM PDT 24
Finished Apr 16 03:07:36 PM PDT 24
Peak memory 265616 kb
Host smart-373db847-c77d-451f-8af8-5c8fcd617889
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656393947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.656393947
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.561203870
Short name T601
Test name
Test status
Simulation time 4771717402 ps
CPU time 117.19 seconds
Started Apr 16 02:56:07 PM PDT 24
Finished Apr 16 02:58:05 PM PDT 24
Peak memory 248860 kb
Host smart-97d59e22-3d2e-4662-afb7-b533dfcc5394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56120
3870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.561203870
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3002698672
Short name T534
Test name
Test status
Simulation time 3220003769 ps
CPU time 62.26 seconds
Started Apr 16 02:56:09 PM PDT 24
Finished Apr 16 02:57:12 PM PDT 24
Peak memory 249164 kb
Host smart-0bb6b2e5-c48e-4542-a128-0ab3984f2796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30026
98672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3002698672
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1280230868
Short name T322
Test name
Test status
Simulation time 174507662666 ps
CPU time 1354.33 seconds
Started Apr 16 02:56:13 PM PDT 24
Finished Apr 16 03:18:48 PM PDT 24
Peak memory 289540 kb
Host smart-4a4f6b7b-fbc7-4239-b0a8-6c283165b569
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280230868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1280230868
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3692996396
Short name T646
Test name
Test status
Simulation time 25427500237 ps
CPU time 642.99 seconds
Started Apr 16 02:56:17 PM PDT 24
Finished Apr 16 03:07:01 PM PDT 24
Peak memory 265484 kb
Host smart-5a1995d6-375e-4b68-b20f-1c6b523c0ede
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692996396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3692996396
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.4230541820
Short name T556
Test name
Test status
Simulation time 32755458607 ps
CPU time 228.01 seconds
Started Apr 16 02:56:11 PM PDT 24
Finished Apr 16 03:00:00 PM PDT 24
Peak memory 249116 kb
Host smart-331ca69e-6422-4f17-bf86-2bfa4465910b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230541820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.4230541820
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3366219366
Short name T571
Test name
Test status
Simulation time 78676129 ps
CPU time 9.48 seconds
Started Apr 16 02:56:09 PM PDT 24
Finished Apr 16 02:56:19 PM PDT 24
Peak memory 256304 kb
Host smart-3cfe8930-d2ea-4f4e-b689-27a2a42e1519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33662
19366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3366219366
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1566474439
Short name T67
Test name
Test status
Simulation time 795222374 ps
CPU time 33.77 seconds
Started Apr 16 02:56:09 PM PDT 24
Finished Apr 16 02:56:44 PM PDT 24
Peak memory 254980 kb
Host smart-ace2474b-5be4-468e-bb8f-5802ece0faad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15664
74439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1566474439
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1183386343
Short name T38
Test name
Test status
Simulation time 590799993 ps
CPU time 30.08 seconds
Started Apr 16 02:56:18 PM PDT 24
Finished Apr 16 02:56:49 PM PDT 24
Peak memory 254884 kb
Host smart-06157f00-2811-43f3-aad9-d4fc6b586429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11833
86343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1183386343
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2879967788
Short name T641
Test name
Test status
Simulation time 1554579595 ps
CPU time 62.35 seconds
Started Apr 16 02:56:08 PM PDT 24
Finished Apr 16 02:57:11 PM PDT 24
Peak memory 248988 kb
Host smart-353950f2-fddb-433c-9710-aa4e8c6a772e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28799
67788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2879967788
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.212136221
Short name T260
Test name
Test status
Simulation time 9357723848 ps
CPU time 1113.51 seconds
Started Apr 16 02:56:13 PM PDT 24
Finished Apr 16 03:14:47 PM PDT 24
Peak memory 281936 kb
Host smart-eacb60f4-999f-40c2-8478-716690ef3ca5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212136221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.212136221
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.4013064600
Short name T245
Test name
Test status
Simulation time 70844085655 ps
CPU time 2070 seconds
Started Apr 16 02:56:18 PM PDT 24
Finished Apr 16 03:30:49 PM PDT 24
Peak memory 306420 kb
Host smart-c2cf2136-b866-46b8-8d47-8d6a5da842a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013064600 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.4013064600
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1938307177
Short name T593
Test name
Test status
Simulation time 37388373734 ps
CPU time 1859.61 seconds
Started Apr 16 02:56:13 PM PDT 24
Finished Apr 16 03:27:14 PM PDT 24
Peak memory 289168 kb
Host smart-2da7735c-def3-4a20-a296-96c3e697cf5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938307177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1938307177
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2055974871
Short name T374
Test name
Test status
Simulation time 18953572945 ps
CPU time 153.13 seconds
Started Apr 16 02:56:14 PM PDT 24
Finished Apr 16 02:58:48 PM PDT 24
Peak memory 257100 kb
Host smart-300612dd-20c5-4fc5-83c4-72361802051a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20559
74871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2055974871
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3592453602
Short name T437
Test name
Test status
Simulation time 484788443 ps
CPU time 24.52 seconds
Started Apr 16 02:56:12 PM PDT 24
Finished Apr 16 02:56:37 PM PDT 24
Peak memory 254388 kb
Host smart-c3d47a85-c622-4b08-93e9-e732b9996f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35924
53602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3592453602
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2817851341
Short name T698
Test name
Test status
Simulation time 409151607024 ps
CPU time 2157.76 seconds
Started Apr 16 02:56:18 PM PDT 24
Finished Apr 16 03:32:17 PM PDT 24
Peak memory 284936 kb
Host smart-151610ab-8367-41b1-854a-71e8d68123ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817851341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2817851341
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.669149896
Short name T83
Test name
Test status
Simulation time 37257891734 ps
CPU time 809.35 seconds
Started Apr 16 02:56:18 PM PDT 24
Finished Apr 16 03:09:49 PM PDT 24
Peak memory 273736 kb
Host smart-da008846-a41c-4b58-9814-6be65e7ac94b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669149896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.669149896
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.4128504935
Short name T443
Test name
Test status
Simulation time 1267980192 ps
CPU time 28.83 seconds
Started Apr 16 02:56:11 PM PDT 24
Finished Apr 16 02:56:41 PM PDT 24
Peak memory 249044 kb
Host smart-db4c8278-5b47-4a13-9360-fdc330fda852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41285
04935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.4128504935
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3427385782
Short name T45
Test name
Test status
Simulation time 147004521 ps
CPU time 12.27 seconds
Started Apr 16 02:56:14 PM PDT 24
Finished Apr 16 02:56:27 PM PDT 24
Peak memory 253924 kb
Host smart-85f0aad3-aaa2-40fb-b912-d70e4e5e9a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34273
85782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3427385782
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2486527306
Short name T446
Test name
Test status
Simulation time 122814804 ps
CPU time 4.82 seconds
Started Apr 16 02:56:12 PM PDT 24
Finished Apr 16 02:56:17 PM PDT 24
Peak memory 239360 kb
Host smart-2d0ae39e-f943-4e69-8925-afb89d44f945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24865
27306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2486527306
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1586044727
Short name T378
Test name
Test status
Simulation time 3700037025 ps
CPU time 52.28 seconds
Started Apr 16 02:56:18 PM PDT 24
Finished Apr 16 02:57:12 PM PDT 24
Peak memory 249188 kb
Host smart-e733a552-b33c-49db-9239-1165cda60b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15860
44727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1586044727
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3688294930
Short name T587
Test name
Test status
Simulation time 50485707551 ps
CPU time 1374.17 seconds
Started Apr 16 02:56:25 PM PDT 24
Finished Apr 16 03:19:21 PM PDT 24
Peak memory 289548 kb
Host smart-9d590b9e-5580-4c08-9cc5-881b0e62a931
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688294930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3688294930
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2952351198
Short name T662
Test name
Test status
Simulation time 2417032726 ps
CPU time 137.66 seconds
Started Apr 16 02:56:19 PM PDT 24
Finished Apr 16 02:58:38 PM PDT 24
Peak memory 249012 kb
Host smart-9db6a2fc-18d1-4aa0-b170-ede436d54cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29523
51198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2952351198
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2509511473
Short name T505
Test name
Test status
Simulation time 509171685 ps
CPU time 26.78 seconds
Started Apr 16 02:56:18 PM PDT 24
Finished Apr 16 02:56:45 PM PDT 24
Peak memory 248968 kb
Host smart-df2c5808-5337-4e1b-9daf-12dc9d381642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25095
11473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2509511473
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1052103789
Short name T326
Test name
Test status
Simulation time 41665750406 ps
CPU time 1373.11 seconds
Started Apr 16 02:56:31 PM PDT 24
Finished Apr 16 03:19:25 PM PDT 24
Peak memory 269620 kb
Host smart-032a47c6-9f92-4941-8abc-37547ac813cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052103789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1052103789
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1024422887
Short name T679
Test name
Test status
Simulation time 40219707453 ps
CPU time 960.14 seconds
Started Apr 16 02:56:22 PM PDT 24
Finished Apr 16 03:12:23 PM PDT 24
Peak memory 273720 kb
Host smart-8717146b-893a-471d-87b5-a199e99f8dd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024422887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1024422887
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2808016742
Short name T315
Test name
Test status
Simulation time 10821952078 ps
CPU time 219.8 seconds
Started Apr 16 02:56:26 PM PDT 24
Finished Apr 16 03:00:08 PM PDT 24
Peak memory 248424 kb
Host smart-b5f4c077-98a7-44a6-8432-07cb5041319b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808016742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2808016742
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.944748291
Short name T693
Test name
Test status
Simulation time 636238778 ps
CPU time 19.74 seconds
Started Apr 16 02:56:19 PM PDT 24
Finished Apr 16 02:56:41 PM PDT 24
Peak memory 255836 kb
Host smart-d063e196-57ed-4b59-85ef-4866f793c7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94474
8291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.944748291
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2710283045
Short name T535
Test name
Test status
Simulation time 296101374 ps
CPU time 18.75 seconds
Started Apr 16 02:56:19 PM PDT 24
Finished Apr 16 02:56:39 PM PDT 24
Peak memory 254024 kb
Host smart-10b5370e-4496-4ea1-a629-37b758308134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27102
83045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2710283045
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1302961525
Short name T258
Test name
Test status
Simulation time 46079134 ps
CPU time 5.97 seconds
Started Apr 16 02:56:18 PM PDT 24
Finished Apr 16 02:56:25 PM PDT 24
Peak memory 247572 kb
Host smart-9adb1359-6bd3-40e6-9d29-2835309e0413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13029
61525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1302961525
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2316735177
Short name T495
Test name
Test status
Simulation time 538639447 ps
CPU time 32.21 seconds
Started Apr 16 02:56:23 PM PDT 24
Finished Apr 16 02:56:56 PM PDT 24
Peak memory 249040 kb
Host smart-b498865f-f4dd-4a93-9e04-e83396281eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23167
35177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2316735177
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.1032914592
Short name T75
Test name
Test status
Simulation time 459944733890 ps
CPU time 8148.4 seconds
Started Apr 16 02:56:25 PM PDT 24
Finished Apr 16 05:12:16 PM PDT 24
Peak memory 322408 kb
Host smart-828c5b7b-5956-49b0-b8c0-8fe4563ff23a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032914592 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.1032914592
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.653304724
Short name T32
Test name
Test status
Simulation time 28540105429 ps
CPU time 2132.01 seconds
Started Apr 16 02:56:22 PM PDT 24
Finished Apr 16 03:31:55 PM PDT 24
Peak memory 289576 kb
Host smart-1f225655-f217-428b-a845-bc9b66403604
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653304724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.653304724
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3376937085
Short name T604
Test name
Test status
Simulation time 4956084089 ps
CPU time 149.35 seconds
Started Apr 16 02:56:24 PM PDT 24
Finished Apr 16 02:58:55 PM PDT 24
Peak memory 257296 kb
Host smart-f22d5237-a00d-40b0-ac22-a675212d5eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33769
37085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3376937085
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2393095488
Short name T524
Test name
Test status
Simulation time 229686663 ps
CPU time 8.43 seconds
Started Apr 16 02:56:31 PM PDT 24
Finished Apr 16 02:56:40 PM PDT 24
Peak memory 253816 kb
Host smart-023509fa-ea2a-4d26-9b79-53f0323334de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23930
95488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2393095488
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2424623141
Short name T349
Test name
Test status
Simulation time 60732814189 ps
CPU time 2592.69 seconds
Started Apr 16 02:56:33 PM PDT 24
Finished Apr 16 03:39:46 PM PDT 24
Peak memory 289180 kb
Host smart-9e09bbde-fabe-4f9c-9bcc-39c80933a352
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424623141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2424623141
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3577330498
Short name T695
Test name
Test status
Simulation time 69931735750 ps
CPU time 854.23 seconds
Started Apr 16 02:56:29 PM PDT 24
Finished Apr 16 03:10:45 PM PDT 24
Peak memory 273720 kb
Host smart-936b8d16-ba5c-4b86-8c19-1c1d016f9e76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577330498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3577330498
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1285390266
Short name T4
Test name
Test status
Simulation time 53713406641 ps
CPU time 532.57 seconds
Started Apr 16 02:56:29 PM PDT 24
Finished Apr 16 03:05:23 PM PDT 24
Peak memory 254644 kb
Host smart-c43ae78d-2527-4c01-a087-10d4acd7d520
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285390266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1285390266
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.779314962
Short name T217
Test name
Test status
Simulation time 1015623912 ps
CPU time 15.08 seconds
Started Apr 16 02:56:26 PM PDT 24
Finished Apr 16 02:56:43 PM PDT 24
Peak memory 249084 kb
Host smart-09ff4773-b6cd-4657-80bc-f107d6a8a799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77931
4962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.779314962
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1585205021
Short name T86
Test name
Test status
Simulation time 746081426 ps
CPU time 13.08 seconds
Started Apr 16 02:56:24 PM PDT 24
Finished Apr 16 02:56:39 PM PDT 24
Peak memory 254260 kb
Host smart-caf83da3-5d64-4a00-9404-ad9c59f78038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15852
05021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1585205021
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1616943427
Short name T167
Test name
Test status
Simulation time 1503987775 ps
CPU time 22.5 seconds
Started Apr 16 02:56:31 PM PDT 24
Finished Apr 16 02:56:54 PM PDT 24
Peak memory 255392 kb
Host smart-b8be9154-c6e3-40e9-8303-51f1280bc60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16169
43427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1616943427
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.21130282
Short name T464
Test name
Test status
Simulation time 2815344882 ps
CPU time 44.49 seconds
Started Apr 16 02:56:24 PM PDT 24
Finished Apr 16 02:57:11 PM PDT 24
Peak memory 256192 kb
Host smart-5a8347ef-5110-442d-86a9-9c5635f23b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21130
282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.21130282
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3576384190
Short name T97
Test name
Test status
Simulation time 150909966755 ps
CPU time 2287.89 seconds
Started Apr 16 02:56:35 PM PDT 24
Finished Apr 16 03:34:44 PM PDT 24
Peak memory 271672 kb
Host smart-1c5cf13e-55c2-485c-93a9-5ad4e7b71b6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576384190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3576384190
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2864691483
Short name T664
Test name
Test status
Simulation time 2891077962 ps
CPU time 104.11 seconds
Started Apr 16 02:56:34 PM PDT 24
Finished Apr 16 02:58:19 PM PDT 24
Peak memory 255740 kb
Host smart-cd9bb5b9-e924-4ada-ad35-d25a24db536f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28646
91483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2864691483
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.713573379
Short name T419
Test name
Test status
Simulation time 2870517284 ps
CPU time 27.85 seconds
Started Apr 16 02:56:29 PM PDT 24
Finished Apr 16 02:56:58 PM PDT 24
Peak memory 255268 kb
Host smart-d6ed637e-165d-40a3-9dec-bbe220e3b587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71357
3379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.713573379
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3912817379
Short name T338
Test name
Test status
Simulation time 30315461553 ps
CPU time 1481.72 seconds
Started Apr 16 02:56:36 PM PDT 24
Finished Apr 16 03:21:19 PM PDT 24
Peak memory 265500 kb
Host smart-e4710525-ae2e-49d9-a329-e38ceae11253
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912817379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3912817379
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2066985890
Short name T302
Test name
Test status
Simulation time 7557436901 ps
CPU time 303.89 seconds
Started Apr 16 02:56:36 PM PDT 24
Finished Apr 16 03:01:41 PM PDT 24
Peak memory 248084 kb
Host smart-f661fdfd-f562-4859-8e50-efe839f63d7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066985890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2066985890
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1067837409
Short name T20
Test name
Test status
Simulation time 351416120 ps
CPU time 32.84 seconds
Started Apr 16 02:56:35 PM PDT 24
Finished Apr 16 02:57:09 PM PDT 24
Peak memory 249256 kb
Host smart-e0234e67-939c-4186-afe6-4a77043f654e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10678
37409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1067837409
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3895716005
Short name T686
Test name
Test status
Simulation time 926880928 ps
CPU time 54.63 seconds
Started Apr 16 02:56:29 PM PDT 24
Finished Apr 16 02:57:25 PM PDT 24
Peak memory 256012 kb
Host smart-0d538b56-92e0-481f-b166-d00e330658dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38957
16005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3895716005
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.731763766
Short name T658
Test name
Test status
Simulation time 802377464 ps
CPU time 14.29 seconds
Started Apr 16 02:56:39 PM PDT 24
Finished Apr 16 02:56:54 PM PDT 24
Peak memory 247576 kb
Host smart-87c36de6-a3d6-4988-8e15-443ed8b31f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73176
3766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.731763766
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2146587806
Short name T578
Test name
Test status
Simulation time 1195599202 ps
CPU time 14.59 seconds
Started Apr 16 02:56:30 PM PDT 24
Finished Apr 16 02:56:45 PM PDT 24
Peak memory 256156 kb
Host smart-26e74cf6-2f53-478d-bb16-bc7af6e93f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21465
87806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2146587806
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1247812296
Short name T569
Test name
Test status
Simulation time 4423562020 ps
CPU time 312.88 seconds
Started Apr 16 02:56:38 PM PDT 24
Finished Apr 16 03:01:51 PM PDT 24
Peak memory 265500 kb
Host smart-3cdc8684-ddde-413e-8aab-1a5a20963d96
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247812296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1247812296
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2228961394
Short name T220
Test name
Test status
Simulation time 139810621814 ps
CPU time 2097.37 seconds
Started Apr 16 02:56:40 PM PDT 24
Finished Apr 16 03:31:38 PM PDT 24
Peak memory 289492 kb
Host smart-60d43c91-7516-4939-aaa2-03324b6ada70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228961394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2228961394
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2047196123
Short name T622
Test name
Test status
Simulation time 3180804344 ps
CPU time 66.57 seconds
Started Apr 16 02:56:39 PM PDT 24
Finished Apr 16 02:57:46 PM PDT 24
Peak memory 248964 kb
Host smart-2282eab4-b583-46b5-993e-64c2b7618cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20471
96123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2047196123
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1037063272
Short name T59
Test name
Test status
Simulation time 1124902943 ps
CPU time 60.86 seconds
Started Apr 16 02:56:37 PM PDT 24
Finished Apr 16 02:57:39 PM PDT 24
Peak memory 255624 kb
Host smart-3ee9ae4c-8879-470a-b456-ff2392688ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
63272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1037063272
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3695650413
Short name T376
Test name
Test status
Simulation time 55965739413 ps
CPU time 1701.36 seconds
Started Apr 16 02:56:40 PM PDT 24
Finished Apr 16 03:25:02 PM PDT 24
Peak memory 272736 kb
Host smart-dbaf0179-0277-4789-ad45-ffaa4f8d0c82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695650413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3695650413
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1332628356
Short name T325
Test name
Test status
Simulation time 129301841760 ps
CPU time 406.28 seconds
Started Apr 16 02:56:39 PM PDT 24
Finished Apr 16 03:03:26 PM PDT 24
Peak memory 248112 kb
Host smart-a0431ef9-1ba7-4914-9b83-611ba45d71a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332628356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1332628356
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2124415614
Short name T402
Test name
Test status
Simulation time 263671660 ps
CPU time 15.3 seconds
Started Apr 16 02:56:35 PM PDT 24
Finished Apr 16 02:56:51 PM PDT 24
Peak memory 255468 kb
Host smart-9b2cfb3a-86db-472a-9da7-4674b4de5509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21244
15614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2124415614
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.584607438
Short name T705
Test name
Test status
Simulation time 681155651 ps
CPU time 45.28 seconds
Started Apr 16 02:56:36 PM PDT 24
Finished Apr 16 02:57:22 PM PDT 24
Peak memory 256116 kb
Host smart-8f1d9162-23bd-4faf-98de-985884dfc124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58460
7438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.584607438
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.215951520
Short name T554
Test name
Test status
Simulation time 485835377 ps
CPU time 33.17 seconds
Started Apr 16 02:56:36 PM PDT 24
Finished Apr 16 02:57:10 PM PDT 24
Peak memory 249056 kb
Host smart-c0d955d1-c321-4251-8d56-23d182db1040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21595
1520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.215951520
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.225825611
Short name T160
Test name
Test status
Simulation time 276555623382 ps
CPU time 3713.71 seconds
Started Apr 16 02:56:40 PM PDT 24
Finished Apr 16 03:58:35 PM PDT 24
Peak memory 290232 kb
Host smart-98cfeaec-f8d3-4505-b890-93ee51c99d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225825611 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.225825611
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.33120926
Short name T449
Test name
Test status
Simulation time 77787056605 ps
CPU time 1081.54 seconds
Started Apr 16 02:56:49 PM PDT 24
Finished Apr 16 03:14:52 PM PDT 24
Peak memory 285020 kb
Host smart-8f1afb0a-46c0-4656-9179-9e86b0042b75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33120926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.33120926
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3406574077
Short name T189
Test name
Test status
Simulation time 18025385240 ps
CPU time 249.65 seconds
Started Apr 16 02:56:42 PM PDT 24
Finished Apr 16 03:00:52 PM PDT 24
Peak memory 257024 kb
Host smart-aca11d66-9e60-405b-86bc-0b894d92ec4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34065
74077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3406574077
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3083882923
Short name T575
Test name
Test status
Simulation time 1216586798 ps
CPU time 53.98 seconds
Started Apr 16 02:56:42 PM PDT 24
Finished Apr 16 02:57:37 PM PDT 24
Peak memory 255920 kb
Host smart-8074c038-b1ea-45b0-ad31-83a833dfd5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30838
82923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3083882923
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1135773485
Short name T370
Test name
Test status
Simulation time 153329386646 ps
CPU time 1872.41 seconds
Started Apr 16 02:56:49 PM PDT 24
Finished Apr 16 03:28:02 PM PDT 24
Peak memory 281908 kb
Host smart-93e86743-9348-46e0-b687-2eefb8220060
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135773485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1135773485
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3902711647
Short name T311
Test name
Test status
Simulation time 11574687736 ps
CPU time 239.95 seconds
Started Apr 16 02:56:49 PM PDT 24
Finished Apr 16 03:00:50 PM PDT 24
Peak memory 248520 kb
Host smart-f2fc37d0-73ae-441c-b76d-1cd89733f725
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902711647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3902711647
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.4002555625
Short name T18
Test name
Test status
Simulation time 1415954960 ps
CPU time 27.68 seconds
Started Apr 16 02:56:43 PM PDT 24
Finished Apr 16 02:57:11 PM PDT 24
Peak memory 249188 kb
Host smart-51a7277d-1875-42f8-946d-db335c3f8e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40025
55625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.4002555625
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.870124651
Short name T438
Test name
Test status
Simulation time 1359915816 ps
CPU time 74.43 seconds
Started Apr 16 02:56:42 PM PDT 24
Finished Apr 16 02:57:57 PM PDT 24
Peak memory 255776 kb
Host smart-7268948c-2e6b-425e-a3cf-c43f0b287352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87012
4651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.870124651
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1519467268
Short name T493
Test name
Test status
Simulation time 3752354048 ps
CPU time 48.64 seconds
Started Apr 16 02:56:43 PM PDT 24
Finished Apr 16 02:57:32 PM PDT 24
Peak memory 249112 kb
Host smart-d0bac7a0-05bc-4d17-b229-c782bacaf6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15194
67268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1519467268
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3549682698
Short name T465
Test name
Test status
Simulation time 2392184735 ps
CPU time 65.21 seconds
Started Apr 16 02:56:42 PM PDT 24
Finished Apr 16 02:57:48 PM PDT 24
Peak memory 256512 kb
Host smart-33f87234-7a60-4257-9e5b-89be05819eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35496
82698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3549682698
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.4102201744
Short name T488
Test name
Test status
Simulation time 3095723256 ps
CPU time 129.53 seconds
Started Apr 16 02:56:48 PM PDT 24
Finished Apr 16 02:58:59 PM PDT 24
Peak memory 257368 kb
Host smart-85213eaa-a1c7-459a-8d2a-0771f9948ffd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102201744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.4102201744
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1844699353
Short name T594
Test name
Test status
Simulation time 29907167689 ps
CPU time 1765.3 seconds
Started Apr 16 02:56:52 PM PDT 24
Finished Apr 16 03:26:18 PM PDT 24
Peak memory 281960 kb
Host smart-b07f7343-6daf-44fd-9d5d-eafba59e69f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844699353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1844699353
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2182222037
Short name T407
Test name
Test status
Simulation time 771249041 ps
CPU time 63.17 seconds
Started Apr 16 02:56:49 PM PDT 24
Finished Apr 16 02:57:54 PM PDT 24
Peak memory 248716 kb
Host smart-01aa3b43-d70f-4381-ac3b-340942caf9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21822
22037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2182222037
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.38611141
Short name T689
Test name
Test status
Simulation time 1144134472 ps
CPU time 72.36 seconds
Started Apr 16 02:56:51 PM PDT 24
Finished Apr 16 02:58:04 PM PDT 24
Peak memory 255688 kb
Host smart-c5c4c4b2-9d72-455c-873b-208585fcf7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38611
141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.38611141
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.7591971
Short name T298
Test name
Test status
Simulation time 51822987027 ps
CPU time 1512.1 seconds
Started Apr 16 02:56:52 PM PDT 24
Finished Apr 16 03:22:05 PM PDT 24
Peak memory 270668 kb
Host smart-9ac77c17-39bb-48a0-ade7-f765c3bd7712
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7591971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.7591971
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3667607066
Short name T659
Test name
Test status
Simulation time 23651436883 ps
CPU time 1330.93 seconds
Started Apr 16 02:56:54 PM PDT 24
Finished Apr 16 03:19:06 PM PDT 24
Peak memory 273736 kb
Host smart-f6a6b4c7-36ba-4457-9378-36d121f4c6de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667607066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3667607066
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.531932990
Short name T516
Test name
Test status
Simulation time 798316712 ps
CPU time 37.23 seconds
Started Apr 16 02:56:48 PM PDT 24
Finished Apr 16 02:57:26 PM PDT 24
Peak memory 249000 kb
Host smart-bbb884c5-6f8e-48a6-b103-7c436824ed32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53193
2990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.531932990
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1596246779
Short name T377
Test name
Test status
Simulation time 1012178184 ps
CPU time 53.78 seconds
Started Apr 16 02:56:47 PM PDT 24
Finished Apr 16 02:57:41 PM PDT 24
Peak memory 255540 kb
Host smart-f34364fe-5fbd-4285-a9b3-dfe3dd93a4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15962
46779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1596246779
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1793918431
Short name T572
Test name
Test status
Simulation time 210702949 ps
CPU time 21.57 seconds
Started Apr 16 02:56:53 PM PDT 24
Finished Apr 16 02:57:15 PM PDT 24
Peak memory 256168 kb
Host smart-20f8eb18-7a51-4a1d-93d7-3c7ed05e774f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17939
18431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1793918431
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2436386007
Short name T375
Test name
Test status
Simulation time 45468275 ps
CPU time 5.11 seconds
Started Apr 16 02:56:49 PM PDT 24
Finished Apr 16 02:56:55 PM PDT 24
Peak memory 249040 kb
Host smart-8109c360-bad4-4a53-801d-3e63df91b820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24363
86007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2436386007
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2192716364
Short name T422
Test name
Test status
Simulation time 127147648983 ps
CPU time 1910.1 seconds
Started Apr 16 02:57:02 PM PDT 24
Finished Apr 16 03:28:53 PM PDT 24
Peak memory 267860 kb
Host smart-983c3608-35d7-4893-8763-c4f0062fef74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192716364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2192716364
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.59249469
Short name T397
Test name
Test status
Simulation time 3444778270 ps
CPU time 137.25 seconds
Started Apr 16 02:56:57 PM PDT 24
Finished Apr 16 02:59:15 PM PDT 24
Peak memory 256928 kb
Host smart-d4384423-57bd-467c-8bd7-00b76deedb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59249
469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.59249469
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.146491148
Short name T621
Test name
Test status
Simulation time 505094154 ps
CPU time 9.64 seconds
Started Apr 16 02:56:56 PM PDT 24
Finished Apr 16 02:57:06 PM PDT 24
Peak memory 252952 kb
Host smart-10848891-35d3-493d-9aa1-46bbef007dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14649
1148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.146491148
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3274645006
Short name T702
Test name
Test status
Simulation time 62733340141 ps
CPU time 1726.08 seconds
Started Apr 16 02:56:58 PM PDT 24
Finished Apr 16 03:25:44 PM PDT 24
Peak memory 283884 kb
Host smart-193c0e56-fecd-4f62-aff6-dc31da38c95d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274645006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3274645006
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3130024090
Short name T31
Test name
Test status
Simulation time 10496641642 ps
CPU time 1027.81 seconds
Started Apr 16 02:57:01 PM PDT 24
Finished Apr 16 03:14:10 PM PDT 24
Peak memory 281816 kb
Host smart-2b97de3f-8092-49b5-a4ed-6811abd5bfdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130024090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3130024090
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2054110358
Short name T320
Test name
Test status
Simulation time 45301118841 ps
CPU time 467.64 seconds
Started Apr 16 02:57:00 PM PDT 24
Finished Apr 16 03:04:49 PM PDT 24
Peak memory 247124 kb
Host smart-a8cfc97e-9977-47f4-9b13-dba483cd63d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054110358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2054110358
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1800186413
Short name T39
Test name
Test status
Simulation time 396478374 ps
CPU time 28.9 seconds
Started Apr 16 02:56:50 PM PDT 24
Finished Apr 16 02:57:20 PM PDT 24
Peak memory 255972 kb
Host smart-27495b65-5cd5-496f-96cf-2425363d4a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18001
86413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1800186413
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1037240434
Short name T656
Test name
Test status
Simulation time 382869365 ps
CPU time 17.17 seconds
Started Apr 16 02:56:56 PM PDT 24
Finished Apr 16 02:57:14 PM PDT 24
Peak memory 255592 kb
Host smart-12bd3c42-4a57-494d-90a7-a467df71074d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10372
40434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1037240434
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3146920354
Short name T546
Test name
Test status
Simulation time 1790842033 ps
CPU time 60.45 seconds
Started Apr 16 02:57:00 PM PDT 24
Finished Apr 16 02:58:00 PM PDT 24
Peak memory 255604 kb
Host smart-419b8b91-7ba7-4005-8126-35247b2a4b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31469
20354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3146920354
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.607464782
Short name T661
Test name
Test status
Simulation time 1445410513 ps
CPU time 41.45 seconds
Started Apr 16 02:56:49 PM PDT 24
Finished Apr 16 02:57:32 PM PDT 24
Peak memory 249000 kb
Host smart-228fb026-cbf2-4e6a-a7d0-cd4a310f98dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60746
4782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.607464782
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3631132110
Short name T605
Test name
Test status
Simulation time 28923396341 ps
CPU time 1791.97 seconds
Started Apr 16 02:57:01 PM PDT 24
Finished Apr 16 03:26:53 PM PDT 24
Peak memory 290104 kb
Host smart-b1b5c536-3db5-47ea-8dbe-511c66ed5e16
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631132110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3631132110
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.4196332883
Short name T691
Test name
Test status
Simulation time 19547054836 ps
CPU time 1092.78 seconds
Started Apr 16 02:57:10 PM PDT 24
Finished Apr 16 03:15:24 PM PDT 24
Peak memory 289524 kb
Host smart-871ed5f2-7c25-49c5-b524-f831cf8a0be0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196332883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.4196332883
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1859325770
Short name T391
Test name
Test status
Simulation time 137095123 ps
CPU time 3.76 seconds
Started Apr 16 02:57:05 PM PDT 24
Finished Apr 16 02:57:09 PM PDT 24
Peak memory 239336 kb
Host smart-0255885e-1243-4433-9496-4638067e1198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18593
25770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1859325770
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1838521913
Short name T651
Test name
Test status
Simulation time 131394286 ps
CPU time 14.97 seconds
Started Apr 16 02:57:04 PM PDT 24
Finished Apr 16 02:57:19 PM PDT 24
Peak memory 249084 kb
Host smart-7786f19c-d75d-42e7-bd97-4a40e481aef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18385
21913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1838521913
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3628744747
Short name T655
Test name
Test status
Simulation time 5935933677 ps
CPU time 606.3 seconds
Started Apr 16 02:57:12 PM PDT 24
Finished Apr 16 03:07:19 PM PDT 24
Peak memory 265692 kb
Host smart-8f63bb88-7ed2-4b90-bec1-04469738a2dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628744747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3628744747
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2567508778
Short name T560
Test name
Test status
Simulation time 40526185109 ps
CPU time 2273.63 seconds
Started Apr 16 02:57:11 PM PDT 24
Finished Apr 16 03:35:05 PM PDT 24
Peak memory 289448 kb
Host smart-4630b16b-eada-49aa-a7d0-190f61d7a936
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567508778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2567508778
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3463532544
Short name T645
Test name
Test status
Simulation time 1296457694 ps
CPU time 31.53 seconds
Started Apr 16 02:57:03 PM PDT 24
Finished Apr 16 02:57:35 PM PDT 24
Peak memory 249044 kb
Host smart-4590fe9a-df0a-489e-9821-a8b3b356ab4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34635
32544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3463532544
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.459324309
Short name T46
Test name
Test status
Simulation time 527528088 ps
CPU time 36.07 seconds
Started Apr 16 02:57:07 PM PDT 24
Finished Apr 16 02:57:43 PM PDT 24
Peak memory 249012 kb
Host smart-f55cecc3-9511-4fe7-b51c-1e963ee51809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45932
4309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.459324309
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2714729637
Short name T631
Test name
Test status
Simulation time 435885231 ps
CPU time 25.73 seconds
Started Apr 16 02:57:14 PM PDT 24
Finished Apr 16 02:57:40 PM PDT 24
Peak memory 249052 kb
Host smart-3ad75a61-be3c-4154-81f9-9832c1123bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27147
29637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2714729637
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3112190970
Short name T411
Test name
Test status
Simulation time 236765612 ps
CPU time 15 seconds
Started Apr 16 02:57:05 PM PDT 24
Finished Apr 16 02:57:20 PM PDT 24
Peak memory 249288 kb
Host smart-3870efe9-ed27-469f-a311-9407f6d676ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31121
90970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3112190970
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2146179670
Short name T164
Test name
Test status
Simulation time 47666506059 ps
CPU time 4640.94 seconds
Started Apr 16 02:57:16 PM PDT 24
Finished Apr 16 04:14:39 PM PDT 24
Peak memory 322712 kb
Host smart-51757ed3-36ab-43b4-b5fd-04c45313d4c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146179670 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2146179670
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.897523289
Short name T201
Test name
Test status
Simulation time 23984646 ps
CPU time 2.37 seconds
Started Apr 16 02:54:53 PM PDT 24
Finished Apr 16 02:54:57 PM PDT 24
Peak memory 249284 kb
Host smart-24c5a420-d7eb-4f7a-9f30-ba52d9d3d41d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=897523289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.897523289
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1815731711
Short name T170
Test name
Test status
Simulation time 83564167981 ps
CPU time 1570.92 seconds
Started Apr 16 02:54:50 PM PDT 24
Finished Apr 16 03:21:03 PM PDT 24
Peak memory 273736 kb
Host smart-a2f58648-0215-4c8d-9462-317fd55d730f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815731711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1815731711
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3122920246
Short name T365
Test name
Test status
Simulation time 584448832 ps
CPU time 8.45 seconds
Started Apr 16 02:54:54 PM PDT 24
Finished Apr 16 02:55:04 PM PDT 24
Peak memory 240824 kb
Host smart-8ee19a73-bb48-4a5e-a82d-284d0227b076
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3122920246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3122920246
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2453869731
Short name T37
Test name
Test status
Simulation time 343057479 ps
CPU time 15.52 seconds
Started Apr 16 02:54:50 PM PDT 24
Finished Apr 16 02:55:07 PM PDT 24
Peak memory 256844 kb
Host smart-94530274-da06-4ebf-bbe9-e41433608978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24538
69731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2453869731
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1703062130
Short name T461
Test name
Test status
Simulation time 634525480 ps
CPU time 39.73 seconds
Started Apr 16 02:54:49 PM PDT 24
Finished Apr 16 02:55:30 PM PDT 24
Peak memory 255560 kb
Host smart-a5183115-7c58-4298-9c98-dd1b0c4e885f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17030
62130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1703062130
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.4237608034
Short name T347
Test name
Test status
Simulation time 64013848321 ps
CPU time 1871.87 seconds
Started Apr 16 02:54:51 PM PDT 24
Finished Apr 16 03:26:04 PM PDT 24
Peak memory 273696 kb
Host smart-b99e3b6a-2594-4bef-80b6-fb4f56e0a003
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237608034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.4237608034
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2012699169
Short name T533
Test name
Test status
Simulation time 50352074352 ps
CPU time 3145.38 seconds
Started Apr 16 02:54:49 PM PDT 24
Finished Apr 16 03:47:17 PM PDT 24
Peak memory 289392 kb
Host smart-d6f6467d-689f-4894-a1a8-9dbfbdd0f570
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012699169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2012699169
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1369273095
Short name T331
Test name
Test status
Simulation time 22085873628 ps
CPU time 446.85 seconds
Started Apr 16 02:54:51 PM PDT 24
Finished Apr 16 03:02:20 PM PDT 24
Peak memory 247268 kb
Host smart-3f07a45e-26b5-4678-82d1-5e39d7e480d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369273095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1369273095
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2951075710
Short name T369
Test name
Test status
Simulation time 275148841 ps
CPU time 8.3 seconds
Started Apr 16 02:54:50 PM PDT 24
Finished Apr 16 02:55:00 PM PDT 24
Peak memory 249012 kb
Host smart-2f870fa3-a36f-45ec-af61-7bfff41e465d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29510
75710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2951075710
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2643472257
Short name T427
Test name
Test status
Simulation time 330483725 ps
CPU time 27.43 seconds
Started Apr 16 02:54:52 PM PDT 24
Finished Apr 16 02:55:20 PM PDT 24
Peak memory 248980 kb
Host smart-d6a56142-d991-45b9-9eea-801f680ae919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26434
72257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2643472257
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.4022470366
Short name T13
Test name
Test status
Simulation time 349396137 ps
CPU time 12.41 seconds
Started Apr 16 02:54:51 PM PDT 24
Finished Apr 16 02:55:05 PM PDT 24
Peak memory 274660 kb
Host smart-a1aac8ac-5769-44b4-b482-5d11517ebcb4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4022470366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.4022470366
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2922711975
Short name T502
Test name
Test status
Simulation time 3210557634 ps
CPU time 48.96 seconds
Started Apr 16 02:54:50 PM PDT 24
Finished Apr 16 02:55:40 PM PDT 24
Peak memory 249164 kb
Host smart-d0f3257a-7f01-42e3-8e60-c27ffb465116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29227
11975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2922711975
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2454547979
Short name T471
Test name
Test status
Simulation time 157238121 ps
CPU time 6.03 seconds
Started Apr 16 02:54:50 PM PDT 24
Finished Apr 16 02:54:58 PM PDT 24
Peak memory 251252 kb
Host smart-57e7bb4b-b499-4f43-a331-66c945180b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24545
47979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2454547979
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.457530465
Short name T366
Test name
Test status
Simulation time 14668062324 ps
CPU time 87.22 seconds
Started Apr 16 02:54:56 PM PDT 24
Finished Apr 16 02:56:25 PM PDT 24
Peak memory 250580 kb
Host smart-e59f6f8b-6fcc-4ad5-b2e0-7570d96cc5ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457530465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.457530465
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1883911327
Short name T626
Test name
Test status
Simulation time 102041350471 ps
CPU time 5028.39 seconds
Started Apr 16 02:54:54 PM PDT 24
Finished Apr 16 04:18:44 PM PDT 24
Peak memory 371448 kb
Host smart-4651fe32-4410-4320-b6a2-04565a78babe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883911327 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1883911327
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2957553678
Short name T430
Test name
Test status
Simulation time 34936862987 ps
CPU time 2165.33 seconds
Started Apr 16 02:57:15 PM PDT 24
Finished Apr 16 03:33:22 PM PDT 24
Peak memory 289528 kb
Host smart-55cb6428-4501-4d8a-a9e4-0b0ee557c1e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957553678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2957553678
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.592287940
Short name T280
Test name
Test status
Simulation time 2065849926 ps
CPU time 122.26 seconds
Started Apr 16 02:57:16 PM PDT 24
Finished Apr 16 02:59:19 PM PDT 24
Peak memory 248796 kb
Host smart-38c53b67-7b02-4968-95e7-556b17795a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59228
7940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.592287940
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3703111546
Short name T227
Test name
Test status
Simulation time 7922964028 ps
CPU time 44.53 seconds
Started Apr 16 02:57:13 PM PDT 24
Finished Apr 16 02:57:58 PM PDT 24
Peak memory 249168 kb
Host smart-4707953b-6f2c-424f-b705-02666b667a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37031
11546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3703111546
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1456918189
Short name T335
Test name
Test status
Simulation time 60780226609 ps
CPU time 1418.85 seconds
Started Apr 16 02:57:16 PM PDT 24
Finished Apr 16 03:20:55 PM PDT 24
Peak memory 289176 kb
Host smart-212345d8-c15d-4ea5-813a-8247afa5364a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456918189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1456918189
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2945495046
Short name T98
Test name
Test status
Simulation time 15278756915 ps
CPU time 713.87 seconds
Started Apr 16 02:57:14 PM PDT 24
Finished Apr 16 03:09:09 PM PDT 24
Peak memory 266512 kb
Host smart-0264b9ae-b4eb-4465-ac20-eb4ac1d26a06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945495046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2945495046
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1157716243
Short name T312
Test name
Test status
Simulation time 34491354365 ps
CPU time 332.94 seconds
Started Apr 16 02:57:17 PM PDT 24
Finished Apr 16 03:02:51 PM PDT 24
Peak memory 248328 kb
Host smart-db24c3d0-2516-49e4-8fd9-6609dc80fb22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157716243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1157716243
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.952475541
Short name T371
Test name
Test status
Simulation time 1105796889 ps
CPU time 63.57 seconds
Started Apr 16 02:57:17 PM PDT 24
Finished Apr 16 02:58:21 PM PDT 24
Peak memory 256240 kb
Host smart-34deaa1f-79b6-45fc-907e-b5575b369b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95247
5541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.952475541
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3754956780
Short name T479
Test name
Test status
Simulation time 725821015 ps
CPU time 14.03 seconds
Started Apr 16 02:57:15 PM PDT 24
Finished Apr 16 02:57:29 PM PDT 24
Peak memory 253772 kb
Host smart-ad70d0ae-61c5-444f-90c9-9aa4d03eeb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37549
56780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3754956780
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.131960769
Short name T490
Test name
Test status
Simulation time 1312813884 ps
CPU time 21.8 seconds
Started Apr 16 02:57:16 PM PDT 24
Finished Apr 16 02:57:38 PM PDT 24
Peak memory 255616 kb
Host smart-3025028a-5257-42fe-ae0e-503928169e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13196
0769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.131960769
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2274070978
Short name T474
Test name
Test status
Simulation time 725690790 ps
CPU time 9.77 seconds
Started Apr 16 02:57:13 PM PDT 24
Finished Apr 16 02:57:24 PM PDT 24
Peak memory 252764 kb
Host smart-ae2d2b28-33ca-40ac-876b-619c0bd6313c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22740
70978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2274070978
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1792488337
Short name T66
Test name
Test status
Simulation time 819797124 ps
CPU time 68.37 seconds
Started Apr 16 02:57:22 PM PDT 24
Finished Apr 16 02:58:31 PM PDT 24
Peak memory 249008 kb
Host smart-1d31e676-6a4c-4a5d-98af-c8d0587b59cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792488337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1792488337
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1129926447
Short name T74
Test name
Test status
Simulation time 66758420336 ps
CPU time 1328.55 seconds
Started Apr 16 02:57:24 PM PDT 24
Finished Apr 16 03:19:33 PM PDT 24
Peak memory 289392 kb
Host smart-786ea0e4-ffbd-4e09-9c22-2b908a446d9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129926447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1129926447
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1581238522
Short name T599
Test name
Test status
Simulation time 1388047230 ps
CPU time 75.3 seconds
Started Apr 16 02:57:20 PM PDT 24
Finished Apr 16 02:58:36 PM PDT 24
Peak memory 256984 kb
Host smart-feef2502-6ad7-4a7c-80b6-e546b28584c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15812
38522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1581238522
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2318198787
Short name T629
Test name
Test status
Simulation time 468002218 ps
CPU time 17.18 seconds
Started Apr 16 02:57:22 PM PDT 24
Finished Apr 16 02:57:39 PM PDT 24
Peak memory 255396 kb
Host smart-14621a4c-2f5b-4f50-bcdb-e603849daad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23181
98787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2318198787
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1306252906
Short name T294
Test name
Test status
Simulation time 165111187238 ps
CPU time 2520.43 seconds
Started Apr 16 02:57:23 PM PDT 24
Finished Apr 16 03:39:25 PM PDT 24
Peak memory 289268 kb
Host smart-634684c5-4105-40bf-b20d-5c2e001e7708
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306252906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1306252906
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.706595691
Short name T414
Test name
Test status
Simulation time 6747783142 ps
CPU time 715.51 seconds
Started Apr 16 02:57:28 PM PDT 24
Finished Apr 16 03:09:24 PM PDT 24
Peak memory 272824 kb
Host smart-ed386dde-9b52-4d83-80ba-6c9c29883ec2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706595691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.706595691
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1985791927
Short name T494
Test name
Test status
Simulation time 435239228 ps
CPU time 11.58 seconds
Started Apr 16 02:57:23 PM PDT 24
Finished Apr 16 02:57:35 PM PDT 24
Peak memory 248988 kb
Host smart-a96a8318-7fdf-477d-a46b-39aa01e9ae0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19857
91927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1985791927
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3732924086
Short name T25
Test name
Test status
Simulation time 270478681 ps
CPU time 26.52 seconds
Started Apr 16 02:57:20 PM PDT 24
Finished Apr 16 02:57:47 PM PDT 24
Peak memory 247404 kb
Host smart-23a5fa2a-7a46-4c00-8242-d01203e1a1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37329
24086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3732924086
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.560114367
Short name T487
Test name
Test status
Simulation time 3167652411 ps
CPU time 16.68 seconds
Started Apr 16 02:57:24 PM PDT 24
Finished Apr 16 02:57:42 PM PDT 24
Peak memory 249112 kb
Host smart-e5832205-f3c9-4656-9ec0-1e19d237a974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56011
4367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.560114367
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1146797004
Short name T36
Test name
Test status
Simulation time 30319548 ps
CPU time 3.76 seconds
Started Apr 16 02:57:21 PM PDT 24
Finished Apr 16 02:57:25 PM PDT 24
Peak memory 240844 kb
Host smart-f7029eaf-af67-475c-9cf6-0aff7ca03161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11467
97004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1146797004
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.427749732
Short name T165
Test name
Test status
Simulation time 51465727634 ps
CPU time 2668.32 seconds
Started Apr 16 02:57:30 PM PDT 24
Finished Apr 16 03:41:59 PM PDT 24
Peak memory 289416 kb
Host smart-98ef254c-4ee6-4d4d-b76d-794137da757d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427749732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.427749732
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2375290998
Short name T225
Test name
Test status
Simulation time 17671170006 ps
CPU time 1185.59 seconds
Started Apr 16 02:57:28 PM PDT 24
Finished Apr 16 03:17:15 PM PDT 24
Peak memory 271932 kb
Host smart-fd0fdf17-f5a8-477c-9084-f2979c77b65f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375290998 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2375290998
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.639541093
Short name T215
Test name
Test status
Simulation time 51605402044 ps
CPU time 641.57 seconds
Started Apr 16 02:57:32 PM PDT 24
Finished Apr 16 03:08:15 PM PDT 24
Peak memory 272764 kb
Host smart-2defb11c-81d1-48eb-81ab-7ff6a375a0c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639541093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.639541093
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2337356707
Short name T602
Test name
Test status
Simulation time 937497426 ps
CPU time 23.76 seconds
Started Apr 16 02:57:31 PM PDT 24
Finished Apr 16 02:57:55 PM PDT 24
Peak memory 256252 kb
Host smart-0159d7ac-700b-4506-bda6-c4416db4ec94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23373
56707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2337356707
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1337767060
Short name T563
Test name
Test status
Simulation time 1301860216 ps
CPU time 69.65 seconds
Started Apr 16 02:57:28 PM PDT 24
Finished Apr 16 02:58:38 PM PDT 24
Peak memory 255064 kb
Host smart-b59c0268-7999-467d-9723-887e3229f4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13377
67060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1337767060
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1879604342
Short name T342
Test name
Test status
Simulation time 60933889197 ps
CPU time 1602.7 seconds
Started Apr 16 02:57:33 PM PDT 24
Finished Apr 16 03:24:17 PM PDT 24
Peak memory 265584 kb
Host smart-ce613c5a-dcd8-4c2f-a631-dc8fc1d8d757
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879604342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1879604342
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2352535873
Short name T69
Test name
Test status
Simulation time 54201189026 ps
CPU time 1394.13 seconds
Started Apr 16 02:57:30 PM PDT 24
Finished Apr 16 03:20:45 PM PDT 24
Peak memory 281488 kb
Host smart-55285baf-52f7-4e7f-a503-1bb07e0b4251
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352535873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2352535873
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.263296982
Short name T525
Test name
Test status
Simulation time 4311391964 ps
CPU time 176.42 seconds
Started Apr 16 02:57:34 PM PDT 24
Finished Apr 16 03:00:31 PM PDT 24
Peak memory 248392 kb
Host smart-b9cc6c30-28ca-4346-b668-ea561c519c22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263296982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.263296982
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3184076379
Short name T635
Test name
Test status
Simulation time 1846532924 ps
CPU time 10.11 seconds
Started Apr 16 02:57:27 PM PDT 24
Finished Apr 16 02:57:38 PM PDT 24
Peak memory 249036 kb
Host smart-5965f930-5acc-4013-baab-1b71433ea6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31840
76379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3184076379
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1998554117
Short name T58
Test name
Test status
Simulation time 973434774 ps
CPU time 15.74 seconds
Started Apr 16 02:57:26 PM PDT 24
Finished Apr 16 02:57:42 PM PDT 24
Peak memory 253972 kb
Host smart-1c84e82a-e2f6-44e8-bf2d-d520030cc7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19985
54117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1998554117
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.811831922
Short name T213
Test name
Test status
Simulation time 1306321914 ps
CPU time 67.82 seconds
Started Apr 16 02:57:29 PM PDT 24
Finished Apr 16 02:58:38 PM PDT 24
Peak memory 249064 kb
Host smart-c42c6f03-c2f9-42e6-9dcf-eb125bf4f691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81183
1922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.811831922
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.2519919906
Short name T68
Test name
Test status
Simulation time 99102248103 ps
CPU time 1660.71 seconds
Started Apr 16 02:57:36 PM PDT 24
Finished Apr 16 03:25:18 PM PDT 24
Peak memory 283192 kb
Host smart-7ee7747b-9f0d-4d33-beea-bdda36b28146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519919906 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.2519919906
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.615719952
Short name T675
Test name
Test status
Simulation time 22884358303 ps
CPU time 1389.08 seconds
Started Apr 16 02:57:47 PM PDT 24
Finished Apr 16 03:20:57 PM PDT 24
Peak memory 271872 kb
Host smart-f00dd44f-1132-4cd1-9f87-9e84d2506365
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615719952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.615719952
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3255650946
Short name T685
Test name
Test status
Simulation time 37827186158 ps
CPU time 162.87 seconds
Started Apr 16 02:57:38 PM PDT 24
Finished Apr 16 03:00:22 PM PDT 24
Peak memory 249152 kb
Host smart-e3b7b64e-802c-4c8b-9b6c-8ec66d5fc805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32556
50946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3255650946
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.4270468449
Short name T72
Test name
Test status
Simulation time 2103197936 ps
CPU time 58.58 seconds
Started Apr 16 02:57:42 PM PDT 24
Finished Apr 16 02:58:41 PM PDT 24
Peak memory 249292 kb
Host smart-f981e54e-92a0-4b31-846a-47b50d4ed151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42704
68449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.4270468449
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2898744096
Short name T550
Test name
Test status
Simulation time 16183747753 ps
CPU time 675.13 seconds
Started Apr 16 02:57:45 PM PDT 24
Finished Apr 16 03:09:01 PM PDT 24
Peak memory 273324 kb
Host smart-dc3d3ecf-d099-4d23-8d2b-5387b9af1d9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898744096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2898744096
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.594997665
Short name T381
Test name
Test status
Simulation time 143218616025 ps
CPU time 1821.64 seconds
Started Apr 16 02:57:46 PM PDT 24
Finished Apr 16 03:28:08 PM PDT 24
Peak memory 273648 kb
Host smart-97cfd456-1584-4437-b102-583d67cdf19d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594997665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.594997665
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3990086229
Short name T667
Test name
Test status
Simulation time 70541182684 ps
CPU time 490.96 seconds
Started Apr 16 02:57:46 PM PDT 24
Finished Apr 16 03:05:58 PM PDT 24
Peak memory 248048 kb
Host smart-e7bf12ac-25a6-42d2-8b79-42d802ca07cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990086229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3990086229
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.607496251
Short name T274
Test name
Test status
Simulation time 178208873 ps
CPU time 6.53 seconds
Started Apr 16 02:57:41 PM PDT 24
Finished Apr 16 02:57:49 PM PDT 24
Peak memory 249088 kb
Host smart-d4fc4e9c-3a7b-44b1-8996-0b61521f0554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60749
6251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.607496251
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3200887015
Short name T368
Test name
Test status
Simulation time 228217797 ps
CPU time 19.16 seconds
Started Apr 16 02:57:42 PM PDT 24
Finished Apr 16 02:58:02 PM PDT 24
Peak memory 249048 kb
Host smart-e9b4a34d-7dcc-4fb9-b74d-1251a91f1805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32008
87015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3200887015
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.310353310
Short name T219
Test name
Test status
Simulation time 1017671706 ps
CPU time 12.88 seconds
Started Apr 16 02:57:41 PM PDT 24
Finished Apr 16 02:57:54 PM PDT 24
Peak memory 254564 kb
Host smart-3c42d90e-255b-419a-ab4d-d650b6f4a8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31035
3310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.310353310
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2079784351
Short name T410
Test name
Test status
Simulation time 798782901 ps
CPU time 31.32 seconds
Started Apr 16 02:57:38 PM PDT 24
Finished Apr 16 02:58:10 PM PDT 24
Peak memory 256068 kb
Host smart-7b018f40-e844-402b-ab47-1288d9140c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20797
84351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2079784351
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2631268143
Short name T2
Test name
Test status
Simulation time 22124868094 ps
CPU time 1316.01 seconds
Started Apr 16 02:57:46 PM PDT 24
Finished Apr 16 03:19:42 PM PDT 24
Peak memory 289500 kb
Host smart-8ffa1cf7-17e2-45f4-a781-df7f6d199e13
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631268143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2631268143
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.673177504
Short name T183
Test name
Test status
Simulation time 67726195509 ps
CPU time 1899.28 seconds
Started Apr 16 02:57:53 PM PDT 24
Finished Apr 16 03:29:33 PM PDT 24
Peak memory 283592 kb
Host smart-05132884-b46a-4ff4-9f97-92d958ef1801
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673177504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.673177504
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3646147244
Short name T453
Test name
Test status
Simulation time 6966196802 ps
CPU time 114.35 seconds
Started Apr 16 02:57:52 PM PDT 24
Finished Apr 16 02:59:47 PM PDT 24
Peak memory 256876 kb
Host smart-d52ab4b7-63f3-43bc-aec5-b1a426fc5d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36461
47244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3646147244
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3230544330
Short name T704
Test name
Test status
Simulation time 1686268342 ps
CPU time 16.23 seconds
Started Apr 16 02:57:54 PM PDT 24
Finished Apr 16 02:58:11 PM PDT 24
Peak memory 254672 kb
Host smart-16673866-0328-4cda-a57b-64f323c2bdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32305
44330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3230544330
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2910489211
Short name T700
Test name
Test status
Simulation time 101743114103 ps
CPU time 2110.09 seconds
Started Apr 16 02:57:55 PM PDT 24
Finished Apr 16 03:33:06 PM PDT 24
Peak memory 273412 kb
Host smart-486f4216-8ef5-48e9-b318-3b6fb788ffbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910489211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2910489211
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3599887442
Short name T640
Test name
Test status
Simulation time 65297687684 ps
CPU time 1141.35 seconds
Started Apr 16 02:57:58 PM PDT 24
Finished Apr 16 03:17:01 PM PDT 24
Peak memory 273712 kb
Host smart-4eb36a56-4c0d-4ab7-a529-98bb6a9a4b47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599887442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3599887442
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2750691730
Short name T566
Test name
Test status
Simulation time 6904586813 ps
CPU time 292.84 seconds
Started Apr 16 02:57:54 PM PDT 24
Finished Apr 16 03:02:48 PM PDT 24
Peak memory 255132 kb
Host smart-e17504f9-a77a-47bc-b28c-43aedb52bc1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750691730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2750691730
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3169721821
Short name T543
Test name
Test status
Simulation time 296271554 ps
CPU time 23.86 seconds
Started Apr 16 02:57:49 PM PDT 24
Finished Apr 16 02:58:13 PM PDT 24
Peak memory 249040 kb
Host smart-876cdc2f-ed10-444f-b081-dc6eae9fe0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31697
21821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3169721821
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.65758291
Short name T501
Test name
Test status
Simulation time 228816005 ps
CPU time 17.8 seconds
Started Apr 16 02:57:53 PM PDT 24
Finished Apr 16 02:58:12 PM PDT 24
Peak memory 255652 kb
Host smart-b3d79c95-8bda-4799-9fba-fd5e0f58146d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65758
291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.65758291
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3899755684
Short name T300
Test name
Test status
Simulation time 1280424067 ps
CPU time 35.95 seconds
Started Apr 16 02:57:51 PM PDT 24
Finished Apr 16 02:58:28 PM PDT 24
Peak memory 256124 kb
Host smart-8d6139e5-bf51-44e5-9fe2-491d8a565035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38997
55684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3899755684
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.464666681
Short name T526
Test name
Test status
Simulation time 455054540 ps
CPU time 9 seconds
Started Apr 16 02:57:47 PM PDT 24
Finished Apr 16 02:57:57 PM PDT 24
Peak memory 253208 kb
Host smart-b23ec1cc-14f3-47bd-a16a-09e95e5adbec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46466
6681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.464666681
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.190089025
Short name T408
Test name
Test status
Simulation time 3138714136 ps
CPU time 185.94 seconds
Started Apr 16 02:57:56 PM PDT 24
Finished Apr 16 03:01:03 PM PDT 24
Peak memory 257348 kb
Host smart-9e9f0404-ac96-47c4-b9e4-2b99133c4767
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190089025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.190089025
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1590258994
Short name T82
Test name
Test status
Simulation time 62404126578 ps
CPU time 2056.2 seconds
Started Apr 16 02:57:58 PM PDT 24
Finished Apr 16 03:32:15 PM PDT 24
Peak memory 322208 kb
Host smart-e962e7b5-dfca-42de-ad83-598a9bd6f69d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590258994 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1590258994
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1098733086
Short name T701
Test name
Test status
Simulation time 1390158195 ps
CPU time 84.7 seconds
Started Apr 16 02:57:58 PM PDT 24
Finished Apr 16 02:59:23 PM PDT 24
Peak memory 256952 kb
Host smart-493da7fb-82e1-4bc7-8aa7-56ab93a5ac06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10987
33086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1098733086
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2678122170
Short name T644
Test name
Test status
Simulation time 1160007613 ps
CPU time 34.11 seconds
Started Apr 16 02:57:56 PM PDT 24
Finished Apr 16 02:58:31 PM PDT 24
Peak memory 256076 kb
Host smart-822c3450-103e-48ab-8fdb-bac3c87ae8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26781
22170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2678122170
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1214632496
Short name T343
Test name
Test status
Simulation time 17579194571 ps
CPU time 1407.47 seconds
Started Apr 16 02:58:04 PM PDT 24
Finished Apr 16 03:21:32 PM PDT 24
Peak memory 290016 kb
Host smart-08dd7d22-44f0-4cd6-9826-06542bbd14e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214632496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1214632496
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3561443935
Short name T682
Test name
Test status
Simulation time 36452333568 ps
CPU time 2187.75 seconds
Started Apr 16 02:58:07 PM PDT 24
Finished Apr 16 03:34:36 PM PDT 24
Peak memory 286772 kb
Host smart-4fdca198-2eb0-49f2-865d-301e5de0bde2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561443935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3561443935
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2160687714
Short name T321
Test name
Test status
Simulation time 24498445923 ps
CPU time 495.6 seconds
Started Apr 16 02:58:01 PM PDT 24
Finished Apr 16 03:06:17 PM PDT 24
Peak memory 247392 kb
Host smart-84bfd7b9-666b-4c67-9f7d-b05cdf96f312
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160687714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2160687714
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3188465561
Short name T586
Test name
Test status
Simulation time 637923894 ps
CPU time 18.35 seconds
Started Apr 16 02:57:58 PM PDT 24
Finished Apr 16 02:58:17 PM PDT 24
Peak memory 249024 kb
Host smart-a4dcc941-a960-4801-b188-abaf5312999d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31884
65561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3188465561
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1241932076
Short name T439
Test name
Test status
Simulation time 892129319 ps
CPU time 55.59 seconds
Started Apr 16 02:57:58 PM PDT 24
Finished Apr 16 02:58:54 PM PDT 24
Peak memory 256208 kb
Host smart-19ff4d83-e25a-4bcc-8c46-f2611a2e8cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12419
32076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1241932076
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2856068668
Short name T562
Test name
Test status
Simulation time 286973025 ps
CPU time 20.27 seconds
Started Apr 16 02:58:03 PM PDT 24
Finished Apr 16 02:58:24 PM PDT 24
Peak memory 255308 kb
Host smart-93bac4a5-1e3a-40d2-accd-fa087dc9aa9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28560
68668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2856068668
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2032692477
Short name T17
Test name
Test status
Simulation time 761427647 ps
CPU time 34.1 seconds
Started Apr 16 02:57:57 PM PDT 24
Finished Apr 16 02:58:32 PM PDT 24
Peak memory 249184 kb
Host smart-1e38c4a4-2288-4800-a821-facda0ef10db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20326
92477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2032692477
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3497977515
Short name T577
Test name
Test status
Simulation time 16366440997 ps
CPU time 1638.19 seconds
Started Apr 16 02:58:08 PM PDT 24
Finished Apr 16 03:25:26 PM PDT 24
Peak memory 289572 kb
Host smart-2659c4e5-69b2-4ae8-ab4e-19a30613d015
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497977515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3497977515
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2531342920
Short name T256
Test name
Test status
Simulation time 161700591794 ps
CPU time 1676.01 seconds
Started Apr 16 02:58:07 PM PDT 24
Finished Apr 16 03:26:04 PM PDT 24
Peak memory 287644 kb
Host smart-f2b88f1f-05de-4366-b16c-8db1e8feb4fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531342920 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2531342920
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2747479757
Short name T93
Test name
Test status
Simulation time 46157129210 ps
CPU time 933.17 seconds
Started Apr 16 02:58:12 PM PDT 24
Finished Apr 16 03:13:46 PM PDT 24
Peak memory 281916 kb
Host smart-87fff796-62fd-460c-b47f-714a2aab438e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747479757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2747479757
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3896009306
Short name T383
Test name
Test status
Simulation time 7351799754 ps
CPU time 123.98 seconds
Started Apr 16 02:58:11 PM PDT 24
Finished Apr 16 03:00:15 PM PDT 24
Peak memory 257040 kb
Host smart-57db8576-8c4f-49e2-a579-45450c98113e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38960
09306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3896009306
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3214904825
Short name T683
Test name
Test status
Simulation time 3302517923 ps
CPU time 51.72 seconds
Started Apr 16 02:58:12 PM PDT 24
Finished Apr 16 02:59:04 PM PDT 24
Peak memory 249160 kb
Host smart-359127ab-8b6d-487f-a68d-298c5d1c762e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32149
04825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3214904825
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.859292694
Short name T313
Test name
Test status
Simulation time 36647352152 ps
CPU time 1822.56 seconds
Started Apr 16 02:58:09 PM PDT 24
Finished Apr 16 03:28:33 PM PDT 24
Peak memory 273688 kb
Host smart-68e6c80a-1a25-40d4-8592-d1e728cb169c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859292694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.859292694
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2111623653
Short name T450
Test name
Test status
Simulation time 8872034511 ps
CPU time 918.48 seconds
Started Apr 16 02:58:10 PM PDT 24
Finished Apr 16 03:13:30 PM PDT 24
Peak memory 269612 kb
Host smart-d2a77468-4bb4-4e0d-91c4-1f9678c7da91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111623653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2111623653
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1090086873
Short name T332
Test name
Test status
Simulation time 14513066325 ps
CPU time 581.34 seconds
Started Apr 16 02:58:12 PM PDT 24
Finished Apr 16 03:07:54 PM PDT 24
Peak memory 248076 kb
Host smart-362413f1-e64f-4512-b25f-7e3dce0e2eb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090086873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1090086873
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2603161300
Short name T436
Test name
Test status
Simulation time 18360807666 ps
CPU time 54.28 seconds
Started Apr 16 02:58:07 PM PDT 24
Finished Apr 16 02:59:02 PM PDT 24
Peak memory 256404 kb
Host smart-7f46c9e0-083a-4dcd-bf81-8acb7815b8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26031
61300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2603161300
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2380364625
Short name T603
Test name
Test status
Simulation time 1213453000 ps
CPU time 19.37 seconds
Started Apr 16 02:58:07 PM PDT 24
Finished Apr 16 02:58:27 PM PDT 24
Peak memory 249352 kb
Host smart-bcbc75c6-623d-4f14-9127-83988c526fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23803
64625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2380364625
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3474123607
Short name T44
Test name
Test status
Simulation time 2939239243 ps
CPU time 45.05 seconds
Started Apr 16 02:58:11 PM PDT 24
Finished Apr 16 02:58:56 PM PDT 24
Peak memory 256812 kb
Host smart-30caf874-ef25-4be4-ab77-df02f9939bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34741
23607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3474123607
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2552303184
Short name T206
Test name
Test status
Simulation time 276625569 ps
CPU time 14 seconds
Started Apr 16 02:58:05 PM PDT 24
Finished Apr 16 02:58:19 PM PDT 24
Peak memory 249004 kb
Host smart-8439fc1f-adff-4d6a-a677-95a0f21ec78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25523
03184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2552303184
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2960711311
Short name T91
Test name
Test status
Simulation time 118214413620 ps
CPU time 2086.16 seconds
Started Apr 16 02:58:15 PM PDT 24
Finished Apr 16 03:33:02 PM PDT 24
Peak memory 285040 kb
Host smart-83bec2b9-3b67-4053-a41e-94c9dda9a863
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960711311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2960711311
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.525043995
Short name T162
Test name
Test status
Simulation time 18115213688 ps
CPU time 816.57 seconds
Started Apr 16 02:58:16 PM PDT 24
Finished Apr 16 03:11:53 PM PDT 24
Peak memory 273784 kb
Host smart-d98a3340-2bb2-45a8-8913-afecb1864413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525043995 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.525043995
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1891638753
Short name T553
Test name
Test status
Simulation time 44096441513 ps
CPU time 969.76 seconds
Started Apr 16 02:58:21 PM PDT 24
Finished Apr 16 03:14:31 PM PDT 24
Peak memory 281716 kb
Host smart-ad6d6163-192f-486c-8b98-d7e84a34e76e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891638753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1891638753
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1103858962
Short name T389
Test name
Test status
Simulation time 5356397471 ps
CPU time 99.93 seconds
Started Apr 16 02:58:21 PM PDT 24
Finished Apr 16 03:00:02 PM PDT 24
Peak memory 250212 kb
Host smart-4287d8af-aa98-472f-b2c4-c003b73da707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11038
58962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1103858962
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2719457492
Short name T491
Test name
Test status
Simulation time 628945623 ps
CPU time 29.3 seconds
Started Apr 16 02:58:16 PM PDT 24
Finished Apr 16 02:58:46 PM PDT 24
Peak memory 255548 kb
Host smart-aca6c285-5d9d-473d-ba99-a748c5559216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27194
57492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2719457492
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3587512983
Short name T299
Test name
Test status
Simulation time 11273092111 ps
CPU time 887.46 seconds
Started Apr 16 02:58:19 PM PDT 24
Finished Apr 16 03:13:07 PM PDT 24
Peak memory 273736 kb
Host smart-0ee8b849-066e-4634-95f9-c9a11a749dc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587512983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3587512983
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.397405438
Short name T7
Test name
Test status
Simulation time 20344592139 ps
CPU time 860.36 seconds
Started Apr 16 02:58:27 PM PDT 24
Finished Apr 16 03:12:49 PM PDT 24
Peak memory 273092 kb
Host smart-af6ad269-110e-4d12-a221-ed111c3711b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397405438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.397405438
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.91715755
Short name T512
Test name
Test status
Simulation time 15144262446 ps
CPU time 78.41 seconds
Started Apr 16 02:58:22 PM PDT 24
Finished Apr 16 02:59:41 PM PDT 24
Peak memory 248180 kb
Host smart-68c63735-67fe-4d0e-855d-71e7c3a0c9e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91715755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.91715755
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1572496549
Short name T445
Test name
Test status
Simulation time 1130543871 ps
CPU time 40.04 seconds
Started Apr 16 02:58:16 PM PDT 24
Finished Apr 16 02:58:57 PM PDT 24
Peak memory 249032 kb
Host smart-0f902a03-4be5-4963-ad01-b44dc1c82fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15724
96549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1572496549
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1086925908
Short name T416
Test name
Test status
Simulation time 1837639983 ps
CPU time 39.36 seconds
Started Apr 16 02:58:16 PM PDT 24
Finished Apr 16 02:58:56 PM PDT 24
Peak memory 248700 kb
Host smart-14acafdc-f9ff-4af5-b38c-35eed0c288dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10869
25908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1086925908
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1408117267
Short name T431
Test name
Test status
Simulation time 971363676 ps
CPU time 47.64 seconds
Started Apr 16 02:58:16 PM PDT 24
Finished Apr 16 02:59:04 PM PDT 24
Peak memory 249296 kb
Host smart-25f80987-d712-42bb-91e3-1dc1d7258c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14081
17267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1408117267
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.710740583
Short name T53
Test name
Test status
Simulation time 14046185183 ps
CPU time 1284.79 seconds
Started Apr 16 02:58:24 PM PDT 24
Finished Apr 16 03:19:49 PM PDT 24
Peak memory 289896 kb
Host smart-50d0278b-6732-4d33-ade9-6423f119412d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710740583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.710740583
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.494291806
Short name T301
Test name
Test status
Simulation time 74231841862 ps
CPU time 1291.53 seconds
Started Apr 16 02:58:29 PM PDT 24
Finished Apr 16 03:20:02 PM PDT 24
Peak memory 289548 kb
Host smart-0d1c015f-6db7-435b-b28e-09ef3bf03d8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494291806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.494291806
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.904253599
Short name T476
Test name
Test status
Simulation time 4130301717 ps
CPU time 233.29 seconds
Started Apr 16 02:58:26 PM PDT 24
Finished Apr 16 03:02:20 PM PDT 24
Peak memory 257148 kb
Host smart-d1755cde-3fbf-4be6-abc2-15d265942289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90425
3599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.904253599
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2955728814
Short name T372
Test name
Test status
Simulation time 249498588 ps
CPU time 14.06 seconds
Started Apr 16 02:58:25 PM PDT 24
Finished Apr 16 02:58:40 PM PDT 24
Peak memory 253832 kb
Host smart-4c6af473-5cde-4c20-8dd7-c2394160c444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29557
28814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2955728814
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2169700282
Short name T521
Test name
Test status
Simulation time 46359125374 ps
CPU time 1300.65 seconds
Started Apr 16 02:58:37 PM PDT 24
Finished Apr 16 03:20:19 PM PDT 24
Peak memory 281896 kb
Host smart-eb1bf81b-dbad-462d-8411-e7977b9765b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169700282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2169700282
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2940471978
Short name T318
Test name
Test status
Simulation time 9553340348 ps
CPU time 382.14 seconds
Started Apr 16 02:58:37 PM PDT 24
Finished Apr 16 03:05:00 PM PDT 24
Peak memory 248048 kb
Host smart-3a521473-bb5b-4d97-aa4c-c55c820f3bc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940471978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2940471978
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1475278815
Short name T481
Test name
Test status
Simulation time 599114073 ps
CPU time 36.03 seconds
Started Apr 16 02:58:26 PM PDT 24
Finished Apr 16 02:59:02 PM PDT 24
Peak memory 249028 kb
Host smart-722b48f1-1ca9-4f37-8c6b-0ac99094e40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14752
78815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1475278815
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2370987398
Short name T547
Test name
Test status
Simulation time 717620663 ps
CPU time 39.86 seconds
Started Apr 16 02:58:26 PM PDT 24
Finished Apr 16 02:59:06 PM PDT 24
Peak memory 255468 kb
Host smart-891f035f-18dc-477b-ac95-a60b156bd747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23709
87398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2370987398
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3838580780
Short name T253
Test name
Test status
Simulation time 362197105 ps
CPU time 26.95 seconds
Started Apr 16 02:58:31 PM PDT 24
Finished Apr 16 02:58:59 PM PDT 24
Peak memory 254860 kb
Host smart-536f22c6-cf47-41d3-9240-a12045cd5fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38385
80780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3838580780
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.659650925
Short name T545
Test name
Test status
Simulation time 3927911452 ps
CPU time 56.07 seconds
Started Apr 16 02:58:26 PM PDT 24
Finished Apr 16 02:59:23 PM PDT 24
Peak memory 256884 kb
Host smart-9c15d3a2-fa4b-4d1e-ba50-b8168b1c0c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65965
0925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.659650925
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.297801045
Short name T382
Test name
Test status
Simulation time 32958189358 ps
CPU time 700.02 seconds
Started Apr 16 02:58:38 PM PDT 24
Finished Apr 16 03:10:18 PM PDT 24
Peak memory 271952 kb
Host smart-f6a32301-0cbd-4df0-b73c-3429668d660f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297801045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.297801045
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3525637762
Short name T517
Test name
Test status
Simulation time 43085662790 ps
CPU time 216.12 seconds
Started Apr 16 02:58:34 PM PDT 24
Finished Apr 16 03:02:11 PM PDT 24
Peak memory 257324 kb
Host smart-1e72be08-9f83-427c-b019-7bce16a4545b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35256
37762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3525637762
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.4068458453
Short name T498
Test name
Test status
Simulation time 748908055 ps
CPU time 44.9 seconds
Started Apr 16 02:58:37 PM PDT 24
Finished Apr 16 02:59:23 PM PDT 24
Peak memory 255624 kb
Host smart-fd9a51f4-20bd-4781-959d-7efd0b74e220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40684
58453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4068458453
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3603008838
Short name T344
Test name
Test status
Simulation time 27216184682 ps
CPU time 1400.98 seconds
Started Apr 16 02:58:45 PM PDT 24
Finished Apr 16 03:22:07 PM PDT 24
Peak memory 271048 kb
Host smart-28c6b032-4ec1-4133-9e98-e936b52fb644
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603008838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3603008838
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3361411248
Short name T678
Test name
Test status
Simulation time 17054365116 ps
CPU time 1554.98 seconds
Started Apr 16 02:58:43 PM PDT 24
Finished Apr 16 03:24:39 PM PDT 24
Peak memory 289924 kb
Host smart-be0c2390-996b-4731-9e8b-fe6c28196ea6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361411248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3361411248
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2168313306
Short name T576
Test name
Test status
Simulation time 19124986957 ps
CPU time 400.24 seconds
Started Apr 16 02:58:40 PM PDT 24
Finished Apr 16 03:05:20 PM PDT 24
Peak memory 248328 kb
Host smart-0a484720-8f84-4dc5-9079-9acb15ed8192
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168313306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2168313306
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2440664297
Short name T469
Test name
Test status
Simulation time 599439061 ps
CPU time 37.6 seconds
Started Apr 16 02:58:34 PM PDT 24
Finished Apr 16 02:59:12 PM PDT 24
Peak memory 249088 kb
Host smart-8aaff835-757f-4ff1-801f-682f3d6469ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24406
64297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2440664297
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.965876498
Short name T674
Test name
Test status
Simulation time 213665438 ps
CPU time 27.2 seconds
Started Apr 16 02:58:38 PM PDT 24
Finished Apr 16 02:59:06 PM PDT 24
Peak memory 247560 kb
Host smart-b6de9fd0-3760-4836-9da7-84acd135457e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96587
6498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.965876498
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.687572311
Short name T401
Test name
Test status
Simulation time 1379961157 ps
CPU time 18.55 seconds
Started Apr 16 02:58:37 PM PDT 24
Finished Apr 16 02:58:56 PM PDT 24
Peak memory 249028 kb
Host smart-34a10bb4-79ab-4f05-80a0-8775891aa5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68757
2311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.687572311
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2312056002
Short name T161
Test name
Test status
Simulation time 64570248283 ps
CPU time 6334.29 seconds
Started Apr 16 02:58:44 PM PDT 24
Finished Apr 16 04:44:20 PM PDT 24
Peak memory 371100 kb
Host smart-ae5aebfa-aadb-4e07-a081-75af9214bff4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312056002 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2312056002
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.883348241
Short name T194
Test name
Test status
Simulation time 32774974 ps
CPU time 2.98 seconds
Started Apr 16 02:54:55 PM PDT 24
Finished Apr 16 02:55:00 PM PDT 24
Peak memory 249336 kb
Host smart-d49d2157-eb7d-45f7-8998-1bb77df1037d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=883348241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.883348241
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.224111350
Short name T610
Test name
Test status
Simulation time 297803191048 ps
CPU time 1408.34 seconds
Started Apr 16 02:54:54 PM PDT 24
Finished Apr 16 03:18:23 PM PDT 24
Peak memory 289324 kb
Host smart-c5bb449e-f5e5-4194-8e31-6e5bdabdee4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224111350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.224111350
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2892973155
Short name T561
Test name
Test status
Simulation time 418722135 ps
CPU time 10.93 seconds
Started Apr 16 02:54:54 PM PDT 24
Finished Apr 16 02:55:06 PM PDT 24
Peak memory 249040 kb
Host smart-a24cf39d-c5bf-4f15-bbeb-f4b77b676929
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2892973155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2892973155
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3753237939
Short name T653
Test name
Test status
Simulation time 12145371811 ps
CPU time 186.03 seconds
Started Apr 16 02:54:56 PM PDT 24
Finished Apr 16 02:58:03 PM PDT 24
Peak memory 257188 kb
Host smart-b3a2188e-3a6f-4305-8265-dc39b8949fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37532
37939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3753237939
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2291101292
Short name T1
Test name
Test status
Simulation time 877646188 ps
CPU time 53.67 seconds
Started Apr 16 02:54:56 PM PDT 24
Finished Apr 16 02:55:51 PM PDT 24
Peak memory 256688 kb
Host smart-021e2887-3a2c-4dad-bb6d-6a975c42183a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22911
01292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2291101292
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.4292253325
Short name T345
Test name
Test status
Simulation time 8160115047 ps
CPU time 560.92 seconds
Started Apr 16 02:54:56 PM PDT 24
Finished Apr 16 03:04:18 PM PDT 24
Peak memory 265508 kb
Host smart-c3509c55-0826-4c7d-b9ff-928f04575413
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292253325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.4292253325
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2079243849
Short name T548
Test name
Test status
Simulation time 10699061167 ps
CPU time 1172.62 seconds
Started Apr 16 02:54:56 PM PDT 24
Finished Apr 16 03:14:31 PM PDT 24
Peak memory 281936 kb
Host smart-397b4d6b-77d1-476a-ba43-64b519c4f70c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079243849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2079243849
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1374374362
Short name T636
Test name
Test status
Simulation time 11672820005 ps
CPU time 224.67 seconds
Started Apr 16 02:54:55 PM PDT 24
Finished Apr 16 02:58:41 PM PDT 24
Peak memory 248268 kb
Host smart-77afd135-eea1-4c4e-8c89-5fc2c51dc47d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374374362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1374374362
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1193403179
Short name T173
Test name
Test status
Simulation time 907110561 ps
CPU time 53.45 seconds
Started Apr 16 02:54:58 PM PDT 24
Finished Apr 16 02:55:53 PM PDT 24
Peak memory 248992 kb
Host smart-fc77d07b-5584-4133-a490-aa91d25b7cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11934
03179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1193403179
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3831105158
Short name T62
Test name
Test status
Simulation time 69153064 ps
CPU time 6.02 seconds
Started Apr 16 02:54:59 PM PDT 24
Finished Apr 16 02:55:06 PM PDT 24
Peak memory 252984 kb
Host smart-1f604b9c-efa1-4a7b-a662-f249b4bc1070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38311
05158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3831105158
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.4012364586
Short name T12
Test name
Test status
Simulation time 938147231 ps
CPU time 12.94 seconds
Started Apr 16 02:54:57 PM PDT 24
Finished Apr 16 02:55:12 PM PDT 24
Peak memory 273884 kb
Host smart-37cb308c-b9d2-4fd9-9dcb-2170a1db7ec3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4012364586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.4012364586
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3352015835
Short name T259
Test name
Test status
Simulation time 362861807 ps
CPU time 21.37 seconds
Started Apr 16 02:54:58 PM PDT 24
Finished Apr 16 02:55:21 PM PDT 24
Peak memory 249056 kb
Host smart-6d0ca0cc-aeea-44b2-9a91-87af0cb40584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33520
15835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3352015835
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3026233873
Short name T394
Test name
Test status
Simulation time 2693804049 ps
CPU time 39.75 seconds
Started Apr 16 02:54:56 PM PDT 24
Finished Apr 16 02:55:37 PM PDT 24
Peak memory 249124 kb
Host smart-94881c38-5edd-49a6-83b1-163e436cb3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30262
33873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3026233873
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2906310898
Short name T613
Test name
Test status
Simulation time 83734535252 ps
CPU time 2191.96 seconds
Started Apr 16 02:54:59 PM PDT 24
Finished Apr 16 03:31:32 PM PDT 24
Peak memory 289352 kb
Host smart-6e0a9186-fb3e-414f-8995-f6ff70ffe880
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906310898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2906310898
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2037852977
Short name T690
Test name
Test status
Simulation time 106004550537 ps
CPU time 1721.63 seconds
Started Apr 16 02:54:56 PM PDT 24
Finished Apr 16 03:23:40 PM PDT 24
Peak memory 290204 kb
Host smart-83c42eaa-f5de-4a00-a5b3-a738dacf1317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037852977 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2037852977
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3304505919
Short name T54
Test name
Test status
Simulation time 86898870020 ps
CPU time 2659.41 seconds
Started Apr 16 02:58:52 PM PDT 24
Finished Apr 16 03:43:12 PM PDT 24
Peak memory 286516 kb
Host smart-d09794f5-660f-4d31-91d7-7d4b29041a23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304505919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3304505919
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3153686115
Short name T78
Test name
Test status
Simulation time 1658543459 ps
CPU time 124.5 seconds
Started Apr 16 02:58:52 PM PDT 24
Finished Apr 16 03:00:57 PM PDT 24
Peak memory 256868 kb
Host smart-a8cfa09e-5477-4144-aef4-b3ee29ecd863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31536
86115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3153686115
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2885339280
Short name T630
Test name
Test status
Simulation time 780411545 ps
CPU time 53.59 seconds
Started Apr 16 02:58:48 PM PDT 24
Finished Apr 16 02:59:43 PM PDT 24
Peak memory 255480 kb
Host smart-9a93217f-da76-406d-aa0f-5b2c8ee9146d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28853
39280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2885339280
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3036119284
Short name T216
Test name
Test status
Simulation time 113290937442 ps
CPU time 1658.82 seconds
Started Apr 16 02:58:56 PM PDT 24
Finished Apr 16 03:26:36 PM PDT 24
Peak memory 273352 kb
Host smart-e9162a7f-54b9-415f-b7c4-d1e764601a76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036119284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3036119284
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3125121241
Short name T608
Test name
Test status
Simulation time 42807816611 ps
CPU time 2168.97 seconds
Started Apr 16 02:58:56 PM PDT 24
Finished Apr 16 03:35:06 PM PDT 24
Peak memory 273672 kb
Host smart-46297fe9-c76e-4f93-907b-0faa20a6e1af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125121241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3125121241
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1546730054
Short name T611
Test name
Test status
Simulation time 681517732 ps
CPU time 46.72 seconds
Started Apr 16 02:58:47 PM PDT 24
Finished Apr 16 02:59:34 PM PDT 24
Peak memory 256180 kb
Host smart-23c7a60b-61e8-41fd-921e-41a9632bb7e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15467
30054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1546730054
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1232872406
Short name T384
Test name
Test status
Simulation time 421700959 ps
CPU time 4.61 seconds
Started Apr 16 02:58:48 PM PDT 24
Finished Apr 16 02:58:53 PM PDT 24
Peak memory 239124 kb
Host smart-bf9aec24-a492-4537-95cf-8e5b0b921e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12328
72406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1232872406
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.4131046941
Short name T489
Test name
Test status
Simulation time 980635537 ps
CPU time 21.35 seconds
Started Apr 16 02:58:49 PM PDT 24
Finished Apr 16 02:59:11 PM PDT 24
Peak memory 254140 kb
Host smart-ba85e913-9f8e-4a39-b9c5-0e0d97f90e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41310
46941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.4131046941
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3188987517
Short name T632
Test name
Test status
Simulation time 3402316862 ps
CPU time 16.26 seconds
Started Apr 16 02:58:50 PM PDT 24
Finished Apr 16 02:59:07 PM PDT 24
Peak memory 249156 kb
Host smart-38a40638-095e-4a83-a9ff-e82a5a0fdab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31889
87517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3188987517
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.869760802
Short name T244
Test name
Test status
Simulation time 9813730251 ps
CPU time 447.43 seconds
Started Apr 16 02:58:56 PM PDT 24
Finished Apr 16 03:06:24 PM PDT 24
Peak memory 255948 kb
Host smart-d7a2cd15-a351-4e65-addb-e69e02f48e10
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869760802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.869760802
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1565329922
Short name T70
Test name
Test status
Simulation time 361712941646 ps
CPU time 9329.07 seconds
Started Apr 16 02:58:54 PM PDT 24
Finished Apr 16 05:34:25 PM PDT 24
Peak memory 404172 kb
Host smart-30098497-4a68-41d7-bc3e-e6ebb61afef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565329922 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1565329922
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2808296829
Short name T620
Test name
Test status
Simulation time 208626917316 ps
CPU time 3075.38 seconds
Started Apr 16 02:59:03 PM PDT 24
Finished Apr 16 03:50:19 PM PDT 24
Peak memory 289088 kb
Host smart-abc05f01-07a5-4b7d-9d7e-3a9d78e1b87b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808296829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2808296829
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2006851082
Short name T643
Test name
Test status
Simulation time 612053410 ps
CPU time 12.67 seconds
Started Apr 16 02:59:03 PM PDT 24
Finished Apr 16 02:59:16 PM PDT 24
Peak memory 255176 kb
Host smart-4561c08d-b653-453a-8d55-d923259b6cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
51082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2006851082
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.4005093351
Short name T459
Test name
Test status
Simulation time 1476548498 ps
CPU time 43.63 seconds
Started Apr 16 02:59:05 PM PDT 24
Finished Apr 16 02:59:49 PM PDT 24
Peak memory 248740 kb
Host smart-ed207544-9655-48d6-a774-87ccb588b304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40050
93351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.4005093351
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.467585228
Short name T346
Test name
Test status
Simulation time 27166134092 ps
CPU time 1542.83 seconds
Started Apr 16 02:59:04 PM PDT 24
Finished Apr 16 03:24:47 PM PDT 24
Peak memory 273520 kb
Host smart-d19a9b32-f222-4871-9d0e-8f19fe63ccf0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467585228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.467585228
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2105347178
Short name T428
Test name
Test status
Simulation time 110652212792 ps
CPU time 1823.07 seconds
Started Apr 16 02:59:04 PM PDT 24
Finished Apr 16 03:29:28 PM PDT 24
Peak memory 273728 kb
Host smart-7d3022f0-eca6-4f64-bc9f-7e64e26c33a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105347178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2105347178
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.4163246407
Short name T305
Test name
Test status
Simulation time 24833042399 ps
CPU time 271.14 seconds
Started Apr 16 02:59:01 PM PDT 24
Finished Apr 16 03:03:33 PM PDT 24
Peak memory 247476 kb
Host smart-023569d3-4ae3-49dd-ba87-75474615aa0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163246407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.4163246407
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1241468664
Short name T385
Test name
Test status
Simulation time 3212284329 ps
CPU time 24.91 seconds
Started Apr 16 02:58:58 PM PDT 24
Finished Apr 16 02:59:24 PM PDT 24
Peak memory 256312 kb
Host smart-b30251aa-30b5-40f5-a63d-d3a05358549f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12414
68664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1241468664
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2577677437
Short name T473
Test name
Test status
Simulation time 3640609192 ps
CPU time 54.18 seconds
Started Apr 16 02:58:58 PM PDT 24
Finished Apr 16 02:59:53 PM PDT 24
Peak memory 255208 kb
Host smart-5de04bfd-c052-4384-a01b-794c1de9edd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25776
77437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2577677437
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.755136444
Short name T230
Test name
Test status
Simulation time 345540749 ps
CPU time 29.93 seconds
Started Apr 16 02:58:59 PM PDT 24
Finished Apr 16 02:59:30 PM PDT 24
Peak memory 256228 kb
Host smart-869647e5-d3e7-4a56-ba7d-440d3541632a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75513
6444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.755136444
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2458741569
Short name T235
Test name
Test status
Simulation time 18789418650 ps
CPU time 1199 seconds
Started Apr 16 02:59:05 PM PDT 24
Finished Apr 16 03:19:05 PM PDT 24
Peak memory 288504 kb
Host smart-59abae24-8419-4454-be66-89c0437bcfab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458741569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2458741569
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1841312644
Short name T687
Test name
Test status
Simulation time 95524878375 ps
CPU time 8421 seconds
Started Apr 16 02:59:07 PM PDT 24
Finished Apr 16 05:19:30 PM PDT 24
Peak memory 339364 kb
Host smart-a570aa57-b7c4-4044-a4c4-b1943ba5c198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841312644 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1841312644
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4008256456
Short name T615
Test name
Test status
Simulation time 9539709815 ps
CPU time 1175.09 seconds
Started Apr 16 02:59:14 PM PDT 24
Finished Apr 16 03:18:50 PM PDT 24
Peak memory 289596 kb
Host smart-b2c44bd2-38c7-458e-9c3c-d08b5ba3c91f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008256456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4008256456
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2619231862
Short name T367
Test name
Test status
Simulation time 2122704279 ps
CPU time 113.39 seconds
Started Apr 16 02:59:12 PM PDT 24
Finished Apr 16 03:01:07 PM PDT 24
Peak memory 248840 kb
Host smart-7ea9d894-9873-4eff-a0f9-ba1a26219822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26192
31862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2619231862
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2775644672
Short name T513
Test name
Test status
Simulation time 5178684968 ps
CPU time 78.01 seconds
Started Apr 16 02:59:13 PM PDT 24
Finished Apr 16 03:00:31 PM PDT 24
Peak memory 248944 kb
Host smart-5661c447-cbd2-45b9-96f5-e0475aee5509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27756
44672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2775644672
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1220912681
Short name T607
Test name
Test status
Simulation time 84599578365 ps
CPU time 791.8 seconds
Started Apr 16 02:59:12 PM PDT 24
Finished Apr 16 03:12:24 PM PDT 24
Peak memory 266780 kb
Host smart-8af50a71-eaab-4171-a757-6601986ccdca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220912681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1220912681
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.101655141
Short name T57
Test name
Test status
Simulation time 49875259982 ps
CPU time 2690.4 seconds
Started Apr 16 02:59:17 PM PDT 24
Finished Apr 16 03:44:08 PM PDT 24
Peak memory 289504 kb
Host smart-54047454-bb8f-4b56-a4a5-780d0785f79a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101655141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.101655141
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2561921492
Short name T688
Test name
Test status
Simulation time 5005831317 ps
CPU time 208.98 seconds
Started Apr 16 02:59:13 PM PDT 24
Finished Apr 16 03:02:43 PM PDT 24
Peak memory 248396 kb
Host smart-049c99d8-1dd5-435c-85a0-6cbeb00803a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561921492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2561921492
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3559692831
Short name T652
Test name
Test status
Simulation time 263524698 ps
CPU time 12.99 seconds
Started Apr 16 02:59:09 PM PDT 24
Finished Apr 16 02:59:22 PM PDT 24
Peak memory 257208 kb
Host smart-e8fb81d2-b605-4b2d-a15d-aba3570b0158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35596
92831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3559692831
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.4077617954
Short name T398
Test name
Test status
Simulation time 1218237418 ps
CPU time 39.63 seconds
Started Apr 16 02:59:07 PM PDT 24
Finished Apr 16 02:59:47 PM PDT 24
Peak memory 255576 kb
Host smart-58eedbfb-25b8-4c7b-a11d-96d278590749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40776
17954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.4077617954
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2459650012
Short name T50
Test name
Test status
Simulation time 814064949 ps
CPU time 27.2 seconds
Started Apr 16 02:59:12 PM PDT 24
Finished Apr 16 02:59:40 PM PDT 24
Peak memory 247364 kb
Host smart-2005ce5d-b5d3-4b56-ac3c-22aa19e3c441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24596
50012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2459650012
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2858562579
Short name T470
Test name
Test status
Simulation time 3730003423 ps
CPU time 36.99 seconds
Started Apr 16 02:59:07 PM PDT 24
Finished Apr 16 02:59:45 PM PDT 24
Peak memory 257344 kb
Host smart-5d6c66aa-42ec-410d-a79b-1b625435ced6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28585
62579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2858562579
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3849946600
Short name T538
Test name
Test status
Simulation time 16062870830 ps
CPU time 1310.97 seconds
Started Apr 16 02:59:28 PM PDT 24
Finished Apr 16 03:21:20 PM PDT 24
Peak memory 289388 kb
Host smart-9478140a-3e57-44a0-9192-3937395d044f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849946600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3849946600
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2151093712
Short name T232
Test name
Test status
Simulation time 1740791014 ps
CPU time 99.74 seconds
Started Apr 16 02:59:26 PM PDT 24
Finished Apr 16 03:01:06 PM PDT 24
Peak memory 256992 kb
Host smart-eab4c7cd-79ba-4411-bd98-c9dd2adcafa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21510
93712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2151093712
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2516708004
Short name T467
Test name
Test status
Simulation time 449784621 ps
CPU time 13.04 seconds
Started Apr 16 02:59:21 PM PDT 24
Finished Apr 16 02:59:35 PM PDT 24
Peak memory 249068 kb
Host smart-7c23d680-0d31-4b7a-94f0-5f3bd0febf7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25167
08004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2516708004
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3210790895
Short name T618
Test name
Test status
Simulation time 62397752879 ps
CPU time 1336.84 seconds
Started Apr 16 02:59:25 PM PDT 24
Finished Apr 16 03:21:42 PM PDT 24
Peak memory 289572 kb
Host smart-191ede45-462b-4c44-bc01-2fe6c638495b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210790895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3210790895
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3408737540
Short name T317
Test name
Test status
Simulation time 21238876649 ps
CPU time 239.3 seconds
Started Apr 16 02:59:27 PM PDT 24
Finished Apr 16 03:03:27 PM PDT 24
Peak memory 247932 kb
Host smart-f1c4b4d9-61e8-4357-93e7-e1e2a00120d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408737540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3408737540
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.691880957
Short name T475
Test name
Test status
Simulation time 422683342 ps
CPU time 33.14 seconds
Started Apr 16 02:59:22 PM PDT 24
Finished Apr 16 02:59:56 PM PDT 24
Peak memory 249044 kb
Host smart-01e50209-3c9a-4ce2-b7c0-cf6a7fad6b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69188
0957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.691880957
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1414422812
Short name T48
Test name
Test status
Simulation time 1864171051 ps
CPU time 29.13 seconds
Started Apr 16 02:59:22 PM PDT 24
Finished Apr 16 02:59:52 PM PDT 24
Peak memory 255520 kb
Host smart-03b848f7-ebd7-492f-a8b4-b5c5f7d5d9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14144
22812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1414422812
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2404220800
Short name T462
Test name
Test status
Simulation time 663177408 ps
CPU time 53.52 seconds
Started Apr 16 02:59:26 PM PDT 24
Finished Apr 16 03:00:19 PM PDT 24
Peak memory 256192 kb
Host smart-0db41413-0413-4086-b5fa-c220f56e6b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24042
20800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2404220800
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.4087797162
Short name T567
Test name
Test status
Simulation time 1015493055 ps
CPU time 29.95 seconds
Started Apr 16 02:59:22 PM PDT 24
Finished Apr 16 02:59:53 PM PDT 24
Peak memory 257136 kb
Host smart-5bc18668-0fbd-498e-b5c9-a17ccabf4561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40877
97162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4087797162
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2575293088
Short name T94
Test name
Test status
Simulation time 5022725320 ps
CPU time 296.61 seconds
Started Apr 16 02:59:24 PM PDT 24
Finished Apr 16 03:04:21 PM PDT 24
Peak memory 251548 kb
Host smart-9fc6e785-48bf-4c3c-8194-e60af7a8b478
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575293088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2575293088
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2390000748
Short name T277
Test name
Test status
Simulation time 72917681985 ps
CPU time 6358.08 seconds
Started Apr 16 02:59:25 PM PDT 24
Finished Apr 16 04:45:24 PM PDT 24
Peak memory 317064 kb
Host smart-c4da4bfa-c63d-4c33-afa0-f7e4462311b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390000748 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2390000748
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3231545092
Short name T278
Test name
Test status
Simulation time 144886695356 ps
CPU time 1199.43 seconds
Started Apr 16 02:59:29 PM PDT 24
Finished Apr 16 03:19:29 PM PDT 24
Peak memory 272544 kb
Host smart-7a89b053-1bea-428a-89b8-35cde6282a36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231545092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3231545092
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1574034499
Short name T480
Test name
Test status
Simulation time 34851629 ps
CPU time 5.21 seconds
Started Apr 16 02:59:31 PM PDT 24
Finished Apr 16 02:59:37 PM PDT 24
Peak memory 250040 kb
Host smart-250e948f-a8c4-487a-8743-8284f927a6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15740
34499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1574034499
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1475271771
Short name T584
Test name
Test status
Simulation time 101899275 ps
CPU time 4.29 seconds
Started Apr 16 02:59:27 PM PDT 24
Finished Apr 16 02:59:32 PM PDT 24
Peak memory 250176 kb
Host smart-849541be-8f8c-4b39-a24b-19a5ffec8481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14752
71771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1475271771
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3742604210
Short name T663
Test name
Test status
Simulation time 49013284601 ps
CPU time 1155.83 seconds
Started Apr 16 02:59:30 PM PDT 24
Finished Apr 16 03:18:46 PM PDT 24
Peak memory 289040 kb
Host smart-00e8b896-c216-4ad0-a5f3-eff703328ace
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742604210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3742604210
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3918661021
Short name T466
Test name
Test status
Simulation time 30738164693 ps
CPU time 1737.07 seconds
Started Apr 16 02:59:30 PM PDT 24
Finished Apr 16 03:28:28 PM PDT 24
Peak memory 281848 kb
Host smart-3be21798-fefd-4589-b18d-0f25840ae37e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918661021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3918661021
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.368807949
Short name T43
Test name
Test status
Simulation time 2219673368 ps
CPU time 19.33 seconds
Started Apr 16 02:59:30 PM PDT 24
Finished Apr 16 02:59:50 PM PDT 24
Peak memory 248264 kb
Host smart-ec20c714-0f2b-486e-bb5a-b4bfdb50fa2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36880
7949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.368807949
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1416865622
Short name T590
Test name
Test status
Simulation time 1280831975 ps
CPU time 28.08 seconds
Started Apr 16 02:59:30 PM PDT 24
Finished Apr 16 02:59:59 PM PDT 24
Peak memory 254848 kb
Host smart-2c055af6-8734-4dc3-bbbd-c376bf0273d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14168
65622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1416865622
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.140407277
Short name T262
Test name
Test status
Simulation time 2089772545 ps
CPU time 14.19 seconds
Started Apr 16 02:59:26 PM PDT 24
Finished Apr 16 02:59:41 PM PDT 24
Peak memory 247564 kb
Host smart-62825087-8d77-47a1-8c5d-f813dcae85fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14040
7277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.140407277
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3958373854
Short name T364
Test name
Test status
Simulation time 12942637582 ps
CPU time 42.96 seconds
Started Apr 16 02:59:31 PM PDT 24
Finished Apr 16 03:00:15 PM PDT 24
Peak memory 256288 kb
Host smart-cefc8a67-d4b0-4ca8-99aa-651ca7866973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39583
73854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3958373854
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1247799277
Short name T224
Test name
Test status
Simulation time 16107860294 ps
CPU time 761.03 seconds
Started Apr 16 02:59:33 PM PDT 24
Finished Apr 16 03:12:15 PM PDT 24
Peak memory 273804 kb
Host smart-5a748749-2260-4e5b-8bc9-574dd9f707e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247799277 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1247799277
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3857932634
Short name T624
Test name
Test status
Simulation time 70614171405 ps
CPU time 1855.64 seconds
Started Apr 16 02:59:38 PM PDT 24
Finished Apr 16 03:30:35 PM PDT 24
Peak memory 273732 kb
Host smart-730a1172-11b4-4828-a09a-875aab6a7b5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857932634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3857932634
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2006886807
Short name T596
Test name
Test status
Simulation time 2306867403 ps
CPU time 92.24 seconds
Started Apr 16 02:59:35 PM PDT 24
Finished Apr 16 03:01:08 PM PDT 24
Peak memory 256880 kb
Host smart-0e291f30-aa85-46e8-8d20-3a3b28efaa35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
86807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2006886807
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2927633725
Short name T403
Test name
Test status
Simulation time 888513431 ps
CPU time 23.05 seconds
Started Apr 16 02:59:35 PM PDT 24
Finished Apr 16 02:59:58 PM PDT 24
Peak memory 256136 kb
Host smart-4df83fda-c747-451b-ab72-4151ad1eefeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29276
33725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2927633725
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3522574244
Short name T426
Test name
Test status
Simulation time 57960657415 ps
CPU time 1773.33 seconds
Started Apr 16 02:59:40 PM PDT 24
Finished Apr 16 03:29:15 PM PDT 24
Peak memory 287080 kb
Host smart-df1943d4-7f3b-45f4-b518-2da980390f79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522574244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3522574244
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.283000401
Short name T304
Test name
Test status
Simulation time 33104645353 ps
CPU time 337.18 seconds
Started Apr 16 02:59:40 PM PDT 24
Finished Apr 16 03:05:18 PM PDT 24
Peak memory 248208 kb
Host smart-e6bf395a-8f3f-44b9-8ae1-6fb5a923eabf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283000401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.283000401
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1320501317
Short name T229
Test name
Test status
Simulation time 662036874 ps
CPU time 35.82 seconds
Started Apr 16 02:59:36 PM PDT 24
Finished Apr 16 03:00:13 PM PDT 24
Peak memory 256220 kb
Host smart-18dc7e0c-93e4-4c3d-a8cd-26a56501c58a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13205
01317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1320501317
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.149280078
Short name T210
Test name
Test status
Simulation time 2356295565 ps
CPU time 63.26 seconds
Started Apr 16 02:59:35 PM PDT 24
Finished Apr 16 03:00:39 PM PDT 24
Peak memory 255844 kb
Host smart-153b92d0-ad7b-448e-8f9a-9c9656f762de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14928
0078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.149280078
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2597100044
Short name T264
Test name
Test status
Simulation time 822946513 ps
CPU time 47.66 seconds
Started Apr 16 02:59:39 PM PDT 24
Finished Apr 16 03:00:28 PM PDT 24
Peak memory 255748 kb
Host smart-5006516e-afc2-4a23-8781-968f7f1289cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25971
00044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2597100044
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1353545202
Short name T418
Test name
Test status
Simulation time 300211110 ps
CPU time 18.3 seconds
Started Apr 16 02:59:36 PM PDT 24
Finished Apr 16 02:59:55 PM PDT 24
Peak memory 255996 kb
Host smart-04e7cc27-eebf-43f0-be01-38cf31f98b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13535
45202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1353545202
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.63963400
Short name T236
Test name
Test status
Simulation time 55739763715 ps
CPU time 1216.76 seconds
Started Apr 16 02:59:39 PM PDT 24
Finished Apr 16 03:19:57 PM PDT 24
Peak memory 286656 kb
Host smart-0fc6c59f-3ccb-4d00-bce4-8dcd383a1663
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63963400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_hand
ler_stress_all.63963400
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.858185049
Short name T222
Test name
Test status
Simulation time 46177041449 ps
CPU time 661.66 seconds
Started Apr 16 02:59:40 PM PDT 24
Finished Apr 16 03:10:42 PM PDT 24
Peak memory 269884 kb
Host smart-e497fb6e-1ff0-41f6-884a-b29856ac3c56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858185049 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.858185049
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.57291099
Short name T3
Test name
Test status
Simulation time 305984625400 ps
CPU time 3099.91 seconds
Started Apr 16 02:59:53 PM PDT 24
Finished Apr 16 03:51:34 PM PDT 24
Peak memory 289436 kb
Host smart-38dab8cc-e3d6-4c39-9dd1-a86fc4aad791
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57291099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.57291099
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3398948678
Short name T166
Test name
Test status
Simulation time 3756462072 ps
CPU time 64.33 seconds
Started Apr 16 02:59:47 PM PDT 24
Finished Apr 16 03:00:52 PM PDT 24
Peak memory 249140 kb
Host smart-cfa15924-e960-4815-a337-2b0e7ccd8fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33989
48678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3398948678
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.705601977
Short name T423
Test name
Test status
Simulation time 729155924 ps
CPU time 16.88 seconds
Started Apr 16 02:59:44 PM PDT 24
Finished Apr 16 03:00:01 PM PDT 24
Peak memory 255404 kb
Host smart-95266ef1-7aae-48f2-bfb3-4cda5a68c0ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70560
1977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.705601977
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1151806033
Short name T310
Test name
Test status
Simulation time 29965018471 ps
CPU time 1738.73 seconds
Started Apr 16 02:59:53 PM PDT 24
Finished Apr 16 03:28:52 PM PDT 24
Peak memory 271748 kb
Host smart-7da280dc-ec6b-4378-b70c-8c7651f8dc0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151806033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1151806033
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1710783377
Short name T570
Test name
Test status
Simulation time 112928136094 ps
CPU time 1784.1 seconds
Started Apr 16 02:59:57 PM PDT 24
Finished Apr 16 03:29:42 PM PDT 24
Peak memory 273004 kb
Host smart-5379ce55-0706-4741-ba19-ce0063cf1c8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710783377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1710783377
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1755605386
Short name T282
Test name
Test status
Simulation time 29496925374 ps
CPU time 600.36 seconds
Started Apr 16 02:59:53 PM PDT 24
Finished Apr 16 03:09:54 PM PDT 24
Peak memory 247300 kb
Host smart-4be1fbe9-4487-4eae-9070-6e6095463517
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755605386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1755605386
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2040068342
Short name T598
Test name
Test status
Simulation time 55929878 ps
CPU time 4.42 seconds
Started Apr 16 02:59:42 PM PDT 24
Finished Apr 16 02:59:47 PM PDT 24
Peak memory 240856 kb
Host smart-e0618b4f-e7f1-48b4-8ef8-8d79a2d359cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20400
68342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2040068342
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2130398502
Short name T668
Test name
Test status
Simulation time 839124405 ps
CPU time 25.69 seconds
Started Apr 16 02:59:46 PM PDT 24
Finished Apr 16 03:00:13 PM PDT 24
Peak memory 255496 kb
Host smart-0178b776-2c6c-411e-9877-7168729af6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21303
98502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2130398502
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.977597980
Short name T665
Test name
Test status
Simulation time 51829175 ps
CPU time 4.08 seconds
Started Apr 16 02:59:49 PM PDT 24
Finished Apr 16 02:59:54 PM PDT 24
Peak memory 239268 kb
Host smart-c1249e2b-d47a-4d31-b372-af500f06b018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97759
7980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.977597980
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.833580346
Short name T595
Test name
Test status
Simulation time 1202256268 ps
CPU time 21 seconds
Started Apr 16 02:59:45 PM PDT 24
Finished Apr 16 03:00:06 PM PDT 24
Peak memory 256220 kb
Host smart-676a9611-ea03-4dd2-9457-7b140349a159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83358
0346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.833580346
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2935237287
Short name T616
Test name
Test status
Simulation time 27427724453 ps
CPU time 1674.65 seconds
Started Apr 16 02:59:57 PM PDT 24
Finished Apr 16 03:27:52 PM PDT 24
Peak memory 289668 kb
Host smart-b9407ef2-4cdb-47ab-ba67-1a2b1b2c5f28
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935237287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2935237287
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3968820891
Short name T223
Test name
Test status
Simulation time 94118583467 ps
CPU time 2497.57 seconds
Started Apr 16 02:59:58 PM PDT 24
Finished Apr 16 03:41:37 PM PDT 24
Peak memory 290252 kb
Host smart-31eaccf6-46f1-4be2-bf28-bc8531479524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968820891 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3968820891
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3176014613
Short name T638
Test name
Test status
Simulation time 60861064241 ps
CPU time 1260.54 seconds
Started Apr 16 03:00:02 PM PDT 24
Finished Apr 16 03:21:03 PM PDT 24
Peak memory 273028 kb
Host smart-183f4569-3572-4b7b-abe6-75c21f0db14d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176014613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3176014613
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1276926579
Short name T600
Test name
Test status
Simulation time 9876045622 ps
CPU time 107.76 seconds
Started Apr 16 03:00:02 PM PDT 24
Finished Apr 16 03:01:50 PM PDT 24
Peak memory 257348 kb
Host smart-bc018791-d74e-4fdf-a626-65901acfc68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12769
26579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1276926579
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3968270012
Short name T623
Test name
Test status
Simulation time 1901041729 ps
CPU time 26.34 seconds
Started Apr 16 03:00:03 PM PDT 24
Finished Apr 16 03:00:30 PM PDT 24
Peak memory 254172 kb
Host smart-391123f8-3e55-4b25-a016-bae61a5e7596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39682
70012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3968270012
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3377531732
Short name T336
Test name
Test status
Simulation time 14124453503 ps
CPU time 1083.93 seconds
Started Apr 16 03:00:08 PM PDT 24
Finished Apr 16 03:18:12 PM PDT 24
Peak memory 273680 kb
Host smart-785c0f97-4b54-41df-a6aa-c906d6ed9e94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377531732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3377531732
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.421460234
Short name T628
Test name
Test status
Simulation time 7882778061 ps
CPU time 771.84 seconds
Started Apr 16 03:00:08 PM PDT 24
Finished Apr 16 03:13:00 PM PDT 24
Peak memory 273744 kb
Host smart-91363e42-8cbd-4ada-b450-882bcaae6eab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421460234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.421460234
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.611025679
Short name T328
Test name
Test status
Simulation time 13645236040 ps
CPU time 291.31 seconds
Started Apr 16 03:00:04 PM PDT 24
Finished Apr 16 03:04:56 PM PDT 24
Peak memory 247952 kb
Host smart-403e4e06-52c4-40fe-8cc9-401ddde1becc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611025679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.611025679
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2077087321
Short name T519
Test name
Test status
Simulation time 224440264 ps
CPU time 25.39 seconds
Started Apr 16 02:59:56 PM PDT 24
Finished Apr 16 03:00:22 PM PDT 24
Peak memory 255684 kb
Host smart-776fc58c-bf21-435d-99bf-9f2a165cdc81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20770
87321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2077087321
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1295346744
Short name T373
Test name
Test status
Simulation time 754714443 ps
CPU time 47.79 seconds
Started Apr 16 03:00:02 PM PDT 24
Finished Apr 16 03:00:50 PM PDT 24
Peak memory 255704 kb
Host smart-a18ef0c4-fe55-4d08-ba4c-5a38bc2e227a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12953
46744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1295346744
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3139094782
Short name T77
Test name
Test status
Simulation time 120503356 ps
CPU time 7.9 seconds
Started Apr 16 03:00:01 PM PDT 24
Finished Apr 16 03:00:09 PM PDT 24
Peak memory 249008 kb
Host smart-c34a42be-aa00-46af-b179-f9eea4c9ee2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31390
94782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3139094782
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.4252423898
Short name T582
Test name
Test status
Simulation time 80408646 ps
CPU time 3.98 seconds
Started Apr 16 02:59:57 PM PDT 24
Finished Apr 16 03:00:02 PM PDT 24
Peak memory 240836 kb
Host smart-738d6a29-cf9a-4da7-af45-2d85957cc811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42524
23898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.4252423898
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3112722315
Short name T85
Test name
Test status
Simulation time 72742120691 ps
CPU time 4306.64 seconds
Started Apr 16 03:00:08 PM PDT 24
Finished Apr 16 04:11:55 PM PDT 24
Peak memory 306592 kb
Host smart-c089a77a-1405-4ffe-a50e-c349dce77a66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112722315 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3112722315
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.263674282
Short name T511
Test name
Test status
Simulation time 138144791739 ps
CPU time 1075.2 seconds
Started Apr 16 03:00:15 PM PDT 24
Finished Apr 16 03:18:10 PM PDT 24
Peak memory 273712 kb
Host smart-34f9bf28-c225-4b54-8905-7fa2a6876189
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263674282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.263674282
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1349102188
Short name T463
Test name
Test status
Simulation time 2475250484 ps
CPU time 109.95 seconds
Started Apr 16 03:00:17 PM PDT 24
Finished Apr 16 03:02:07 PM PDT 24
Peak memory 257284 kb
Host smart-0fbfe112-f3fd-4af0-81be-fa3fee5e0668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13491
02188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1349102188
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3159080315
Short name T637
Test name
Test status
Simulation time 235801871 ps
CPU time 20.33 seconds
Started Apr 16 03:00:13 PM PDT 24
Finished Apr 16 03:00:33 PM PDT 24
Peak memory 249096 kb
Host smart-0abf3aa4-4c78-4d15-8f24-5b53cc12cc55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31590
80315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3159080315
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.692454329
Short name T168
Test name
Test status
Simulation time 25292719880 ps
CPU time 1667.28 seconds
Started Apr 16 03:00:16 PM PDT 24
Finished Apr 16 03:28:04 PM PDT 24
Peak memory 265476 kb
Host smart-cb7bb9bf-2871-413e-80f8-ad69dad9f1bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692454329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.692454329
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2721815470
Short name T614
Test name
Test status
Simulation time 18603932034 ps
CPU time 1472.6 seconds
Started Apr 16 03:00:21 PM PDT 24
Finished Apr 16 03:24:54 PM PDT 24
Peak memory 289500 kb
Host smart-2e0ce07b-dc7e-4ca0-becf-4a5710629f4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721815470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2721815470
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2344538136
Short name T619
Test name
Test status
Simulation time 21085608323 ps
CPU time 443.49 seconds
Started Apr 16 03:00:18 PM PDT 24
Finished Apr 16 03:07:42 PM PDT 24
Peak memory 247184 kb
Host smart-a1f6ab41-a8f9-4922-b45e-c64ecf61460a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344538136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2344538136
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1100998192
Short name T468
Test name
Test status
Simulation time 319414927 ps
CPU time 34.05 seconds
Started Apr 16 03:00:11 PM PDT 24
Finished Apr 16 03:00:45 PM PDT 24
Peak memory 256220 kb
Host smart-66774482-9bd3-4452-8b9e-dce4e373870d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11009
98192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1100998192
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.880238191
Short name T247
Test name
Test status
Simulation time 165797004 ps
CPU time 18.37 seconds
Started Apr 16 03:00:16 PM PDT 24
Finished Apr 16 03:00:35 PM PDT 24
Peak memory 256244 kb
Host smart-3d1b5e67-1637-451b-9bc3-ac339fe17bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88023
8191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.880238191
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.734314255
Short name T26
Test name
Test status
Simulation time 2423031688 ps
CPU time 71.18 seconds
Started Apr 16 03:00:12 PM PDT 24
Finished Apr 16 03:01:24 PM PDT 24
Peak memory 256356 kb
Host smart-69779ce1-1342-4c6c-a34f-5313eda7240d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73431
4255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.734314255
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.793979449
Short name T237
Test name
Test status
Simulation time 14117537165 ps
CPU time 1479.61 seconds
Started Apr 16 03:00:19 PM PDT 24
Finished Apr 16 03:24:59 PM PDT 24
Peak memory 289640 kb
Host smart-ec8c9951-b794-47ed-ae64-da35b733d108
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793979449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.793979449
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2533301090
Short name T28
Test name
Test status
Simulation time 43809730496 ps
CPU time 1576.88 seconds
Started Apr 16 03:00:19 PM PDT 24
Finished Apr 16 03:26:37 PM PDT 24
Peak memory 305992 kb
Host smart-757d9b53-f974-46dd-a2bb-ea1f7d253c1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533301090 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2533301090
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1751515236
Short name T273
Test name
Test status
Simulation time 152598374265 ps
CPU time 1917.85 seconds
Started Apr 16 03:00:25 PM PDT 24
Finished Apr 16 03:32:24 PM PDT 24
Peak memory 273720 kb
Host smart-81cd029d-835c-4c40-a578-334b22c96311
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751515236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1751515236
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3859718334
Short name T499
Test name
Test status
Simulation time 20203003467 ps
CPU time 212.54 seconds
Started Apr 16 03:00:25 PM PDT 24
Finished Apr 16 03:03:58 PM PDT 24
Peak memory 257344 kb
Host smart-fca2bc9e-f7fd-4c8f-90d5-264d43d20216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38597
18334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3859718334
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2835839004
Short name T591
Test name
Test status
Simulation time 67981195 ps
CPU time 9.87 seconds
Started Apr 16 03:00:23 PM PDT 24
Finished Apr 16 03:00:34 PM PDT 24
Peak memory 249104 kb
Host smart-553bc00c-5deb-4814-ae36-7cb7a8750482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28358
39004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2835839004
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1018315380
Short name T671
Test name
Test status
Simulation time 54123344865 ps
CPU time 2252.89 seconds
Started Apr 16 03:00:24 PM PDT 24
Finished Apr 16 03:37:58 PM PDT 24
Peak memory 286840 kb
Host smart-e9252322-1d9c-4e98-88b3-1c6fa7666e3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018315380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1018315380
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2882637155
Short name T268
Test name
Test status
Simulation time 54351916055 ps
CPU time 1729.98 seconds
Started Apr 16 03:00:29 PM PDT 24
Finished Apr 16 03:29:20 PM PDT 24
Peak memory 281928 kb
Host smart-5b23c958-e415-497b-8392-8fd49dfb1aaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882637155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2882637155
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.650525302
Short name T303
Test name
Test status
Simulation time 26503021640 ps
CPU time 606.79 seconds
Started Apr 16 03:00:24 PM PDT 24
Finished Apr 16 03:10:32 PM PDT 24
Peak memory 248232 kb
Host smart-ae806fc5-ebbc-470a-bd7e-fea126fd24dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650525302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.650525302
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.28208900
Short name T23
Test name
Test status
Simulation time 1042734149 ps
CPU time 34.14 seconds
Started Apr 16 03:00:21 PM PDT 24
Finished Apr 16 03:00:56 PM PDT 24
Peak memory 249020 kb
Host smart-f026e096-0c3c-4c46-9fa0-33dd1a34ef71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28208
900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.28208900
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3966235264
Short name T187
Test name
Test status
Simulation time 659286111 ps
CPU time 38.08 seconds
Started Apr 16 03:00:20 PM PDT 24
Finished Apr 16 03:00:59 PM PDT 24
Peak memory 255632 kb
Host smart-972bcc98-2ed6-468d-875e-44ec0dce7422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39662
35264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3966235264
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.106399415
Short name T676
Test name
Test status
Simulation time 1188007614 ps
CPU time 9.05 seconds
Started Apr 16 03:00:23 PM PDT 24
Finished Apr 16 03:00:33 PM PDT 24
Peak memory 247400 kb
Host smart-a483d2f8-891c-4520-90d8-c36f4abb4dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10639
9415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.106399415
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.946972551
Short name T185
Test name
Test status
Simulation time 566109763 ps
CPU time 36.19 seconds
Started Apr 16 03:00:21 PM PDT 24
Finished Apr 16 03:00:58 PM PDT 24
Peak memory 249176 kb
Host smart-e2c67554-df50-4d59-b229-7d226e609d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94697
2551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.946972551
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1894701220
Short name T76
Test name
Test status
Simulation time 57820459857 ps
CPU time 3269.87 seconds
Started Apr 16 03:00:28 PM PDT 24
Finished Apr 16 03:54:59 PM PDT 24
Peak memory 306236 kb
Host smart-70682fd6-480c-415d-a7fc-545c41cc6483
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894701220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1894701220
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1034611240
Short name T472
Test name
Test status
Simulation time 18698395146 ps
CPU time 1184.21 seconds
Started Apr 16 03:00:30 PM PDT 24
Finished Apr 16 03:20:15 PM PDT 24
Peak memory 281964 kb
Host smart-36459951-7322-4b2e-8a8b-56414bf1a4bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034611240 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1034611240
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2793134952
Short name T198
Test name
Test status
Simulation time 153472140 ps
CPU time 3.68 seconds
Started Apr 16 02:54:58 PM PDT 24
Finished Apr 16 02:55:03 PM PDT 24
Peak memory 249256 kb
Host smart-e9896b09-0abf-44a2-880c-36ed2c7f963e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2793134952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2793134952
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3089986095
Short name T666
Test name
Test status
Simulation time 23636738214 ps
CPU time 1071.23 seconds
Started Apr 16 02:54:58 PM PDT 24
Finished Apr 16 03:12:51 PM PDT 24
Peak memory 289832 kb
Host smart-8d0908cd-4cf0-4578-856f-2f1f699a83dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089986095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3089986095
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3923206766
Short name T657
Test name
Test status
Simulation time 3496941409 ps
CPU time 37.81 seconds
Started Apr 16 02:54:59 PM PDT 24
Finished Apr 16 02:55:38 PM PDT 24
Peak memory 249160 kb
Host smart-b473194b-862e-4e7b-89d6-6680cda7b2fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3923206766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3923206766
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3120284919
Short name T212
Test name
Test status
Simulation time 3128722655 ps
CPU time 121.42 seconds
Started Apr 16 02:55:05 PM PDT 24
Finished Apr 16 02:57:08 PM PDT 24
Peak memory 250136 kb
Host smart-84c8559f-b97b-42d3-9969-48aa2b21867a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31202
84919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3120284919
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3985121844
Short name T583
Test name
Test status
Simulation time 114784661 ps
CPU time 11.14 seconds
Started Apr 16 02:54:54 PM PDT 24
Finished Apr 16 02:55:07 PM PDT 24
Peak memory 248972 kb
Host smart-2a94b8ef-c912-4058-9613-55f8afaba352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39851
21844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3985121844
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2520479880
Short name T309
Test name
Test status
Simulation time 40610272855 ps
CPU time 764.33 seconds
Started Apr 16 02:55:05 PM PDT 24
Finished Apr 16 03:07:50 PM PDT 24
Peak memory 265452 kb
Host smart-6d9e342d-16a3-45fa-a0bd-4bf02d43f597
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520479880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2520479880
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3991571966
Short name T330
Test name
Test status
Simulation time 10992337081 ps
CPU time 425.93 seconds
Started Apr 16 02:54:59 PM PDT 24
Finished Apr 16 03:02:06 PM PDT 24
Peak memory 248384 kb
Host smart-2863c4b0-71ba-4fdd-b513-7fd172889a3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991571966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3991571966
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.409713630
Short name T52
Test name
Test status
Simulation time 373949631 ps
CPU time 25.88 seconds
Started Apr 16 02:54:54 PM PDT 24
Finished Apr 16 02:55:21 PM PDT 24
Peak memory 257204 kb
Host smart-9fff5acd-de53-4558-bea0-54182fd00be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40971
3630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.409713630
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1208333412
Short name T87
Test name
Test status
Simulation time 1136017957 ps
CPU time 65.28 seconds
Started Apr 16 02:54:56 PM PDT 24
Finished Apr 16 02:56:03 PM PDT 24
Peak memory 255696 kb
Host smart-f6d43be6-a96c-415b-8092-9d551cf4c34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12083
33412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1208333412
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1108596089
Short name T400
Test name
Test status
Simulation time 118523390 ps
CPU time 13.33 seconds
Started Apr 16 02:55:00 PM PDT 24
Finished Apr 16 02:55:15 PM PDT 24
Peak memory 254992 kb
Host smart-ddc2b5f1-faf7-43b5-983f-62fe97aef847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11085
96089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1108596089
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1626709143
Short name T458
Test name
Test status
Simulation time 450949809 ps
CPU time 29.03 seconds
Started Apr 16 02:54:55 PM PDT 24
Finished Apr 16 02:55:26 PM PDT 24
Peak memory 249228 kb
Host smart-8d3ef634-070a-455d-9d92-7121435207ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16267
09143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1626709143
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.4119490957
Short name T413
Test name
Test status
Simulation time 1026704005 ps
CPU time 93.14 seconds
Started Apr 16 02:54:57 PM PDT 24
Finished Apr 16 02:56:31 PM PDT 24
Peak memory 257224 kb
Host smart-0ac88648-500d-4554-97e0-5eaa33f67b1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119490957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.4119490957
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2309374054
Short name T195
Test name
Test status
Simulation time 57987656 ps
CPU time 2.38 seconds
Started Apr 16 02:54:58 PM PDT 24
Finished Apr 16 02:55:02 PM PDT 24
Peak memory 249300 kb
Host smart-10f0f148-2d18-4b17-aa08-555504089df5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2309374054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2309374054
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2361528894
Short name T64
Test name
Test status
Simulation time 51814878361 ps
CPU time 2853.91 seconds
Started Apr 16 02:55:02 PM PDT 24
Finished Apr 16 03:42:37 PM PDT 24
Peak memory 289564 kb
Host smart-93a326d7-e907-4024-9b13-5eb9e94addd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361528894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2361528894
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.12864527
Short name T417
Test name
Test status
Simulation time 220385511 ps
CPU time 12.06 seconds
Started Apr 16 02:55:03 PM PDT 24
Finished Apr 16 02:55:16 PM PDT 24
Peak memory 240860 kb
Host smart-94d0b1b9-a579-42c7-9edc-ced58b0d7fc7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=12864527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.12864527
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4027843323
Short name T642
Test name
Test status
Simulation time 12645911405 ps
CPU time 158.04 seconds
Started Apr 16 02:54:59 PM PDT 24
Finished Apr 16 02:57:39 PM PDT 24
Peak memory 257332 kb
Host smart-1abf487f-1520-42cb-a990-acbf5d6d7445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40278
43323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4027843323
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.610447904
Short name T522
Test name
Test status
Simulation time 281448489 ps
CPU time 22.14 seconds
Started Apr 16 02:54:59 PM PDT 24
Finished Apr 16 02:55:23 PM PDT 24
Peak memory 255888 kb
Host smart-4f0b8de0-e1c7-4e5c-a70b-dab4a74d27fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61044
7904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.610447904
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1157539078
Short name T292
Test name
Test status
Simulation time 52062986528 ps
CPU time 795.73 seconds
Started Apr 16 02:54:59 PM PDT 24
Finished Apr 16 03:08:17 PM PDT 24
Peak memory 268568 kb
Host smart-6f7c0337-15b4-4ad0-8d10-0b549ca85c48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157539078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1157539078
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2459655631
Short name T275
Test name
Test status
Simulation time 112745877680 ps
CPU time 1519.3 seconds
Started Apr 16 02:55:01 PM PDT 24
Finished Apr 16 03:20:22 PM PDT 24
Peak memory 272316 kb
Host smart-75daaec8-584d-494c-923c-3ec11623930f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459655631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2459655631
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.4130885828
Short name T327
Test name
Test status
Simulation time 3733137060 ps
CPU time 78.32 seconds
Started Apr 16 02:54:57 PM PDT 24
Finished Apr 16 02:56:17 PM PDT 24
Peak memory 248344 kb
Host smart-56355683-ebf8-4dd8-a4af-038664c47349
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130885828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.4130885828
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2418010195
Short name T415
Test name
Test status
Simulation time 695875780 ps
CPU time 42.67 seconds
Started Apr 16 02:55:01 PM PDT 24
Finished Apr 16 02:55:45 PM PDT 24
Peak memory 248988 kb
Host smart-dd8e0ca1-daa0-47ea-9adf-a85d27ecdb07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24180
10195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2418010195
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1566001497
Short name T580
Test name
Test status
Simulation time 273576091 ps
CPU time 18.07 seconds
Started Apr 16 02:54:59 PM PDT 24
Finished Apr 16 02:55:18 PM PDT 24
Peak memory 255744 kb
Host smart-5e2123db-f44e-49d4-8d3d-d6b976e12f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15660
01497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1566001497
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2133992917
Short name T555
Test name
Test status
Simulation time 4232994046 ps
CPU time 48.07 seconds
Started Apr 16 02:55:06 PM PDT 24
Finished Apr 16 02:55:55 PM PDT 24
Peak memory 249140 kb
Host smart-5e0ea2c2-8f23-4cfd-bfd3-265958bbc235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21339
92917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2133992917
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.339990815
Short name T627
Test name
Test status
Simulation time 11298019745 ps
CPU time 970.65 seconds
Started Apr 16 02:55:00 PM PDT 24
Finished Apr 16 03:11:12 PM PDT 24
Peak memory 281964 kb
Host smart-ddea6c6b-28dd-4dc2-8c24-ff65d0b79c3f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339990815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.339990815
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2278738858
Short name T200
Test name
Test status
Simulation time 161502721 ps
CPU time 3.64 seconds
Started Apr 16 02:55:10 PM PDT 24
Finished Apr 16 02:55:15 PM PDT 24
Peak memory 249232 kb
Host smart-8ad739dd-0dd0-4532-a9fe-222b2db5ab7f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2278738858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2278738858
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3289895486
Short name T532
Test name
Test status
Simulation time 7326988489 ps
CPU time 528.74 seconds
Started Apr 16 02:55:06 PM PDT 24
Finished Apr 16 03:03:56 PM PDT 24
Peak memory 265660 kb
Host smart-d019c6d2-a62d-470f-b8a9-e0d586d23a9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289895486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3289895486
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2302934544
Short name T510
Test name
Test status
Simulation time 1387547743 ps
CPU time 16.2 seconds
Started Apr 16 02:55:07 PM PDT 24
Finished Apr 16 02:55:24 PM PDT 24
Peak memory 240848 kb
Host smart-84357d9b-827e-4ffd-a779-f84e20958f30
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2302934544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2302934544
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2510325443
Short name T396
Test name
Test status
Simulation time 20035658000 ps
CPU time 253.14 seconds
Started Apr 16 02:55:05 PM PDT 24
Finished Apr 16 02:59:19 PM PDT 24
Peak memory 255856 kb
Host smart-98bbc2e5-aa11-457a-bf57-c53ded573f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25103
25443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2510325443
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1573827308
Short name T581
Test name
Test status
Simulation time 2591337349 ps
CPU time 33.68 seconds
Started Apr 16 02:55:07 PM PDT 24
Finished Apr 16 02:55:41 PM PDT 24
Peak memory 256344 kb
Host smart-a5d780c1-2b77-433d-858a-a0769b3f5775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15738
27308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1573827308
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1136280030
Short name T485
Test name
Test status
Simulation time 149802989305 ps
CPU time 2076.22 seconds
Started Apr 16 02:55:12 PM PDT 24
Finished Apr 16 03:29:49 PM PDT 24
Peak memory 271276 kb
Host smart-2770710c-a9c9-4008-8f47-979721ea9087
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136280030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1136280030
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3082031996
Short name T540
Test name
Test status
Simulation time 4216886298 ps
CPU time 156.8 seconds
Started Apr 16 02:55:03 PM PDT 24
Finished Apr 16 02:57:41 PM PDT 24
Peak memory 248216 kb
Host smart-7d1e73ce-83b5-4d16-bdec-9aff4d793876
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082031996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3082031996
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.741241731
Short name T218
Test name
Test status
Simulation time 905073792 ps
CPU time 43.17 seconds
Started Apr 16 02:55:05 PM PDT 24
Finished Apr 16 02:55:49 PM PDT 24
Peak memory 256292 kb
Host smart-f87034d7-c0a1-4daf-ad88-152dfc9e9cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74124
1731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.741241731
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2665807829
Short name T96
Test name
Test status
Simulation time 657135633 ps
CPU time 26.16 seconds
Started Apr 16 02:55:04 PM PDT 24
Finished Apr 16 02:55:31 PM PDT 24
Peak memory 254916 kb
Host smart-a69209a4-bcfd-4273-ae2f-81cdfb65de94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26658
07829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2665807829
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2389398613
Short name T574
Test name
Test status
Simulation time 2825369406 ps
CPU time 49.17 seconds
Started Apr 16 02:55:07 PM PDT 24
Finished Apr 16 02:55:57 PM PDT 24
Peak memory 249176 kb
Host smart-4f3a75ca-a784-44f8-a73c-322af7e2d32e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23893
98613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2389398613
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1719090200
Short name T433
Test name
Test status
Simulation time 151626155869 ps
CPU time 2097.52 seconds
Started Apr 16 02:55:05 PM PDT 24
Finished Apr 16 03:30:04 PM PDT 24
Peak memory 289736 kb
Host smart-e43148ae-ec41-4439-9d67-e376b60bd60d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719090200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1719090200
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.576996198
Short name T457
Test name
Test status
Simulation time 30438329848 ps
CPU time 1269.31 seconds
Started Apr 16 02:55:12 PM PDT 24
Finished Apr 16 03:16:23 PM PDT 24
Peak memory 281684 kb
Host smart-66d5d0bb-78f3-4c71-b95d-323f604e20c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576996198 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.576996198
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1759833650
Short name T205
Test name
Test status
Simulation time 131111222 ps
CPU time 2.51 seconds
Started Apr 16 02:55:13 PM PDT 24
Finished Apr 16 02:55:17 PM PDT 24
Peak memory 249340 kb
Host smart-a546ce01-5066-41d7-bd28-73d4f7c2479f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1759833650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1759833650
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.161521922
Short name T182
Test name
Test status
Simulation time 90165559 ps
CPU time 5.76 seconds
Started Apr 16 02:55:09 PM PDT 24
Finished Apr 16 02:55:15 PM PDT 24
Peak memory 240836 kb
Host smart-3dcd9899-48a3-4dcc-8b8c-c37f9a6d2fe6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=161521922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.161521922
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1740934476
Short name T503
Test name
Test status
Simulation time 550657780 ps
CPU time 31.91 seconds
Started Apr 16 02:55:09 PM PDT 24
Finished Apr 16 02:55:42 PM PDT 24
Peak memory 255968 kb
Host smart-2ba67eb3-7423-40b3-9fe7-53141d6c9104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17409
34476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1740934476
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.295558693
Short name T520
Test name
Test status
Simulation time 149622656 ps
CPU time 16.28 seconds
Started Apr 16 02:55:13 PM PDT 24
Finished Apr 16 02:55:30 PM PDT 24
Peak memory 255696 kb
Host smart-f26ca17b-f49c-4ce4-a699-b022fe0fdced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29555
8693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.295558693
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1436480317
Short name T333
Test name
Test status
Simulation time 48623608980 ps
CPU time 1282.41 seconds
Started Apr 16 02:55:12 PM PDT 24
Finished Apr 16 03:16:35 PM PDT 24
Peak memory 288860 kb
Host smart-f541135d-fc64-40b5-b2b1-e646474471ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436480317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1436480317
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.224390924
Short name T435
Test name
Test status
Simulation time 15081497924 ps
CPU time 600.27 seconds
Started Apr 16 02:55:12 PM PDT 24
Finished Apr 16 03:05:14 PM PDT 24
Peak memory 265764 kb
Host smart-1b4f6025-d71d-4899-8626-2cd788a1f233
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224390924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.224390924
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2187496800
Short name T650
Test name
Test status
Simulation time 2527876359 ps
CPU time 107.23 seconds
Started Apr 16 02:55:10 PM PDT 24
Finished Apr 16 02:56:58 PM PDT 24
Peak memory 247216 kb
Host smart-028e7f1c-c589-49f8-ab6b-dc1405aac624
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187496800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2187496800
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.535588546
Short name T573
Test name
Test status
Simulation time 284122798 ps
CPU time 18.48 seconds
Started Apr 16 02:55:10 PM PDT 24
Finished Apr 16 02:55:29 PM PDT 24
Peak memory 256252 kb
Host smart-d4a23b6a-3087-4e27-bcb3-3cd6d98d5825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53558
8546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.535588546
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.113820386
Short name T276
Test name
Test status
Simulation time 234197304 ps
CPU time 18.57 seconds
Started Apr 16 02:55:12 PM PDT 24
Finished Apr 16 02:55:32 PM PDT 24
Peak memory 247952 kb
Host smart-bb944873-bf90-474c-ae5b-6bab617462bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11382
0386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.113820386
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.4223438658
Short name T549
Test name
Test status
Simulation time 481312294 ps
CPU time 30.96 seconds
Started Apr 16 02:55:12 PM PDT 24
Finished Apr 16 02:55:44 PM PDT 24
Peak memory 255784 kb
Host smart-2b9ed682-e662-47dc-9b68-860f30951e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42234
38658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.4223438658
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1979693651
Short name T564
Test name
Test status
Simulation time 1500166356 ps
CPU time 22.37 seconds
Started Apr 16 02:55:12 PM PDT 24
Finished Apr 16 02:55:35 PM PDT 24
Peak memory 255772 kb
Host smart-df7cbceb-d0d0-4ea2-8a1e-38009384e86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19796
93651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1979693651
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3842766177
Short name T241
Test name
Test status
Simulation time 55928547700 ps
CPU time 3015.47 seconds
Started Apr 16 02:55:14 PM PDT 24
Finished Apr 16 03:45:31 PM PDT 24
Peak memory 289144 kb
Host smart-40d48c1d-b47a-43bf-864a-843965ec9886
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842766177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3842766177
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.65347727
Short name T192
Test name
Test status
Simulation time 44385775 ps
CPU time 3.57 seconds
Started Apr 16 02:55:17 PM PDT 24
Finished Apr 16 02:55:23 PM PDT 24
Peak memory 249312 kb
Host smart-afc97dcc-2769-4455-8532-2e74bec3badd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=65347727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.65347727
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3755495579
Short name T478
Test name
Test status
Simulation time 9115589952 ps
CPU time 880.63 seconds
Started Apr 16 02:55:10 PM PDT 24
Finished Apr 16 03:09:52 PM PDT 24
Peak memory 270900 kb
Host smart-87bcee6c-20c1-4cf3-bcb8-c630b4cc619d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755495579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3755495579
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1943127517
Short name T448
Test name
Test status
Simulation time 1426711415 ps
CPU time 61.3 seconds
Started Apr 16 02:55:16 PM PDT 24
Finished Apr 16 02:56:19 PM PDT 24
Peak memory 249040 kb
Host smart-db31fa3f-de7d-4aea-84c6-53a3c410e62b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1943127517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1943127517
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.416251045
Short name T19
Test name
Test status
Simulation time 2045958379 ps
CPU time 169.84 seconds
Started Apr 16 02:55:09 PM PDT 24
Finished Apr 16 02:58:00 PM PDT 24
Peak memory 256760 kb
Host smart-8e8a9454-7525-44c3-87ed-f0a9e7272a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41625
1045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.416251045
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3859877164
Short name T231
Test name
Test status
Simulation time 198523115 ps
CPU time 11.41 seconds
Started Apr 16 02:55:13 PM PDT 24
Finished Apr 16 02:55:26 PM PDT 24
Peak memory 253092 kb
Host smart-617b9ab8-311b-4cbd-b0f5-3b48304129cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38598
77164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3859877164
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.27900310
Short name T609
Test name
Test status
Simulation time 59654577634 ps
CPU time 1037.96 seconds
Started Apr 16 02:55:16 PM PDT 24
Finished Apr 16 03:12:36 PM PDT 24
Peak memory 282272 kb
Host smart-3c4cf5d3-bbc2-4af6-9ead-1a2e3e6bb038
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27900310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.27900310
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.761377541
Short name T432
Test name
Test status
Simulation time 36904545581 ps
CPU time 2230.7 seconds
Started Apr 16 02:55:15 PM PDT 24
Finished Apr 16 03:32:28 PM PDT 24
Peak memory 288316 kb
Host smart-4f8e74e5-cda9-42da-8190-fa83db6a8bfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761377541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.761377541
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.134131636
Short name T482
Test name
Test status
Simulation time 491676669 ps
CPU time 28.3 seconds
Started Apr 16 02:55:14 PM PDT 24
Finished Apr 16 02:55:44 PM PDT 24
Peak memory 249044 kb
Host smart-bf131966-7193-4493-b283-937b1b9dd91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13413
1636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.134131636
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3501167481
Short name T699
Test name
Test status
Simulation time 239439110 ps
CPU time 9.65 seconds
Started Apr 16 02:55:13 PM PDT 24
Finished Apr 16 02:55:24 PM PDT 24
Peak memory 249444 kb
Host smart-fb71a76e-773a-4f2c-b1f7-144446203534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35011
67481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3501167481
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3800094806
Short name T270
Test name
Test status
Simulation time 1255600232 ps
CPU time 19.55 seconds
Started Apr 16 02:55:14 PM PDT 24
Finished Apr 16 02:55:36 PM PDT 24
Peak memory 249040 kb
Host smart-5e85c594-0cf6-4054-9c41-ced77bfe15c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38000
94806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3800094806
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3921953973
Short name T589
Test name
Test status
Simulation time 276774332 ps
CPU time 21.32 seconds
Started Apr 16 02:55:11 PM PDT 24
Finished Apr 16 02:55:33 PM PDT 24
Peak memory 249004 kb
Host smart-05cfe7d7-aaf0-4ae6-a5d5-7238bad99151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39219
53973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3921953973
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1168031011
Short name T440
Test name
Test status
Simulation time 130517517878 ps
CPU time 1954.44 seconds
Started Apr 16 02:55:15 PM PDT 24
Finished Apr 16 03:27:52 PM PDT 24
Peak memory 289672 kb
Host smart-3051ec90-d426-425b-b603-2467385d9644
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168031011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1168031011
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2433851474
Short name T221
Test name
Test status
Simulation time 276309226120 ps
CPU time 5322.21 seconds
Started Apr 16 02:55:17 PM PDT 24
Finished Apr 16 04:24:02 PM PDT 24
Peak memory 305924 kb
Host smart-b9a08dd9-7923-47a1-9b86-0d6d5e5e4767
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433851474 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2433851474
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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