Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	83606	1			T4	6		T5	10		T9	7
class_i[0x1]	59348	1			T6	1		T9	1		T83	8
class_i[0x2]	42821	1			T4	4277		T5	21		T26	10
class_i[0x3]	50118	1			T9	3		T83	1		T17	583

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	54440	1			T4	1122		T5	7		T9	2
alert[0x1]	63605	1			T4	1028		T5	12		T6	1
alert[0x2]	57070	1			T4	1081		T5	5		T9	4
alert[0x3]	60778	1			T4	1052		T5	7		T83	3

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

235605

1

T4

4283

T5

21

T9

7

esc_ping_fail

288

1

T5

10

T6

1

T9

4

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	54352	1			T4	1122		T5	4		T9	1
esc_integrity_fail	alert[0x1]	63525	1			T4	1028		T5	8		T9	3
esc_integrity_fail	alert[0x2]	57014	1			T4	1081		T5	4		T9	3
esc_integrity_fail	alert[0x3]	60714	1			T4	1052		T5	5		T83	1
esc_ping_fail	alert[0x0]	88	1			T5	3		T9	1		T83	3
esc_ping_fail	alert[0x1]	80	1			T5	4		T6	1		T9	2
esc_ping_fail	alert[0x2]	56	1			T5	1		T9	1		T83	1
esc_ping_fail	alert[0x3]	64	1			T5	2		T83	2		T26	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	83504	1			T4	6		T9	7		T83	3
esc_integrity_fail	class_i[0x1]	59281	1			T83	1		T20	1781		T25	9
esc_integrity_fail	class_i[0x2]	42752	1			T4	4277		T5	21		T26	10
esc_integrity_fail	class_i[0x3]	50068	1			T17	583		T102	22		T15	1314
esc_ping_fail	class_i[0x0]	102	1			T5	10		T83	1		T91	2
esc_ping_fail	class_i[0x1]	67	1			T6	1		T9	1		T83	7
esc_ping_fail	class_i[0x2]	69	1			T326	1		T333	1		T318	4
esc_ping_fail	class_i[0x3]	50	1			T9	3		T83	1		T288	1