Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	685210656	0	0	625
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	685210656	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	685210656	685050575	0	0
tb.dut.CheckAccuCntDw	0	0	625	625	0	0
tb.dut.CheckEscCntDw	0	0	625	625	0	0
tb.dut.CheckNAlerts	0	0	625	625	0	0
tb.dut.CheckNClasses	0	0	625	625	0	0
tb.dut.CheckNEscSev	0	0	625	625	0	0
tb.dut.CrashdumpKnownO_A	0	0	685210656	685050575	0	0
tb.dut.EdnKnownO_A	0	0	685210656	685050575	0	0
tb.dut.EscPKnownO_A	0	0	685210656	685050575	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	685210656	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	685210656	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	685210656	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	685210656	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	685210656	70	0	0
tb.dut.IrqAKnownO_A	0	0	685210656	685050575	0	0
tb.dut.IrqBKnownO_A	0	0	685210656	685050575	0	0
tb.dut.IrqCKnownO_A	0	0	685210656	685050575	0	0
tb.dut.IrqDKnownO_A	0	0	685210656	685050575	0	0
tb.dut.TlAReadyKnownO_A	0	0	685210656	685050575	0	0
tb.dut.TlDValidKnownO_A	0	0	685210656	685050575	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	709215064	3029807	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	709215064	14251	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	709215064	14547	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	709215064	14524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	709215064	14449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	709215064	14580	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	709215064	14786	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	709215064	14569	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	709215064	14482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	709215064	14399	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	709215064	14085	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	709215064	14339	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	709215064	14295	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	709215064	14662	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	709215064	14461	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	709215064	14593	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	709215064	13929	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	709215064	14219	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	709215064	14258	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	709215064	14059	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	709215064	14193	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	709215064	14298	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	709215064	14225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	709215064	14366	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	709215064	14605	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	709215064	14019	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	709215064	14072	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	709215064	14627	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	709215064	14522	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	709215064	14169	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	709215064	14631	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	709215064	14459	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	709215064	14247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	709215064	14376	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	709215064	14433	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	709215064	14625	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	709215064	14320	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	709215064	14223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	709215064	14211	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	709215064	14734	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	709215064	14439	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	709215064	14230	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	709215064	13861	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	709215064	14576	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	709215064	14275	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	709215064	14586	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	709215064	14278	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	709215064	14655	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	709215064	14350	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	709215064	14235	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	709215064	14228	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	709215064	14239	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	709215064	14503	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	709215064	14371	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	709215064	14869	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	709215064	14157	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	709215064	14375	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	709215064	14694	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	709215064	14248	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	709215064	14435	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	709215064	14102	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	709215064	14185	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	709215064	14442	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	709215064	14606	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	709215064	14589	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	709215064	14389	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	709215064	14193	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	709215064	14149	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	709215064	14792	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	709215064	14566	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	709215064	29132	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	709215064	14793	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	709215064	14011	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	709215064	14606	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	709215064	14543	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	709215064	14926	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	709215064	14468	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	709215064	14427	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	709215064	14101	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	685210656	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	685210656	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	685210656	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	685210656	2904	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	685210656	232781	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	685210656	368825656	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	685210656	221	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	685210656	818	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	685210656	45	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	685210656	415	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	685076009	275600842	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	685210656	911	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	685210656	898	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	685210656	877	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	685210656	858	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	685210656	644	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	685210656	67349	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	685210656	529	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	685210656	70	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	685210656	1267	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	685210656	1057	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	685210656	685050575	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	685210656	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	685210656	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	685210656	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	685210656	5694	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	685210656	178341	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	685210656	393030659	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	685210656	199	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	685210656	482	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	685210656	29	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	685210656	238	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	685076009	322611192	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	685210656	568	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	685210656	557	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	685210656	545	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	685210656	541	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	685210656	880	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	685210656	94125	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	685210656	781	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	685210656	68	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	685210656	1295	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	685210656	1085	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	685210656	685050575	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	685210656	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	685210656	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	685210656	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	685210656	3250	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	685210656	156919	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	685210656	427289060	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	685210656	253	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	685210656	428	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	685210656	27	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	685210656	180	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	685076009	345705159	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	685210656	498	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	685210656	495	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	685210656	490	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	685210656	483	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	685210656	821	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	685210656	106889	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	685210656	740	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	685210656	54	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	685210656	1236	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	685210656	1026	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	685210656	685050575	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	685210656	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	685210656	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	685210656	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	685210656	2714	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	685210656	191893	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	685210656	413846513	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	685210656	290	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	685210656	441	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	685210656	24	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	685210656	197	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	685076009	315177258	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	685210656	518	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	685210656	514	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	685210656	508	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	685210656	497	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	685210656	781	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	685210656	81900	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	685210656	693	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	685210656	61	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	685210656	1315	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	685210656	1105	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	685210656	685050575	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	709215064	129965657	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	709215064	708575608	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	709215064	708575608	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	709215064	179502005	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	709215064	708575608	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	709215064	708575608	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
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tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
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tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0

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