Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	140	1			T8	1		T20	1		T15	3
index[0x1]	176	1			T3	1		T46	1		T26	3
index[0x2]	202	1			T46	1		T29	1		T66	1
index[0x3]	152	1			T1	1		T3	1		T20	2

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	212	1			T3	1		T46	1		T25	2
lens_less_than_1000[1]	106	1			T20	1		T26	1		T49	1
lens_less_than_1000[2]	97	1			T17	1		T26	1		T66	1
lens_less_than_1000[3]	80	1			T20	2		T32	1		T30	1
lens_less_than_1000[4]	66	1			T1	1		T26	1		T15	1
lens_less_than_1000[5]	40	1			T86	1		T75	2		T28	1
lens_less_than_1000[6]	24	1			T32	2		T80	1		T285	2
lens_less_than_1000[7]	15	1			T3	1		T8	1		T46	1
lens_less_than_1000[8]	11	1			T80	1		T98	1		T105	1
lens_less_than_1000[9]	8	1			T32	2		T92	1		T118	1
len_2	11	1			T74	1		T286	2		T287	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	46	1			T15	2		T288	1		T249	1
index[0x0]	lens_less_than_1000[1]	20	1			T20	1		T50	1		T55	1
index[0x0]	lens_less_than_1000[2]	19	1			T88	1		T289	1		T290	1
index[0x0]	lens_less_than_1000[3]	22	1			T32	1		T118	1		T291	1
index[0x0]	lens_less_than_1000[4]	13	1			T15	1		T16	1		T292	1
index[0x0]	lens_less_than_1000[5]	9	1			T75	1		T293	1		T294	1
index[0x0]	lens_less_than_1000[6]	6	1			T285	1		T98	1		T198	1
index[0x0]	lens_less_than_1000[7]	1	1			T8	1		-	-		-	-
index[0x0]	lens_less_than_1000[8]	2	1			T295	1		T263	1		-	-
index[0x0]	len_2	2	1			T100	2		-	-		-	-
index[0x1]	lens_less_than_1000[0]	50	1			T85	1		T16	3		T31	2
index[0x1]	lens_less_than_1000[1]	27	1			T26	1		T72	1		T80	1
index[0x1]	lens_less_than_1000[2]	38	1			T26	1		T249	1		T296	1
index[0x1]	lens_less_than_1000[3]	17	1			T104	1		T120	2		T295	1
index[0x1]	lens_less_than_1000[4]	19	1			T26	1		T80	1		T31	1
index[0x1]	lens_less_than_1000[5]	7	1			T86	1		T112	1		T283	1
index[0x1]	lens_less_than_1000[6]	6	1			T80	1		T297	1		T298	1
index[0x1]	lens_less_than_1000[7]	7	1			T3	1		T46	1		T299	1
index[0x1]	lens_less_than_1000[8]	3	1			T98	1		T105	1		T300	1
index[0x1]	lens_less_than_1000[9]	1	1			T32	1		-	-		-	-
index[0x1]	len_2	1	1			T301	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	71	1			T46	1		T29	1		T31	5
index[0x2]	lens_less_than_1000[1]	33	1			T49	1		T32	1		T31	1
index[0x2]	lens_less_than_1000[2]	24	1			T66	1		T80	1		T302	1
index[0x2]	lens_less_than_1000[3]	19	1			T43	2		T120	1		T295	7
index[0x2]	lens_less_than_1000[4]	17	1			T32	1		T16	1		T118	1
index[0x2]	lens_less_than_1000[5]	14	1			T108	1		T130	1		T111	1
index[0x2]	lens_less_than_1000[6]	9	1			T32	1		T89	1		T60	1
index[0x2]	lens_less_than_1000[7]	5	1			T303	1		T130	1		T193	1
index[0x2]	lens_less_than_1000[8]	3	1			T80	1		T304	1		T305	1
index[0x2]	lens_less_than_1000[9]	2	1			T118	1		T306	1		-	-
index[0x2]	len_2	5	1			T74	1		T125	1		T122	1
index[0x3]	lens_less_than_1000[0]	45	1			T3	1		T25	2		T15	1
index[0x3]	lens_less_than_1000[1]	26	1			T32	2		T235	1		T55	1
index[0x3]	lens_less_than_1000[2]	16	1			T17	1		T31	1		T75	1
index[0x3]	lens_less_than_1000[3]	22	1			T20	2		T30	1		T74	1
index[0x3]	lens_less_than_1000[4]	17	1			T1	1		T51	1		T96	1
index[0x3]	lens_less_than_1000[5]	10	1			T75	1		T28	1		T121	1
index[0x3]	lens_less_than_1000[6]	3	1			T32	1		T285	1		T111	1
index[0x3]	lens_less_than_1000[7]	2	1			T101	1		T265	1		-	-
index[0x3]	lens_less_than_1000[8]	3	1			T265	1		T307	1		T308	1
index[0x3]	lens_less_than_1000[9]	5	1			T32	1		T92	1		T309	2
index[0x3]	len_2	3	1			T286	2		T287	1		-	-