Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	70	1			T15	2		T86	1		T81	1
class_index[0x1]	68	1			T14	1		T15	3		T16	1
class_index[0x2]	54	1			T15	4		T93	1		T89	3
class_index[0x3]	61	1			T20	4		T17	1		T15	4

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	98	1			T20	4		T14	1		T15	2
intr_timeout_cnt[1]	49	1			T15	6		T86	1		T31	1
intr_timeout_cnt[2]	21	1			T81	1		T89	2		T99	1
intr_timeout_cnt[3]	20	1			T17	1		T15	3		T80	1
intr_timeout_cnt[4]	18	1			T15	2		T92	2		T89	1
intr_timeout_cnt[5]	14	1			T50	1		T94	1		T57	1
intr_timeout_cnt[6]	7	1			T61	1		T261	1		T262	1
intr_timeout_cnt[7]	7	1			T89	1		T106	1		T263	1
intr_timeout_cnt[8]	13	1			T92	1		T94	1		T261	1
intr_timeout_cnt[9]	6	1			T95	1		T98	1		T100	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[6]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T88	1		T31	3		T50	1
class_index[0x0]	intr_timeout_cnt[1]	12	1			T15	1		T86	1		T98	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T81	1		T99	1		T264	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T15	1		T120	1		T18	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T92	1		T265	2		T266	1
class_index[0x0]	intr_timeout_cnt[5]	7	1			T50	1		T267	2		T106	1
class_index[0x0]	intr_timeout_cnt[7]	2	1			T106	1		T111	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T94	1		T268	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T265	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	25	1			T14	1		T16	1		T31	1
class_index[0x1]	intr_timeout_cnt[1]	17	1			T15	2		T31	1		T99	1
class_index[0x1]	intr_timeout_cnt[2]	3	1			T269	1		T270	1		T271	1
class_index[0x1]	intr_timeout_cnt[3]	7	1			T80	1		T267	1		T272	1
class_index[0x1]	intr_timeout_cnt[4]	5	1			T15	1		T105	1		T261	1
class_index[0x1]	intr_timeout_cnt[5]	1	1			T57	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	4	1			T61	1		T250	1		T251	2
class_index[0x1]	intr_timeout_cnt[7]	3	1			T263	1		T273	1		T274	1
class_index[0x1]	intr_timeout_cnt[8]	3	1			T92	1		T261	1		T264	1
class_index[0x2]	intr_timeout_cnt[0]	18	1			T93	1		T89	1		T117	1
class_index[0x2]	intr_timeout_cnt[1]	8	1			T15	1		T275	1		T271	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T276	1		T277	1		T278	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T15	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	8	1			T15	1		T89	1		T101	3
class_index[0x2]	intr_timeout_cnt[5]	4	1			T94	1		T116	1		T265	1
class_index[0x2]	intr_timeout_cnt[6]	3	1			T261	1		T262	1		T196	1
class_index[0x2]	intr_timeout_cnt[7]	1	1			T89	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T268	1		T264	1		T111	1
class_index[0x2]	intr_timeout_cnt[9]	4	1			T95	1		T100	1		T115	1
class_index[0x3]	intr_timeout_cnt[0]	25	1			T20	4		T15	2		T86	1
class_index[0x3]	intr_timeout_cnt[1]	12	1			T15	2		T42	1		T113	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T89	2		T107	1		T279	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T17	1		T264	2		T276	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T92	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	2	1			T280	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T281	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	5	1			T282	1		T283	1		T284	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T98	1		-	-		-	-