Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	340122	1			T1	17		T2	1599		T3	37
all_values[1]	340122	1			T1	17		T2	1599		T3	37
all_values[2]	340122	1			T1	17		T2	1599		T3	37
all_values[3]	340122	1			T1	17		T2	1599		T3	37

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

676848

1

T1

37

T2

3230

T3

87

auto[1]

683640

1

T1

31

T2

3166

T3

61

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

814167

1

T1

36

T2

3236

T3

76

auto[1]

546321

1

T1

32

T2

3160

T3

72

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97716	1			T1	3		T2	408		T3	7
all_values[0]	auto[0]	auto[1]	72051	1			T1	3		T2	403		T3	7
all_values[0]	auto[1]	auto[0]	98546	1			T1	6		T2	396		T3	12
all_values[0]	auto[1]	auto[1]	71809	1			T1	5		T2	392		T3	11
all_values[1]	auto[0]	auto[0]	103140	1			T1	6		T2	419		T3	11
all_values[1]	auto[0]	auto[1]	66318	1			T1	5		T2	402		T3	10
all_values[1]	auto[1]	auto[0]	104623	1			T1	3		T2	397		T3	8
all_values[1]	auto[1]	auto[1]	66041	1			T1	3		T2	381		T3	8
all_values[2]	auto[0]	auto[0]	102265	1			T1	5		T2	401		T3	12
all_values[2]	auto[0]	auto[1]	66732	1			T1	5		T2	391		T3	11
all_values[2]	auto[1]	auto[0]	103766	1			T1	4		T2	414		T3	7
all_values[2]	auto[1]	auto[1]	67359	1			T1	3		T2	393		T3	7
all_values[3]	auto[0]	auto[0]	100887	1			T1	5		T2	404		T3	15
all_values[3]	auto[0]	auto[1]	67739	1			T1	5		T2	402		T3	14
all_values[3]	auto[1]	auto[0]	103224	1			T1	4		T2	397		T3	4
all_values[3]	auto[1]	auto[1]	68272	1			T1	3		T2	396		T3	4