Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	340122	1			T1	17		T2	1599		T3	37
all_pins[1]	340122	1			T1	17		T2	1599		T3	37
all_pins[2]	340122	1			T1	17		T2	1599		T3	37
all_pins[3]	340122	1			T1	17		T2	1599		T3	37

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1087007	1			T1	54		T2	4834		T3	118
values[0x1]	273481	1			T1	14		T2	1562		T3	30
transitions[0x0=>0x1]	181895	1			T1	11		T2	992		T3	19
transitions[0x1=>0x0]	182152	1			T1	11		T2	993		T3	20

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	268313	1			T1	12		T2	1207		T3	26
all_pins[0]	values[0x1]	71809	1			T1	5		T2	392		T3	11
all_pins[0]	transitions[0x0=>0x1]	71207	1			T1	5		T2	391		T3	10
all_pins[0]	transitions[0x1=>0x0]	67927	1			T1	3		T2	396		T3	4
all_pins[1]	values[0x0]	274081	1			T1	14		T2	1218		T3	29
all_pins[1]	values[0x1]	66041	1			T1	3		T2	381		T3	8
all_pins[1]	transitions[0x0=>0x1]	35797	1			T1	1		T2	181		T3	4
all_pins[1]	transitions[0x1=>0x0]	41565	1			T1	3		T2	192		T3	7
all_pins[2]	values[0x0]	272763	1			T1	14		T2	1206		T3	30
all_pins[2]	values[0x1]	67359	1			T1	3		T2	393		T3	7
all_pins[2]	transitions[0x0=>0x1]	37226	1			T1	3		T2	208		T3	3
all_pins[2]	transitions[0x1=>0x0]	35908	1			T1	3		T2	196		T3	4
all_pins[3]	values[0x0]	271850	1			T1	14		T2	1203		T3	33
all_pins[3]	values[0x1]	68272	1			T1	3		T2	396		T3	4
all_pins[3]	transitions[0x0=>0x1]	37665	1			T1	2		T2	212		T3	2
all_pins[3]	transitions[0x1=>0x0]	36752	1			T1	2		T2	209		T3	5