Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1			T171	7		T172	7		T173	7
all_values[1]	275	1			T171	7		T172	7		T173	7
all_values[2]	275	1			T171	7		T172	7		T173	7
all_values[3]	275	1			T171	7		T172	7		T173	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

583

1

T171

16

T172

11

T173

13

auto[1]

517

1

T171

12

T172

17

T173

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

435

1

T171

12

T172

8

T173

18

auto[1]

665

1

T171

16

T172

20

T173

10

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

647

1

T171

16

T172

14

T173

20

auto[1]

453

1

T171

12

T172

14

T173

8

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

48

1

T171

1

T355

1

T255

2

all_values[0]

auto[0]

auto[0]

auto[1]

22

1

T171

2

T172

2

T173

1

all_values[0]

auto[0]

auto[1]

auto[0]

41

1

T172

1

T255

1

T356

2

all_values[0]

auto[0]

auto[1]

auto[1]

35

1

T172

1

T173

1

T355

1

all_values[0]

auto[1]

auto[0]

auto[1]

60

1

T171

1

T172

2

T173

2

all_values[0]

auto[1]

auto[1]

auto[1]

69

1

T171

3

T172

1

T173

3

all_values[1]

auto[0]

auto[0]

auto[0]

58

1

T171

1

T172

2

T173

2

all_values[1]

auto[0]

auto[0]

auto[1]

30

1

T171

1

T357

1

T358

1

all_values[1]

auto[0]

auto[1]

auto[0]

50

1

T171

1

T172

1

T173

3

all_values[1]

auto[0]

auto[1]

auto[1]

24

1

T172

2

T255

1

T356

1

all_values[1]

auto[1]

auto[0]

auto[1]

65

1

T171

3

T173

2

T255

1

all_values[1]

auto[1]

auto[1]

auto[1]

48

1

T171

1

T172

2

T247

1

all_values[2]

auto[0]

auto[0]

auto[0]

71

1

T171

4

T173

3

T355

4

all_values[2]

auto[0]

auto[0]

auto[1]

27

1

T171

1

T247

1

T357

1

all_values[2]

auto[0]

auto[1]

auto[0]

55

1

T172

2

T173

4

T247

1

all_values[2]

auto[0]

auto[1]

auto[1]

22

1

T172

1

T255

3

T359

1

all_values[2]

auto[1]

auto[0]

auto[1]

53

1

T171

1

T172

2

T247

1

all_values[2]

auto[1]

auto[1]

auto[1]

47

1

T171

1

T172

2

T255

3

all_values[3]

auto[0]

auto[0]

auto[0]

57

1

T171

1

T173

2

T255

2

all_values[3]

auto[0]

auto[0]

auto[1]

28

1

T247

1

T357

1

T360

1

all_values[3]

auto[0]

auto[1]

auto[0]

55

1

T171

4

T172

2

T173

4

all_values[3]

auto[0]

auto[1]

auto[1]

24

1

T355

1

T255

1

T361

1

all_values[3]

auto[1]

auto[0]

auto[1]

64

1

T172

3

T173

1

T355

2

all_values[3]

auto[1]

auto[1]

auto[1]

47

1

T171

2

T172

2

T247

3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal