Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	85217	1			T22	1114		T20	722		T44	1453
accum_cnt_1000	201371	1			T22	989		T23	96		T20	4387
accum_cnt_100	26253	1			T22	50		T23	31		T20	207
accum_cnt_50	58420	1			T1	12		T3	36		T5	23
accum_cnt_10	183491	1			T1	32		T3	41		T4	2
accum_cnt_0	411326	1			T1	4		T2	4740		T3	31

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	251674	1			T1	12		T2	1185		T3	27
class_index[0x1]	251674	1			T1	12		T2	1185		T3	27
class_index[0x2]	251674	1			T1	12		T2	1185		T3	27
class_index[0x3]	251674	1			T1	12		T2	1185		T3	27

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22815	1			T22	458		T44	426		T29	453
class_index[0x0]	accum_cnt_1000	50386	1			T22	405		T23	43		T20	725
class_index[0x0]	accum_cnt_100	8432	1			T22	22		T23	17		T20	34
class_index[0x0]	accum_cnt_50	14859	1			T1	2		T3	17		T22	18
class_index[0x0]	accum_cnt_10	57607	1			T1	9		T3	8		T5	31
class_index[0x0]	accum_cnt_0	83957	1			T1	1		T2	1185		T3	2
class_index[0x1]	accum_cnt_2000	19834	1			T44	464		T46	617		T29	482
class_index[0x1]	accum_cnt_1000	56299	1			T20	1520		T44	406		T46	578
class_index[0x1]	accum_cnt_100	5824	1			T20	72		T44	25		T46	33
class_index[0x1]	accum_cnt_50	18141	1			T1	4		T20	67		T44	18
class_index[0x1]	accum_cnt_10	38678	1			T1	7		T7	3		T9	18
class_index[0x1]	accum_cnt_0	105179	1			T1	1		T2	1185		T3	27
class_index[0x2]	accum_cnt_2000	19630	1			T22	656		T20	34		T46	484
class_index[0x2]	accum_cnt_1000	43847	1			T22	584		T20	628		T46	472
class_index[0x2]	accum_cnt_100	5934	1			T22	28		T20	16		T17	3
class_index[0x2]	accum_cnt_50	14054	1			T1	2		T5	23		T22	23
class_index[0x2]	accum_cnt_10	42872	1			T1	9		T3	27		T5	18
class_index[0x2]	accum_cnt_0	116933	1			T1	1		T2	1185		T4	1233
class_index[0x3]	accum_cnt_2000	22938	1			T20	688		T44	563		T46	623
class_index[0x3]	accum_cnt_1000	50839	1			T23	53		T20	1514		T44	568
class_index[0x3]	accum_cnt_100	6063	1			T23	14		T20	85		T44	30
class_index[0x3]	accum_cnt_50	11366	1			T1	4		T3	19		T23	15
class_index[0x3]	accum_cnt_10	44334	1			T1	7		T3	6		T4	2
class_index[0x3]	accum_cnt_0	105257	1			T1	1		T2	1185		T3	2