Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	8005	1			T26	1		T102	30		T15	36
alert[0x1]	9063	1			T9	1		T102	229		T15	26
alert[0x2]	2901	1			T20	3		T26	1		T15	2
alert[0x3]	1255	1			T17	25		T25	149		T249	19
alert[0x4]	5812	1			T17	2		T249	7		T31	94
alert[0x5]	7375	1			T83	1		T26	1		T85	5
alert[0x6]	3384	1			T6	1		T102	82		T15	84
alert[0x7]	7338	1			T5	1		T26	1		T25	18
alert[0x8]	6713	1			T20	11		T26	1		T102	399
alert[0x9]	3695	1			T17	1		T91	1		T102	8
alert[0xa]	4847	1			T5	1		T83	2		T20	3
alert[0xb]	7955	1			T83	1		T26	1		T25	127
alert[0xc]	5777	1			T5	1		T20	56		T91	1
alert[0xd]	2665	1			T25	367		T102	36		T15	8
alert[0xe]	4587	1			T25	15		T102	30		T66	290
alert[0xf]	3276	1			T5	3		T9	1		T91	1
alert[0x10]	8037	1			T91	1		T102	19		T249	21
alert[0x11]	3457	1			T26	1		T25	47		T102	105
alert[0x12]	4167	1			T9	1		T26	1		T102	73
alert[0x13]	4267	1			T6	1		T20	7		T102	35
alert[0x14]	4810	1			T5	2		T83	1		T91	1
alert[0x15]	5783	1			T91	1		T25	281		T15	42
alert[0x16]	7071	1			T20	3		T15	2		T66	97
alert[0x17]	4998	1			T102	33		T66	179		T288	1
alert[0x18]	7043	1			T25	57		T102	269		T15	189
alert[0x19]	4050	1			T83	1		T31	687		T313	1
alert[0x1a]	7525	1			T102	12		T15	72		T249	8
alert[0x1b]	4022	1			T9	1		T83	1		T25	26
alert[0x1c]	7065	1			T20	5		T66	1		T314	1
alert[0x1d]	7040	1			T6	1		T25	282		T102	552
alert[0x1e]	14192	1			T9	1		T102	4		T66	38
alert[0x1f]	3308	1			T20	3		T25	170		T288	1
alert[0x20]	2464	1			T6	1		T102	23		T66	92
alert[0x21]	4814	1			T5	1		T83	2		T249	299
alert[0x22]	3781	1			T6	1		T91	1		T31	18
alert[0x23]	4859	1			T26	1		T15	201		T249	450
alert[0x24]	3421	1			T83	1		T20	6		T25	29
alert[0x25]	4388	1			T102	12		T15	119		T31	118
alert[0x26]	4319	1			T5	1		T26	1		T25	83
alert[0x27]	6644	1			T83	1		T20	74		T17	15
alert[0x28]	4630	1			T5	1		T102	1135		T15	1
alert[0x29]	5591	1			T20	27		T26	1		T25	40
alert[0x2a]	9049	1			T5	1		T102	71		T66	101
alert[0x2b]	7532	1			T102	14		T15	3		T50	1
alert[0x2c]	3109	1			T5	1		T25	524		T102	38
alert[0x2d]	2368	1			T25	96		T249	873		T118	64
alert[0x2e]	1534	1			T9	1		T17	28		T91	1
alert[0x2f]	4324	1			T26	1		T25	62		T102	28
alert[0x30]	16332	1			T15	20		T249	13		T31	3144
alert[0x31]	13390	1			T20	13		T102	131		T66	180
alert[0x32]	2506	1			T25	82		T15	6		T66	371
alert[0x33]	14754	1			T6	1		T9	1		T102	257
alert[0x34]	5379	1			T9	1		T17	1		T91	1
alert[0x35]	3816	1			T9	1		T102	1		T66	159
alert[0x36]	12166	1			T5	2		T288	1		T249	10
alert[0x37]	7018	1			T25	55		T249	16		T118	191
alert[0x38]	3319	1			T5	1		T83	1		T40	1
alert[0x39]	2483	1			T5	1		T83	1		T102	19
alert[0x3a]	3879	1			T9	1		T83	1		T20	6
alert[0x3b]	4130	1			T20	8		T25	14		T102	242
alert[0x3c]	5735	1			T83	1		T20	4		T25	564
alert[0x3d]	5106	1			T5	1		T20	168		T91	1
alert[0x3e]	7667	1			T26	1		T66	141		T118	27
alert[0x3f]	5084	1			T25	1154		T102	35		T15	1
alert[0x40]	6127	1			T9	1		T102	1348		T66	44

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	75652	1			T6	1		T20	394		T91	1
class_i[0x1]	95368	1			T6	1		T9	11		T83	14
class_i[0x2]	76620	1			T5	18		T6	4		T83	1
class_i[0x3]	125561	1			T20	3		T26	1		T91	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

372501

1

T20

397

T17

72

T25

6158

alert_ping_fail

700

1

T5

18

T6

6

T9

11

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	7993	1			T102	30		T15	36		T118	52
alert_integrity_fail	alert[0x1]	9057	1			T102	229		T15	26		T66	154
alert_integrity_fail	alert[0x2]	2886	1			T20	3		T15	2		T249	365
alert_integrity_fail	alert[0x3]	1246	1			T17	25		T25	149		T249	19
alert_integrity_fail	alert[0x4]	5801	1			T17	2		T249	7		T31	94
alert_integrity_fail	alert[0x5]	7361	1			T85	5		T15	7		T249	102
alert_integrity_fail	alert[0x6]	3369	1			T102	82		T15	84		T66	12
alert_integrity_fail	alert[0x7]	7324	1			T25	18		T66	1415		T249	1
alert_integrity_fail	alert[0x8]	6699	1			T20	11		T102	399		T66	376
alert_integrity_fail	alert[0x9]	3685	1			T17	1		T102	8		T85	1
alert_integrity_fail	alert[0xa]	4832	1			T20	3		T25	344		T66	2291
alert_integrity_fail	alert[0xb]	7943	1			T25	127		T66	117		T92	44
alert_integrity_fail	alert[0xc]	5765	1			T20	56		T102	55		T249	137
alert_integrity_fail	alert[0xd]	2658	1			T25	367		T102	36		T15	8
alert_integrity_fail	alert[0xe]	4574	1			T25	15		T102	30		T66	290
alert_integrity_fail	alert[0xf]	3267	1			T66	16		T249	40		T80	22
alert_integrity_fail	alert[0x10]	8017	1			T102	19		T249	21		T50	1
alert_integrity_fail	alert[0x11]	3449	1			T25	47		T102	105		T31	14
alert_integrity_fail	alert[0x12]	4159	1			T102	73		T66	23		T51	24
alert_integrity_fail	alert[0x13]	4254	1			T20	7		T102	35		T15	19
alert_integrity_fail	alert[0x14]	4796	1			T102	6		T15	1		T66	76
alert_integrity_fail	alert[0x15]	5770	1			T25	281		T15	42		T249	21
alert_integrity_fail	alert[0x16]	7064	1			T20	3		T15	2		T66	97
alert_integrity_fail	alert[0x17]	4989	1			T102	33		T66	179		T249	29
alert_integrity_fail	alert[0x18]	7032	1			T25	57		T102	269		T15	189
alert_integrity_fail	alert[0x19]	4038	1			T31	687		T51	7		T95	4
alert_integrity_fail	alert[0x1a]	7512	1			T102	12		T15	72		T249	8
alert_integrity_fail	alert[0x1b]	4009	1			T25	26		T66	8		T31	28
alert_integrity_fail	alert[0x1c]	7049	1			T20	5		T66	1		T104	137
alert_integrity_fail	alert[0x1d]	7027	1			T25	282		T102	552		T66	36
alert_integrity_fail	alert[0x1e]	14186	1			T102	4		T66	38		T249	1
alert_integrity_fail	alert[0x1f]	3287	1			T20	3		T25	170		T31	77
alert_integrity_fail	alert[0x20]	2452	1			T102	23		T66	92		T80	20
alert_integrity_fail	alert[0x21]	4799	1			T249	299		T31	241		T89	144
alert_integrity_fail	alert[0x22]	3762	1			T31	18		T118	3		T89	30
alert_integrity_fail	alert[0x23]	4851	1			T15	201		T249	450		T31	422
alert_integrity_fail	alert[0x24]	3412	1			T20	6		T25	29		T102	146
alert_integrity_fail	alert[0x25]	4378	1			T102	12		T15	119		T31	118
alert_integrity_fail	alert[0x26]	4313	1			T25	83		T102	12		T249	15
alert_integrity_fail	alert[0x27]	6636	1			T20	74		T17	15		T102	46
alert_integrity_fail	alert[0x28]	4620	1			T102	1135		T15	1		T66	52
alert_integrity_fail	alert[0x29]	5579	1			T20	27		T25	40		T249	75
alert_integrity_fail	alert[0x2a]	9036	1			T102	71		T66	101		T291	2
alert_integrity_fail	alert[0x2b]	7524	1			T102	14		T15	3		T50	1
alert_integrity_fail	alert[0x2c]	3097	1			T25	524		T102	38		T66	87
alert_integrity_fail	alert[0x2d]	2355	1			T25	96		T249	873		T118	64
alert_integrity_fail	alert[0x2e]	1518	1			T17	28		T31	143		T51	6
alert_integrity_fail	alert[0x2f]	4314	1			T25	62		T102	28		T66	380
alert_integrity_fail	alert[0x30]	16325	1			T15	20		T249	13		T31	3144
alert_integrity_fail	alert[0x31]	13384	1			T20	13		T102	131		T66	180
alert_integrity_fail	alert[0x32]	2499	1			T25	82		T15	6		T66	371
alert_integrity_fail	alert[0x33]	14743	1			T102	257		T249	21		T80	1
alert_integrity_fail	alert[0x34]	5370	1			T17	1		T25	1560		T66	51
alert_integrity_fail	alert[0x35]	3807	1			T102	1		T66	159		T249	44
alert_integrity_fail	alert[0x36]	12159	1			T249	10		T31	265		T50	6
alert_integrity_fail	alert[0x37]	7009	1			T25	55		T249	16		T118	191
alert_integrity_fail	alert[0x38]	3310	1			T89	52		T104	182		T108	51
alert_integrity_fail	alert[0x39]	2477	1			T102	19		T249	16		T31	13
alert_integrity_fail	alert[0x3a]	3867	1			T20	6		T25	12		T66	225
alert_integrity_fail	alert[0x3b]	4121	1			T20	8		T25	14		T102	242
alert_integrity_fail	alert[0x3c]	5728	1			T20	4		T25	564		T15	1
alert_integrity_fail	alert[0x3d]	5097	1			T20	168		T15	20		T249	488
alert_integrity_fail	alert[0x3e]	7660	1			T66	141		T118	27		T315	8
alert_integrity_fail	alert[0x3f]	5080	1			T25	1154		T102	35		T15	1
alert_integrity_fail	alert[0x40]	6121	1			T102	1348		T66	44		T31	21
alert_ping_fail	alert[0x0]	12	1			T26	1		T316	1		T317	2
alert_ping_fail	alert[0x1]	6	1			T9	1		T40	1		T286	1
alert_ping_fail	alert[0x2]	15	1			T26	1		T288	1		T313	1
alert_ping_fail	alert[0x3]	9	1			T318	3		T319	1		T320	1
alert_ping_fail	alert[0x4]	11	1			T38	1		T321	1		T317	1
alert_ping_fail	alert[0x5]	14	1			T83	1		T26	1		T38	1
alert_ping_fail	alert[0x6]	15	1			T6	1		T288	1		T36	1
alert_ping_fail	alert[0x7]	14	1			T5	1		T26	1		T321	1
alert_ping_fail	alert[0x8]	14	1			T26	1		T322	1		T286	1
alert_ping_fail	alert[0x9]	10	1			T91	1		T288	1		T323	1
alert_ping_fail	alert[0xa]	15	1			T5	1		T83	2		T38	1
alert_ping_fail	alert[0xb]	12	1			T83	1		T26	1		T40	1
alert_ping_fail	alert[0xc]	12	1			T5	1		T91	1		T191	1
alert_ping_fail	alert[0xd]	7	1			T313	1		T237	1		T316	1
alert_ping_fail	alert[0xe]	13	1			T27	1		T286	2		T324	1
alert_ping_fail	alert[0xf]	9	1			T5	3		T9	1		T91	1
alert_ping_fail	alert[0x10]	20	1			T91	1		T40	1		T286	4
alert_ping_fail	alert[0x11]	8	1			T26	1		T286	1		T316	1
alert_ping_fail	alert[0x12]	8	1			T9	1		T26	1		T313	1
alert_ping_fail	alert[0x13]	13	1			T6	1		T302	1		T38	1
alert_ping_fail	alert[0x14]	14	1			T5	2		T83	1		T91	1
alert_ping_fail	alert[0x15]	13	1			T91	1		T38	1		T322	1
alert_ping_fail	alert[0x16]	7	1			T36	1		T286	1		T237	1
alert_ping_fail	alert[0x17]	9	1			T288	1		T38	1		T286	1
alert_ping_fail	alert[0x18]	11	1			T314	1		T313	1		T325	1
alert_ping_fail	alert[0x19]	12	1			T83	1		T313	1		T321	2
alert_ping_fail	alert[0x1a]	13	1			T38	1		T40	1		T326	1
alert_ping_fail	alert[0x1b]	13	1			T9	1		T83	1		T36	1
alert_ping_fail	alert[0x1c]	16	1			T314	1		T322	1		T27	1
alert_ping_fail	alert[0x1d]	13	1			T6	1		T286	1		T313	1
alert_ping_fail	alert[0x1e]	6	1			T9	1		T321	1		T297	1
alert_ping_fail	alert[0x1f]	21	1			T288	1		T38	1		T286	1
alert_ping_fail	alert[0x20]	12	1			T6	1		T36	1		T40	1
alert_ping_fail	alert[0x21]	15	1			T5	1		T83	2		T322	1
alert_ping_fail	alert[0x22]	19	1			T6	1		T91	1		T36	2
alert_ping_fail	alert[0x23]	8	1			T26	1		T38	1		T316	1
alert_ping_fail	alert[0x24]	9	1			T83	1		T288	1		T324	1
alert_ping_fail	alert[0x25]	10	1			T326	2		T313	1		T242	1
alert_ping_fail	alert[0x26]	6	1			T5	1		T26	1		T40	1
alert_ping_fail	alert[0x27]	8	1			T83	1		T26	1		T38	1
alert_ping_fail	alert[0x28]	10	1			T5	1		T326	1		T239	1
alert_ping_fail	alert[0x29]	12	1			T26	1		T322	1		T286	1
alert_ping_fail	alert[0x2a]	13	1			T5	1		T288	1		T313	1
alert_ping_fail	alert[0x2b]	8	1			T314	1		T313	1		T293	1
alert_ping_fail	alert[0x2c]	12	1			T5	1		T74	1		T40	1
alert_ping_fail	alert[0x2d]	13	1			T326	1		T322	2		T293	2
alert_ping_fail	alert[0x2e]	16	1			T9	1		T91	1		T40	1
alert_ping_fail	alert[0x2f]	10	1			T26	1		T313	1		T327	2
alert_ping_fail	alert[0x30]	7	1			T38	1		T326	1		T321	1
alert_ping_fail	alert[0x31]	6	1			T324	1		T328	1		T329	1
alert_ping_fail	alert[0x32]	7	1			T288	1		T286	1		T242	1
alert_ping_fail	alert[0x33]	11	1			T6	1		T9	1		T38	2
alert_ping_fail	alert[0x34]	9	1			T9	1		T91	1		T326	1
alert_ping_fail	alert[0x35]	9	1			T9	1		T323	1		T322	1
alert_ping_fail	alert[0x36]	7	1			T5	2		T288	1		T313	1
alert_ping_fail	alert[0x37]	9	1			T322	1		T316	1		T318	1
alert_ping_fail	alert[0x38]	9	1			T5	1		T83	1		T40	1
alert_ping_fail	alert[0x39]	6	1			T5	1		T83	1		T326	1
alert_ping_fail	alert[0x3a]	12	1			T9	1		T83	1		T26	1
alert_ping_fail	alert[0x3b]	9	1			T326	1		T322	1		T330	1
alert_ping_fail	alert[0x3c]	7	1			T83	1		T288	1		T313	1
alert_ping_fail	alert[0x3d]	9	1			T5	1		T91	1		T38	1
alert_ping_fail	alert[0x3e]	7	1			T26	1		T326	1		T286	1
alert_ping_fail	alert[0x3f]	4	1			T321	1		T331	1		T332	1
alert_ping_fail	alert[0x40]	6	1			T9	1		T288	1		T317	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	75516	1			T20	394		T25	35		T15	11
alert_integrity_fail	class_i[0x1]	95129	1			T25	6004		T102	5535		T15	349
alert_integrity_fail	class_i[0x2]	76407	1			T17	72		T25	27		T85	8
alert_integrity_fail	class_i[0x3]	125449	1			T20	3		T25	92		T15	4
alert_ping_fail	class_i[0x0]	136	1			T6	1		T91	1		T288	5
alert_ping_fail	class_i[0x1]	239	1			T6	1		T9	11		T83	14
alert_ping_fail	class_i[0x2]	213	1			T5	18		T6	4		T83	1
alert_ping_fail	class_i[0x3]	112	1			T26	1		T91	1		T288	3