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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.64 100.00 100.00 100.00 99.38 99.60


Total test records in report: 830
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T772 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4205491905 Apr 18 01:51:12 PM PDT 24 Apr 18 01:51:21 PM PDT 24 393956346 ps
T155 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1376976132 Apr 18 01:51:08 PM PDT 24 Apr 18 01:53:52 PM PDT 24 9872527968 ps
T163 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3891963705 Apr 18 01:50:35 PM PDT 24 Apr 18 01:55:35 PM PDT 24 4581041313 ps
T159 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.772181973 Apr 18 01:50:29 PM PDT 24 Apr 18 01:53:30 PM PDT 24 5821756042 ps
T773 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2335952873 Apr 18 01:50:46 PM PDT 24 Apr 18 01:50:48 PM PDT 24 6443996 ps
T774 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2333102088 Apr 18 01:51:16 PM PDT 24 Apr 18 01:51:28 PM PDT 24 344452811 ps
T775 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1464429830 Apr 18 01:50:39 PM PDT 24 Apr 18 01:50:53 PM PDT 24 779079645 ps
T776 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3603628445 Apr 18 01:50:31 PM PDT 24 Apr 18 01:50:57 PM PDT 24 335673828 ps
T178 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.556432859 Apr 18 01:51:01 PM PDT 24 Apr 18 01:51:43 PM PDT 24 584829148 ps
T777 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3915113120 Apr 18 01:51:12 PM PDT 24 Apr 18 01:51:18 PM PDT 24 98555083 ps
T157 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1366881177 Apr 18 01:50:42 PM PDT 24 Apr 18 01:54:22 PM PDT 24 1568002115 ps
T778 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3768353381 Apr 18 01:51:17 PM PDT 24 Apr 18 01:51:19 PM PDT 24 15654963 ps
T363 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2483178718 Apr 18 01:50:40 PM PDT 24 Apr 18 01:59:00 PM PDT 24 30171155645 ps
T188 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.821538927 Apr 18 01:50:34 PM PDT 24 Apr 18 01:50:37 PM PDT 24 62279762 ps
T779 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1088229683 Apr 18 01:50:46 PM PDT 24 Apr 18 01:50:48 PM PDT 24 8853406 ps
T780 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3465429256 Apr 18 01:51:10 PM PDT 24 Apr 18 01:51:30 PM PDT 24 272126749 ps
T781 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2741274238 Apr 18 01:50:40 PM PDT 24 Apr 18 01:50:50 PM PDT 24 482653443 ps
T782 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3940856574 Apr 18 01:51:06 PM PDT 24 Apr 18 01:51:08 PM PDT 24 18669173 ps
T783 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2969460288 Apr 18 01:50:39 PM PDT 24 Apr 18 01:51:26 PM PDT 24 2559557871 ps
T784 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.4075905324 Apr 18 01:51:11 PM PDT 24 Apr 18 01:51:13 PM PDT 24 15719512 ps
T785 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1251662257 Apr 18 01:50:45 PM PDT 24 Apr 18 01:51:05 PM PDT 24 215864770 ps
T786 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2087421289 Apr 18 01:50:50 PM PDT 24 Apr 18 01:50:53 PM PDT 24 18226108 ps
T787 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1476154284 Apr 18 01:51:25 PM PDT 24 Apr 18 01:51:28 PM PDT 24 7854071 ps
T162 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1580569555 Apr 18 01:50:44 PM PDT 24 Apr 18 01:56:38 PM PDT 24 15718473970 ps
T147 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1773060433 Apr 18 01:50:51 PM PDT 24 Apr 18 01:54:33 PM PDT 24 2394349871 ps
T174 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.784056586 Apr 18 01:50:29 PM PDT 24 Apr 18 01:51:44 PM PDT 24 909341980 ps
T788 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1863472175 Apr 18 01:50:42 PM PDT 24 Apr 18 01:50:47 PM PDT 24 99315233 ps
T789 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2481316689 Apr 18 01:50:48 PM PDT 24 Apr 18 01:50:54 PM PDT 24 32999043 ps
T180 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3691816923 Apr 18 01:50:35 PM PDT 24 Apr 18 01:51:48 PM PDT 24 5165237217 ps
T790 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.675680149 Apr 18 01:50:44 PM PDT 24 Apr 18 01:50:51 PM PDT 24 263754488 ps
T791 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3724243590 Apr 18 01:51:05 PM PDT 24 Apr 18 01:51:07 PM PDT 24 14956227 ps
T792 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.350698978 Apr 18 01:51:20 PM PDT 24 Apr 18 01:51:22 PM PDT 24 6580665 ps
T793 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3406419123 Apr 18 01:50:36 PM PDT 24 Apr 18 01:50:38 PM PDT 24 20137032 ps
T794 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.693603508 Apr 18 01:50:41 PM PDT 24 Apr 18 01:50:50 PM PDT 24 181329371 ps
T795 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3833864456 Apr 18 01:50:40 PM PDT 24 Apr 18 01:50:42 PM PDT 24 35349689 ps
T796 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3986924427 Apr 18 01:50:38 PM PDT 24 Apr 18 01:50:43 PM PDT 24 48897423 ps
T797 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2322321949 Apr 18 01:50:39 PM PDT 24 Apr 18 01:50:47 PM PDT 24 93190140 ps
T798 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1006323526 Apr 18 01:50:42 PM PDT 24 Apr 18 01:50:52 PM PDT 24 702374898 ps
T799 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2422714610 Apr 18 01:50:48 PM PDT 24 Apr 18 01:50:50 PM PDT 24 9975286 ps
T800 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.221689087 Apr 18 01:50:35 PM PDT 24 Apr 18 01:50:46 PM PDT 24 432483243 ps
T208 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2755199436 Apr 18 01:50:40 PM PDT 24 Apr 18 01:56:53 PM PDT 24 5872045849 ps
T801 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.540260697 Apr 18 01:51:03 PM PDT 24 Apr 18 01:51:12 PM PDT 24 115699414 ps
T164 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2484617131 Apr 18 01:50:34 PM PDT 24 Apr 18 01:59:59 PM PDT 24 9122853785 ps
T802 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4201089424 Apr 18 01:50:36 PM PDT 24 Apr 18 01:50:44 PM PDT 24 272567753 ps
T803 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3362170179 Apr 18 01:50:33 PM PDT 24 Apr 18 01:51:10 PM PDT 24 2735331930 ps
T804 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2079140729 Apr 18 01:50:30 PM PDT 24 Apr 18 01:50:39 PM PDT 24 186382818 ps
T805 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3466853963 Apr 18 01:51:18 PM PDT 24 Apr 18 01:51:20 PM PDT 24 19389041 ps
T806 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2290283817 Apr 18 01:50:48 PM PDT 24 Apr 18 01:51:01 PM PDT 24 324521549 ps
T807 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2758928984 Apr 18 01:50:39 PM PDT 24 Apr 18 01:50:51 PM PDT 24 685225432 ps
T808 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3223671157 Apr 18 01:50:32 PM PDT 24 Apr 18 01:50:41 PM PDT 24 100086175 ps
T364 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.64699484 Apr 18 01:50:30 PM PDT 24 Apr 18 01:56:06 PM PDT 24 8058636164 ps
T809 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2895070394 Apr 18 01:51:09 PM PDT 24 Apr 18 01:51:11 PM PDT 24 16376967 ps
T810 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1496289798 Apr 18 01:50:41 PM PDT 24 Apr 18 01:50:45 PM PDT 24 70141119 ps
T811 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.563312384 Apr 18 01:50:41 PM PDT 24 Apr 18 01:52:27 PM PDT 24 4649111965 ps
T812 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.710010791 Apr 18 01:51:06 PM PDT 24 Apr 18 01:51:11 PM PDT 24 196928474 ps
T813 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1112238989 Apr 18 01:50:37 PM PDT 24 Apr 18 01:50:39 PM PDT 24 25682284 ps
T814 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1268294893 Apr 18 01:50:39 PM PDT 24 Apr 18 01:50:48 PM PDT 24 111755934 ps
T161 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3681549559 Apr 18 01:50:43 PM PDT 24 Apr 18 02:06:17 PM PDT 24 14213215547 ps
T815 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.873830915 Apr 18 01:50:36 PM PDT 24 Apr 18 01:50:46 PM PDT 24 110668293 ps
T167 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1099290839 Apr 18 01:50:25 PM PDT 24 Apr 18 01:55:38 PM PDT 24 4241434598 ps
T816 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3108190838 Apr 18 01:50:57 PM PDT 24 Apr 18 01:50:59 PM PDT 24 6282137 ps
T179 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3697112637 Apr 18 01:50:38 PM PDT 24 Apr 18 01:50:41 PM PDT 24 21270545 ps
T165 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1286862213 Apr 18 01:50:42 PM PDT 24 Apr 18 01:54:02 PM PDT 24 15753120417 ps
T817 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.4244198195 Apr 18 01:51:09 PM PDT 24 Apr 18 01:51:20 PM PDT 24 1024836140 ps
T818 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1261052515 Apr 18 01:50:47 PM PDT 24 Apr 18 01:50:50 PM PDT 24 7201734 ps
T819 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.4072106651 Apr 18 01:50:47 PM PDT 24 Apr 18 01:50:49 PM PDT 24 8801445 ps
T166 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.961454727 Apr 18 01:51:15 PM PDT 24 Apr 18 02:01:29 PM PDT 24 4569442027 ps
T820 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1206775697 Apr 18 01:50:42 PM PDT 24 Apr 18 01:51:02 PM PDT 24 1096007007 ps
T175 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1264040451 Apr 18 01:50:38 PM PDT 24 Apr 18 01:50:41 PM PDT 24 59934602 ps
T821 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3037706771 Apr 18 01:50:44 PM PDT 24 Apr 18 01:51:06 PM PDT 24 286679124 ps
T822 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2016438498 Apr 18 01:50:31 PM PDT 24 Apr 18 01:51:22 PM PDT 24 1294156463 ps
T823 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.643821723 Apr 18 01:50:41 PM PDT 24 Apr 18 01:50:55 PM PDT 24 91281490 ps
T824 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.898419698 Apr 18 01:51:15 PM PDT 24 Apr 18 01:51:59 PM PDT 24 546788704 ps
T825 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2661642113 Apr 18 01:50:59 PM PDT 24 Apr 18 01:51:02 PM PDT 24 32015621 ps
T826 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.373928853 Apr 18 01:50:56 PM PDT 24 Apr 18 01:50:58 PM PDT 24 15326359 ps
T827 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3068637994 Apr 18 01:50:32 PM PDT 24 Apr 18 01:50:40 PM PDT 24 159985676 ps
T160 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2700593635 Apr 18 01:50:37 PM PDT 24 Apr 18 01:52:15 PM PDT 24 1031013036 ps
T828 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2738197079 Apr 18 01:50:44 PM PDT 24 Apr 18 01:50:50 PM PDT 24 64654921 ps
T829 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2977796289 Apr 18 01:50:44 PM PDT 24 Apr 18 01:50:48 PM PDT 24 92666650 ps
T830 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.801808035 Apr 18 01:50:48 PM PDT 24 Apr 18 01:52:06 PM PDT 24 558216550 ps

Test location /workspace/coverage/default/18.alert_handler_entropy.1453232614
Short name T4
Test name
Test status
Simulation time 46561699848 ps
CPU time 1138.97 seconds
Started Apr 18 02:51:25 PM PDT 24
Finished Apr 18 03:10:24 PM PDT 24
Peak memory 287108 kb
Host smart-c6fcf04e-0159-4ef0-878a-ea391ed5a3c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453232614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1453232614
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2822994565
Short name T20
Test name
Test status
Simulation time 36869483205 ps
CPU time 3828.57 seconds
Started Apr 18 02:46:54 PM PDT 24
Finished Apr 18 03:50:44 PM PDT 24
Peak memory 338672 kb
Host smart-1be093b5-c078-4f1a-a61c-d90d1634c657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822994565 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2822994565
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.470069236
Short name T15
Test name
Test status
Simulation time 165362207809 ps
CPU time 2388.2 seconds
Started Apr 18 03:00:22 PM PDT 24
Finished Apr 18 03:40:11 PM PDT 24
Peak memory 290196 kb
Host smart-6c4b70c4-9ad8-4845-ad6b-f0340fd79a5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470069236 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.470069236
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.4040958082
Short name T11
Test name
Test status
Simulation time 621241721 ps
CPU time 9.99 seconds
Started Apr 18 02:47:18 PM PDT 24
Finished Apr 18 02:47:29 PM PDT 24
Peak memory 273672 kb
Host smart-1c118992-34cb-45be-96ec-8fa41748b2e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4040958082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.4040958082
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1497862935
Short name T71
Test name
Test status
Simulation time 122003182 ps
CPU time 7.82 seconds
Started Apr 18 02:49:27 PM PDT 24
Finished Apr 18 02:49:36 PM PDT 24
Peak memory 241032 kb
Host smart-35bfa7c2-715b-4307-91f7-851369da0230
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1497862935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1497862935
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1616690309
Short name T170
Test name
Test status
Simulation time 1893698011 ps
CPU time 37.28 seconds
Started Apr 18 01:50:44 PM PDT 24
Finished Apr 18 01:51:22 PM PDT 24
Peak memory 240000 kb
Host smart-931e3ac7-defb-4ea0-ada1-6e50cada911c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1616690309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1616690309
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1322052079
Short name T107
Test name
Test status
Simulation time 37893871410 ps
CPU time 4191.01 seconds
Started Apr 18 02:48:10 PM PDT 24
Finished Apr 18 03:58:02 PM PDT 24
Peak memory 338916 kb
Host smart-7f8af7dc-55b9-4397-b7c6-d3ecf43e377d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322052079 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1322052079
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1497819548
Short name T105
Test name
Test status
Simulation time 57236221756 ps
CPU time 5448.8 seconds
Started Apr 18 02:54:36 PM PDT 24
Finished Apr 18 04:25:26 PM PDT 24
Peak memory 355156 kb
Host smart-9e9ae563-82bd-4d85-8642-705461d2f63c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497819548 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1497819548
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.4024297694
Short name T28
Test name
Test status
Simulation time 46781733796 ps
CPU time 1258.79 seconds
Started Apr 18 03:00:02 PM PDT 24
Finished Apr 18 03:21:01 PM PDT 24
Peak memory 286408 kb
Host smart-14aa999f-a70c-4844-9f73-ed025eb80860
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024297694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.4024297694
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4116297712
Short name T135
Test name
Test status
Simulation time 43674322275 ps
CPU time 1031.02 seconds
Started Apr 18 01:50:48 PM PDT 24
Finished Apr 18 02:08:00 PM PDT 24
Peak memory 264932 kb
Host smart-c221f72f-0409-4359-b91a-ab0b345e170a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116297712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4116297712
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.393354428
Short name T1
Test name
Test status
Simulation time 1370078855 ps
CPU time 22.81 seconds
Started Apr 18 02:50:02 PM PDT 24
Finished Apr 18 02:50:25 PM PDT 24
Peak memory 248892 kb
Host smart-618d02e7-e44e-46a1-9a17-49adb428a320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39335
4428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.393354428
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.984734690
Short name T144
Test name
Test status
Simulation time 1819188312 ps
CPU time 216.44 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:54:20 PM PDT 24
Peak memory 266088 kb
Host smart-b65858d5-6f90-4cab-95b9-a4fab1e68847
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=984734690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.984734690
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.161611451
Short name T65
Test name
Test status
Simulation time 48520762866 ps
CPU time 2742.85 seconds
Started Apr 18 02:59:43 PM PDT 24
Finished Apr 18 03:45:27 PM PDT 24
Peak memory 288252 kb
Host smart-1b903c82-8b78-46a8-beb6-5a738bfccc3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161611451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.161611451
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1352779466
Short name T249
Test name
Test status
Simulation time 32119808331 ps
CPU time 1827.74 seconds
Started Apr 18 02:53:58 PM PDT 24
Finished Apr 18 03:24:27 PM PDT 24
Peak memory 273724 kb
Host smart-17ef7c51-67a3-42e5-87e1-aa579926d21d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352779466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1352779466
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3805833450
Short name T139
Test name
Test status
Simulation time 1673874692 ps
CPU time 207.72 seconds
Started Apr 18 01:50:34 PM PDT 24
Finished Apr 18 01:54:02 PM PDT 24
Peak memory 272744 kb
Host smart-ad27d8b4-4089-46a3-92e8-11c53dd18258
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3805833450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3805833450
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1510037274
Short name T36
Test name
Test status
Simulation time 234683156691 ps
CPU time 3182.24 seconds
Started Apr 18 02:50:08 PM PDT 24
Finished Apr 18 03:43:11 PM PDT 24
Peak memory 289452 kb
Host smart-4ca1c906-6e5c-458b-bd0e-0fb28e00a5dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510037274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1510037274
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3608698542
Short name T137
Test name
Test status
Simulation time 16785752643 ps
CPU time 1083.9 seconds
Started Apr 18 01:50:50 PM PDT 24
Finished Apr 18 02:08:55 PM PDT 24
Peak memory 264988 kb
Host smart-b5f920bb-9af9-4505-b55e-4626138bb936
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608698542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3608698542
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1746765147
Short name T26
Test name
Test status
Simulation time 127280204159 ps
CPU time 452.56 seconds
Started Apr 18 02:46:29 PM PDT 24
Finished Apr 18 02:54:02 PM PDT 24
Peak memory 248324 kb
Host smart-6128c603-737b-47c6-bf9d-da6193600e58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746765147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1746765147
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3455717718
Short name T172
Test name
Test status
Simulation time 13066411 ps
CPU time 1.43 seconds
Started Apr 18 01:50:39 PM PDT 24
Finished Apr 18 01:50:41 PM PDT 24
Peak memory 235556 kb
Host smart-207762c6-ef53-4f0a-a8d1-0f9f310f803f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3455717718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3455717718
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3110126496
Short name T286
Test name
Test status
Simulation time 48318396542 ps
CPU time 566.12 seconds
Started Apr 18 02:48:02 PM PDT 24
Finished Apr 18 02:57:28 PM PDT 24
Peak memory 248036 kb
Host smart-80ef6613-6266-4c3a-b0ae-03002312935c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110126496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3110126496
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2831158013
Short name T340
Test name
Test status
Simulation time 142149579401 ps
CPU time 1277.31 seconds
Started Apr 18 02:49:03 PM PDT 24
Finished Apr 18 03:10:20 PM PDT 24
Peak memory 265480 kb
Host smart-b2ecc3ca-2a9f-4acb-9966-a1821a31c91a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831158013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2831158013
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2259300038
Short name T134
Test name
Test status
Simulation time 30897647394 ps
CPU time 1156.04 seconds
Started Apr 18 01:50:39 PM PDT 24
Finished Apr 18 02:09:56 PM PDT 24
Peak memory 272136 kb
Host smart-76f2f53b-0a75-4ef2-b1b9-3250763e51bf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259300038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2259300038
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3609129478
Short name T31
Test name
Test status
Simulation time 152086499163 ps
CPU time 1186.27 seconds
Started Apr 18 02:54:31 PM PDT 24
Finished Apr 18 03:14:18 PM PDT 24
Peak memory 289860 kb
Host smart-5359a210-9a47-4980-b484-b3e3ccf22106
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609129478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3609129478
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2359038702
Short name T132
Test name
Test status
Simulation time 4045264474 ps
CPU time 304.39 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:55:38 PM PDT 24
Peak memory 271212 kb
Host smart-ca25f588-4a52-4b5e-af19-69c0212124ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2359038702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2359038702
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3895394665
Short name T5
Test name
Test status
Simulation time 30279171963 ps
CPU time 569.21 seconds
Started Apr 18 02:53:44 PM PDT 24
Finished Apr 18 03:03:13 PM PDT 24
Peak memory 248072 kb
Host smart-e42fcda1-8022-48b8-bd60-7d2b2cc4c24e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895394665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3895394665
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1286862213
Short name T165
Test name
Test status
Simulation time 15753120417 ps
CPU time 197.95 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:54:02 PM PDT 24
Peak memory 264836 kb
Host smart-0a287f35-a41f-40a0-9345-ebde62334c70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1286862213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1286862213
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3933560140
Short name T153
Test name
Test status
Simulation time 8439190732 ps
CPU time 532.85 seconds
Started Apr 18 01:50:43 PM PDT 24
Finished Apr 18 01:59:37 PM PDT 24
Peak memory 265144 kb
Host smart-69085622-0b4f-4616-9f53-d3d4fa78a166
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933560140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3933560140
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2673598741
Short name T335
Test name
Test status
Simulation time 144446419434 ps
CPU time 2191.7 seconds
Started Apr 18 02:56:23 PM PDT 24
Finished Apr 18 03:32:55 PM PDT 24
Peak memory 287224 kb
Host smart-1b73aedb-50d7-4593-8abb-e23e0fd6c0dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673598741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2673598741
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2667583358
Short name T313
Test name
Test status
Simulation time 67221064435 ps
CPU time 431.6 seconds
Started Apr 18 02:59:20 PM PDT 24
Finished Apr 18 03:06:32 PM PDT 24
Peak memory 248292 kb
Host smart-72adb4f9-7a11-4ef6-ae82-b59ca70eefb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667583358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2667583358
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.769375107
Short name T550
Test name
Test status
Simulation time 81145923088 ps
CPU time 2143.83 seconds
Started Apr 18 02:49:26 PM PDT 24
Finished Apr 18 03:25:10 PM PDT 24
Peak memory 273712 kb
Host smart-e1808cf6-f402-4eb4-b2da-27eebd5b2f34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769375107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.769375107
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1839983156
Short name T32
Test name
Test status
Simulation time 127685170934 ps
CPU time 4896.88 seconds
Started Apr 18 02:46:35 PM PDT 24
Finished Apr 18 04:08:13 PM PDT 24
Peak memory 282324 kb
Host smart-2f2f07cd-a8cf-4060-8250-4bc6bcd6485d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839983156 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1839983156
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.109674471
Short name T265
Test name
Test status
Simulation time 245485221374 ps
CPU time 1306.85 seconds
Started Apr 18 02:54:43 PM PDT 24
Finished Apr 18 03:16:30 PM PDT 24
Peak memory 289884 kb
Host smart-ac1ca060-e504-48f9-998d-d98459ed354f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109674471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.109674471
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3481191788
Short name T322
Test name
Test status
Simulation time 8659837137 ps
CPU time 361.99 seconds
Started Apr 18 03:00:42 PM PDT 24
Finished Apr 18 03:06:44 PM PDT 24
Peak memory 255260 kb
Host smart-c9d2ee5f-7757-4cd9-a939-d73391c2164d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481191788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3481191788
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3681549559
Short name T161
Test name
Test status
Simulation time 14213215547 ps
CPU time 933.38 seconds
Started Apr 18 01:50:43 PM PDT 24
Finished Apr 18 02:06:17 PM PDT 24
Peak memory 272224 kb
Host smart-41b68013-fadb-4737-9edd-63bea694f479
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681549559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3681549559
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2644860224
Short name T111
Test name
Test status
Simulation time 81947881773 ps
CPU time 6347.71 seconds
Started Apr 18 02:49:25 PM PDT 24
Finished Apr 18 04:35:14 PM PDT 24
Peak memory 355160 kb
Host smart-19e430e7-89ef-49cb-8507-89c0fddecd45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644860224 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2644860224
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3381946871
Short name T80
Test name
Test status
Simulation time 3819445509 ps
CPU time 318.52 seconds
Started Apr 18 02:49:54 PM PDT 24
Finished Apr 18 02:55:13 PM PDT 24
Peak memory 257240 kb
Host smart-1af16ffa-4a9b-4f7d-844e-79334c8f51c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381946871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3381946871
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4231456045
Short name T171
Test name
Test status
Simulation time 8995842 ps
CPU time 1.6 seconds
Started Apr 18 01:51:11 PM PDT 24
Finished Apr 18 01:51:13 PM PDT 24
Peak memory 236364 kb
Host smart-f7d331b2-ddf6-49a3-b348-ee1af4941a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4231456045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.4231456045
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2276497935
Short name T327
Test name
Test status
Simulation time 48911588965 ps
CPU time 2634.9 seconds
Started Apr 18 02:54:03 PM PDT 24
Finished Apr 18 03:37:58 PM PDT 24
Peak memory 289280 kb
Host smart-25f7b0f5-ac6e-443c-919d-0fb032860d2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276497935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2276497935
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3469146105
Short name T269
Test name
Test status
Simulation time 54873850767 ps
CPU time 1202.28 seconds
Started Apr 18 02:59:21 PM PDT 24
Finished Apr 18 03:19:23 PM PDT 24
Peak memory 289836 kb
Host smart-6790faa4-d584-4047-9bd1-5b1a10b3a7a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469146105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3469146105
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.98334933
Short name T260
Test name
Test status
Simulation time 1075574451 ps
CPU time 69.41 seconds
Started Apr 18 01:51:08 PM PDT 24
Finished Apr 18 01:52:19 PM PDT 24
Peak memory 236548 kb
Host smart-e6b9acc8-3771-4444-ae83-769c367ea6b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=98334933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.98334933
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2484617131
Short name T164
Test name
Test status
Simulation time 9122853785 ps
CPU time 564.04 seconds
Started Apr 18 01:50:34 PM PDT 24
Finished Apr 18 01:59:59 PM PDT 24
Peak memory 269056 kb
Host smart-3a9d03d1-5ef9-412b-acf7-18df44a92269
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484617131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2484617131
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3255776041
Short name T332
Test name
Test status
Simulation time 73589278353 ps
CPU time 318.3 seconds
Started Apr 18 02:51:50 PM PDT 24
Finished Apr 18 02:57:09 PM PDT 24
Peak memory 247264 kb
Host smart-4676d52d-189b-4763-ad7c-d303b622d90e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255776041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3255776041
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3518764893
Short name T264
Test name
Test status
Simulation time 541819608 ps
CPU time 42.42 seconds
Started Apr 18 02:58:29 PM PDT 24
Finished Apr 18 02:59:12 PM PDT 24
Peak memory 249016 kb
Host smart-fd3b8fcb-5db3-42e9-ba74-215e040e5ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35187
64893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3518764893
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.669096619
Short name T142
Test name
Test status
Simulation time 13256809875 ps
CPU time 1049.86 seconds
Started Apr 18 01:50:50 PM PDT 24
Finished Apr 18 02:08:21 PM PDT 24
Peak memory 273164 kb
Host smart-80a147b9-00d6-4c6f-85bc-dd5b3235f207
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669096619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.669096619
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1132806794
Short name T351
Test name
Test status
Simulation time 265353818623 ps
CPU time 3145.97 seconds
Started Apr 18 02:46:04 PM PDT 24
Finished Apr 18 03:38:30 PM PDT 24
Peak memory 289292 kb
Host smart-55bc960a-1940-4c45-a512-8c1f168e6c2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132806794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1132806794
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1431972075
Short name T283
Test name
Test status
Simulation time 23919139682 ps
CPU time 1425.48 seconds
Started Apr 18 02:55:33 PM PDT 24
Finished Apr 18 03:19:19 PM PDT 24
Peak memory 289480 kb
Host smart-8c9e79bb-c1c2-44d4-a2c2-91114e7e3cf4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431972075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1431972075
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2721581183
Short name T320
Test name
Test status
Simulation time 7326639989 ps
CPU time 310.36 seconds
Started Apr 18 02:58:04 PM PDT 24
Finished Apr 18 03:03:15 PM PDT 24
Peak memory 248268 kb
Host smart-1879cb35-1593-4781-b733-630db37f2401
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721581183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2721581183
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4171241836
Short name T196
Test name
Test status
Simulation time 926526613494 ps
CPU time 2936.67 seconds
Started Apr 18 03:01:24 PM PDT 24
Finished Apr 18 03:50:21 PM PDT 24
Peak memory 289528 kb
Host smart-ed6802b3-cd1c-4ab3-88b8-8e762d48df1a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171241836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4171241836
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1920525971
Short name T138
Test name
Test status
Simulation time 8022765485 ps
CPU time 309.23 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:55:41 PM PDT 24
Peak memory 264976 kb
Host smart-9b35a492-45a4-4343-ab03-630f22453db1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1920525971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1920525971
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3801025754
Short name T57
Test name
Test status
Simulation time 33950407169 ps
CPU time 1116.55 seconds
Started Apr 18 03:02:28 PM PDT 24
Finished Apr 18 03:21:05 PM PDT 24
Peak memory 273952 kb
Host smart-44dd6233-a929-4f95-974c-3e1d9ff22f20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801025754 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3801025754
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2755199436
Short name T208
Test name
Test status
Simulation time 5872045849 ps
CPU time 373.19 seconds
Started Apr 18 01:50:40 PM PDT 24
Finished Apr 18 01:56:53 PM PDT 24
Peak memory 265228 kb
Host smart-d3048367-a66f-41d9-b2bf-1d655dfab8fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2755199436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2755199436
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1636753551
Short name T77
Test name
Test status
Simulation time 45939434 ps
CPU time 3.86 seconds
Started Apr 18 02:46:09 PM PDT 24
Finished Apr 18 02:46:13 PM PDT 24
Peak memory 249320 kb
Host smart-188f50bc-3e96-45d2-be37-5d74665fcc7a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1636753551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1636753551
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3006003621
Short name T224
Test name
Test status
Simulation time 19595052 ps
CPU time 2.88 seconds
Started Apr 18 02:46:28 PM PDT 24
Finished Apr 18 02:46:31 PM PDT 24
Peak memory 249308 kb
Host smart-93649943-1dff-4acc-b2a1-4b166faadcc0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3006003621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3006003621
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3083903001
Short name T226
Test name
Test status
Simulation time 90010874 ps
CPU time 3.38 seconds
Started Apr 18 02:49:05 PM PDT 24
Finished Apr 18 02:49:08 PM PDT 24
Peak memory 249180 kb
Host smart-de0123de-fcdc-4a10-92aa-0a1ed169c78f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3083903001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3083903001
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1430010191
Short name T212
Test name
Test status
Simulation time 29815783 ps
CPU time 2.35 seconds
Started Apr 18 02:49:25 PM PDT 24
Finished Apr 18 02:49:29 PM PDT 24
Peak memory 249340 kb
Host smart-d95e3e44-df1e-4acd-b334-6fef5b946553
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1430010191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1430010191
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1233966983
Short name T748
Test name
Test status
Simulation time 6304679 ps
CPU time 1.36 seconds
Started Apr 18 01:50:39 PM PDT 24
Finished Apr 18 01:50:47 PM PDT 24
Peak memory 236384 kb
Host smart-0e14e573-e71b-4898-820b-cd39afda958b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1233966983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1233966983
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2023376300
Short name T278
Test name
Test status
Simulation time 28051609634 ps
CPU time 596.26 seconds
Started Apr 18 02:49:05 PM PDT 24
Finished Apr 18 02:59:02 PM PDT 24
Peak memory 270756 kb
Host smart-6a5180b2-f6aa-4168-8b0d-48db69fc55ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023376300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2023376300
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1486368580
Short name T657
Test name
Test status
Simulation time 41547866262 ps
CPU time 360.44 seconds
Started Apr 18 02:51:23 PM PDT 24
Finished Apr 18 02:57:24 PM PDT 24
Peak memory 255568 kb
Host smart-d13e6df8-9531-4fe6-9a9c-ad7aa740d8a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486368580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1486368580
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2303148823
Short name T263
Test name
Test status
Simulation time 49473472999 ps
CPU time 2700.86 seconds
Started Apr 18 02:54:08 PM PDT 24
Finished Apr 18 03:39:09 PM PDT 24
Peak memory 297760 kb
Host smart-cf959ce3-fd65-45a0-b3c5-4357c057a516
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303148823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2303148823
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3064404611
Short name T233
Test name
Test status
Simulation time 104668910415 ps
CPU time 1570.25 seconds
Started Apr 18 02:55:29 PM PDT 24
Finished Apr 18 03:21:40 PM PDT 24
Peak memory 267564 kb
Host smart-2b557ff5-0566-4fe8-94ff-be9d7178d946
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064404611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3064404611
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1011287286
Short name T100
Test name
Test status
Simulation time 418626596509 ps
CPU time 3454.04 seconds
Started Apr 18 02:56:25 PM PDT 24
Finished Apr 18 03:54:00 PM PDT 24
Peak memory 306012 kb
Host smart-b17ca496-4cba-4c30-a34b-06c22bd4d3e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011287286 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1011287286
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3948150590
Short name T200
Test name
Test status
Simulation time 572403752 ps
CPU time 93.8 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:52:05 PM PDT 24
Peak memory 240020 kb
Host smart-ee6760ef-d8aa-4239-b8d7-6ab0e981b920
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3948150590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3948150590
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.193285700
Short name T136
Test name
Test status
Simulation time 2311860318 ps
CPU time 166.66 seconds
Started Apr 18 01:50:40 PM PDT 24
Finished Apr 18 01:53:27 PM PDT 24
Peak memory 266348 kb
Host smart-f96b66bd-5f9a-42c5-aa63-370d28017802
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=193285700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.193285700
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.821538927
Short name T188
Test name
Test status
Simulation time 62279762 ps
CPU time 2.27 seconds
Started Apr 18 01:50:34 PM PDT 24
Finished Apr 18 01:50:37 PM PDT 24
Peak memory 236508 kb
Host smart-de51b9a5-1721-4e82-aeeb-c2835c6aee35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=821538927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.821538927
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.4011749470
Short name T452
Test name
Test status
Simulation time 170596880932 ps
CPU time 509.16 seconds
Started Apr 18 02:46:04 PM PDT 24
Finished Apr 18 02:54:33 PM PDT 24
Peak memory 248236 kb
Host smart-3e3c5a75-6083-43f9-9171-f095d840c4fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011749470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.4011749470
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.533447889
Short name T118
Test name
Test status
Simulation time 28441503932 ps
CPU time 2739.73 seconds
Started Apr 18 02:49:06 PM PDT 24
Finished Apr 18 03:34:46 PM PDT 24
Peak memory 306220 kb
Host smart-417742ad-87fc-45fd-ad00-3649e684f75b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533447889 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.533447889
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1114073913
Short name T67
Test name
Test status
Simulation time 39773616572 ps
CPU time 2281.89 seconds
Started Apr 18 02:51:04 PM PDT 24
Finished Apr 18 03:29:07 PM PDT 24
Peak memory 289312 kb
Host smart-4c2789ad-7e45-4a57-ba2e-e44495ef9454
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114073913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1114073913
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3188101016
Short name T98
Test name
Test status
Simulation time 199373926791 ps
CPU time 3740.92 seconds
Started Apr 18 02:52:29 PM PDT 24
Finished Apr 18 03:54:51 PM PDT 24
Peak memory 289636 kb
Host smart-4b17c35f-f37f-473a-a988-b77a73451bf1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188101016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3188101016
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3795702257
Short name T348
Test name
Test status
Simulation time 54232123494 ps
CPU time 1504.29 seconds
Started Apr 18 02:52:57 PM PDT 24
Finished Apr 18 03:18:01 PM PDT 24
Peak memory 272000 kb
Host smart-ddcdfc00-48d2-448d-9e18-a274b04c6ff1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795702257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3795702257
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1965588604
Short name T89
Test name
Test status
Simulation time 110299377838 ps
CPU time 6070.39 seconds
Started Apr 18 02:54:09 PM PDT 24
Finished Apr 18 04:35:20 PM PDT 24
Peak memory 332228 kb
Host smart-7e8716e2-8ab5-45ab-b526-d97fa9594ac0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965588604 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1965588604
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3792912957
Short name T92
Test name
Test status
Simulation time 1754402234 ps
CPU time 28.26 seconds
Started Apr 18 02:54:18 PM PDT 24
Finished Apr 18 02:54:47 PM PDT 24
Peak memory 247592 kb
Host smart-dd505735-5d1f-4991-b2ed-c2d3f9c5f566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37929
12957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3792912957
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.960859966
Short name T94
Test name
Test status
Simulation time 589633394 ps
CPU time 33.09 seconds
Started Apr 18 02:54:38 PM PDT 24
Finished Apr 18 02:55:11 PM PDT 24
Peak memory 249040 kb
Host smart-7c4ee817-17ab-40b6-9174-700cc3ef2eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96085
9966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.960859966
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3409965285
Short name T250
Test name
Test status
Simulation time 56439429075 ps
CPU time 3339.62 seconds
Started Apr 18 02:54:41 PM PDT 24
Finished Apr 18 03:50:22 PM PDT 24
Peak memory 269784 kb
Host smart-7b684ae9-196e-4f6b-8e64-b9ff43725d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409965285 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3409965285
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1028121905
Short name T280
Test name
Test status
Simulation time 916933428 ps
CPU time 25.82 seconds
Started Apr 18 02:59:09 PM PDT 24
Finished Apr 18 02:59:35 PM PDT 24
Peak memory 248068 kb
Host smart-d1c6ec23-3709-4190-aeff-406d636f2953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10281
21905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1028121905
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2578661867
Short name T301
Test name
Test status
Simulation time 5817148350 ps
CPU time 63.15 seconds
Started Apr 18 03:00:00 PM PDT 24
Finished Apr 18 03:01:04 PM PDT 24
Peak memory 255524 kb
Host smart-e2ebadda-102f-4df4-a55d-c56829360bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25786
61867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2578661867
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3163174137
Short name T8
Test name
Test status
Simulation time 104944949 ps
CPU time 12.88 seconds
Started Apr 18 03:00:23 PM PDT 24
Finished Apr 18 03:00:37 PM PDT 24
Peak memory 253804 kb
Host smart-f97b78c5-81f1-4f51-b813-7bbeedd6fef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31631
74137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3163174137
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2590959530
Short name T281
Test name
Test status
Simulation time 59028350715 ps
CPU time 2824.05 seconds
Started Apr 18 03:01:23 PM PDT 24
Finished Apr 18 03:48:28 PM PDT 24
Peak memory 306168 kb
Host smart-c8c33ff6-9557-4dfa-8848-95b85d228440
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590959530 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2590959530
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.733657802
Short name T133
Test name
Test status
Simulation time 24843046124 ps
CPU time 491.02 seconds
Started Apr 18 01:50:34 PM PDT 24
Finished Apr 18 01:58:46 PM PDT 24
Peak memory 265180 kb
Host smart-52f2bb30-17b7-4ebf-94b8-1b711e800c43
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733657802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.733657802
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2457865203
Short name T177
Test name
Test status
Simulation time 647162447 ps
CPU time 44.26 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:51:15 PM PDT 24
Peak memory 239280 kb
Host smart-88e103ea-214a-4158-8c7f-814b4f2a0dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2457865203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2457865203
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.556432859
Short name T178
Test name
Test status
Simulation time 584829148 ps
CPU time 41.81 seconds
Started Apr 18 01:51:01 PM PDT 24
Finished Apr 18 01:51:43 PM PDT 24
Peak memory 244436 kb
Host smart-ca9fbbb3-0400-4c93-a3ca-7eeac6513666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=556432859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.556432859
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.784056586
Short name T174
Test name
Test status
Simulation time 909341980 ps
CPU time 73.95 seconds
Started Apr 18 01:50:29 PM PDT 24
Finished Apr 18 01:51:44 PM PDT 24
Peak memory 239272 kb
Host smart-bb9561cc-ad93-431e-a38b-134d2ecfeb30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=784056586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.784056586
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.772181973
Short name T159
Test name
Test status
Simulation time 5821756042 ps
CPU time 179.65 seconds
Started Apr 18 01:50:29 PM PDT 24
Finished Apr 18 01:53:30 PM PDT 24
Peak memory 265996 kb
Host smart-0f4a6b3b-fe34-4f2b-b76f-e2ced2b60c89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=772181973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.772181973
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.616622095
Short name T176
Test name
Test status
Simulation time 684694114 ps
CPU time 26.68 seconds
Started Apr 18 01:50:37 PM PDT 24
Finished Apr 18 01:51:04 PM PDT 24
Peak memory 236516 kb
Host smart-874684ae-ad01-4721-b1b6-73dd0225334d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=616622095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.616622095
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2433554300
Short name T187
Test name
Test status
Simulation time 165549363 ps
CPU time 3.76 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:50:45 PM PDT 24
Peak memory 236700 kb
Host smart-d992c1fc-3b0d-4a3c-baef-08f96359cc35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2433554300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2433554300
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3921893222
Short name T184
Test name
Test status
Simulation time 204727807 ps
CPU time 3.14 seconds
Started Apr 18 01:50:55 PM PDT 24
Finished Apr 18 01:50:59 PM PDT 24
Peak memory 236352 kb
Host smart-2ae98625-3771-4773-ab42-730613540191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3921893222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3921893222
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1957085650
Short name T182
Test name
Test status
Simulation time 143858542 ps
CPU time 2.25 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:50:46 PM PDT 24
Peak memory 236220 kb
Host smart-10f767e6-0c6a-47a8-aef8-f3882c958d13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1957085650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1957085650
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.44384179
Short name T189
Test name
Test status
Simulation time 23809718 ps
CPU time 2.78 seconds
Started Apr 18 01:51:12 PM PDT 24
Finished Apr 18 01:51:15 PM PDT 24
Peak memory 237376 kb
Host smart-6ffea1a0-78f8-459c-881c-c9c3bbc59300
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=44384179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.44384179
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.239203272
Short name T183
Test name
Test status
Simulation time 192671840 ps
CPU time 3.9 seconds
Started Apr 18 01:50:48 PM PDT 24
Finished Apr 18 01:50:53 PM PDT 24
Peak memory 236356 kb
Host smart-6f64ae4a-6ae8-4ac5-9fae-e35ce8bb2978
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=239203272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.239203272
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1957634389
Short name T181
Test name
Test status
Simulation time 49668802 ps
CPU time 2.65 seconds
Started Apr 18 01:50:37 PM PDT 24
Finished Apr 18 01:50:41 PM PDT 24
Peak memory 235496 kb
Host smart-cd9dc766-64d3-404b-9a53-4ebbe9484660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1957634389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1957634389
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.609745109
Short name T168
Test name
Test status
Simulation time 607623316 ps
CPU time 19.81 seconds
Started Apr 18 01:50:35 PM PDT 24
Finished Apr 18 01:50:55 PM PDT 24
Peak memory 244600 kb
Host smart-8e5b6d75-a3b5-49a6-a5fa-476224039182
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=609745109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.609745109
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3697112637
Short name T179
Test name
Test status
Simulation time 21270545 ps
CPU time 2.57 seconds
Started Apr 18 01:50:38 PM PDT 24
Finished Apr 18 01:50:41 PM PDT 24
Peak memory 235492 kb
Host smart-f686e178-378f-4247-b6ff-d12c022e750d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3697112637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3697112637
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3691816923
Short name T180
Test name
Test status
Simulation time 5165237217 ps
CPU time 71.96 seconds
Started Apr 18 01:50:35 PM PDT 24
Finished Apr 18 01:51:48 PM PDT 24
Peak memory 240044 kb
Host smart-278e4f11-b937-4693-abd5-693f18bd851c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3691816923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3691816923
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.7442596
Short name T19
Test name
Test status
Simulation time 2888339971 ps
CPU time 41.83 seconds
Started Apr 18 03:00:29 PM PDT 24
Finished Apr 18 03:01:12 PM PDT 24
Peak memory 249144 kb
Host smart-88bb754a-fb9b-4bf0-b711-930ad4d03288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74425
96 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.7442596
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2578723126
Short name T749
Test name
Test status
Simulation time 1184506650 ps
CPU time 160.71 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:53:13 PM PDT 24
Peak memory 240008 kb
Host smart-32f5e36b-4947-43df-9979-ba944ec39e29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2578723126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2578723126
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3943843628
Short name T207
Test name
Test status
Simulation time 9602855347 ps
CPU time 200.1 seconds
Started Apr 18 01:50:38 PM PDT 24
Finished Apr 18 01:53:59 PM PDT 24
Peak memory 240024 kb
Host smart-bcd8b8c7-a0f0-4928-9d03-c39ebfba6e83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3943843628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3943843628
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1196758771
Short name T745
Test name
Test status
Simulation time 441919096 ps
CPU time 5.42 seconds
Started Apr 18 01:50:37 PM PDT 24
Finished Apr 18 01:50:43 PM PDT 24
Peak memory 239960 kb
Host smart-f11248f0-1b0f-4638-bf44-7f06dec6084a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1196758771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1196758771
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2854378289
Short name T728
Test name
Test status
Simulation time 450774604 ps
CPU time 9.83 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:44 PM PDT 24
Peak memory 240092 kb
Host smart-0e46832c-1d27-40c0-b76f-694c4d37456e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854378289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2854378289
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3223671157
Short name T808
Test name
Test status
Simulation time 100086175 ps
CPU time 8.1 seconds
Started Apr 18 01:50:32 PM PDT 24
Finished Apr 18 01:50:41 PM PDT 24
Peak memory 236368 kb
Host smart-99ba2216-2bd4-4dda-8a22-158f485eac36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3223671157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3223671157
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3833864456
Short name T795
Test name
Test status
Simulation time 35349689 ps
CPU time 1.28 seconds
Started Apr 18 01:50:40 PM PDT 24
Finished Apr 18 01:50:42 PM PDT 24
Peak memory 235248 kb
Host smart-99226665-4ce6-4813-94de-87dd4a96ef19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3833864456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3833864456
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2969460288
Short name T783
Test name
Test status
Simulation time 2559557871 ps
CPU time 47 seconds
Started Apr 18 01:50:39 PM PDT 24
Finished Apr 18 01:51:26 PM PDT 24
Peak memory 244412 kb
Host smart-155d12a8-3089-4e38-8b37-0480ebc31e01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2969460288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2969460288
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1719614381
Short name T708
Test name
Test status
Simulation time 383241355 ps
CPU time 24.4 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:55 PM PDT 24
Peak memory 247332 kb
Host smart-5f9689df-0524-4424-8681-485be3737fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1719614381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1719614381
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2528831600
Short name T715
Test name
Test status
Simulation time 5941803276 ps
CPU time 359.98 seconds
Started Apr 18 01:50:35 PM PDT 24
Finished Apr 18 01:56:35 PM PDT 24
Peak memory 236424 kb
Host smart-d2ef1d97-bb54-473e-8309-59b4f8f907cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2528831600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2528831600
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1245434695
Short name T755
Test name
Test status
Simulation time 431000407 ps
CPU time 8.97 seconds
Started Apr 18 01:50:38 PM PDT 24
Finished Apr 18 01:50:47 PM PDT 24
Peak memory 239824 kb
Host smart-e0640d25-bb7a-43e0-aeee-0152d7060395
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1245434695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1245434695
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2079140729
Short name T804
Test name
Test status
Simulation time 186382818 ps
CPU time 8.12 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:39 PM PDT 24
Peak memory 236920 kb
Host smart-b7f163ac-7895-4feb-9010-e5326ca06391
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079140729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2079140729
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.955895206
Short name T747
Test name
Test status
Simulation time 79608655 ps
CPU time 6.15 seconds
Started Apr 18 01:50:36 PM PDT 24
Finished Apr 18 01:50:43 PM PDT 24
Peak memory 240036 kb
Host smart-d09ebfd8-9b9f-4b47-bca6-6ece1cabd028
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=955895206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.955895206
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2678408762
Short name T757
Test name
Test status
Simulation time 14116448 ps
CPU time 1.48 seconds
Started Apr 18 01:50:32 PM PDT 24
Finished Apr 18 01:50:34 PM PDT 24
Peak memory 235428 kb
Host smart-e6bf682a-93ff-4943-afe9-0a7e8606ca6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2678408762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2678408762
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2200640940
Short name T743
Test name
Test status
Simulation time 276831756 ps
CPU time 20.35 seconds
Started Apr 18 01:50:29 PM PDT 24
Finished Apr 18 01:50:51 PM PDT 24
Peak memory 244540 kb
Host smart-9f60d11d-dc1d-4ac0-a212-226d7e6bd423
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2200640940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2200640940
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2363528956
Short name T150
Test name
Test status
Simulation time 3386763089 ps
CPU time 118.31 seconds
Started Apr 18 01:50:44 PM PDT 24
Finished Apr 18 01:52:43 PM PDT 24
Peak memory 256704 kb
Host smart-43ea5ba9-b112-421f-88c8-e3fac23b7153
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2363528956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2363528956
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1099290839
Short name T167
Test name
Test status
Simulation time 4241434598 ps
CPU time 312.52 seconds
Started Apr 18 01:50:25 PM PDT 24
Finished Apr 18 01:55:38 PM PDT 24
Peak memory 265020 kb
Host smart-0bc2e3f7-8615-4510-a00a-dde65a425180
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099290839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1099290839
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.310384488
Short name T754
Test name
Test status
Simulation time 157457841 ps
CPU time 6.18 seconds
Started Apr 18 01:50:38 PM PDT 24
Finished Apr 18 01:50:45 PM PDT 24
Peak memory 248228 kb
Host smart-c19d59eb-5c62-45af-b7cf-4fc583458cc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=310384488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.310384488
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.693603508
Short name T794
Test name
Test status
Simulation time 181329371 ps
CPU time 9.15 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:50:50 PM PDT 24
Peak memory 250280 kb
Host smart-d68e1499-7b0b-494a-8230-5212aa657290
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693603508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.693603508
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.65923339
Short name T746
Test name
Test status
Simulation time 143192012 ps
CPU time 5.27 seconds
Started Apr 18 01:50:43 PM PDT 24
Finished Apr 18 01:50:50 PM PDT 24
Peak memory 239988 kb
Host smart-1173246b-6ea4-4abb-9d53-e9298e1df303
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=65923339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.65923339
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2583334652
Short name T201
Test name
Test status
Simulation time 174615579 ps
CPU time 25.22 seconds
Started Apr 18 01:50:44 PM PDT 24
Finished Apr 18 01:51:11 PM PDT 24
Peak memory 248216 kb
Host smart-7d268dcd-7bda-4abc-bd4c-5f7a4ab4e34f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2583334652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2583334652
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3346313891
Short name T141
Test name
Test status
Simulation time 7948339862 ps
CPU time 140.64 seconds
Started Apr 18 01:50:44 PM PDT 24
Finished Apr 18 01:53:06 PM PDT 24
Peak memory 256848 kb
Host smart-08e05798-8a01-4229-836c-223543934b43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3346313891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3346313891
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4046241767
Short name T154
Test name
Test status
Simulation time 7352118408 ps
CPU time 447.23 seconds
Started Apr 18 01:50:39 PM PDT 24
Finished Apr 18 01:58:07 PM PDT 24
Peak memory 264948 kb
Host smart-e8636f3d-c5a9-46ed-bc8e-4124c25b4582
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046241767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.4046241767
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4115637338
Short name T722
Test name
Test status
Simulation time 83093790 ps
CPU time 11.19 seconds
Started Apr 18 01:50:40 PM PDT 24
Finished Apr 18 01:50:51 PM PDT 24
Peak memory 247632 kb
Host smart-3a9c568b-1e2e-4a25-9ddd-7716037f1941
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4115637338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.4115637338
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2218908734
Short name T730
Test name
Test status
Simulation time 2101936880 ps
CPU time 38.18 seconds
Started Apr 18 01:50:47 PM PDT 24
Finished Apr 18 01:51:26 PM PDT 24
Peak memory 244832 kb
Host smart-fa164568-2bba-41c7-8925-11b208f11c75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2218908734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2218908734
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1268294893
Short name T814
Test name
Test status
Simulation time 111755934 ps
CPU time 8.65 seconds
Started Apr 18 01:50:39 PM PDT 24
Finished Apr 18 01:50:48 PM PDT 24
Peak memory 240100 kb
Host smart-cd858791-7fa4-4026-b41f-09c904fbc7d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268294893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1268294893
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1513397291
Short name T736
Test name
Test status
Simulation time 132377768 ps
CPU time 5.18 seconds
Started Apr 18 01:51:10 PM PDT 24
Finished Apr 18 01:51:16 PM PDT 24
Peak memory 239960 kb
Host smart-f1a0d56c-8f41-4408-bc97-a72272f6883a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1513397291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1513397291
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2422714610
Short name T799
Test name
Test status
Simulation time 9975286 ps
CPU time 1.35 seconds
Started Apr 18 01:50:48 PM PDT 24
Finished Apr 18 01:50:50 PM PDT 24
Peak memory 234440 kb
Host smart-8870e349-74d1-4c3c-a836-6df405d7b209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2422714610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2422714610
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2290283817
Short name T806
Test name
Test status
Simulation time 324521549 ps
CPU time 12.38 seconds
Started Apr 18 01:50:48 PM PDT 24
Finished Apr 18 01:51:01 PM PDT 24
Peak memory 248088 kb
Host smart-085d9d2d-0bf8-4d26-b2df-b1e314413c53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2290283817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2290283817
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2700593635
Short name T160
Test name
Test status
Simulation time 1031013036 ps
CPU time 97.57 seconds
Started Apr 18 01:50:37 PM PDT 24
Finished Apr 18 01:52:15 PM PDT 24
Peak memory 256468 kb
Host smart-b57a74b8-4274-408c-bdb6-c5fadba63a15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2700593635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2700593635
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2875432134
Short name T152
Test name
Test status
Simulation time 30491797713 ps
CPU time 556.51 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:59:58 PM PDT 24
Peak memory 267884 kb
Host smart-a6edf164-da93-4495-b175-b408241a9fe7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875432134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2875432134
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1464429830
Short name T775
Test name
Test status
Simulation time 779079645 ps
CPU time 13.17 seconds
Started Apr 18 01:50:39 PM PDT 24
Finished Apr 18 01:50:53 PM PDT 24
Peak memory 248364 kb
Host smart-4f967fdb-dae6-4900-b607-f292d36de662
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1464429830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1464429830
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3931484605
Short name T771
Test name
Test status
Simulation time 84346646 ps
CPU time 5.54 seconds
Started Apr 18 01:50:47 PM PDT 24
Finished Apr 18 01:50:53 PM PDT 24
Peak memory 241004 kb
Host smart-1c9258db-20d0-4225-925a-8dd14954c8a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931484605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3931484605
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1496289798
Short name T810
Test name
Test status
Simulation time 70141119 ps
CPU time 3.35 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:50:45 PM PDT 24
Peak memory 236324 kb
Host smart-14900527-83f8-4d43-b637-b8237b85b700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1496289798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1496289798
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3108190838
Short name T816
Test name
Test status
Simulation time 6282137 ps
CPU time 1.49 seconds
Started Apr 18 01:50:57 PM PDT 24
Finished Apr 18 01:50:59 PM PDT 24
Peak memory 235468 kb
Host smart-8b304932-e23d-4370-bdac-5aa209a827e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3108190838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3108190838
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3762232738
Short name T199
Test name
Test status
Simulation time 738099476 ps
CPU time 19.91 seconds
Started Apr 18 01:50:39 PM PDT 24
Finished Apr 18 01:51:00 PM PDT 24
Peak memory 239956 kb
Host smart-9c3d2a62-5875-405a-9c88-25930c9b1009
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3762232738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3762232738
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2483178718
Short name T363
Test name
Test status
Simulation time 30171155645 ps
CPU time 499.97 seconds
Started Apr 18 01:50:40 PM PDT 24
Finished Apr 18 01:59:00 PM PDT 24
Peak memory 265052 kb
Host smart-6d7c2680-57e4-428d-a18f-d01ec5e07b22
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483178718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2483178718
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4201089424
Short name T802
Test name
Test status
Simulation time 272567753 ps
CPU time 6.87 seconds
Started Apr 18 01:50:36 PM PDT 24
Finished Apr 18 01:50:44 PM PDT 24
Peak memory 247424 kb
Host smart-00c641fc-4447-44d3-a544-6eea883d6ec8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4201089424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.4201089424
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1828562196
Short name T724
Test name
Test status
Simulation time 28623869 ps
CPU time 4.7 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:50:48 PM PDT 24
Peak memory 240080 kb
Host smart-13052adb-187b-4423-81c1-64f105ae67c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828562196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1828562196
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.675680149
Short name T790
Test name
Test status
Simulation time 263754488 ps
CPU time 5.71 seconds
Started Apr 18 01:50:44 PM PDT 24
Finished Apr 18 01:50:51 PM PDT 24
Peak memory 236296 kb
Host smart-812c4627-6b69-463f-82ab-641c9e7f84fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=675680149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.675680149
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3037706771
Short name T821
Test name
Test status
Simulation time 286679124 ps
CPU time 21.59 seconds
Started Apr 18 01:50:44 PM PDT 24
Finished Apr 18 01:51:06 PM PDT 24
Peak memory 243664 kb
Host smart-a08e6888-6299-4835-8b31-d71c8cf95a6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3037706771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3037706771
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2230604139
Short name T143
Test name
Test status
Simulation time 26491820639 ps
CPU time 543.44 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:59:45 PM PDT 24
Peak memory 264908 kb
Host smart-8a5749fc-7a73-4c89-b219-c1f16e72868b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230604139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2230604139
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1362946477
Short name T739
Test name
Test status
Simulation time 291111819 ps
CPU time 22.18 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:51:04 PM PDT 24
Peak memory 248104 kb
Host smart-60cbacdc-76a2-44e4-88a7-a31b4021521c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1362946477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1362946477
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.912025526
Short name T169
Test name
Test status
Simulation time 208526996 ps
CPU time 4.44 seconds
Started Apr 18 01:50:43 PM PDT 24
Finished Apr 18 01:50:48 PM PDT 24
Peak memory 236532 kb
Host smart-3e06358a-ffa2-4e4a-b0cb-846de663a922
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=912025526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.912025526
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1006323526
Short name T798
Test name
Test status
Simulation time 702374898 ps
CPU time 8.74 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:50:52 PM PDT 24
Peak memory 250584 kb
Host smart-e3560bd5-ba64-4e9a-a6fd-cb7caa69f28a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006323526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1006323526
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.453635404
Short name T713
Test name
Test status
Simulation time 35164213 ps
CPU time 3.96 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:50:48 PM PDT 24
Peak memory 236316 kb
Host smart-b20713ab-1021-4cf3-8db6-4d6e728e5db8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=453635404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.453635404
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3442726880
Short name T762
Test name
Test status
Simulation time 11408455 ps
CPU time 1.52 seconds
Started Apr 18 01:51:05 PM PDT 24
Finished Apr 18 01:51:06 PM PDT 24
Peak memory 236372 kb
Host smart-7ba9c635-9cb1-4178-8cbe-0d979b71a242
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3442726880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3442726880
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1190656466
Short name T737
Test name
Test status
Simulation time 513927399 ps
CPU time 35.76 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:51:19 PM PDT 24
Peak memory 243624 kb
Host smart-6fb211ee-65ca-45b7-ab1c-f794137702a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1190656466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1190656466
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1773060433
Short name T147
Test name
Test status
Simulation time 2394349871 ps
CPU time 221.36 seconds
Started Apr 18 01:50:51 PM PDT 24
Finished Apr 18 01:54:33 PM PDT 24
Peak memory 265012 kb
Host smart-1913486c-bef9-46bb-9e07-a4ccce86eafb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1773060433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1773060433
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1860058984
Short name T254
Test name
Test status
Simulation time 238715204 ps
CPU time 14.81 seconds
Started Apr 18 01:50:43 PM PDT 24
Finished Apr 18 01:50:59 PM PDT 24
Peak memory 247740 kb
Host smart-03e79fb8-fc3a-478b-8998-908e571e1747
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1860058984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1860058984
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1580623861
Short name T710
Test name
Test status
Simulation time 152549092 ps
CPU time 12.43 seconds
Started Apr 18 01:50:44 PM PDT 24
Finished Apr 18 01:50:57 PM PDT 24
Peak memory 251328 kb
Host smart-47fd48ac-a5a9-4494-8085-f14a21aa799b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580623861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1580623861
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.710010791
Short name T812
Test name
Test status
Simulation time 196928474 ps
CPU time 4.86 seconds
Started Apr 18 01:51:06 PM PDT 24
Finished Apr 18 01:51:11 PM PDT 24
Peak memory 236352 kb
Host smart-1e6d0017-c7f0-41f1-845d-f34fa3204f14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=710010791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.710010791
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1561231475
Short name T726
Test name
Test status
Simulation time 20935692 ps
CPU time 1.44 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:50:44 PM PDT 24
Peak memory 236312 kb
Host smart-689b02ef-6d92-407f-94a8-598e7a99d915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1561231475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1561231475
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.643821723
Short name T823
Test name
Test status
Simulation time 91281490 ps
CPU time 12.97 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:50:55 PM PDT 24
Peak memory 244592 kb
Host smart-07398417-1118-4ede-81f2-bc1d17f14a48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=643821723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.643821723
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1366881177
Short name T157
Test name
Test status
Simulation time 1568002115 ps
CPU time 219.19 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:54:22 PM PDT 24
Peak memory 265956 kb
Host smart-33bcac68-4553-4872-84af-630c347b8a40
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1366881177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1366881177
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.56622424
Short name T707
Test name
Test status
Simulation time 593124011 ps
CPU time 22.81 seconds
Started Apr 18 01:50:43 PM PDT 24
Finished Apr 18 01:51:07 PM PDT 24
Peak memory 248260 kb
Host smart-7a57298f-14db-47db-acbe-a32a6807ee83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=56622424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.56622424
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4205491905
Short name T772
Test name
Test status
Simulation time 393956346 ps
CPU time 8.11 seconds
Started Apr 18 01:51:12 PM PDT 24
Finished Apr 18 01:51:21 PM PDT 24
Peak memory 238804 kb
Host smart-8457dcc9-438e-416f-bc5b-0f67baba8fea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205491905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4205491905
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2977796289
Short name T829
Test name
Test status
Simulation time 92666650 ps
CPU time 3.11 seconds
Started Apr 18 01:50:44 PM PDT 24
Finished Apr 18 01:50:48 PM PDT 24
Peak memory 235324 kb
Host smart-05bc6924-9b70-4632-8c5a-b8136f40c25e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2977796289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2977796289
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2346723864
Short name T764
Test name
Test status
Simulation time 25692896 ps
CPU time 1.51 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:50:44 PM PDT 24
Peak memory 236380 kb
Host smart-2e19acb9-e4a2-4cfa-8702-0db34086575a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2346723864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2346723864
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.793336958
Short name T727
Test name
Test status
Simulation time 6106825683 ps
CPU time 38.91 seconds
Started Apr 18 01:51:03 PM PDT 24
Finished Apr 18 01:51:42 PM PDT 24
Peak memory 243724 kb
Host smart-a5d250bf-9060-4eec-beb0-4ac24fa91c12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=793336958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.793336958
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.568479199
Short name T149
Test name
Test status
Simulation time 5886315950 ps
CPU time 360.28 seconds
Started Apr 18 01:51:02 PM PDT 24
Finished Apr 18 01:57:03 PM PDT 24
Peak memory 264964 kb
Host smart-10192240-5a1e-41b1-b6b0-2b391163512e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=568479199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.568479199
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1251662257
Short name T785
Test name
Test status
Simulation time 215864770 ps
CPU time 19.19 seconds
Started Apr 18 01:50:45 PM PDT 24
Finished Apr 18 01:51:05 PM PDT 24
Peak memory 248216 kb
Host smart-66747fc3-e263-45a9-9615-f475cf6c9c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1251662257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1251662257
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2333102088
Short name T774
Test name
Test status
Simulation time 344452811 ps
CPU time 11.07 seconds
Started Apr 18 01:51:16 PM PDT 24
Finished Apr 18 01:51:28 PM PDT 24
Peak memory 248276 kb
Host smart-67555874-b850-4472-a6e5-bc438822f275
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333102088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2333102088
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.712648145
Short name T204
Test name
Test status
Simulation time 125215013 ps
CPU time 7.86 seconds
Started Apr 18 01:50:45 PM PDT 24
Finished Apr 18 01:50:54 PM PDT 24
Peak memory 236316 kb
Host smart-e1f65f06-2054-44f8-a5a8-ffed21a1ee86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=712648145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.712648145
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2087421289
Short name T786
Test name
Test status
Simulation time 18226108 ps
CPU time 1.47 seconds
Started Apr 18 01:50:50 PM PDT 24
Finished Apr 18 01:50:53 PM PDT 24
Peak memory 235500 kb
Host smart-1055afab-33c5-4fb8-9f64-cd611e239f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2087421289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2087421289
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.111702003
Short name T752
Test name
Test status
Simulation time 1190985929 ps
CPU time 38.11 seconds
Started Apr 18 01:50:54 PM PDT 24
Finished Apr 18 01:51:33 PM PDT 24
Peak memory 243676 kb
Host smart-8973104f-768b-45cc-8728-92bf6dc09bd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=111702003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.111702003
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2657938055
Short name T151
Test name
Test status
Simulation time 1917432868 ps
CPU time 142.65 seconds
Started Apr 18 01:50:52 PM PDT 24
Finished Apr 18 01:53:15 PM PDT 24
Peak memory 256720 kb
Host smart-c0d2a279-7b86-4a1e-976a-c2359ccad80d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2657938055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2657938055
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.540260697
Short name T801
Test name
Test status
Simulation time 115699414 ps
CPU time 8.19 seconds
Started Apr 18 01:51:03 PM PDT 24
Finished Apr 18 01:51:12 PM PDT 24
Peak memory 248272 kb
Host smart-8f4db8e3-2475-47bf-838c-e49e5f2a4ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=540260697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.540260697
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3915113120
Short name T777
Test name
Test status
Simulation time 98555083 ps
CPU time 4.97 seconds
Started Apr 18 01:51:12 PM PDT 24
Finished Apr 18 01:51:18 PM PDT 24
Peak memory 238696 kb
Host smart-6f3b2753-31ed-49bc-a553-3d6927e3ac10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915113120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3915113120
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2633723582
Short name T763
Test name
Test status
Simulation time 495681968 ps
CPU time 10.49 seconds
Started Apr 18 01:51:12 PM PDT 24
Finished Apr 18 01:51:23 PM PDT 24
Peak memory 236324 kb
Host smart-871bf3db-ec06-409b-88ef-03c7fdea73b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2633723582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2633723582
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3445032926
Short name T756
Test name
Test status
Simulation time 23383892 ps
CPU time 1.48 seconds
Started Apr 18 01:50:43 PM PDT 24
Finished Apr 18 01:50:46 PM PDT 24
Peak memory 235492 kb
Host smart-c6404568-ccb0-4972-b10d-8e7634436da4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3445032926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3445032926
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.898419698
Short name T824
Test name
Test status
Simulation time 546788704 ps
CPU time 43.55 seconds
Started Apr 18 01:51:15 PM PDT 24
Finished Apr 18 01:51:59 PM PDT 24
Peak memory 244436 kb
Host smart-15eaaa4b-456c-4609-855d-94164c185d6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=898419698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.898419698
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1376976132
Short name T155
Test name
Test status
Simulation time 9872527968 ps
CPU time 163.76 seconds
Started Apr 18 01:51:08 PM PDT 24
Finished Apr 18 01:53:52 PM PDT 24
Peak memory 256768 kb
Host smart-98ea8e97-5f31-4d8c-8899-18ec5468a7c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1376976132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1376976132
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2354346142
Short name T140
Test name
Test status
Simulation time 12436971233 ps
CPU time 877.1 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 02:05:21 PM PDT 24
Peak memory 265000 kb
Host smart-700a3ac3-19bf-4ba0-9646-936b1883f626
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354346142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2354346142
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.46388818
Short name T733
Test name
Test status
Simulation time 99727188 ps
CPU time 8.22 seconds
Started Apr 18 01:50:55 PM PDT 24
Finished Apr 18 01:51:04 PM PDT 24
Peak memory 248188 kb
Host smart-b6301aea-3afa-4d81-a764-22e4c764ab57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=46388818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.46388818
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.4244198195
Short name T817
Test name
Test status
Simulation time 1024836140 ps
CPU time 10.14 seconds
Started Apr 18 01:51:09 PM PDT 24
Finished Apr 18 01:51:20 PM PDT 24
Peak memory 256300 kb
Host smart-21731150-1582-4654-9eb6-787b03d06b4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244198195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.4244198195
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2481316689
Short name T789
Test name
Test status
Simulation time 32999043 ps
CPU time 5.17 seconds
Started Apr 18 01:50:48 PM PDT 24
Finished Apr 18 01:50:54 PM PDT 24
Peak memory 236368 kb
Host smart-c5f33d47-f78a-4b70-8620-32fa3f02ecf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2481316689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2481316689
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.978129449
Short name T760
Test name
Test status
Simulation time 13266648 ps
CPU time 1.87 seconds
Started Apr 18 01:51:19 PM PDT 24
Finished Apr 18 01:51:21 PM PDT 24
Peak memory 235404 kb
Host smart-6cfc3ac8-545f-40f1-98f4-d51f647a9097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=978129449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.978129449
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3667866284
Short name T740
Test name
Test status
Simulation time 92896185 ps
CPU time 13.31 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:51:40 PM PDT 24
Peak memory 239964 kb
Host smart-df333795-f17f-409b-984e-38b236ddb6fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3667866284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3667866284
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.229712809
Short name T146
Test name
Test status
Simulation time 3262390839 ps
CPU time 131.31 seconds
Started Apr 18 01:51:16 PM PDT 24
Finished Apr 18 01:53:28 PM PDT 24
Peak memory 256592 kb
Host smart-f4a8a683-2ddb-471a-bd95-e29ede67431e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=229712809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.229712809
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.961454727
Short name T166
Test name
Test status
Simulation time 4569442027 ps
CPU time 612.66 seconds
Started Apr 18 01:51:15 PM PDT 24
Finished Apr 18 02:01:29 PM PDT 24
Peak memory 273124 kb
Host smart-86540d9c-1953-4252-a3fa-6f8b6c1c0754
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961454727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.961454727
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.626422969
Short name T253
Test name
Test status
Simulation time 1203344469 ps
CPU time 24.04 seconds
Started Apr 18 01:51:06 PM PDT 24
Finished Apr 18 01:51:30 PM PDT 24
Peak memory 248280 kb
Host smart-48c8be27-08a7-41f7-a237-2dc306564692
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=626422969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.626422969
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1523899825
Short name T719
Test name
Test status
Simulation time 572749954 ps
CPU time 81.41 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:51:53 PM PDT 24
Peak memory 240012 kb
Host smart-4d271c59-c933-4140-b4e0-1bde5afaccd8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1523899825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1523899825
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.409380294
Short name T753
Test name
Test status
Simulation time 858153086 ps
CPU time 145.78 seconds
Started Apr 18 01:50:37 PM PDT 24
Finished Apr 18 01:53:04 PM PDT 24
Peak memory 236164 kb
Host smart-188c37a5-d0ae-49dc-8036-3651bdf10dd9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=409380294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.409380294
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.350010253
Short name T750
Test name
Test status
Simulation time 138719268 ps
CPU time 6.69 seconds
Started Apr 18 01:50:38 PM PDT 24
Finished Apr 18 01:50:45 PM PDT 24
Peak memory 239972 kb
Host smart-a6cfa686-b6ab-46ee-9c8c-3def9ba2700a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=350010253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.350010253
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3068637994
Short name T827
Test name
Test status
Simulation time 159985676 ps
CPU time 7.34 seconds
Started Apr 18 01:50:32 PM PDT 24
Finished Apr 18 01:50:40 PM PDT 24
Peak memory 240304 kb
Host smart-9abe30c7-8ab1-4205-8240-8e84117960d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068637994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3068637994
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.623752050
Short name T202
Test name
Test status
Simulation time 494931921 ps
CPU time 9.15 seconds
Started Apr 18 01:51:15 PM PDT 24
Finished Apr 18 01:51:25 PM PDT 24
Peak memory 236152 kb
Host smart-8751ea5f-e5d3-4d07-9790-bb284bf3fda9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=623752050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.623752050
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3783686195
Short name T770
Test name
Test status
Simulation time 7555591 ps
CPU time 1.42 seconds
Started Apr 18 01:50:38 PM PDT 24
Finished Apr 18 01:50:40 PM PDT 24
Peak memory 236332 kb
Host smart-cc956113-0ede-4861-bfe0-cd198f6fee17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3783686195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3783686195
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2016438498
Short name T822
Test name
Test status
Simulation time 1294156463 ps
CPU time 50.37 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:51:22 PM PDT 24
Peak memory 243696 kb
Host smart-885c409b-318c-43b3-b531-6a7e9b52ce75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2016438498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2016438498
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3828963839
Short name T145
Test name
Test status
Simulation time 2575539834 ps
CPU time 171.98 seconds
Started Apr 18 01:50:36 PM PDT 24
Finished Apr 18 01:53:28 PM PDT 24
Peak memory 256752 kb
Host smart-03a62270-feb5-4220-bbee-31c37b9e52f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3828963839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3828963839
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.64699484
Short name T364
Test name
Test status
Simulation time 8058636164 ps
CPU time 335.07 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:56:06 PM PDT 24
Peak memory 267244 kb
Host smart-c9bd2333-8f3f-4e69-9354-c67bcd126b56
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64699484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.64699484
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.925789112
Short name T712
Test name
Test status
Simulation time 1237251133 ps
CPU time 12.54 seconds
Started Apr 18 01:50:32 PM PDT 24
Finished Apr 18 01:50:46 PM PDT 24
Peak memory 252836 kb
Host smart-ed044ac2-c3e8-471f-bf4e-73bc39f4d9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=925789112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.925789112
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3868200939
Short name T173
Test name
Test status
Simulation time 27753296 ps
CPU time 1.57 seconds
Started Apr 18 01:51:12 PM PDT 24
Finished Apr 18 01:51:14 PM PDT 24
Peak memory 235524 kb
Host smart-44f975f3-6a31-4a79-bce1-25974c99c3db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3868200939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3868200939
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.282811477
Short name T255
Test name
Test status
Simulation time 24771392 ps
CPU time 1.52 seconds
Started Apr 18 01:51:14 PM PDT 24
Finished Apr 18 01:51:16 PM PDT 24
Peak memory 236268 kb
Host smart-3b60cf8b-f2b7-43ff-84f5-b03bc0960fea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=282811477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.282811477
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1237843181
Short name T714
Test name
Test status
Simulation time 16587919 ps
CPU time 1.5 seconds
Started Apr 18 01:50:48 PM PDT 24
Finished Apr 18 01:50:50 PM PDT 24
Peak memory 235488 kb
Host smart-2f896186-abad-4f14-88e4-5e1e8cbadb59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1237843181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1237843181
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.4099605512
Short name T247
Test name
Test status
Simulation time 9177141 ps
CPU time 1.61 seconds
Started Apr 18 01:51:10 PM PDT 24
Finished Apr 18 01:51:12 PM PDT 24
Peak memory 236384 kb
Host smart-9ab100be-cb9d-4a86-851a-76a8c98b7cec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4099605512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.4099605512
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.4072106651
Short name T819
Test name
Test status
Simulation time 8801445 ps
CPU time 1.51 seconds
Started Apr 18 01:50:47 PM PDT 24
Finished Apr 18 01:50:49 PM PDT 24
Peak memory 235448 kb
Host smart-d7d7898e-4abb-4e6b-9bbc-35107465a748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4072106651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.4072106651
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1476154284
Short name T787
Test name
Test status
Simulation time 7854071 ps
CPU time 1.27 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:51:28 PM PDT 24
Peak memory 236268 kb
Host smart-cfbe7a75-057b-4c61-ad53-1bcf61bb1cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1476154284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1476154284
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1261052515
Short name T818
Test name
Test status
Simulation time 7201734 ps
CPU time 1.5 seconds
Started Apr 18 01:50:47 PM PDT 24
Finished Apr 18 01:50:50 PM PDT 24
Peak memory 236380 kb
Host smart-15ce596e-be48-41e9-9eed-d07cc6fcf7ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1261052515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1261052515
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2661642113
Short name T825
Test name
Test status
Simulation time 32015621 ps
CPU time 1.96 seconds
Started Apr 18 01:50:59 PM PDT 24
Finished Apr 18 01:51:02 PM PDT 24
Peak memory 236384 kb
Host smart-68792952-7293-4ddc-a9ea-f2a6c942a768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2661642113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2661642113
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2895070394
Short name T809
Test name
Test status
Simulation time 16376967 ps
CPU time 1.64 seconds
Started Apr 18 01:51:09 PM PDT 24
Finished Apr 18 01:51:11 PM PDT 24
Peak memory 236388 kb
Host smart-ca808c4d-f7ff-48ae-9cbc-14269a14e7a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2895070394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2895070394
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2335952873
Short name T773
Test name
Test status
Simulation time 6443996 ps
CPU time 1.46 seconds
Started Apr 18 01:50:46 PM PDT 24
Finished Apr 18 01:50:48 PM PDT 24
Peak memory 236336 kb
Host smart-bd478f9b-91a3-4b62-b673-c653914fe46f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2335952873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2335952873
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1645735627
Short name T716
Test name
Test status
Simulation time 1687120081 ps
CPU time 123.69 seconds
Started Apr 18 01:50:36 PM PDT 24
Finished Apr 18 01:52:40 PM PDT 24
Peak memory 239984 kb
Host smart-bc458d5e-d337-4dce-952f-1712a683ddd6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1645735627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1645735627
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3505693494
Short name T711
Test name
Test status
Simulation time 823608406 ps
CPU time 87.75 seconds
Started Apr 18 01:50:40 PM PDT 24
Finished Apr 18 01:52:08 PM PDT 24
Peak memory 235280 kb
Host smart-72d718e8-6b27-42d3-ac3f-c10498e12ce7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3505693494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3505693494
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.873830915
Short name T815
Test name
Test status
Simulation time 110668293 ps
CPU time 9.22 seconds
Started Apr 18 01:50:36 PM PDT 24
Finished Apr 18 01:50:46 PM PDT 24
Peak memory 239940 kb
Host smart-a3887408-acd2-4cf9-8529-7ffc4eecfdae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=873830915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.873830915
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1448802467
Short name T725
Test name
Test status
Simulation time 197429915 ps
CPU time 7.06 seconds
Started Apr 18 01:50:40 PM PDT 24
Finished Apr 18 01:50:47 PM PDT 24
Peak memory 255204 kb
Host smart-19388518-aa7c-4aa2-bf67-3c454b339288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448802467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1448802467
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2322321949
Short name T797
Test name
Test status
Simulation time 93190140 ps
CPU time 7.74 seconds
Started Apr 18 01:50:39 PM PDT 24
Finished Apr 18 01:50:47 PM PDT 24
Peak memory 236320 kb
Host smart-95dc24fc-e82d-4160-8236-cb173901cfbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2322321949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2322321949
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3406419123
Short name T793
Test name
Test status
Simulation time 20137032 ps
CPU time 1.35 seconds
Started Apr 18 01:50:36 PM PDT 24
Finished Apr 18 01:50:38 PM PDT 24
Peak memory 235480 kb
Host smart-7f70d7c7-d6c8-48ba-bda0-3f8c4ae4f2da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3406419123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3406419123
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3362170179
Short name T803
Test name
Test status
Simulation time 2735331930 ps
CPU time 36.92 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:51:10 PM PDT 24
Peak memory 243756 kb
Host smart-6dfc1aef-5804-4a31-9292-9a96ced3d74e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3362170179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3362170179
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3765617754
Short name T158
Test name
Test status
Simulation time 6206575179 ps
CPU time 455.46 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:58:17 PM PDT 24
Peak memory 264700 kb
Host smart-7f5c2bb3-fb8e-4900-bc33-f94003ed0929
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765617754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3765617754
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3603628445
Short name T776
Test name
Test status
Simulation time 335673828 ps
CPU time 24.83 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:50:57 PM PDT 24
Peak memory 248140 kb
Host smart-8a615bfd-6d80-4dae-80ad-c1bc284910fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3603628445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3603628445
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.4075905324
Short name T784
Test name
Test status
Simulation time 15719512 ps
CPU time 1.6 seconds
Started Apr 18 01:51:11 PM PDT 24
Finished Apr 18 01:51:13 PM PDT 24
Peak memory 236376 kb
Host smart-4e09c1dd-9593-4884-9657-df6f69b23b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4075905324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.4075905324
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3768353381
Short name T778
Test name
Test status
Simulation time 15654963 ps
CPU time 1.49 seconds
Started Apr 18 01:51:17 PM PDT 24
Finished Apr 18 01:51:19 PM PDT 24
Peak memory 236356 kb
Host smart-2a082ae4-6872-426c-8de1-39b8cb64143a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3768353381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3768353381
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3724243590
Short name T791
Test name
Test status
Simulation time 14956227 ps
CPU time 1.71 seconds
Started Apr 18 01:51:05 PM PDT 24
Finished Apr 18 01:51:07 PM PDT 24
Peak memory 236324 kb
Host smart-d88a1603-b23f-4fa2-aca5-f8b1f9d792a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3724243590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3724243590
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3556312839
Short name T732
Test name
Test status
Simulation time 20742114 ps
CPU time 1.49 seconds
Started Apr 18 01:51:00 PM PDT 24
Finished Apr 18 01:51:02 PM PDT 24
Peak memory 235504 kb
Host smart-a31fbb20-4e12-417f-96d5-fef6aaa6a485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3556312839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3556312839
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3940856574
Short name T782
Test name
Test status
Simulation time 18669173 ps
CPU time 1.44 seconds
Started Apr 18 01:51:06 PM PDT 24
Finished Apr 18 01:51:08 PM PDT 24
Peak memory 236556 kb
Host smart-a8aaeedd-0f5d-48b8-a7ce-4341988f743d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3940856574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3940856574
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3712808730
Short name T357
Test name
Test status
Simulation time 19067855 ps
CPU time 1.31 seconds
Started Apr 18 01:51:15 PM PDT 24
Finished Apr 18 01:51:17 PM PDT 24
Peak memory 235692 kb
Host smart-676d0aff-0005-4e29-a45f-0802b8fc5b1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3712808730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3712808730
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1088229683
Short name T779
Test name
Test status
Simulation time 8853406 ps
CPU time 1.52 seconds
Started Apr 18 01:50:46 PM PDT 24
Finished Apr 18 01:50:48 PM PDT 24
Peak memory 236376 kb
Host smart-032a6834-478b-48f3-bcf2-ebb77f8b4bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1088229683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1088229683
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2795092524
Short name T769
Test name
Test status
Simulation time 10443707 ps
CPU time 1.4 seconds
Started Apr 18 01:50:46 PM PDT 24
Finished Apr 18 01:50:48 PM PDT 24
Peak memory 234532 kb
Host smart-cae9c2e0-3535-4843-b426-4f7b1ea44e47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2795092524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2795092524
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3466853963
Short name T805
Test name
Test status
Simulation time 19389041 ps
CPU time 1.44 seconds
Started Apr 18 01:51:18 PM PDT 24
Finished Apr 18 01:51:20 PM PDT 24
Peak memory 236384 kb
Host smart-296eeedc-6981-4580-80bb-36ec3909294b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3466853963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3466853963
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2430416441
Short name T738
Test name
Test status
Simulation time 9642339 ps
CPU time 1.22 seconds
Started Apr 18 01:51:21 PM PDT 24
Finished Apr 18 01:51:22 PM PDT 24
Peak memory 236396 kb
Host smart-40d99e97-4d60-498b-925b-cfd86f55cf1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2430416441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2430416441
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.801808035
Short name T830
Test name
Test status
Simulation time 558216550 ps
CPU time 77.24 seconds
Started Apr 18 01:50:48 PM PDT 24
Finished Apr 18 01:52:06 PM PDT 24
Peak memory 236348 kb
Host smart-15c89f62-573e-4303-9b90-078688d6f5b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=801808035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.801808035
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1529847574
Short name T734
Test name
Test status
Simulation time 2971701658 ps
CPU time 194.17 seconds
Started Apr 18 01:50:36 PM PDT 24
Finished Apr 18 01:53:51 PM PDT 24
Peak memory 236428 kb
Host smart-ee9467d3-50ce-4d7d-8047-b2de6d19c59d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1529847574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1529847574
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1588706006
Short name T766
Test name
Test status
Simulation time 722966492 ps
CPU time 8.53 seconds
Started Apr 18 01:50:37 PM PDT 24
Finished Apr 18 01:50:46 PM PDT 24
Peak memory 239956 kb
Host smart-9bb1fb45-1c5c-4e0c-bed6-2f9970d9d1f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1588706006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1588706006
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3670532013
Short name T720
Test name
Test status
Simulation time 217179138 ps
CPU time 5.39 seconds
Started Apr 18 01:50:36 PM PDT 24
Finished Apr 18 01:50:42 PM PDT 24
Peak memory 239380 kb
Host smart-0bf6d182-bb79-4201-be0b-64d5be88d05b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670532013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3670532013
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3986924427
Short name T796
Test name
Test status
Simulation time 48897423 ps
CPU time 4.52 seconds
Started Apr 18 01:50:38 PM PDT 24
Finished Apr 18 01:50:43 PM PDT 24
Peak memory 236348 kb
Host smart-41235ba4-aa83-409f-a1e2-18030b61fb11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3986924427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3986924427
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1112238989
Short name T813
Test name
Test status
Simulation time 25682284 ps
CPU time 1.24 seconds
Started Apr 18 01:50:37 PM PDT 24
Finished Apr 18 01:50:39 PM PDT 24
Peak memory 234352 kb
Host smart-7d3c03f8-9b78-47c6-9c6f-c8ae8cd6197c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1112238989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1112238989
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3092461072
Short name T717
Test name
Test status
Simulation time 2236748424 ps
CPU time 37.17 seconds
Started Apr 18 01:50:38 PM PDT 24
Finished Apr 18 01:51:15 PM PDT 24
Peak memory 243756 kb
Host smart-ba4e5eb7-9f63-4e4e-b11c-1c02478229f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3092461072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3092461072
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.563312384
Short name T811
Test name
Test status
Simulation time 4649111965 ps
CPU time 105.48 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:52:27 PM PDT 24
Peak memory 256760 kb
Host smart-ba711fa9-be49-4c5d-8efe-6a8c06646ab0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=563312384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.563312384
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3891963705
Short name T163
Test name
Test status
Simulation time 4581041313 ps
CPU time 299.71 seconds
Started Apr 18 01:50:35 PM PDT 24
Finished Apr 18 01:55:35 PM PDT 24
Peak memory 264956 kb
Host smart-729b4188-7dc6-4e83-9495-ffd11a9315bf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891963705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3891963705
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.221689087
Short name T800
Test name
Test status
Simulation time 432483243 ps
CPU time 10.51 seconds
Started Apr 18 01:50:35 PM PDT 24
Finished Apr 18 01:50:46 PM PDT 24
Peak memory 248188 kb
Host smart-2dcd3652-6c44-451c-9c20-5e72d80696bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=221689087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.221689087
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.373928853
Short name T826
Test name
Test status
Simulation time 15326359 ps
CPU time 1.32 seconds
Started Apr 18 01:50:56 PM PDT 24
Finished Apr 18 01:50:58 PM PDT 24
Peak memory 236336 kb
Host smart-a73d8769-66b9-4105-a5cf-8844b2658cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=373928853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.373928853
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1689180095
Short name T731
Test name
Test status
Simulation time 7761758 ps
CPU time 1.27 seconds
Started Apr 18 01:50:54 PM PDT 24
Finished Apr 18 01:50:55 PM PDT 24
Peak memory 235516 kb
Host smart-e3e9a8c3-69a0-4a5a-9907-bb90b9a5d3a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1689180095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1689180095
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3969644222
Short name T355
Test name
Test status
Simulation time 7504168 ps
CPU time 1.5 seconds
Started Apr 18 01:50:54 PM PDT 24
Finished Apr 18 01:50:55 PM PDT 24
Peak memory 236352 kb
Host smart-f93704e3-b594-4e2f-a7b8-819fb0a5c1cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3969644222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3969644222
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2091832325
Short name T767
Test name
Test status
Simulation time 7807486 ps
CPU time 1.36 seconds
Started Apr 18 01:50:54 PM PDT 24
Finished Apr 18 01:50:55 PM PDT 24
Peak memory 235536 kb
Host smart-aaf1110d-2058-460c-b64e-f6266b9164ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2091832325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2091832325
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2121244174
Short name T360
Test name
Test status
Simulation time 17056737 ps
CPU time 1.3 seconds
Started Apr 18 01:50:54 PM PDT 24
Finished Apr 18 01:50:56 PM PDT 24
Peak memory 235516 kb
Host smart-37399375-4802-4f10-9928-09280d3261ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2121244174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2121244174
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1377172068
Short name T768
Test name
Test status
Simulation time 10504973 ps
CPU time 1.43 seconds
Started Apr 18 01:50:54 PM PDT 24
Finished Apr 18 01:50:56 PM PDT 24
Peak memory 235472 kb
Host smart-7298c308-3e91-41e5-a69d-46906b037860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1377172068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1377172068
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.350698978
Short name T792
Test name
Test status
Simulation time 6580665 ps
CPU time 1.45 seconds
Started Apr 18 01:51:20 PM PDT 24
Finished Apr 18 01:51:22 PM PDT 24
Peak memory 235376 kb
Host smart-29518f6e-fa8c-4cb6-b70c-11d4e19796a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=350698978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.350698978
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.704003129
Short name T358
Test name
Test status
Simulation time 16757037 ps
CPU time 1.8 seconds
Started Apr 18 01:50:57 PM PDT 24
Finished Apr 18 01:51:00 PM PDT 24
Peak memory 236336 kb
Host smart-8fabbb4b-70f3-41fb-9940-24f8c4a2f0f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=704003129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.704003129
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4217055774
Short name T761
Test name
Test status
Simulation time 19449185 ps
CPU time 1.38 seconds
Started Apr 18 01:50:52 PM PDT 24
Finished Apr 18 01:50:59 PM PDT 24
Peak memory 235508 kb
Host smart-b68deb66-fb05-4756-912f-efee09952a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4217055774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4217055774
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2758928984
Short name T807
Test name
Test status
Simulation time 685225432 ps
CPU time 12.1 seconds
Started Apr 18 01:50:39 PM PDT 24
Finished Apr 18 01:50:51 PM PDT 24
Peak memory 251896 kb
Host smart-bb97065d-f3cb-4a7b-bd15-3aa7bf77799a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758928984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2758928984
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1214442637
Short name T744
Test name
Test status
Simulation time 302530552 ps
CPU time 9.56 seconds
Started Apr 18 01:50:34 PM PDT 24
Finished Apr 18 01:50:44 PM PDT 24
Peak memory 236368 kb
Host smart-43ec28a0-a164-421e-b0bd-5df062a0413b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1214442637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1214442637
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.590092084
Short name T742
Test name
Test status
Simulation time 10850919 ps
CPU time 1.35 seconds
Started Apr 18 01:50:36 PM PDT 24
Finished Apr 18 01:50:38 PM PDT 24
Peak memory 234460 kb
Host smart-87511e6c-a412-47a3-9954-c7e1c619bac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=590092084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.590092084
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2905768558
Short name T205
Test name
Test status
Simulation time 398458548 ps
CPU time 13.46 seconds
Started Apr 18 01:50:36 PM PDT 24
Finished Apr 18 01:50:50 PM PDT 24
Peak memory 244572 kb
Host smart-44bc9e0b-fade-44f6-ac7d-9790a4f04b9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2905768558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2905768558
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1580569555
Short name T162
Test name
Test status
Simulation time 15718473970 ps
CPU time 352.79 seconds
Started Apr 18 01:50:44 PM PDT 24
Finished Apr 18 01:56:38 PM PDT 24
Peak memory 268736 kb
Host smart-02f1f833-c0b5-4ee7-ac86-d44a74eae9a0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580569555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1580569555
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3331881677
Short name T758
Test name
Test status
Simulation time 255169364 ps
CPU time 19.44 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:50:51 PM PDT 24
Peak memory 248236 kb
Host smart-192b240a-573d-43b1-9e5c-03f58d30fc3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3331881677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3331881677
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1264040451
Short name T175
Test name
Test status
Simulation time 59934602 ps
CPU time 2.1 seconds
Started Apr 18 01:50:38 PM PDT 24
Finished Apr 18 01:50:41 PM PDT 24
Peak memory 235484 kb
Host smart-996bc95c-e315-441d-944b-c9ffd2d68b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1264040451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1264040451
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3050333836
Short name T729
Test name
Test status
Simulation time 321406351 ps
CPU time 5.74 seconds
Started Apr 18 01:50:43 PM PDT 24
Finished Apr 18 01:50:50 PM PDT 24
Peak memory 239180 kb
Host smart-3f71effb-4d76-4368-8665-6dfed80a607e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050333836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3050333836
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2107845523
Short name T751
Test name
Test status
Simulation time 440545237 ps
CPU time 8.86 seconds
Started Apr 18 01:50:36 PM PDT 24
Finished Apr 18 01:50:45 PM PDT 24
Peak memory 236348 kb
Host smart-709193de-91af-44ed-a11c-5839b8ff6989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2107845523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2107845523
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2797699047
Short name T721
Test name
Test status
Simulation time 9675697 ps
CPU time 1.52 seconds
Started Apr 18 01:50:36 PM PDT 24
Finished Apr 18 01:50:38 PM PDT 24
Peak memory 235524 kb
Host smart-7d15f0b3-62c9-4273-98b1-5ed69db3bc96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2797699047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2797699047
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.761684762
Short name T203
Test name
Test status
Simulation time 122608748 ps
CPU time 13.67 seconds
Started Apr 18 01:50:40 PM PDT 24
Finished Apr 18 01:50:54 PM PDT 24
Peak memory 244348 kb
Host smart-1f913e50-e7ed-4142-a0f2-e5c0adfa89be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=761684762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.761684762
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2555672047
Short name T156
Test name
Test status
Simulation time 10600764478 ps
CPU time 593.77 seconds
Started Apr 18 01:50:40 PM PDT 24
Finished Apr 18 02:00:35 PM PDT 24
Peak memory 264740 kb
Host smart-6f1e9748-cef4-45ad-ac36-eab8db20ad75
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555672047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2555672047
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.916586411
Short name T723
Test name
Test status
Simulation time 1664416618 ps
CPU time 20.74 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:51:02 PM PDT 24
Peak memory 254368 kb
Host smart-661836db-fa81-4a56-af1b-9b6c7efe7b39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=916586411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.916586411
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.310245153
Short name T185
Test name
Test status
Simulation time 586278253 ps
CPU time 11.05 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:50:53 PM PDT 24
Peak memory 249312 kb
Host smart-9237e9d5-07f2-4387-a898-4159580b5c4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310245153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.310245153
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3134075408
Short name T186
Test name
Test status
Simulation time 38874566 ps
CPU time 6.4 seconds
Started Apr 18 01:50:43 PM PDT 24
Finished Apr 18 01:50:50 PM PDT 24
Peak memory 236228 kb
Host smart-66eca65c-3914-4024-b516-9a3f04a8567c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3134075408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3134075408
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3027489975
Short name T361
Test name
Test status
Simulation time 9626243 ps
CPU time 1.62 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:50:45 PM PDT 24
Peak memory 236412 kb
Host smart-03b151f2-fa55-479d-93af-f17955045758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3027489975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3027489975
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.4051335578
Short name T759
Test name
Test status
Simulation time 84671523 ps
CPU time 12.53 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:51:04 PM PDT 24
Peak memory 244524 kb
Host smart-cdae8431-3aad-4414-9e55-696751dec176
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4051335578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.4051335578
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2629148107
Short name T148
Test name
Test status
Simulation time 1543675457 ps
CPU time 99.85 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:52:23 PM PDT 24
Peak memory 256668 kb
Host smart-140201d0-9e87-488e-bf18-6be9b4f55bee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2629148107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2629148107
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2170605644
Short name T709
Test name
Test status
Simulation time 827041861 ps
CPU time 16.65 seconds
Started Apr 18 01:50:38 PM PDT 24
Finished Apr 18 01:50:55 PM PDT 24
Peak memory 248196 kb
Host smart-0732c963-ec41-41bf-9b51-46733b38e937
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2170605644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2170605644
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1522365632
Short name T765
Test name
Test status
Simulation time 71407143 ps
CPU time 11.99 seconds
Started Apr 18 01:50:37 PM PDT 24
Finished Apr 18 01:50:50 PM PDT 24
Peak memory 253456 kb
Host smart-56ee29be-e7e5-4c8a-88c1-6a99f2e72de7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522365632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1522365632
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3089920103
Short name T735
Test name
Test status
Simulation time 130698924 ps
CPU time 9.77 seconds
Started Apr 18 01:50:48 PM PDT 24
Finished Apr 18 01:50:59 PM PDT 24
Peak memory 236220 kb
Host smart-f5bafb33-f962-4ea9-b49a-48ccde054a22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3089920103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3089920103
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1655918102
Short name T356
Test name
Test status
Simulation time 14163368 ps
CPU time 1.27 seconds
Started Apr 18 01:50:43 PM PDT 24
Finished Apr 18 01:50:45 PM PDT 24
Peak memory 236292 kb
Host smart-7e80906f-8188-454e-aa9a-9c17af518fd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1655918102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1655918102
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3465429256
Short name T780
Test name
Test status
Simulation time 272126749 ps
CPU time 19.56 seconds
Started Apr 18 01:51:10 PM PDT 24
Finished Apr 18 01:51:30 PM PDT 24
Peak memory 244556 kb
Host smart-eeec1ea2-8d30-4f2f-9586-441cf78d1e6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3465429256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3465429256
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3210414424
Short name T741
Test name
Test status
Simulation time 649348854 ps
CPU time 10.83 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:50:53 PM PDT 24
Peak memory 248244 kb
Host smart-f4749a81-da32-4855-8d78-140e7fec076d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3210414424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3210414424
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2738197079
Short name T828
Test name
Test status
Simulation time 64654921 ps
CPU time 4.84 seconds
Started Apr 18 01:50:44 PM PDT 24
Finished Apr 18 01:50:50 PM PDT 24
Peak memory 238132 kb
Host smart-de129b7e-6ae0-4e6f-91d2-05c9e2b1197b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738197079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2738197079
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2741274238
Short name T781
Test name
Test status
Simulation time 482653443 ps
CPU time 9.45 seconds
Started Apr 18 01:50:40 PM PDT 24
Finished Apr 18 01:50:50 PM PDT 24
Peak memory 240024 kb
Host smart-b2e63abd-b6e7-4da2-8a1b-f5800b6c7839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2741274238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2741274238
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2531953314
Short name T359
Test name
Test status
Simulation time 8617434 ps
CPU time 1.29 seconds
Started Apr 18 01:50:45 PM PDT 24
Finished Apr 18 01:50:47 PM PDT 24
Peak memory 235376 kb
Host smart-2a0af6fe-e349-4615-98ca-f8c3a038949a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2531953314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2531953314
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1203896301
Short name T718
Test name
Test status
Simulation time 1080106226 ps
CPU time 20.52 seconds
Started Apr 18 01:50:43 PM PDT 24
Finished Apr 18 01:51:05 PM PDT 24
Peak memory 244556 kb
Host smart-9e040b56-93b2-4a59-96e7-b90172f23c95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1203896301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1203896301
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1206775697
Short name T820
Test name
Test status
Simulation time 1096007007 ps
CPU time 18.74 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:51:02 PM PDT 24
Peak memory 253464 kb
Host smart-64d46d89-0acc-466d-af62-61a1a861e44a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1206775697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1206775697
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1863472175
Short name T788
Test name
Test status
Simulation time 99315233 ps
CPU time 2.93 seconds
Started Apr 18 01:50:42 PM PDT 24
Finished Apr 18 01:50:47 PM PDT 24
Peak memory 236300 kb
Host smart-25723cf0-e00d-4107-ae05-162e7a12eefe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1863472175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1863472175
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.152927673
Short name T678
Test name
Test status
Simulation time 18421260287 ps
CPU time 1433.04 seconds
Started Apr 18 02:46:05 PM PDT 24
Finished Apr 18 03:09:58 PM PDT 24
Peak memory 289592 kb
Host smart-cae3490e-a59c-4e61-9971-c73b0df9aeee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152927673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.152927673
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1993499947
Short name T426
Test name
Test status
Simulation time 158690028 ps
CPU time 8.05 seconds
Started Apr 18 02:46:10 PM PDT 24
Finished Apr 18 02:46:18 PM PDT 24
Peak memory 240836 kb
Host smart-c1711b47-e40d-41ef-8ab9-754b99c5243d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1993499947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1993499947
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1899221241
Short name T520
Test name
Test status
Simulation time 5207661468 ps
CPU time 305.52 seconds
Started Apr 18 02:46:05 PM PDT 24
Finished Apr 18 02:51:11 PM PDT 24
Peak memory 257140 kb
Host smart-28491506-83e6-4b6c-9a71-77fd780e35a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18992
21241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1899221241
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.4202733283
Short name T456
Test name
Test status
Simulation time 391811773 ps
CPU time 8.77 seconds
Started Apr 18 02:46:03 PM PDT 24
Finished Apr 18 02:46:12 PM PDT 24
Peak memory 252828 kb
Host smart-709b0a07-f998-417f-b925-1500f4c837ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42027
33283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.4202733283
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.211478262
Short name T296
Test name
Test status
Simulation time 203527443146 ps
CPU time 3211.76 seconds
Started Apr 18 02:46:04 PM PDT 24
Finished Apr 18 03:39:37 PM PDT 24
Peak memory 289584 kb
Host smart-52e235c2-fcfa-4a92-866a-c043e9fa2c5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211478262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.211478262
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3798739311
Short name T620
Test name
Test status
Simulation time 138976771 ps
CPU time 6.58 seconds
Started Apr 18 02:46:04 PM PDT 24
Finished Apr 18 02:46:11 PM PDT 24
Peak memory 249028 kb
Host smart-f8aba0ff-0c2d-4da3-9266-d554b070a72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37987
39311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3798739311
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3669858027
Short name T641
Test name
Test status
Simulation time 543473987 ps
CPU time 9.97 seconds
Started Apr 18 02:46:07 PM PDT 24
Finished Apr 18 02:46:17 PM PDT 24
Peak memory 249924 kb
Host smart-26e5330f-6585-4925-a901-7e214ed5f5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36698
58027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3669858027
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2788971816
Short name T13
Test name
Test status
Simulation time 835570046 ps
CPU time 13.71 seconds
Started Apr 18 02:46:16 PM PDT 24
Finished Apr 18 02:46:30 PM PDT 24
Peak memory 270000 kb
Host smart-c2050e37-dbfe-4a3c-9edb-ee897613bcde
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2788971816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2788971816
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.4059500858
Short name T53
Test name
Test status
Simulation time 1973526175 ps
CPU time 34.61 seconds
Started Apr 18 02:46:05 PM PDT 24
Finished Apr 18 02:46:40 PM PDT 24
Peak memory 248100 kb
Host smart-944eb03a-09ae-4a47-bb19-32a29a2fc40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40595
00858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.4059500858
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3105607826
Short name T419
Test name
Test status
Simulation time 1614886427 ps
CPU time 50.94 seconds
Started Apr 18 02:46:03 PM PDT 24
Finished Apr 18 02:46:54 PM PDT 24
Peak memory 249052 kb
Host smart-f2c8823a-7863-404f-9339-f983205812db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31056
07826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3105607826
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2822627116
Short name T625
Test name
Test status
Simulation time 141940676882 ps
CPU time 2516.99 seconds
Started Apr 18 02:46:08 PM PDT 24
Finished Apr 18 03:28:06 PM PDT 24
Peak memory 305948 kb
Host smart-272e3f3e-d8fe-411e-bfa7-1d5d04c4ba29
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822627116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2822627116
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3419291869
Short name T128
Test name
Test status
Simulation time 15311316611 ps
CPU time 1619.27 seconds
Started Apr 18 02:46:31 PM PDT 24
Finished Apr 18 03:13:31 PM PDT 24
Peak memory 290084 kb
Host smart-464c5b86-14e6-4ff1-828b-bd0d85601b19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419291869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3419291869
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1391059723
Short name T362
Test name
Test status
Simulation time 321067888 ps
CPU time 15.87 seconds
Started Apr 18 02:46:29 PM PDT 24
Finished Apr 18 02:46:45 PM PDT 24
Peak memory 251868 kb
Host smart-e837b3a3-bc82-4d6a-b2fd-ba79603f60f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1391059723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1391059723
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3660547272
Short name T474
Test name
Test status
Simulation time 1563766564 ps
CPU time 68.25 seconds
Started Apr 18 02:46:25 PM PDT 24
Finished Apr 18 02:47:33 PM PDT 24
Peak memory 256968 kb
Host smart-b349f29e-45a8-4028-b650-d5e7a292abed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36605
47272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3660547272
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3677254716
Short name T650
Test name
Test status
Simulation time 587590005 ps
CPU time 42.1 seconds
Started Apr 18 02:46:24 PM PDT 24
Finished Apr 18 02:47:06 PM PDT 24
Peak memory 255772 kb
Host smart-15d7fd88-f05e-4cef-ae04-61bef6985d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36772
54716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3677254716
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2364694375
Short name T74
Test name
Test status
Simulation time 68609287917 ps
CPU time 1446.49 seconds
Started Apr 18 02:46:31 PM PDT 24
Finished Apr 18 03:10:38 PM PDT 24
Peak memory 289380 kb
Host smart-1f1d60c8-5dfd-4497-9359-530388f639f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364694375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2364694375
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3843051110
Short name T573
Test name
Test status
Simulation time 190382552212 ps
CPU time 2503.6 seconds
Started Apr 18 02:46:29 PM PDT 24
Finished Apr 18 03:28:13 PM PDT 24
Peak memory 285960 kb
Host smart-3a349c3f-4670-4ae1-8639-78f742685d7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843051110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3843051110
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.200116610
Short name T24
Test name
Test status
Simulation time 145446465 ps
CPU time 8.39 seconds
Started Apr 18 02:46:13 PM PDT 24
Finished Apr 18 02:46:22 PM PDT 24
Peak memory 249168 kb
Host smart-842e287b-3d13-4d3e-a945-c1260c14c9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20011
6610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.200116610
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2610753639
Short name T597
Test name
Test status
Simulation time 488982013 ps
CPU time 38.91 seconds
Started Apr 18 02:46:28 PM PDT 24
Finished Apr 18 02:47:08 PM PDT 24
Peak memory 249088 kb
Host smart-766e9ceb-0b2e-4dc5-bfc8-996ff023bae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26107
53639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2610753639
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2520072930
Short name T12
Test name
Test status
Simulation time 469167293 ps
CPU time 14.48 seconds
Started Apr 18 02:46:35 PM PDT 24
Finished Apr 18 02:46:50 PM PDT 24
Peak memory 273848 kb
Host smart-8fc17e44-cf9c-46c1-aa28-601f5970b4e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2520072930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2520072930
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3192806196
Short name T554
Test name
Test status
Simulation time 330846526 ps
CPU time 9.1 seconds
Started Apr 18 02:46:30 PM PDT 24
Finished Apr 18 02:46:40 PM PDT 24
Peak memory 249100 kb
Host smart-065f326a-0328-4459-9d40-e31647fa4f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31928
06196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3192806196
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2639555794
Short name T236
Test name
Test status
Simulation time 3414210024 ps
CPU time 44.59 seconds
Started Apr 18 02:46:13 PM PDT 24
Finished Apr 18 02:46:58 PM PDT 24
Peak memory 249180 kb
Host smart-b8e68605-1216-4da0-beee-b9c40cfa0633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26395
55794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2639555794
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3436603222
Short name T101
Test name
Test status
Simulation time 190562785336 ps
CPU time 2623.73 seconds
Started Apr 18 02:46:27 PM PDT 24
Finished Apr 18 03:30:12 PM PDT 24
Peak memory 290124 kb
Host smart-13853329-eeeb-4604-811b-c991b326be60
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436603222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3436603222
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3348151630
Short name T436
Test name
Test status
Simulation time 187962452498 ps
CPU time 1993.21 seconds
Started Apr 18 02:48:59 PM PDT 24
Finished Apr 18 03:22:13 PM PDT 24
Peak memory 273536 kb
Host smart-d306a8f0-2e6a-40f8-9a03-a70714fb2f0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348151630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3348151630
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1255998818
Short name T248
Test name
Test status
Simulation time 1922954728 ps
CPU time 9.37 seconds
Started Apr 18 02:49:05 PM PDT 24
Finished Apr 18 02:49:15 PM PDT 24
Peak memory 240840 kb
Host smart-47a8f620-a610-47d7-9e33-e049210e92c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1255998818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1255998818
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.757021304
Short name T378
Test name
Test status
Simulation time 583180969 ps
CPU time 49.7 seconds
Started Apr 18 02:49:02 PM PDT 24
Finished Apr 18 02:49:52 PM PDT 24
Peak memory 256840 kb
Host smart-4fb0ecf2-447e-44e3-97af-e18dbf4d1c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75702
1304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.757021304
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2801124206
Short name T86
Test name
Test status
Simulation time 543583603 ps
CPU time 8.45 seconds
Started Apr 18 02:48:55 PM PDT 24
Finished Apr 18 02:49:04 PM PDT 24
Peak memory 251920 kb
Host smart-5954c83e-eb47-4f6f-84b0-618f84f09f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28011
24206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2801124206
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2955065195
Short name T198
Test name
Test status
Simulation time 20353551719 ps
CPU time 1286.07 seconds
Started Apr 18 02:49:05 PM PDT 24
Finished Apr 18 03:10:31 PM PDT 24
Peak memory 281928 kb
Host smart-f5195cd5-8c9d-4f92-894b-593fabc2cad1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955065195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2955065195
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2967631205
Short name T562
Test name
Test status
Simulation time 12577982295 ps
CPU time 268 seconds
Started Apr 18 02:49:01 PM PDT 24
Finished Apr 18 02:53:30 PM PDT 24
Peak memory 248300 kb
Host smart-6013574d-924e-4349-83ef-cd9439874a2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967631205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2967631205
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2719282725
Short name T413
Test name
Test status
Simulation time 641697445 ps
CPU time 31.16 seconds
Started Apr 18 02:48:56 PM PDT 24
Finished Apr 18 02:49:27 PM PDT 24
Peak memory 256220 kb
Host smart-3ed47e3d-b4da-43d3-b997-eae568c42973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27192
82725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2719282725
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4271091702
Short name T16
Test name
Test status
Simulation time 1518148348 ps
CPU time 31.2 seconds
Started Apr 18 02:48:56 PM PDT 24
Finished Apr 18 02:49:27 PM PDT 24
Peak memory 255604 kb
Host smart-a5333944-e0b4-41ac-9908-0f5f900bcbf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42710
91702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4271091702
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1619693643
Short name T95
Test name
Test status
Simulation time 4127491336 ps
CPU time 60.92 seconds
Started Apr 18 02:49:02 PM PDT 24
Finished Apr 18 02:50:03 PM PDT 24
Peak memory 256700 kb
Host smart-13ce8a68-f4f8-47b4-a0e1-e9d45851ca1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16196
93643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1619693643
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1443755076
Short name T481
Test name
Test status
Simulation time 411519246 ps
CPU time 30.21 seconds
Started Apr 18 02:48:50 PM PDT 24
Finished Apr 18 02:49:21 PM PDT 24
Peak memory 256296 kb
Host smart-c9c12252-760a-47ec-8185-8eedcff86d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14437
55076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1443755076
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3033433400
Short name T664
Test name
Test status
Simulation time 58405875709 ps
CPU time 1212.86 seconds
Started Apr 18 02:49:25 PM PDT 24
Finished Apr 18 03:09:38 PM PDT 24
Peak memory 288832 kb
Host smart-c5cbb195-17ba-4060-b8fe-39bfe6a81928
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033433400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3033433400
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2041794510
Short name T23
Test name
Test status
Simulation time 10784203248 ps
CPU time 323.96 seconds
Started Apr 18 02:49:16 PM PDT 24
Finished Apr 18 02:54:41 PM PDT 24
Peak memory 256872 kb
Host smart-be202b3b-f917-4838-a191-62fa3c95fd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20417
94510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2041794510
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2111457162
Short name T14
Test name
Test status
Simulation time 277023879 ps
CPU time 21.64 seconds
Started Apr 18 02:49:17 PM PDT 24
Finished Apr 18 02:49:40 PM PDT 24
Peak memory 249032 kb
Host smart-358546d4-7aa1-4443-ade2-9c65051816a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21114
57162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2111457162
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.888281555
Short name T44
Test name
Test status
Simulation time 75243708868 ps
CPU time 2162.74 seconds
Started Apr 18 02:49:26 PM PDT 24
Finished Apr 18 03:25:29 PM PDT 24
Peak memory 289708 kb
Host smart-32e3a707-1ed9-4a12-a6d9-0c71f3ef4468
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888281555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.888281555
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1333844521
Short name T38
Test name
Test status
Simulation time 11584274181 ps
CPU time 479.56 seconds
Started Apr 18 02:49:28 PM PDT 24
Finished Apr 18 02:57:28 PM PDT 24
Peak memory 248148 kb
Host smart-6f639b04-8a43-4a12-ade6-47ab88430909
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333844521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1333844521
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2901271961
Short name T500
Test name
Test status
Simulation time 6326871389 ps
CPU time 29.28 seconds
Started Apr 18 02:49:18 PM PDT 24
Finished Apr 18 02:49:48 PM PDT 24
Peak memory 249296 kb
Host smart-52569da5-79f8-451b-995e-d8aba605bcf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29012
71961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2901271961
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.111972145
Short name T696
Test name
Test status
Simulation time 17979667 ps
CPU time 2.6 seconds
Started Apr 18 02:49:14 PM PDT 24
Finished Apr 18 02:49:18 PM PDT 24
Peak memory 239240 kb
Host smart-52804780-5d88-454e-8500-c607dd037e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11197
2145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.111972145
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3487380706
Short name T277
Test name
Test status
Simulation time 766424789 ps
CPU time 43.51 seconds
Started Apr 18 02:49:19 PM PDT 24
Finished Apr 18 02:50:04 PM PDT 24
Peak memory 255368 kb
Host smart-103daba4-deda-4be3-b39a-59b8eb33530f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34873
80706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3487380706
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1138276408
Short name T235
Test name
Test status
Simulation time 373567060 ps
CPU time 32.88 seconds
Started Apr 18 02:49:18 PM PDT 24
Finished Apr 18 02:49:51 PM PDT 24
Peak memory 256356 kb
Host smart-b023b283-c062-4236-a21c-044c65ae8a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11382
76408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1138276408
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1920284049
Short name T547
Test name
Test status
Simulation time 61628716614 ps
CPU time 1819.1 seconds
Started Apr 18 02:49:26 PM PDT 24
Finished Apr 18 03:19:46 PM PDT 24
Peak memory 289916 kb
Host smart-6df1a9a3-2688-4427-a7ed-618c5f9fe2ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920284049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1920284049
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2257488655
Short name T218
Test name
Test status
Simulation time 133877718 ps
CPU time 2.32 seconds
Started Apr 18 02:49:39 PM PDT 24
Finished Apr 18 02:49:41 PM PDT 24
Peak memory 249328 kb
Host smart-3f52647f-ba5d-45bd-ae94-a036e4d7bf70
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2257488655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2257488655
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.258100163
Short name T546
Test name
Test status
Simulation time 101417346550 ps
CPU time 3055.57 seconds
Started Apr 18 02:49:31 PM PDT 24
Finished Apr 18 03:40:27 PM PDT 24
Peak memory 281952 kb
Host smart-3726b76d-9332-48e7-a299-9cd024b2e38b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258100163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.258100163
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3542974458
Short name T691
Test name
Test status
Simulation time 1052566267 ps
CPU time 14.83 seconds
Started Apr 18 02:49:39 PM PDT 24
Finished Apr 18 02:49:54 PM PDT 24
Peak memory 240780 kb
Host smart-e3235822-aa43-44ac-9470-b281c1e3e8ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3542974458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3542974458
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2917788768
Short name T428
Test name
Test status
Simulation time 3395168364 ps
CPU time 141.82 seconds
Started Apr 18 02:49:29 PM PDT 24
Finished Apr 18 02:51:51 PM PDT 24
Peak memory 251152 kb
Host smart-1d13087d-dc93-4845-b7a9-cfdab699fd67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29177
88768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2917788768
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2998655613
Short name T99
Test name
Test status
Simulation time 2709391508 ps
CPU time 41.87 seconds
Started Apr 18 02:49:30 PM PDT 24
Finished Apr 18 02:50:12 PM PDT 24
Peak memory 249144 kb
Host smart-23d530f2-0d0c-4159-a95c-7a68ea8a131d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29986
55613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2998655613
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1035931150
Short name T589
Test name
Test status
Simulation time 31273858563 ps
CPU time 1592.83 seconds
Started Apr 18 02:49:34 PM PDT 24
Finished Apr 18 03:16:07 PM PDT 24
Peak memory 267640 kb
Host smart-3d4005d6-255a-4b88-a888-6473d47d9fb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035931150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1035931150
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.184896455
Short name T487
Test name
Test status
Simulation time 152148115667 ps
CPU time 2115.64 seconds
Started Apr 18 02:49:34 PM PDT 24
Finished Apr 18 03:24:50 PM PDT 24
Peak memory 281224 kb
Host smart-e4e5d62d-7001-4478-90ff-db191bd632a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184896455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.184896455
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.4010402443
Short name T330
Test name
Test status
Simulation time 20684931074 ps
CPU time 205.99 seconds
Started Apr 18 02:49:36 PM PDT 24
Finished Apr 18 02:53:02 PM PDT 24
Peak memory 255944 kb
Host smart-29d79d5e-6965-4622-8376-36a9013f5732
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010402443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.4010402443
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3668407524
Short name T376
Test name
Test status
Simulation time 1749992512 ps
CPU time 38.79 seconds
Started Apr 18 02:49:29 PM PDT 24
Finished Apr 18 02:50:09 PM PDT 24
Peak memory 249072 kb
Host smart-5ec892b3-18d7-41cc-9bb9-a27942644a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36684
07524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3668407524
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1577709430
Short name T3
Test name
Test status
Simulation time 1138860082 ps
CPU time 64.59 seconds
Started Apr 18 02:49:30 PM PDT 24
Finished Apr 18 02:50:35 PM PDT 24
Peak memory 247596 kb
Host smart-e413f36b-c787-4bdd-84c1-251ad8cdf456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15777
09430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1577709430
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1185287892
Short name T291
Test name
Test status
Simulation time 613239784 ps
CPU time 39.87 seconds
Started Apr 18 02:49:30 PM PDT 24
Finished Apr 18 02:50:11 PM PDT 24
Peak memory 247948 kb
Host smart-7213676e-10af-4bba-a999-0383715cf9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11852
87892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1185287892
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2383631889
Short name T540
Test name
Test status
Simulation time 3877416258 ps
CPU time 46.4 seconds
Started Apr 18 02:49:26 PM PDT 24
Finished Apr 18 02:50:13 PM PDT 24
Peak memory 249376 kb
Host smart-5f81714c-767b-4815-b45c-3fee64775f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23836
31889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2383631889
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.981743711
Short name T512
Test name
Test status
Simulation time 14906383634 ps
CPU time 720.36 seconds
Started Apr 18 02:49:39 PM PDT 24
Finished Apr 18 03:01:40 PM PDT 24
Peak memory 272976 kb
Host smart-86cf2807-1d6f-4b71-bdac-9cf54c1c7ea8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981743711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.981743711
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2686317917
Short name T213
Test name
Test status
Simulation time 141607953 ps
CPU time 3.44 seconds
Started Apr 18 02:49:53 PM PDT 24
Finished Apr 18 02:49:57 PM PDT 24
Peak memory 249312 kb
Host smart-02732282-bad3-4874-b92f-dc8fbf208f1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2686317917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2686317917
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1735639107
Short name T379
Test name
Test status
Simulation time 136327920358 ps
CPU time 1910.65 seconds
Started Apr 18 02:49:50 PM PDT 24
Finished Apr 18 03:21:41 PM PDT 24
Peak memory 273724 kb
Host smart-6ea5d8c0-e6f6-4172-b9fd-617b3ed67bb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735639107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1735639107
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1499809150
Short name T68
Test name
Test status
Simulation time 1289987484 ps
CPU time 28.94 seconds
Started Apr 18 02:49:55 PM PDT 24
Finished Apr 18 02:50:24 PM PDT 24
Peak memory 249004 kb
Host smart-374ad89b-7168-42f6-8c44-f60d2222d03c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1499809150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1499809150
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1808842586
Short name T663
Test name
Test status
Simulation time 2005378114 ps
CPU time 91.26 seconds
Started Apr 18 02:49:51 PM PDT 24
Finished Apr 18 02:51:22 PM PDT 24
Peak memory 256852 kb
Host smart-b52a18ec-4fcd-4bb2-9030-53c8ba750388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18088
42586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1808842586
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.4156885690
Short name T693
Test name
Test status
Simulation time 746570688 ps
CPU time 18.28 seconds
Started Apr 18 02:49:44 PM PDT 24
Finished Apr 18 02:50:03 PM PDT 24
Peak memory 249072 kb
Host smart-3a797112-ce2b-4f09-9f39-e9e6a0e23050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41568
85690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.4156885690
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1315285904
Short name T576
Test name
Test status
Simulation time 12758206626 ps
CPU time 591.8 seconds
Started Apr 18 02:49:50 PM PDT 24
Finished Apr 18 02:59:42 PM PDT 24
Peak memory 265512 kb
Host smart-656c5f58-a211-4206-b64f-badc9812c855
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315285904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1315285904
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2870747351
Short name T522
Test name
Test status
Simulation time 189751032432 ps
CPU time 1193.02 seconds
Started Apr 18 02:49:52 PM PDT 24
Finished Apr 18 03:09:45 PM PDT 24
Peak memory 273348 kb
Host smart-845cea48-b26c-4feb-b34a-26f06f75d0fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870747351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2870747351
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1749984869
Short name T237
Test name
Test status
Simulation time 5307208935 ps
CPU time 93.14 seconds
Started Apr 18 02:49:50 PM PDT 24
Finished Apr 18 02:51:23 PM PDT 24
Peak memory 248548 kb
Host smart-3694fd9e-081f-429e-8f0c-ed08eba2cf98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749984869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1749984869
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.4236349000
Short name T652
Test name
Test status
Simulation time 8436998603 ps
CPU time 45.47 seconds
Started Apr 18 02:49:43 PM PDT 24
Finished Apr 18 02:50:29 PM PDT 24
Peak memory 256308 kb
Host smart-0907aabd-4c50-4ac8-afaa-4d3a2f4cd379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42363
49000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.4236349000
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.19237858
Short name T671
Test name
Test status
Simulation time 292623176 ps
CPU time 28.49 seconds
Started Apr 18 02:49:43 PM PDT 24
Finished Apr 18 02:50:12 PM PDT 24
Peak memory 255032 kb
Host smart-ff884fe3-7d77-4225-9076-38448b6dce0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19237
858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.19237858
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3998074309
Short name T197
Test name
Test status
Simulation time 95548063 ps
CPU time 6.25 seconds
Started Apr 18 02:49:50 PM PDT 24
Finished Apr 18 02:49:56 PM PDT 24
Peak memory 251196 kb
Host smart-99d38129-3cad-4f0a-9573-e97405b1b297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39980
74309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3998074309
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3957853642
Short name T555
Test name
Test status
Simulation time 2808440111 ps
CPU time 40.01 seconds
Started Apr 18 02:49:45 PM PDT 24
Finished Apr 18 02:50:25 PM PDT 24
Peak memory 256400 kb
Host smart-89b925bf-0b3c-4c00-82ee-09783d855c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39578
53642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3957853642
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2229185490
Short name T223
Test name
Test status
Simulation time 41428300 ps
CPU time 4 seconds
Started Apr 18 02:50:19 PM PDT 24
Finished Apr 18 02:50:23 PM PDT 24
Peak memory 249320 kb
Host smart-2710901f-7194-4bc7-bf42-5a3e1e8059c7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2229185490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2229185490
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.841765709
Short name T577
Test name
Test status
Simulation time 85321756770 ps
CPU time 1437.88 seconds
Started Apr 18 02:50:09 PM PDT 24
Finished Apr 18 03:14:08 PM PDT 24
Peak memory 268648 kb
Host smart-d099ee0f-80bf-41a1-b9df-f2ee70aa1fc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841765709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.841765709
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.145096625
Short name T405
Test name
Test status
Simulation time 353015429 ps
CPU time 6.2 seconds
Started Apr 18 02:50:13 PM PDT 24
Finished Apr 18 02:50:20 PM PDT 24
Peak memory 240832 kb
Host smart-2bfe42a0-c01a-4e5a-8fe2-843820cf3fa8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=145096625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.145096625
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.678181306
Short name T391
Test name
Test status
Simulation time 1433787718 ps
CPU time 32.75 seconds
Started Apr 18 02:50:03 PM PDT 24
Finished Apr 18 02:50:36 PM PDT 24
Peak memory 248976 kb
Host smart-77eed88b-3f86-400d-8c97-8b8675f36899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67818
1306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.678181306
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.4233210173
Short name T90
Test name
Test status
Simulation time 6271704636 ps
CPU time 27.08 seconds
Started Apr 18 02:50:03 PM PDT 24
Finished Apr 18 02:50:31 PM PDT 24
Peak memory 255064 kb
Host smart-c82b0e9a-4747-4242-a1e3-ef6e1d5a53a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42332
10173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.4233210173
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3207898333
Short name T403
Test name
Test status
Simulation time 42507102969 ps
CPU time 2186.43 seconds
Started Apr 18 02:50:14 PM PDT 24
Finished Apr 18 03:26:41 PM PDT 24
Peak memory 289108 kb
Host smart-fe0b3b12-80c6-453d-b758-6da634be6295
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207898333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3207898333
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3207961747
Short name T323
Test name
Test status
Simulation time 3094439113 ps
CPU time 121.47 seconds
Started Apr 18 02:50:09 PM PDT 24
Finished Apr 18 02:52:11 PM PDT 24
Peak memory 248232 kb
Host smart-86158448-ba4d-4eac-af02-c5d6a2b74408
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207961747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3207961747
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2193494284
Short name T489
Test name
Test status
Simulation time 526890150 ps
CPU time 11.17 seconds
Started Apr 18 02:49:59 PM PDT 24
Finished Apr 18 02:50:10 PM PDT 24
Peak memory 248992 kb
Host smart-f13bb5d9-97b4-4e42-9ef7-3570814761db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21934
94284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2193494284
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3132890353
Short name T81
Test name
Test status
Simulation time 1406026900 ps
CPU time 46.94 seconds
Started Apr 18 02:50:04 PM PDT 24
Finished Apr 18 02:50:51 PM PDT 24
Peak memory 256308 kb
Host smart-74d80220-6a32-4e1c-b039-8fa19d0f37b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31328
90353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3132890353
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.109530504
Short name T400
Test name
Test status
Simulation time 239879614 ps
CPU time 7.93 seconds
Started Apr 18 02:50:01 PM PDT 24
Finished Apr 18 02:50:09 PM PDT 24
Peak memory 240864 kb
Host smart-28f84dfd-8fa7-4395-a256-9ed797d5b743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10953
0504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.109530504
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1951792579
Short name T622
Test name
Test status
Simulation time 1833223843 ps
CPU time 149.03 seconds
Started Apr 18 02:50:15 PM PDT 24
Finished Apr 18 02:52:44 PM PDT 24
Peak memory 256920 kb
Host smart-1b54563c-3b23-4f6e-b815-3a40007d5537
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951792579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1951792579
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.2106282312
Short name T106
Test name
Test status
Simulation time 191716181558 ps
CPU time 4948.18 seconds
Started Apr 18 02:50:19 PM PDT 24
Finished Apr 18 04:12:48 PM PDT 24
Peak memory 355248 kb
Host smart-485e9f69-c545-4e85-b353-2bcfe7e9de58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106282312 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.2106282312
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2809000528
Short name T214
Test name
Test status
Simulation time 49458984 ps
CPU time 4.19 seconds
Started Apr 18 02:50:41 PM PDT 24
Finished Apr 18 02:50:46 PM PDT 24
Peak memory 249272 kb
Host smart-fe8c7714-e2c9-4879-9a84-be91fd629b0c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2809000528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2809000528
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.4015573137
Short name T52
Test name
Test status
Simulation time 13266504716 ps
CPU time 983.36 seconds
Started Apr 18 02:50:30 PM PDT 24
Finished Apr 18 03:06:54 PM PDT 24
Peak memory 288808 kb
Host smart-c1aea5c6-fc28-44d9-b048-38bce4c4b1e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015573137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.4015573137
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2403206155
Short name T367
Test name
Test status
Simulation time 6426505477 ps
CPU time 43.31 seconds
Started Apr 18 02:50:40 PM PDT 24
Finished Apr 18 02:51:24 PM PDT 24
Peak memory 240972 kb
Host smart-722eeea2-8cc9-4e73-98de-1730174f86c7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2403206155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2403206155
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1144904697
Short name T566
Test name
Test status
Simulation time 2380485097 ps
CPU time 46.75 seconds
Started Apr 18 02:50:30 PM PDT 24
Finished Apr 18 02:51:17 PM PDT 24
Peak memory 257104 kb
Host smart-14a5d647-897d-486d-ad21-c894e9b577b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11449
04697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1144904697
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.577546162
Short name T435
Test name
Test status
Simulation time 772044242 ps
CPU time 23.53 seconds
Started Apr 18 02:50:30 PM PDT 24
Finished Apr 18 02:50:54 PM PDT 24
Peak memory 255700 kb
Host smart-23de15f6-fba5-46a2-96d6-9690d6e2d462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57754
6162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.577546162
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1539007446
Short name T311
Test name
Test status
Simulation time 8026535583 ps
CPU time 705.15 seconds
Started Apr 18 02:50:33 PM PDT 24
Finished Apr 18 03:02:19 PM PDT 24
Peak memory 266580 kb
Host smart-bffedff7-f91b-47ab-82ae-1bb94099cd34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539007446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1539007446
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.4036557518
Short name T79
Test name
Test status
Simulation time 167898277112 ps
CPU time 2033.83 seconds
Started Apr 18 02:50:33 PM PDT 24
Finished Apr 18 03:24:27 PM PDT 24
Peak memory 271264 kb
Host smart-de1f20c7-dbce-41de-b8f4-feb7fa9a9042
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036557518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.4036557518
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1291395028
Short name T318
Test name
Test status
Simulation time 9477338819 ps
CPU time 379.31 seconds
Started Apr 18 02:50:27 PM PDT 24
Finished Apr 18 02:56:47 PM PDT 24
Peak memory 247304 kb
Host smart-20f037ea-2b5b-49e2-b29f-e6586246d82a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291395028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1291395028
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1301928467
Short name T454
Test name
Test status
Simulation time 17279322 ps
CPU time 3.36 seconds
Started Apr 18 02:50:28 PM PDT 24
Finished Apr 18 02:50:31 PM PDT 24
Peak memory 240824 kb
Host smart-05877246-77bf-4eb5-8ac3-c8d145882c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13019
28467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1301928467
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.968571812
Short name T45
Test name
Test status
Simulation time 214265186 ps
CPU time 12.57 seconds
Started Apr 18 02:50:28 PM PDT 24
Finished Apr 18 02:50:41 PM PDT 24
Peak memory 249052 kb
Host smart-aa70f479-169d-4c8c-bf10-8dde3b9cf8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96857
1812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.968571812
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1113355145
Short name T113
Test name
Test status
Simulation time 3972562273 ps
CPU time 56.46 seconds
Started Apr 18 02:50:29 PM PDT 24
Finished Apr 18 02:51:26 PM PDT 24
Peak memory 255728 kb
Host smart-dcffb9ef-4654-4070-b20b-660e5315f047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11133
55145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1113355145
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.4147122267
Short name T455
Test name
Test status
Simulation time 243135427 ps
CPU time 14.11 seconds
Started Apr 18 02:50:23 PM PDT 24
Finished Apr 18 02:50:37 PM PDT 24
Peak memory 248896 kb
Host smart-c5024398-4227-4fe1-a74d-86a59829b111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41471
22267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.4147122267
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3405048840
Short name T564
Test name
Test status
Simulation time 8283902448 ps
CPU time 172.3 seconds
Started Apr 18 02:50:40 PM PDT 24
Finished Apr 18 02:53:33 PM PDT 24
Peak memory 257344 kb
Host smart-5a59eaaa-99b3-49c0-ae2b-0c37115e6b15
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405048840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3405048840
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2800773260
Short name T210
Test name
Test status
Simulation time 38946905 ps
CPU time 3.03 seconds
Started Apr 18 02:50:52 PM PDT 24
Finished Apr 18 02:50:55 PM PDT 24
Peak memory 249288 kb
Host smart-9b659826-b9e6-4fb5-894a-2d886f07cac0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2800773260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2800773260
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1111483442
Short name T519
Test name
Test status
Simulation time 103114574765 ps
CPU time 1172.34 seconds
Started Apr 18 02:50:42 PM PDT 24
Finished Apr 18 03:10:15 PM PDT 24
Peak memory 273628 kb
Host smart-def83e98-da78-4653-8520-9c8324dbd77d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111483442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1111483442
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3921547240
Short name T518
Test name
Test status
Simulation time 132806956 ps
CPU time 8.08 seconds
Started Apr 18 02:50:47 PM PDT 24
Finished Apr 18 02:50:56 PM PDT 24
Peak memory 240772 kb
Host smart-6b6352f0-8caa-4fdf-93c0-8af080e01b6f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3921547240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3921547240
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3608264791
Short name T513
Test name
Test status
Simulation time 9034410525 ps
CPU time 268.04 seconds
Started Apr 18 02:50:43 PM PDT 24
Finished Apr 18 02:55:11 PM PDT 24
Peak memory 250184 kb
Host smart-7654dc6b-d2e2-476e-a585-266586d6545a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36082
64791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3608264791
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2869325781
Short name T525
Test name
Test status
Simulation time 436460078 ps
CPU time 14.87 seconds
Started Apr 18 02:50:42 PM PDT 24
Finished Apr 18 02:50:57 PM PDT 24
Peak memory 252100 kb
Host smart-7d8ae40d-58c7-459a-a657-a54384895645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28693
25781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2869325781
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3859333665
Short name T293
Test name
Test status
Simulation time 168566520052 ps
CPU time 2315.22 seconds
Started Apr 18 02:50:49 PM PDT 24
Finished Apr 18 03:29:24 PM PDT 24
Peak memory 288540 kb
Host smart-36acd060-5b98-496b-93d6-61c707c67726
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859333665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3859333665
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3713087890
Short name T503
Test name
Test status
Simulation time 29514026337 ps
CPU time 1744.97 seconds
Started Apr 18 02:50:49 PM PDT 24
Finished Apr 18 03:19:54 PM PDT 24
Peak memory 281924 kb
Host smart-82842fe8-bfc7-4e38-8e6b-5488cd211912
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713087890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3713087890
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3985383589
Short name T316
Test name
Test status
Simulation time 50985464022 ps
CPU time 515.96 seconds
Started Apr 18 02:50:42 PM PDT 24
Finished Apr 18 02:59:19 PM PDT 24
Peak memory 247412 kb
Host smart-41db2a33-d36b-4a59-9775-01fe6c61a5ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985383589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3985383589
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3611762320
Short name T492
Test name
Test status
Simulation time 886465470 ps
CPU time 23.82 seconds
Started Apr 18 02:50:44 PM PDT 24
Finished Apr 18 02:51:08 PM PDT 24
Peak memory 249036 kb
Host smart-d00398da-3a30-453e-9374-f3e4e72f8dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36117
62320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3611762320
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3137178913
Short name T308
Test name
Test status
Simulation time 262149862 ps
CPU time 23.72 seconds
Started Apr 18 02:50:43 PM PDT 24
Finished Apr 18 02:51:06 PM PDT 24
Peak memory 248636 kb
Host smart-c3a2fe66-6ff9-493c-a90d-3082198b3d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31371
78913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3137178913
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2096393535
Short name T267
Test name
Test status
Simulation time 2150723533 ps
CPU time 33.58 seconds
Started Apr 18 02:50:45 PM PDT 24
Finished Apr 18 02:51:19 PM PDT 24
Peak memory 255892 kb
Host smart-181cd985-a45c-4b89-8583-a2a3fa281695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20963
93535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2096393535
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2697385440
Short name T243
Test name
Test status
Simulation time 2461993535 ps
CPU time 36.44 seconds
Started Apr 18 02:50:40 PM PDT 24
Finished Apr 18 02:51:17 PM PDT 24
Peak memory 256284 kb
Host smart-d7f5a265-7212-4d85-ae0d-38ebec77f37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26973
85440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2697385440
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.533488106
Short name T117
Test name
Test status
Simulation time 478102319276 ps
CPU time 2685.71 seconds
Started Apr 18 02:50:48 PM PDT 24
Finished Apr 18 03:35:34 PM PDT 24
Peak memory 303440 kb
Host smart-3234ace3-f211-461c-81c5-bf2d623f8244
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533488106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.533488106
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.621733164
Short name T225
Test name
Test status
Simulation time 12895109 ps
CPU time 2.28 seconds
Started Apr 18 02:51:10 PM PDT 24
Finished Apr 18 02:51:12 PM PDT 24
Peak memory 249316 kb
Host smart-0943e756-47b4-4b68-b090-50031ccd4097
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=621733164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.621733164
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1282894402
Short name T494
Test name
Test status
Simulation time 26134292664 ps
CPU time 1536.49 seconds
Started Apr 18 02:51:04 PM PDT 24
Finished Apr 18 03:16:41 PM PDT 24
Peak memory 270764 kb
Host smart-280d6765-63ff-4df1-bb16-bf19c0f2b2e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282894402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1282894402
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3249422428
Short name T659
Test name
Test status
Simulation time 211683183 ps
CPU time 12.25 seconds
Started Apr 18 02:51:05 PM PDT 24
Finished Apr 18 02:51:18 PM PDT 24
Peak memory 240836 kb
Host smart-f903beea-b1b3-4a81-8558-fcc5c6ca5578
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3249422428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3249422428
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.402212612
Short name T674
Test name
Test status
Simulation time 8323717098 ps
CPU time 239.14 seconds
Started Apr 18 02:51:00 PM PDT 24
Finished Apr 18 02:54:59 PM PDT 24
Peak memory 257268 kb
Host smart-73b08b59-e382-460a-b4f0-8adf9ec89155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40221
2612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.402212612
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2516317147
Short name T602
Test name
Test status
Simulation time 6080166148 ps
CPU time 29.56 seconds
Started Apr 18 02:50:59 PM PDT 24
Finished Apr 18 02:51:28 PM PDT 24
Peak memory 256196 kb
Host smart-1f0ec0ce-5cff-419e-92e9-b2c18dacc2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25163
17147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2516317147
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2807564089
Short name T473
Test name
Test status
Simulation time 54564582035 ps
CPU time 1193.29 seconds
Started Apr 18 02:51:06 PM PDT 24
Finished Apr 18 03:10:59 PM PDT 24
Peak memory 289896 kb
Host smart-8b52ed39-9aba-492e-94a0-44afe40d50d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807564089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2807564089
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1450002537
Short name T469
Test name
Test status
Simulation time 6955390926 ps
CPU time 309.04 seconds
Started Apr 18 02:51:04 PM PDT 24
Finished Apr 18 02:56:13 PM PDT 24
Peak memory 256048 kb
Host smart-20e534c2-c8a3-4c65-8abf-f9ddd9c680e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450002537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1450002537
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.367732701
Short name T446
Test name
Test status
Simulation time 148982371 ps
CPU time 14.23 seconds
Started Apr 18 02:50:59 PM PDT 24
Finished Apr 18 02:51:14 PM PDT 24
Peak memory 249012 kb
Host smart-dede48ef-bfbf-4811-9b0c-3dee867bf3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36773
2701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.367732701
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3952945211
Short name T59
Test name
Test status
Simulation time 1339409804 ps
CPU time 36.7 seconds
Started Apr 18 02:50:58 PM PDT 24
Finished Apr 18 02:51:35 PM PDT 24
Peak memory 249084 kb
Host smart-86e7567b-e58b-4da4-be6f-79fc85fc4d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39529
45211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3952945211
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1895745433
Short name T193
Test name
Test status
Simulation time 799979361 ps
CPU time 26.76 seconds
Started Apr 18 02:50:59 PM PDT 24
Finished Apr 18 02:51:26 PM PDT 24
Peak memory 256104 kb
Host smart-1c04477c-6b7d-440c-aab2-215641adde79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18957
45433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1895745433
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.86079482
Short name T527
Test name
Test status
Simulation time 378104969 ps
CPU time 11.6 seconds
Started Apr 18 02:50:53 PM PDT 24
Finished Apr 18 02:51:05 PM PDT 24
Peak memory 254228 kb
Host smart-7ea93cbd-ea5f-4e7c-a9e5-f4ccdc3178f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86079
482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.86079482
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.841726674
Short name T553
Test name
Test status
Simulation time 86382131901 ps
CPU time 1149.35 seconds
Started Apr 18 02:51:08 PM PDT 24
Finished Apr 18 03:10:18 PM PDT 24
Peak memory 273716 kb
Host smart-4b141d44-8864-40f0-bab5-7fafdecc6ee6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841726674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.841726674
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2938996483
Short name T18
Test name
Test status
Simulation time 65132867935 ps
CPU time 3089.38 seconds
Started Apr 18 02:51:09 PM PDT 24
Finished Apr 18 03:42:39 PM PDT 24
Peak memory 297768 kb
Host smart-73ebf005-0f28-41fe-a9df-98830e2abf56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938996483 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2938996483
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4134874614
Short name T211
Test name
Test status
Simulation time 17057888 ps
CPU time 2.43 seconds
Started Apr 18 02:51:33 PM PDT 24
Finished Apr 18 02:51:36 PM PDT 24
Peak memory 249344 kb
Host smart-97fb3b07-8ed3-4b40-9709-bc41c9879d1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4134874614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4134874614
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.260673435
Short name T404
Test name
Test status
Simulation time 445159025 ps
CPU time 6.78 seconds
Started Apr 18 02:51:28 PM PDT 24
Finished Apr 18 02:51:36 PM PDT 24
Peak memory 240856 kb
Host smart-550fa1e0-0707-47b8-a0ad-8adcf0d120f5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=260673435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.260673435
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3959869666
Short name T415
Test name
Test status
Simulation time 260920952 ps
CPU time 27.65 seconds
Started Apr 18 02:51:19 PM PDT 24
Finished Apr 18 02:51:47 PM PDT 24
Peak memory 256328 kb
Host smart-55245da0-ca3b-45ea-9333-ef0c71f3695a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39598
69666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3959869666
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.4071457649
Short name T7
Test name
Test status
Simulation time 132890897 ps
CPU time 9.47 seconds
Started Apr 18 02:51:13 PM PDT 24
Finished Apr 18 02:51:23 PM PDT 24
Peak memory 249120 kb
Host smart-e3d89e1e-5142-4a9b-a818-0af62126dbb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40714
57649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.4071457649
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2539880346
Short name T302
Test name
Test status
Simulation time 34288259626 ps
CPU time 705.17 seconds
Started Apr 18 02:51:29 PM PDT 24
Finished Apr 18 03:03:14 PM PDT 24
Peak memory 265548 kb
Host smart-3bc0b253-a296-4091-9f81-6d18295949a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539880346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2539880346
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.683877460
Short name T689
Test name
Test status
Simulation time 100711778337 ps
CPU time 2108.77 seconds
Started Apr 18 02:51:29 PM PDT 24
Finished Apr 18 03:26:39 PM PDT 24
Peak memory 289636 kb
Host smart-9570230c-89a3-480f-8e2d-0b4e1ed2c737
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683877460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.683877460
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1091489731
Short name T76
Test name
Test status
Simulation time 416256653 ps
CPU time 24.04 seconds
Started Apr 18 02:51:11 PM PDT 24
Finished Apr 18 02:51:36 PM PDT 24
Peak memory 254792 kb
Host smart-8a2db3c9-3755-4c64-a299-78f8ad15eaef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10914
89731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1091489731
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.4127834975
Short name T475
Test name
Test status
Simulation time 3367224742 ps
CPU time 49.1 seconds
Started Apr 18 02:51:11 PM PDT 24
Finished Apr 18 02:52:00 PM PDT 24
Peak memory 249512 kb
Host smart-381b814c-fb49-4e20-8ca9-99bcae5ab780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41278
34975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4127834975
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1281387943
Short name T259
Test name
Test status
Simulation time 1237939179 ps
CPU time 28.3 seconds
Started Apr 18 02:51:23 PM PDT 24
Finished Apr 18 02:51:52 PM PDT 24
Peak memory 247996 kb
Host smart-3194b379-9809-4913-9083-24422dd1aa85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12813
87943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1281387943
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2701073694
Short name T676
Test name
Test status
Simulation time 60913397 ps
CPU time 6.41 seconds
Started Apr 18 02:51:09 PM PDT 24
Finished Apr 18 02:51:16 PM PDT 24
Peak memory 249096 kb
Host smart-f47ec6d0-6715-4401-afff-d40183482fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27010
73694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2701073694
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.4043070119
Short name T621
Test name
Test status
Simulation time 283951194276 ps
CPU time 1679.89 seconds
Started Apr 18 02:51:28 PM PDT 24
Finished Apr 18 03:19:29 PM PDT 24
Peak memory 281940 kb
Host smart-507210be-0759-45d5-9305-99507c40d549
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043070119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.4043070119
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1484232777
Short name T217
Test name
Test status
Simulation time 22341141 ps
CPU time 2.36 seconds
Started Apr 18 02:51:53 PM PDT 24
Finished Apr 18 02:51:57 PM PDT 24
Peak memory 249236 kb
Host smart-066eae53-dc69-448c-b507-03e23c197927
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1484232777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1484232777
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2288928636
Short name T438
Test name
Test status
Simulation time 24762817699 ps
CPU time 1552.66 seconds
Started Apr 18 02:51:49 PM PDT 24
Finished Apr 18 03:17:42 PM PDT 24
Peak memory 269852 kb
Host smart-c38fa514-4ce5-4c2c-8190-5e53e99d7f5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288928636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2288928636
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.529730218
Short name T229
Test name
Test status
Simulation time 198693337 ps
CPU time 7.04 seconds
Started Apr 18 02:51:50 PM PDT 24
Finished Apr 18 02:51:58 PM PDT 24
Peak memory 240848 kb
Host smart-17317db1-dd32-40a5-a41c-fe75eda7809f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=529730218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.529730218
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.47236840
Short name T230
Test name
Test status
Simulation time 8485830612 ps
CPU time 118.61 seconds
Started Apr 18 02:51:43 PM PDT 24
Finished Apr 18 02:53:43 PM PDT 24
Peak memory 257092 kb
Host smart-4e0ef90e-571c-4315-8ea9-c9a009abcc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47236
840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.47236840
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.324706736
Short name T680
Test name
Test status
Simulation time 502924205 ps
CPU time 30.21 seconds
Started Apr 18 02:51:43 PM PDT 24
Finished Apr 18 02:52:13 PM PDT 24
Peak memory 255036 kb
Host smart-819f7a40-5bdb-4bba-aca0-acecd8f1e1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32470
6736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.324706736
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.422452590
Short name T459
Test name
Test status
Simulation time 12075534553 ps
CPU time 1013.55 seconds
Started Apr 18 02:51:50 PM PDT 24
Finished Apr 18 03:08:44 PM PDT 24
Peak memory 273736 kb
Host smart-5e1b5038-d044-44bf-b47e-ddcae4b061d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422452590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.422452590
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3831019779
Short name T304
Test name
Test status
Simulation time 169360858900 ps
CPU time 2225.26 seconds
Started Apr 18 02:51:47 PM PDT 24
Finished Apr 18 03:28:53 PM PDT 24
Peak memory 289180 kb
Host smart-91dcc891-e3e1-4974-a65a-f734ece8d04e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831019779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3831019779
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3247485948
Short name T78
Test name
Test status
Simulation time 19464169767 ps
CPU time 60.14 seconds
Started Apr 18 02:51:38 PM PDT 24
Finished Apr 18 02:52:38 PM PDT 24
Peak memory 255992 kb
Host smart-0aaf58a2-075f-41d2-a7ad-0604bc552c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32474
85948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3247485948
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1127283783
Short name T30
Test name
Test status
Simulation time 1131084060 ps
CPU time 62.46 seconds
Started Apr 18 02:51:44 PM PDT 24
Finished Apr 18 02:52:47 PM PDT 24
Peak memory 256144 kb
Host smart-8b737610-4859-425a-8fcc-decdee5686c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11272
83783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1127283783
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.4193376042
Short name T274
Test name
Test status
Simulation time 1488562148 ps
CPU time 42.31 seconds
Started Apr 18 02:51:44 PM PDT 24
Finished Apr 18 02:52:27 PM PDT 24
Peak memory 255772 kb
Host smart-50c0a370-d355-4c07-892a-dcfbd478748c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41933
76042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.4193376042
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2128368917
Short name T490
Test name
Test status
Simulation time 466401498 ps
CPU time 17.77 seconds
Started Apr 18 02:51:33 PM PDT 24
Finished Apr 18 02:51:51 PM PDT 24
Peak memory 248976 kb
Host smart-8cf0f882-792d-4390-a098-3d09b4a9822e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21283
68917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2128368917
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2824007952
Short name T276
Test name
Test status
Simulation time 120632799867 ps
CPU time 1911.39 seconds
Started Apr 18 02:51:55 PM PDT 24
Finished Apr 18 03:23:48 PM PDT 24
Peak memory 285768 kb
Host smart-4eebbf35-c9c7-4b75-bad0-3dc445ddb313
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824007952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2824007952
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.103754788
Short name T222
Test name
Test status
Simulation time 52609935 ps
CPU time 2.58 seconds
Started Apr 18 02:46:56 PM PDT 24
Finished Apr 18 02:46:59 PM PDT 24
Peak memory 249296 kb
Host smart-4da84cd6-ac3a-4d9e-880f-c42c099d0933
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=103754788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.103754788
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2911004951
Short name T465
Test name
Test status
Simulation time 15584720921 ps
CPU time 1189.64 seconds
Started Apr 18 02:46:52 PM PDT 24
Finished Apr 18 03:06:42 PM PDT 24
Peak memory 289824 kb
Host smart-8c4725c7-10a0-4c6b-93d1-93f083de3c0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911004951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2911004951
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1269717480
Short name T381
Test name
Test status
Simulation time 1337451807 ps
CPU time 55.11 seconds
Started Apr 18 02:46:49 PM PDT 24
Finished Apr 18 02:47:45 PM PDT 24
Peak memory 250732 kb
Host smart-e752b68c-81ea-4ad2-80b8-47c8f6c0b1d2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1269717480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1269717480
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1583341528
Short name T240
Test name
Test status
Simulation time 11031363147 ps
CPU time 59.68 seconds
Started Apr 18 02:46:43 PM PDT 24
Finished Apr 18 02:47:43 PM PDT 24
Peak memory 249188 kb
Host smart-5c7afc09-6f9d-4edc-bbe7-7ea6a58454f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15833
41528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1583341528
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.4060332662
Short name T595
Test name
Test status
Simulation time 953951728 ps
CPU time 33.79 seconds
Started Apr 18 02:46:45 PM PDT 24
Finished Apr 18 02:47:19 PM PDT 24
Peak memory 255740 kb
Host smart-b9500c55-8c88-41c1-a2c0-2903dac813c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40603
32662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.4060332662
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2519834984
Short name T483
Test name
Test status
Simulation time 7408432108 ps
CPU time 665.19 seconds
Started Apr 18 02:46:50 PM PDT 24
Finished Apr 18 02:57:56 PM PDT 24
Peak memory 267588 kb
Host smart-bdece7ae-99cb-44d2-a025-d0a62042e59f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519834984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2519834984
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.387070928
Short name T460
Test name
Test status
Simulation time 61418046934 ps
CPU time 1893.91 seconds
Started Apr 18 02:46:50 PM PDT 24
Finished Apr 18 03:18:24 PM PDT 24
Peak memory 281888 kb
Host smart-d6b198a5-d665-4b53-a8c6-72a9cbb33f26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387070928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.387070928
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.245235292
Short name T329
Test name
Test status
Simulation time 18605094590 ps
CPU time 419.51 seconds
Started Apr 18 02:46:51 PM PDT 24
Finished Apr 18 02:53:51 PM PDT 24
Peak memory 256460 kb
Host smart-1a91bba3-fbca-460d-af31-3b313cab0bbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245235292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.245235292
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2310450442
Short name T532
Test name
Test status
Simulation time 586142798 ps
CPU time 18.08 seconds
Started Apr 18 02:46:40 PM PDT 24
Finished Apr 18 02:46:58 PM PDT 24
Peak memory 255912 kb
Host smart-a1e2dcda-4bf3-4fc0-b31c-e74738a09398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23104
50442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2310450442
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3432519039
Short name T58
Test name
Test status
Simulation time 4269466515 ps
CPU time 32.3 seconds
Started Apr 18 02:46:40 PM PDT 24
Finished Apr 18 02:47:13 PM PDT 24
Peak memory 256380 kb
Host smart-35d213c3-c1eb-4f85-8260-e7998723e666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34325
19039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3432519039
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.219745755
Short name T33
Test name
Test status
Simulation time 703814880 ps
CPU time 21.89 seconds
Started Apr 18 02:46:54 PM PDT 24
Finished Apr 18 02:47:16 PM PDT 24
Peak memory 270644 kb
Host smart-7a05fc14-a30b-4b2c-b4b1-fea8f0ffa5fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=219745755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.219745755
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2555715050
Short name T685
Test name
Test status
Simulation time 578827029 ps
CPU time 32.62 seconds
Started Apr 18 02:46:45 PM PDT 24
Finished Apr 18 02:47:17 PM PDT 24
Peak memory 255016 kb
Host smart-d85b881f-b984-48b4-b730-8ae9421596cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25557
15050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2555715050
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3096309043
Short name T642
Test name
Test status
Simulation time 2272383302 ps
CPU time 35.6 seconds
Started Apr 18 02:46:39 PM PDT 24
Finished Apr 18 02:47:15 PM PDT 24
Peak memory 249184 kb
Host smart-b5ef1ec5-bdb9-49ea-a545-768eca016081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30963
09043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3096309043
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3934618540
Short name T64
Test name
Test status
Simulation time 7472736687 ps
CPU time 149.24 seconds
Started Apr 18 02:46:49 PM PDT 24
Finished Apr 18 02:49:19 PM PDT 24
Peak memory 257348 kb
Host smart-332de166-c4e1-4e79-ba95-fdb6c68f1644
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934618540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3934618540
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1812055046
Short name T660
Test name
Test status
Simulation time 23417062905 ps
CPU time 771.19 seconds
Started Apr 18 02:52:02 PM PDT 24
Finished Apr 18 03:04:54 PM PDT 24
Peak memory 273564 kb
Host smart-b82b5359-a30b-4d72-89ba-3a58132795b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812055046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1812055046
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2938916675
Short name T514
Test name
Test status
Simulation time 1488429014 ps
CPU time 137.06 seconds
Started Apr 18 02:52:00 PM PDT 24
Finished Apr 18 02:54:19 PM PDT 24
Peak memory 256856 kb
Host smart-ca032770-4e77-45d4-948f-acac019a0466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29389
16675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2938916675
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1169469048
Short name T551
Test name
Test status
Simulation time 5458147269 ps
CPU time 63.13 seconds
Started Apr 18 02:51:59 PM PDT 24
Finished Apr 18 02:53:04 PM PDT 24
Peak memory 255904 kb
Host smart-56d62a98-c0e8-47bf-9b9d-c7e6688f0369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11694
69048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1169469048
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2877969979
Short name T346
Test name
Test status
Simulation time 460567350550 ps
CPU time 2240.76 seconds
Started Apr 18 02:52:01 PM PDT 24
Finished Apr 18 03:29:23 PM PDT 24
Peak memory 284828 kb
Host smart-7823b06c-5057-4ce8-b64d-12493df3e753
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877969979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2877969979
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.19452845
Short name T303
Test name
Test status
Simulation time 101403301269 ps
CPU time 1620.15 seconds
Started Apr 18 02:52:04 PM PDT 24
Finished Apr 18 03:19:05 PM PDT 24
Peak memory 272872 kb
Host smart-9bbb7616-2379-45ec-ab4e-c1232c59f6d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19452845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.19452845
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1858711077
Short name T317
Test name
Test status
Simulation time 8878431239 ps
CPU time 381.7 seconds
Started Apr 18 02:51:59 PM PDT 24
Finished Apr 18 02:58:22 PM PDT 24
Peak memory 248384 kb
Host smart-ada26f55-2a1d-4c04-a17d-6f650b1d7df3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858711077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1858711077
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2551899285
Short name T567
Test name
Test status
Simulation time 2086023680 ps
CPU time 28.33 seconds
Started Apr 18 02:51:54 PM PDT 24
Finished Apr 18 02:52:23 PM PDT 24
Peak memory 256220 kb
Host smart-3998ee49-0d53-4422-b492-96f956f0b8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25518
99285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2551899285
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.657970216
Short name T398
Test name
Test status
Simulation time 206294449 ps
CPU time 18.79 seconds
Started Apr 18 02:52:00 PM PDT 24
Finished Apr 18 02:52:20 PM PDT 24
Peak memory 247652 kb
Host smart-cc786637-9f77-4568-b4a8-5db0db16155a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65797
0216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.657970216
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1382870385
Short name T266
Test name
Test status
Simulation time 210083856 ps
CPU time 22.94 seconds
Started Apr 18 02:52:00 PM PDT 24
Finished Apr 18 02:52:24 PM PDT 24
Peak memory 255028 kb
Host smart-1fecdc56-c784-4733-a2aa-d01fd0aa936c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13828
70385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1382870385
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.648746780
Short name T386
Test name
Test status
Simulation time 294308862 ps
CPU time 28.44 seconds
Started Apr 18 02:51:54 PM PDT 24
Finished Apr 18 02:52:24 PM PDT 24
Peak memory 256128 kb
Host smart-2f82540f-30bf-4577-9d9f-d863d6237a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64874
6780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.648746780
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2021433996
Short name T271
Test name
Test status
Simulation time 47442397905 ps
CPU time 1610.17 seconds
Started Apr 18 02:52:04 PM PDT 24
Finished Apr 18 03:18:55 PM PDT 24
Peak memory 298316 kb
Host smart-3e354fde-cfce-4171-a03f-202c311f9bf8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021433996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2021433996
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3134265586
Short name T568
Test name
Test status
Simulation time 32092307864 ps
CPU time 1885.86 seconds
Started Apr 18 02:52:24 PM PDT 24
Finished Apr 18 03:23:51 PM PDT 24
Peak memory 287676 kb
Host smart-8cd04d9b-17d2-47b4-bcec-241ba72c3e32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134265586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3134265586
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.825656275
Short name T511
Test name
Test status
Simulation time 485244446 ps
CPU time 13.41 seconds
Started Apr 18 02:52:19 PM PDT 24
Finished Apr 18 02:52:33 PM PDT 24
Peak memory 252332 kb
Host smart-f5551958-8157-4a11-8509-ce133196c69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82565
6275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.825656275
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.25930447
Short name T434
Test name
Test status
Simulation time 696589428 ps
CPU time 37.52 seconds
Started Apr 18 02:52:31 PM PDT 24
Finished Apr 18 02:53:09 PM PDT 24
Peak memory 255732 kb
Host smart-676aae0a-979e-4a89-8e30-811e032c88a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25930
447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.25930447
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1427895772
Short name T354
Test name
Test status
Simulation time 28002268049 ps
CPU time 1491.29 seconds
Started Apr 18 02:52:25 PM PDT 24
Finished Apr 18 03:17:17 PM PDT 24
Peak memory 273036 kb
Host smart-c746016d-fc91-46dc-9b1d-a0c61865490d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427895772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1427895772
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.213642073
Short name T46
Test name
Test status
Simulation time 43951681876 ps
CPU time 2782.5 seconds
Started Apr 18 02:52:30 PM PDT 24
Finished Apr 18 03:38:53 PM PDT 24
Peak memory 289532 kb
Host smart-a29b3d74-50dc-478b-a398-f7e18c02d110
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213642073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.213642073
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1232481674
Short name T477
Test name
Test status
Simulation time 19266355699 ps
CPU time 414.86 seconds
Started Apr 18 02:52:26 PM PDT 24
Finished Apr 18 02:59:21 PM PDT 24
Peak memory 248432 kb
Host smart-0004c022-9eac-4475-a97b-8594abc8c7f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232481674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1232481674
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.963264745
Short name T458
Test name
Test status
Simulation time 65712621 ps
CPU time 9.36 seconds
Started Apr 18 02:52:09 PM PDT 24
Finished Apr 18 02:52:19 PM PDT 24
Peak memory 248900 kb
Host smart-de2ae9cb-069d-4890-a9c5-7a7a5cdefa04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96326
4745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.963264745
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1160646914
Short name T292
Test name
Test status
Simulation time 254771790 ps
CPU time 18.11 seconds
Started Apr 18 02:52:09 PM PDT 24
Finished Apr 18 02:52:28 PM PDT 24
Peak memory 247596 kb
Host smart-0a299b18-d380-49b7-ba56-8115c78b1366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11606
46914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1160646914
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2294687120
Short name T591
Test name
Test status
Simulation time 198954860 ps
CPU time 15.76 seconds
Started Apr 18 02:52:19 PM PDT 24
Finished Apr 18 02:52:35 PM PDT 24
Peak memory 255088 kb
Host smart-5d9f1d5a-151d-448d-a056-758922322bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22946
87120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2294687120
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2428246239
Short name T499
Test name
Test status
Simulation time 12396086990 ps
CPU time 43.01 seconds
Started Apr 18 02:52:15 PM PDT 24
Finished Apr 18 02:52:59 PM PDT 24
Peak memory 256504 kb
Host smart-c35a4f97-5b84-49e3-b1eb-70f979e30ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24282
46239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2428246239
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1629161223
Short name T425
Test name
Test status
Simulation time 113675143149 ps
CPU time 2079.01 seconds
Started Apr 18 02:52:57 PM PDT 24
Finished Apr 18 03:27:36 PM PDT 24
Peak memory 283920 kb
Host smart-44338767-455b-4647-afc7-395868e689fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629161223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1629161223
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.598179887
Short name T491
Test name
Test status
Simulation time 10063148273 ps
CPU time 179.09 seconds
Started Apr 18 02:52:43 PM PDT 24
Finished Apr 18 02:55:43 PM PDT 24
Peak memory 256724 kb
Host smart-79155887-c03a-4cb8-862a-da6ca4ac33ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59817
9887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.598179887
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2882616930
Short name T437
Test name
Test status
Simulation time 85622801 ps
CPU time 9.36 seconds
Started Apr 18 02:52:41 PM PDT 24
Finished Apr 18 02:52:51 PM PDT 24
Peak memory 255592 kb
Host smart-b326d352-6d22-4758-b7c7-71f5727f97c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28826
16930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2882616930
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1840686916
Short name T653
Test name
Test status
Simulation time 23958970302 ps
CPU time 1536.1 seconds
Started Apr 18 02:52:54 PM PDT 24
Finished Apr 18 03:18:30 PM PDT 24
Peak memory 265600 kb
Host smart-5e9a7c4b-4655-49a0-8688-b4618d8e06d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840686916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1840686916
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2665652674
Short name T571
Test name
Test status
Simulation time 27018158866 ps
CPU time 549.4 seconds
Started Apr 18 02:52:54 PM PDT 24
Finished Apr 18 03:02:03 PM PDT 24
Peak memory 247456 kb
Host smart-f03eaffb-e048-4f11-99c6-657dff099387
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665652674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2665652674
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1614854080
Short name T389
Test name
Test status
Simulation time 2475022938 ps
CPU time 43.72 seconds
Started Apr 18 02:52:38 PM PDT 24
Finished Apr 18 02:53:22 PM PDT 24
Peak memory 249184 kb
Host smart-0eb89a98-5c98-47da-a036-db91c6a409ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16148
54080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1614854080
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.745195718
Short name T449
Test name
Test status
Simulation time 1878278635 ps
CPU time 28.15 seconds
Started Apr 18 02:52:33 PM PDT 24
Finished Apr 18 02:53:02 PM PDT 24
Peak memory 255764 kb
Host smart-38f8b31c-61c9-46c3-9d31-e2e51c829f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74519
5718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.745195718
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2597238350
Short name T385
Test name
Test status
Simulation time 243992872 ps
CPU time 6.7 seconds
Started Apr 18 02:52:48 PM PDT 24
Finished Apr 18 02:52:55 PM PDT 24
Peak memory 252084 kb
Host smart-e54d8398-0883-40de-a6d7-6258bf50e383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25972
38350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2597238350
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3439736592
Short name T10
Test name
Test status
Simulation time 2493918704 ps
CPU time 35.63 seconds
Started Apr 18 02:52:38 PM PDT 24
Finished Apr 18 02:53:14 PM PDT 24
Peak memory 256360 kb
Host smart-62e1b9c4-64f8-431f-99fa-e102372fa71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34397
36592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3439736592
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.329189197
Short name T129
Test name
Test status
Simulation time 702120657364 ps
CPU time 3300.13 seconds
Started Apr 18 02:52:54 PM PDT 24
Finished Apr 18 03:47:55 PM PDT 24
Peak memory 297992 kb
Host smart-f5285e33-1296-4d30-9949-3db871e7a878
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329189197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.329189197
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.358297313
Short name T131
Test name
Test status
Simulation time 62328179995 ps
CPU time 1921.54 seconds
Started Apr 18 02:53:05 PM PDT 24
Finished Apr 18 03:25:07 PM PDT 24
Peak memory 273672 kb
Host smart-4e26d012-c54c-4c8c-b132-e2a6155b0d27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358297313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.358297313
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.4153023757
Short name T700
Test name
Test status
Simulation time 11731638732 ps
CPU time 165.71 seconds
Started Apr 18 02:53:03 PM PDT 24
Finished Apr 18 02:55:49 PM PDT 24
Peak memory 257200 kb
Host smart-cf0463f7-849f-4280-bfe5-a764c4cf7418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41530
23757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.4153023757
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1023058392
Short name T516
Test name
Test status
Simulation time 378241044 ps
CPU time 40.99 seconds
Started Apr 18 02:52:59 PM PDT 24
Finished Apr 18 02:53:40 PM PDT 24
Peak memory 248680 kb
Host smart-0240cd9e-fa41-4b45-b762-14b424d566cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10230
58392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1023058392
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2898951194
Short name T614
Test name
Test status
Simulation time 69440610864 ps
CPU time 1146.56 seconds
Started Apr 18 02:53:13 PM PDT 24
Finished Apr 18 03:12:20 PM PDT 24
Peak memory 265556 kb
Host smart-d12e3537-50ff-4b41-8ed0-98aa6288d279
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898951194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2898951194
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2642057263
Short name T232
Test name
Test status
Simulation time 61946016825 ps
CPU time 1227.37 seconds
Started Apr 18 02:53:13 PM PDT 24
Finished Apr 18 03:13:41 PM PDT 24
Peak memory 286920 kb
Host smart-c3cdf633-51b4-41ec-894f-00500ea2cbda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642057263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2642057263
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3379835930
Short name T288
Test name
Test status
Simulation time 48473861499 ps
CPU time 311.43 seconds
Started Apr 18 02:53:12 PM PDT 24
Finished Apr 18 02:58:24 PM PDT 24
Peak memory 256428 kb
Host smart-b13c0a2e-91ca-421d-a1cc-f530ca18c992
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379835930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3379835930
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.78666748
Short name T371
Test name
Test status
Simulation time 1502392040 ps
CPU time 47.34 seconds
Started Apr 18 02:52:59 PM PDT 24
Finished Apr 18 02:53:47 PM PDT 24
Peak memory 249032 kb
Host smart-f5a5e90a-68fe-4758-9f86-88c0a16241ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78666
748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.78666748
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2852008483
Short name T521
Test name
Test status
Simulation time 267812511 ps
CPU time 9.29 seconds
Started Apr 18 02:52:58 PM PDT 24
Finished Apr 18 02:53:08 PM PDT 24
Peak memory 256024 kb
Host smart-8f247a38-32f8-4dae-9ef0-cc8d66234793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28520
08483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2852008483
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3076689337
Short name T583
Test name
Test status
Simulation time 148212714 ps
CPU time 14.79 seconds
Started Apr 18 02:53:03 PM PDT 24
Finished Apr 18 02:53:19 PM PDT 24
Peak memory 255804 kb
Host smart-4da9e597-12e3-4935-a676-7e9a3b6de480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30766
89337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3076689337
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3155948582
Short name T396
Test name
Test status
Simulation time 886518339 ps
CPU time 12.49 seconds
Started Apr 18 02:52:58 PM PDT 24
Finished Apr 18 02:53:11 PM PDT 24
Peak memory 249036 kb
Host smart-7f0bb13b-e1d6-4e46-9538-cc0d236c958f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31559
48582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3155948582
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2365500994
Short name T306
Test name
Test status
Simulation time 142594877686 ps
CPU time 2134.6 seconds
Started Apr 18 02:53:09 PM PDT 24
Finished Apr 18 03:28:44 PM PDT 24
Peak memory 286436 kb
Host smart-f39a185c-d681-4dd6-96ba-954a9c889dfd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365500994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2365500994
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.4102520490
Short name T112
Test name
Test status
Simulation time 17909538744 ps
CPU time 1675.79 seconds
Started Apr 18 02:53:10 PM PDT 24
Finished Apr 18 03:21:06 PM PDT 24
Peak memory 305764 kb
Host smart-7cc1a884-b7a2-4be8-8212-d02c48341072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102520490 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.4102520490
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.201081673
Short name T390
Test name
Test status
Simulation time 26005280179 ps
CPU time 1739.68 seconds
Started Apr 18 02:53:24 PM PDT 24
Finished Apr 18 03:22:24 PM PDT 24
Peak memory 289000 kb
Host smart-d71f80ff-7113-4c64-9877-27a79da3ffe1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201081673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.201081673
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1983995446
Short name T258
Test name
Test status
Simulation time 4855712756 ps
CPU time 80.49 seconds
Started Apr 18 02:53:23 PM PDT 24
Finished Apr 18 02:54:44 PM PDT 24
Peak memory 257344 kb
Host smart-cd7266a0-dd0e-4f1f-87c3-e8dca954933a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19839
95446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1983995446
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.4221358830
Short name T502
Test name
Test status
Simulation time 1597822764 ps
CPU time 39.3 seconds
Started Apr 18 02:53:24 PM PDT 24
Finished Apr 18 02:54:04 PM PDT 24
Peak memory 256008 kb
Host smart-9935a1b4-a57a-484f-ad01-f6bccb6c2930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42213
58830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.4221358830
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1795651895
Short name T601
Test name
Test status
Simulation time 126584923334 ps
CPU time 1898.14 seconds
Started Apr 18 02:53:28 PM PDT 24
Finished Apr 18 03:25:07 PM PDT 24
Peak memory 273724 kb
Host smart-c624495e-799b-4257-b885-3446fc258ad5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795651895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1795651895
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1900747964
Short name T103
Test name
Test status
Simulation time 22312439721 ps
CPU time 1391.13 seconds
Started Apr 18 02:53:34 PM PDT 24
Finished Apr 18 03:16:45 PM PDT 24
Peak memory 271944 kb
Host smart-5e3fbe05-8761-4fae-a939-6731ceb3c35d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900747964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1900747964
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2858948922
Short name T505
Test name
Test status
Simulation time 15066652770 ps
CPU time 647.62 seconds
Started Apr 18 02:53:28 PM PDT 24
Finished Apr 18 03:04:17 PM PDT 24
Peak memory 247364 kb
Host smart-7e3a0dd6-e545-4c69-b693-15c90ea302bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858948922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2858948922
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2022485715
Short name T471
Test name
Test status
Simulation time 3310784171 ps
CPU time 47.25 seconds
Started Apr 18 02:53:13 PM PDT 24
Finished Apr 18 02:54:01 PM PDT 24
Peak memory 249164 kb
Host smart-212963f6-6582-48b9-bb4b-747c6cd162e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20224
85715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2022485715
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1519255873
Short name T441
Test name
Test status
Simulation time 674991010 ps
CPU time 38.18 seconds
Started Apr 18 02:53:20 PM PDT 24
Finished Apr 18 02:53:59 PM PDT 24
Peak memory 255920 kb
Host smart-dedfa97a-f49c-4a18-9eed-903088cc41cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15192
55873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1519255873
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3425125074
Short name T116
Test name
Test status
Simulation time 8383198046 ps
CPU time 72.23 seconds
Started Apr 18 02:53:27 PM PDT 24
Finished Apr 18 02:54:40 PM PDT 24
Peak memory 257048 kb
Host smart-1377a024-0048-4cc1-b77c-c28a5b2582f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34251
25074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3425125074
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2434073253
Short name T599
Test name
Test status
Simulation time 3095115589 ps
CPU time 47.12 seconds
Started Apr 18 02:53:11 PM PDT 24
Finished Apr 18 02:53:59 PM PDT 24
Peak memory 256588 kb
Host smart-47bc241e-41ec-4769-80db-7c190241c2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24340
73253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2434073253
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1023541456
Short name T96
Test name
Test status
Simulation time 16816098595 ps
CPU time 1428.04 seconds
Started Apr 18 02:53:34 PM PDT 24
Finished Apr 18 03:17:22 PM PDT 24
Peak memory 289672 kb
Host smart-9c65f575-a301-4142-ae4c-a62c1026caac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023541456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1023541456
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3869033270
Short name T115
Test name
Test status
Simulation time 65462593756 ps
CPU time 1284.51 seconds
Started Apr 18 02:53:39 PM PDT 24
Finished Apr 18 03:15:04 PM PDT 24
Peak memory 282064 kb
Host smart-3009b918-950f-4537-83c7-c8f27d8385e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869033270 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3869033270
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1149959005
Short name T501
Test name
Test status
Simulation time 37763208327 ps
CPU time 1256.07 seconds
Started Apr 18 02:53:43 PM PDT 24
Finished Apr 18 03:14:40 PM PDT 24
Peak memory 273672 kb
Host smart-53be5cea-48ca-44f3-b254-fb59ce4ba932
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149959005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1149959005
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.216240824
Short name T231
Test name
Test status
Simulation time 1758440475 ps
CPU time 130.53 seconds
Started Apr 18 02:53:44 PM PDT 24
Finished Apr 18 02:55:55 PM PDT 24
Peak memory 251012 kb
Host smart-e88bd411-bef0-4ea7-a8b5-f92b967afb1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21624
0824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.216240824
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3388984380
Short name T658
Test name
Test status
Simulation time 1236464281 ps
CPU time 24.21 seconds
Started Apr 18 02:53:39 PM PDT 24
Finished Apr 18 02:54:04 PM PDT 24
Peak memory 248836 kb
Host smart-ab959011-1fbc-442e-8056-cf10d190629b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33889
84380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3388984380
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3855383868
Short name T299
Test name
Test status
Simulation time 34087058731 ps
CPU time 2014.2 seconds
Started Apr 18 02:53:43 PM PDT 24
Finished Apr 18 03:27:18 PM PDT 24
Peak memory 273564 kb
Host smart-8d1dc270-f5f6-48e6-9a7e-68addff6c5b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855383868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3855383868
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2538472467
Short name T432
Test name
Test status
Simulation time 55808062913 ps
CPU time 1356.26 seconds
Started Apr 18 02:53:47 PM PDT 24
Finished Apr 18 03:16:24 PM PDT 24
Peak memory 281396 kb
Host smart-4116d562-b065-4596-9771-e08d30a8b32a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538472467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2538472467
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.345104156
Short name T41
Test name
Test status
Simulation time 554409970 ps
CPU time 34.09 seconds
Started Apr 18 02:53:37 PM PDT 24
Finished Apr 18 02:54:12 PM PDT 24
Peak memory 256256 kb
Host smart-3686f91a-3692-4f28-921c-ebbb6afb761f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34510
4156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.345104156
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.4270007207
Short name T127
Test name
Test status
Simulation time 807087974 ps
CPU time 19.95 seconds
Started Apr 18 02:53:42 PM PDT 24
Finished Apr 18 02:54:03 PM PDT 24
Peak memory 255048 kb
Host smart-6a7d83e0-d744-46f1-afdf-c7aae04c124c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42700
07207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4270007207
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.400372195
Short name T423
Test name
Test status
Simulation time 3404221530 ps
CPU time 44.07 seconds
Started Apr 18 02:53:43 PM PDT 24
Finished Apr 18 02:54:27 PM PDT 24
Peak memory 249532 kb
Host smart-60db5ba9-63fc-4b95-8d2a-520d0942a9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40037
2195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.400372195
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1738389347
Short name T411
Test name
Test status
Simulation time 51393779 ps
CPU time 4.08 seconds
Started Apr 18 02:53:39 PM PDT 24
Finished Apr 18 02:53:44 PM PDT 24
Peak memory 240832 kb
Host smart-9e2debf7-9c5b-40e7-b722-e1952e31965b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17383
89347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1738389347
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1780659612
Short name T584
Test name
Test status
Simulation time 90986086476 ps
CPU time 2793.33 seconds
Started Apr 18 02:53:50 PM PDT 24
Finished Apr 18 03:40:24 PM PDT 24
Peak memory 299240 kb
Host smart-06a70ecf-fc37-481d-9915-af3f46013e7d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780659612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1780659612
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.945448045
Short name T108
Test name
Test status
Simulation time 93175413679 ps
CPU time 1669.58 seconds
Started Apr 18 02:53:52 PM PDT 24
Finished Apr 18 03:21:43 PM PDT 24
Peak memory 298440 kb
Host smart-22f50dfc-7a96-4476-b55f-d2dbca89284d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945448045 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.945448045
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2627804548
Short name T47
Test name
Test status
Simulation time 3284538623 ps
CPU time 95.83 seconds
Started Apr 18 02:53:58 PM PDT 24
Finished Apr 18 02:55:34 PM PDT 24
Peak memory 249168 kb
Host smart-ababc868-9237-4608-b6cf-3b90be23f040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26278
04548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2627804548
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1381955267
Short name T569
Test name
Test status
Simulation time 155224624 ps
CPU time 10.91 seconds
Started Apr 18 02:53:58 PM PDT 24
Finished Apr 18 02:54:09 PM PDT 24
Peak memory 253148 kb
Host smart-d30e4dfc-89f4-40ff-b1a0-cac7bb3ddb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13819
55267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1381955267
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2712207253
Short name T75
Test name
Test status
Simulation time 83768496110 ps
CPU time 2598.36 seconds
Started Apr 18 02:54:07 PM PDT 24
Finished Apr 18 03:37:26 PM PDT 24
Peak memory 289452 kb
Host smart-bdf9a8e9-69f5-4829-8c13-8f51efe051a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712207253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2712207253
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.986367551
Short name T325
Test name
Test status
Simulation time 2102204783 ps
CPU time 96.91 seconds
Started Apr 18 02:54:04 PM PDT 24
Finished Apr 18 02:55:41 PM PDT 24
Peak memory 247160 kb
Host smart-9d97826a-73c6-4873-b956-d11e05c37ba4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986367551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.986367551
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3468061272
Short name T654
Test name
Test status
Simulation time 132535504 ps
CPU time 7.82 seconds
Started Apr 18 02:53:52 PM PDT 24
Finished Apr 18 02:54:00 PM PDT 24
Peak memory 254312 kb
Host smart-ef42b118-64c2-4c52-bc27-93e38a354722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34680
61272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3468061272
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1894561149
Short name T629
Test name
Test status
Simulation time 995352291 ps
CPU time 33.05 seconds
Started Apr 18 02:53:56 PM PDT 24
Finished Apr 18 02:54:29 PM PDT 24
Peak memory 255592 kb
Host smart-7ed9d0ae-d9ca-4cfd-bcca-c67f8c91e318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18945
61149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1894561149
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.4001947360
Short name T670
Test name
Test status
Simulation time 75543252 ps
CPU time 9.13 seconds
Started Apr 18 02:54:00 PM PDT 24
Finished Apr 18 02:54:10 PM PDT 24
Peak memory 249068 kb
Host smart-00ada3c5-10fe-415f-b9c2-8ff1aa000072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40019
47360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.4001947360
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2544970685
Short name T637
Test name
Test status
Simulation time 191104699 ps
CPU time 12.69 seconds
Started Apr 18 02:53:54 PM PDT 24
Finished Apr 18 02:54:08 PM PDT 24
Peak memory 249064 kb
Host smart-c775a8aa-2dbd-47c2-8a47-dc8ba72fa9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25449
70685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2544970685
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2047101939
Short name T697
Test name
Test status
Simulation time 103259873226 ps
CPU time 1468.18 seconds
Started Apr 18 02:54:18 PM PDT 24
Finished Apr 18 03:18:47 PM PDT 24
Peak memory 273488 kb
Host smart-1f32a452-daee-4917-94ae-90fac27f515d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047101939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2047101939
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2593375540
Short name T238
Test name
Test status
Simulation time 731703411 ps
CPU time 60.82 seconds
Started Apr 18 02:54:18 PM PDT 24
Finished Apr 18 02:55:19 PM PDT 24
Peak memory 249004 kb
Host smart-e85cddc1-e5e3-4e94-96c3-1db90d533949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25933
75540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2593375540
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2052719082
Short name T643
Test name
Test status
Simulation time 96151300 ps
CPU time 9.03 seconds
Started Apr 18 02:54:18 PM PDT 24
Finished Apr 18 02:54:28 PM PDT 24
Peak memory 254968 kb
Host smart-76c747c4-e6bd-4093-aa41-f20f42bd8305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20527
19082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2052719082
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.356818271
Short name T239
Test name
Test status
Simulation time 39418127112 ps
CPU time 2237.52 seconds
Started Apr 18 02:54:24 PM PDT 24
Finished Apr 18 03:31:42 PM PDT 24
Peak memory 288604 kb
Host smart-7bb0ceea-f538-49c9-93ad-678efe10f7f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356818271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.356818271
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.893303378
Short name T22
Test name
Test status
Simulation time 200977728239 ps
CPU time 3087.67 seconds
Started Apr 18 02:54:28 PM PDT 24
Finished Apr 18 03:45:56 PM PDT 24
Peak memory 288288 kb
Host smart-1dc2c5e6-b5f0-49ee-a05c-23bbebadfafc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893303378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.893303378
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1006726537
Short name T609
Test name
Test status
Simulation time 31322204967 ps
CPU time 348.02 seconds
Started Apr 18 02:54:18 PM PDT 24
Finished Apr 18 03:00:06 PM PDT 24
Peak memory 248084 kb
Host smart-667fc4a8-b54b-415e-96ff-2621b3c62d4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006726537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1006726537
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2683255921
Short name T73
Test name
Test status
Simulation time 330532257 ps
CPU time 3.92 seconds
Started Apr 18 02:54:13 PM PDT 24
Finished Apr 18 02:54:17 PM PDT 24
Peak memory 240820 kb
Host smart-ec687882-eb37-470c-b901-69bf05b58ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26832
55921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2683255921
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3058632208
Short name T467
Test name
Test status
Simulation time 428029323 ps
CPU time 34.37 seconds
Started Apr 18 02:54:15 PM PDT 24
Finished Apr 18 02:54:50 PM PDT 24
Peak memory 256012 kb
Host smart-852003f4-37f4-4b63-94eb-3a5ab5fb97ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30586
32208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3058632208
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3128448483
Short name T541
Test name
Test status
Simulation time 423542379 ps
CPU time 12.64 seconds
Started Apr 18 02:54:13 PM PDT 24
Finished Apr 18 02:54:26 PM PDT 24
Peak memory 248968 kb
Host smart-51551dc6-4414-458d-b68c-23ca991ecc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31284
48483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3128448483
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1386273275
Short name T102
Test name
Test status
Simulation time 33147901714 ps
CPU time 1655.56 seconds
Started Apr 18 02:54:36 PM PDT 24
Finished Apr 18 03:22:12 PM PDT 24
Peak memory 273348 kb
Host smart-9c9b29fd-a855-4acf-a5c8-69feac6d4963
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386273275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1386273275
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.4265266162
Short name T667
Test name
Test status
Simulation time 6279440122 ps
CPU time 168.93 seconds
Started Apr 18 02:54:36 PM PDT 24
Finished Apr 18 02:57:26 PM PDT 24
Peak memory 250184 kb
Host smart-406da156-975a-4e19-990a-de9210017844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42652
66162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.4265266162
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2201012383
Short name T600
Test name
Test status
Simulation time 1066686251 ps
CPU time 27.06 seconds
Started Apr 18 02:54:37 PM PDT 24
Finished Apr 18 02:55:04 PM PDT 24
Peak memory 255448 kb
Host smart-75c0af07-c318-44c2-914c-211ebb4cd7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22010
12383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2201012383
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2051378851
Short name T604
Test name
Test status
Simulation time 107326550567 ps
CPU time 1493.2 seconds
Started Apr 18 02:54:42 PM PDT 24
Finished Apr 18 03:19:36 PM PDT 24
Peak memory 273140 kb
Host smart-583ac8dd-ff59-4a2a-a501-57e372a1b60d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051378851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2051378851
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.768236076
Short name T537
Test name
Test status
Simulation time 15265951061 ps
CPU time 798.55 seconds
Started Apr 18 02:54:43 PM PDT 24
Finished Apr 18 03:08:01 PM PDT 24
Peak memory 273012 kb
Host smart-6ac5b99c-5d7d-4947-92b1-5cb11250e60e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768236076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.768236076
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2885552978
Short name T319
Test name
Test status
Simulation time 45213114395 ps
CPU time 494.01 seconds
Started Apr 18 02:54:36 PM PDT 24
Finished Apr 18 03:02:51 PM PDT 24
Peak memory 248184 kb
Host smart-a4c930b6-23cf-4a53-be77-e8727d05dc4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885552978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2885552978
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.355687367
Short name T701
Test name
Test status
Simulation time 3840506566 ps
CPU time 58.36 seconds
Started Apr 18 02:54:37 PM PDT 24
Finished Apr 18 02:55:36 PM PDT 24
Peak memory 256352 kb
Host smart-db07a022-9288-4194-924d-05199dc6cb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35568
7367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.355687367
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1351499965
Short name T702
Test name
Test status
Simulation time 4154953301 ps
CPU time 65.5 seconds
Started Apr 18 02:54:32 PM PDT 24
Finished Apr 18 02:55:38 PM PDT 24
Peak memory 255764 kb
Host smart-dd42dfb7-01a6-458b-862d-50916abe444d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13514
99965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1351499965
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1955182081
Short name T228
Test name
Test status
Simulation time 2996989856 ps
CPU time 49.56 seconds
Started Apr 18 02:54:37 PM PDT 24
Finished Apr 18 02:55:27 PM PDT 24
Peak memory 256236 kb
Host smart-e3b66f7a-5a41-4ec5-a3c4-ce9e4b85e538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19551
82081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1955182081
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.4115037848
Short name T677
Test name
Test status
Simulation time 30252418323 ps
CPU time 1592.18 seconds
Started Apr 18 02:55:04 PM PDT 24
Finished Apr 18 03:21:37 PM PDT 24
Peak memory 289432 kb
Host smart-512fa0e9-6621-4bff-9d2e-eae141697562
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115037848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.4115037848
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1285774970
Short name T300
Test name
Test status
Simulation time 5447326827 ps
CPU time 167.25 seconds
Started Apr 18 02:54:59 PM PDT 24
Finished Apr 18 02:57:47 PM PDT 24
Peak memory 257136 kb
Host smart-6e7a11eb-5c62-432e-b162-bb1867038a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12857
74970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1285774970
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.488777651
Short name T382
Test name
Test status
Simulation time 169240448 ps
CPU time 10.59 seconds
Started Apr 18 02:54:53 PM PDT 24
Finished Apr 18 02:55:04 PM PDT 24
Peak memory 252008 kb
Host smart-ac8beff5-5492-42df-b73f-3eeb19f0ea89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48877
7651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.488777651
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1367420095
Short name T350
Test name
Test status
Simulation time 88327688781 ps
CPU time 2592.73 seconds
Started Apr 18 02:55:04 PM PDT 24
Finished Apr 18 03:38:17 PM PDT 24
Peak memory 289732 kb
Host smart-0173ec21-c21f-4443-9e4c-4925173a1297
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367420095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1367420095
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1546752997
Short name T623
Test name
Test status
Simulation time 41524664854 ps
CPU time 1990.35 seconds
Started Apr 18 02:55:09 PM PDT 24
Finished Apr 18 03:28:20 PM PDT 24
Peak memory 286972 kb
Host smart-e80e59ae-c970-41b9-9636-48f1f7c761b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546752997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1546752997
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3781955588
Short name T314
Test name
Test status
Simulation time 4570129525 ps
CPU time 97.06 seconds
Started Apr 18 02:55:02 PM PDT 24
Finished Apr 18 02:56:40 PM PDT 24
Peak memory 248508 kb
Host smart-a050d497-fc8f-43e0-9ea7-a4243fbcddbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781955588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3781955588
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3032307149
Short name T590
Test name
Test status
Simulation time 2104957030 ps
CPU time 28.57 seconds
Started Apr 18 02:54:48 PM PDT 24
Finished Apr 18 02:55:17 PM PDT 24
Peak memory 248888 kb
Host smart-0975a562-9e49-4600-a3db-998cebda4586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30323
07149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3032307149
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1213974530
Short name T587
Test name
Test status
Simulation time 505492031 ps
CPU time 26.99 seconds
Started Apr 18 02:54:51 PM PDT 24
Finished Apr 18 02:55:18 PM PDT 24
Peak memory 255896 kb
Host smart-4386b96f-ce1a-4238-9d65-97beceaeee76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12139
74530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1213974530
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3439912354
Short name T619
Test name
Test status
Simulation time 366725790 ps
CPU time 10.61 seconds
Started Apr 18 02:55:02 PM PDT 24
Finished Apr 18 02:55:13 PM PDT 24
Peak memory 249064 kb
Host smart-a16243dd-7e78-4f1d-a028-8f1246a79d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34399
12354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3439912354
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1057430746
Short name T402
Test name
Test status
Simulation time 297071456 ps
CPU time 32.94 seconds
Started Apr 18 02:54:48 PM PDT 24
Finished Apr 18 02:55:21 PM PDT 24
Peak memory 256648 kb
Host smart-dafb25ea-7785-47af-a7af-d8e52857a82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10574
30746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1057430746
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.4242631542
Short name T651
Test name
Test status
Simulation time 4689823715 ps
CPU time 127.56 seconds
Started Apr 18 02:55:09 PM PDT 24
Finished Apr 18 02:57:17 PM PDT 24
Peak memory 256576 kb
Host smart-b36bb480-d387-4939-8126-772dd6664c6c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242631542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.4242631542
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1919105065
Short name T215
Test name
Test status
Simulation time 56370330 ps
CPU time 2.12 seconds
Started Apr 18 02:47:15 PM PDT 24
Finished Apr 18 02:47:18 PM PDT 24
Peak memory 249324 kb
Host smart-8af3b68f-6b1c-44bb-835e-b2e466cf86be
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1919105065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1919105065
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1984061023
Short name T85
Test name
Test status
Simulation time 42878463654 ps
CPU time 1208.27 seconds
Started Apr 18 02:47:05 PM PDT 24
Finished Apr 18 03:07:13 PM PDT 24
Peak memory 272932 kb
Host smart-88973ba4-4210-4d4c-982d-a3d28557ade1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984061023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1984061023
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3143928485
Short name T480
Test name
Test status
Simulation time 2102534776 ps
CPU time 25.29 seconds
Started Apr 18 02:47:18 PM PDT 24
Finished Apr 18 02:47:43 PM PDT 24
Peak memory 240832 kb
Host smart-c456009a-d4cb-449f-93ec-ebbddec52ee2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3143928485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3143928485
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1640060842
Short name T470
Test name
Test status
Simulation time 3703116330 ps
CPU time 145.3 seconds
Started Apr 18 02:46:59 PM PDT 24
Finished Apr 18 02:49:25 PM PDT 24
Peak memory 256984 kb
Host smart-23df24dd-9a4f-43ef-9a26-b557e6d61439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16400
60842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1640060842
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1298795787
Short name T565
Test name
Test status
Simulation time 1571843247 ps
CPU time 51.86 seconds
Started Apr 18 02:46:59 PM PDT 24
Finished Apr 18 02:47:51 PM PDT 24
Peak memory 255616 kb
Host smart-fc340e7f-adab-46e6-a29d-6c2e43bf876e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12987
95787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1298795787
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2452413089
Short name T341
Test name
Test status
Simulation time 28466327451 ps
CPU time 1669.99 seconds
Started Apr 18 02:47:09 PM PDT 24
Finished Apr 18 03:14:59 PM PDT 24
Peak memory 273664 kb
Host smart-b056141c-f940-48e7-a73f-13dfc0fd59dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452413089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2452413089
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1796686455
Short name T29
Test name
Test status
Simulation time 105551850468 ps
CPU time 1568.99 seconds
Started Apr 18 02:47:09 PM PDT 24
Finished Apr 18 03:13:18 PM PDT 24
Peak memory 273432 kb
Host smart-32bdff04-5a38-40d2-8814-4d3a15a7b82c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796686455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1796686455
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.989783488
Short name T6
Test name
Test status
Simulation time 23645932311 ps
CPU time 210.24 seconds
Started Apr 18 02:47:04 PM PDT 24
Finished Apr 18 02:50:35 PM PDT 24
Peak memory 248376 kb
Host smart-fb1e0e98-9012-42a7-abff-e2f2b84019de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989783488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.989783488
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1059284067
Short name T388
Test name
Test status
Simulation time 827535974 ps
CPU time 12.06 seconds
Started Apr 18 02:46:55 PM PDT 24
Finished Apr 18 02:47:08 PM PDT 24
Peak memory 255720 kb
Host smart-8368e19c-cfa0-4d84-a5d0-62b033884145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10592
84067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1059284067
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1911224105
Short name T507
Test name
Test status
Simulation time 3071545866 ps
CPU time 46.11 seconds
Started Apr 18 02:46:54 PM PDT 24
Finished Apr 18 02:47:41 PM PDT 24
Peak memory 255448 kb
Host smart-75a5c207-6e52-4093-88f6-624d81d2bc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19112
24105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1911224105
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3452035750
Short name T315
Test name
Test status
Simulation time 82615728 ps
CPU time 4.14 seconds
Started Apr 18 02:47:04 PM PDT 24
Finished Apr 18 02:47:08 PM PDT 24
Peak memory 239396 kb
Host smart-5ad6dd2e-852c-43d5-8845-c08e5fe79387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34520
35750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3452035750
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.4189561093
Short name T82
Test name
Test status
Simulation time 391143842 ps
CPU time 34.68 seconds
Started Apr 18 02:46:54 PM PDT 24
Finished Apr 18 02:47:29 PM PDT 24
Peak memory 256240 kb
Host smart-31b27092-5326-4086-bcef-8b7abbbea05c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41895
61093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.4189561093
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.343275974
Short name T130
Test name
Test status
Simulation time 75413958846 ps
CPU time 1391.08 seconds
Started Apr 18 02:47:13 PM PDT 24
Finished Apr 18 03:10:24 PM PDT 24
Peak memory 289588 kb
Host smart-95004f87-8eee-42f2-9848-d0c36c765a23
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343275974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.343275974
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2490291794
Short name T104
Test name
Test status
Simulation time 95582275153 ps
CPU time 1678.72 seconds
Started Apr 18 02:55:22 PM PDT 24
Finished Apr 18 03:23:22 PM PDT 24
Peak memory 272992 kb
Host smart-2d996b41-8557-4636-96b0-828882ea5310
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490291794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2490291794
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3327492979
Short name T462
Test name
Test status
Simulation time 9343683296 ps
CPU time 129.93 seconds
Started Apr 18 02:55:18 PM PDT 24
Finished Apr 18 02:57:28 PM PDT 24
Peak memory 257016 kb
Host smart-fe773f45-00d8-4fd7-ac6a-fc57def4132a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33274
92979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3327492979
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.290323524
Short name T93
Test name
Test status
Simulation time 454168842 ps
CPU time 15.61 seconds
Started Apr 18 02:55:19 PM PDT 24
Finished Apr 18 02:55:35 PM PDT 24
Peak memory 249028 kb
Host smart-74587cba-ac1d-4f82-ab61-17b6344de358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29032
3524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.290323524
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3497606676
Short name T125
Test name
Test status
Simulation time 382804717601 ps
CPU time 1933.66 seconds
Started Apr 18 02:55:32 PM PDT 24
Finished Apr 18 03:27:46 PM PDT 24
Peak memory 287320 kb
Host smart-9dc367bd-cf4e-4113-970c-2c1faf20a3c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497606676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3497606676
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2742560220
Short name T328
Test name
Test status
Simulation time 14276734994 ps
CPU time 573.18 seconds
Started Apr 18 02:55:28 PM PDT 24
Finished Apr 18 03:05:01 PM PDT 24
Peak memory 248020 kb
Host smart-f669544e-88d0-46b9-a58f-32ce447e651a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742560220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2742560220
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.695110517
Short name T497
Test name
Test status
Simulation time 77563188 ps
CPU time 5.86 seconds
Started Apr 18 02:55:18 PM PDT 24
Finished Apr 18 02:55:24 PM PDT 24
Peak memory 240832 kb
Host smart-2d2faa1d-56b8-46e9-b0bd-cfba3738a2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69511
0517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.695110517
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2837650441
Short name T603
Test name
Test status
Simulation time 7332327825 ps
CPU time 53.37 seconds
Started Apr 18 02:55:17 PM PDT 24
Finished Apr 18 02:56:11 PM PDT 24
Peak memory 255740 kb
Host smart-a7cc814c-e183-4039-85c6-165dbe56ee49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28376
50441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2837650441
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1946817812
Short name T241
Test name
Test status
Simulation time 396363691 ps
CPU time 29.8 seconds
Started Apr 18 02:55:23 PM PDT 24
Finished Apr 18 02:55:53 PM PDT 24
Peak memory 247492 kb
Host smart-9f656aef-cfea-47fd-b625-10fb50af2e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19468
17812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1946817812
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.762477640
Short name T410
Test name
Test status
Simulation time 4733196609 ps
CPU time 32.14 seconds
Started Apr 18 02:55:13 PM PDT 24
Finished Apr 18 02:55:45 PM PDT 24
Peak memory 249404 kb
Host smart-0a63ebd5-cab4-4fdb-bb8d-554e216c0d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76247
7640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.762477640
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.633390050
Short name T25
Test name
Test status
Simulation time 51881665623 ps
CPU time 1028.6 seconds
Started Apr 18 02:55:53 PM PDT 24
Finished Apr 18 03:13:03 PM PDT 24
Peak memory 272576 kb
Host smart-6127cfd7-f6a8-4d2f-84db-2db081baffe7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633390050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.633390050
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3252708144
Short name T377
Test name
Test status
Simulation time 8427523399 ps
CPU time 141.6 seconds
Started Apr 18 02:55:49 PM PDT 24
Finished Apr 18 02:58:10 PM PDT 24
Peak memory 256860 kb
Host smart-4c10db2f-bc59-47fa-bb19-9bba77db18ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32527
08144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3252708144
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1787850592
Short name T37
Test name
Test status
Simulation time 157469295 ps
CPU time 3.73 seconds
Started Apr 18 02:55:48 PM PDT 24
Finished Apr 18 02:55:52 PM PDT 24
Peak memory 239164 kb
Host smart-f731bf5e-87ac-4775-8ca9-3b7f355dbef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17878
50592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1787850592
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.607602042
Short name T343
Test name
Test status
Simulation time 103598724971 ps
CPU time 1544.61 seconds
Started Apr 18 02:55:53 PM PDT 24
Finished Apr 18 03:21:39 PM PDT 24
Peak memory 273728 kb
Host smart-75ac7e94-f63b-4856-b985-9f93c7be008d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607602042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.607602042
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3149384542
Short name T617
Test name
Test status
Simulation time 19744983332 ps
CPU time 959.05 seconds
Started Apr 18 02:55:57 PM PDT 24
Finished Apr 18 03:11:57 PM PDT 24
Peak memory 273692 kb
Host smart-7f25a5bb-9639-49a1-b29e-ead38342e54a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149384542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3149384542
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2530392147
Short name T688
Test name
Test status
Simulation time 3613340925 ps
CPU time 138.73 seconds
Started Apr 18 02:55:53 PM PDT 24
Finished Apr 18 02:58:12 PM PDT 24
Peak memory 248308 kb
Host smart-df49c098-2b44-46f5-a495-804f845b6e19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530392147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2530392147
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3698650150
Short name T121
Test name
Test status
Simulation time 1095219708 ps
CPU time 28.96 seconds
Started Apr 18 02:55:46 PM PDT 24
Finished Apr 18 02:56:15 PM PDT 24
Peak memory 249028 kb
Host smart-90ec9baa-2e7c-461d-8474-9646ca2b406f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36986
50150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3698650150
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.454666697
Short name T397
Test name
Test status
Simulation time 276193710 ps
CPU time 16.51 seconds
Started Apr 18 02:55:48 PM PDT 24
Finished Apr 18 02:56:05 PM PDT 24
Peak memory 253588 kb
Host smart-05daed2c-14e2-40ea-994a-655d29ee708e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45466
6697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.454666697
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3841417106
Short name T284
Test name
Test status
Simulation time 1170176233 ps
CPU time 16.43 seconds
Started Apr 18 02:55:53 PM PDT 24
Finished Apr 18 02:56:10 PM PDT 24
Peak memory 248940 kb
Host smart-08106d1a-18e2-4164-84ed-bc8058ec4714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38414
17106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3841417106
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.94346018
Short name T373
Test name
Test status
Simulation time 234053379 ps
CPU time 10.99 seconds
Started Apr 18 02:55:35 PM PDT 24
Finished Apr 18 02:55:47 PM PDT 24
Peak memory 249028 kb
Host smart-f10dafc5-7a41-48c9-8b75-93c757b644d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94346
018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.94346018
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1915709497
Short name T509
Test name
Test status
Simulation time 39740242145 ps
CPU time 905.41 seconds
Started Apr 18 02:55:56 PM PDT 24
Finished Apr 18 03:11:03 PM PDT 24
Peak memory 287364 kb
Host smart-c5fa63d6-d6d2-4e1a-b121-f657861e0903
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915709497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1915709497
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.4225463220
Short name T645
Test name
Test status
Simulation time 36014553078 ps
CPU time 2078.97 seconds
Started Apr 18 02:56:16 PM PDT 24
Finished Apr 18 03:30:55 PM PDT 24
Peak memory 289628 kb
Host smart-3f8ab424-6323-45cf-af58-a379cdf6e963
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225463220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4225463220
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3276655408
Short name T461
Test name
Test status
Simulation time 1387854893 ps
CPU time 20.64 seconds
Started Apr 18 02:56:12 PM PDT 24
Finished Apr 18 02:56:33 PM PDT 24
Peak memory 255944 kb
Host smart-91e7d574-bb58-48f5-a0fc-4529d4337fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32766
55408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3276655408
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1713317426
Short name T570
Test name
Test status
Simulation time 549994567 ps
CPU time 17.65 seconds
Started Apr 18 02:56:11 PM PDT 24
Finished Apr 18 02:56:29 PM PDT 24
Peak memory 255756 kb
Host smart-810d0564-ef81-444e-845e-e4b61be51e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17133
17426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1713317426
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3890725036
Short name T43
Test name
Test status
Simulation time 526704341386 ps
CPU time 2022.85 seconds
Started Apr 18 02:56:21 PM PDT 24
Finished Apr 18 03:30:04 PM PDT 24
Peak memory 281948 kb
Host smart-a0608193-ce97-4d52-8fe0-a429d102e8cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890725036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3890725036
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3241564835
Short name T618
Test name
Test status
Simulation time 6945289668 ps
CPU time 82.57 seconds
Started Apr 18 02:56:16 PM PDT 24
Finished Apr 18 02:57:39 PM PDT 24
Peak memory 248048 kb
Host smart-b4b59c16-a29d-4833-81db-38fb498a349b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241564835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3241564835
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.261504028
Short name T581
Test name
Test status
Simulation time 374962686 ps
CPU time 22.97 seconds
Started Apr 18 02:56:06 PM PDT 24
Finished Apr 18 02:56:30 PM PDT 24
Peak memory 256416 kb
Host smart-8d7031fb-0849-45fb-afba-351bfd99cbfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26150
4028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.261504028
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2889909180
Short name T246
Test name
Test status
Simulation time 116516800 ps
CPU time 8.09 seconds
Started Apr 18 02:56:12 PM PDT 24
Finished Apr 18 02:56:20 PM PDT 24
Peak memory 249832 kb
Host smart-84aad0e1-dd06-4268-8c06-818b0d389ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28899
09180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2889909180
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3678911148
Short name T665
Test name
Test status
Simulation time 2320178655 ps
CPU time 11.69 seconds
Started Apr 18 02:56:15 PM PDT 24
Finished Apr 18 02:56:27 PM PDT 24
Peak memory 247688 kb
Host smart-674610b4-055f-4f43-84d9-06488b924718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36789
11148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3678911148
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3229673045
Short name T374
Test name
Test status
Simulation time 1666909084 ps
CPU time 26.91 seconds
Started Apr 18 02:56:01 PM PDT 24
Finished Apr 18 02:56:29 PM PDT 24
Peak memory 249148 kb
Host smart-83b71ec6-963e-463f-a24b-0d713d66ff3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32296
73045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3229673045
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.322806220
Short name T560
Test name
Test status
Simulation time 10955437720 ps
CPU time 492.6 seconds
Started Apr 18 02:56:21 PM PDT 24
Finished Apr 18 03:04:34 PM PDT 24
Peak memory 265576 kb
Host smart-f8fb43ec-f05e-4530-8279-2359e5cc679a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322806220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.322806220
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.4195829185
Short name T484
Test name
Test status
Simulation time 10529781008 ps
CPU time 927.4 seconds
Started Apr 18 02:56:41 PM PDT 24
Finished Apr 18 03:12:09 PM PDT 24
Peak memory 281876 kb
Host smart-62b987c0-42b9-4c73-9618-550280fe3259
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195829185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.4195829185
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.577429678
Short name T630
Test name
Test status
Simulation time 18402588581 ps
CPU time 109.27 seconds
Started Apr 18 02:56:31 PM PDT 24
Finished Apr 18 02:58:21 PM PDT 24
Peak memory 256652 kb
Host smart-66a408f7-621b-45ae-a92f-a0cf7a822602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57742
9678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.577429678
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.720847468
Short name T270
Test name
Test status
Simulation time 4951758674 ps
CPU time 52.11 seconds
Started Apr 18 02:56:31 PM PDT 24
Finished Apr 18 02:57:24 PM PDT 24
Peak memory 256448 kb
Host smart-fa3adb86-3d41-4221-98f0-bc45727a3a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72084
7468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.720847468
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3105130115
Short name T633
Test name
Test status
Simulation time 85917563641 ps
CPU time 1326.02 seconds
Started Apr 18 02:56:46 PM PDT 24
Finished Apr 18 03:18:52 PM PDT 24
Peak memory 273736 kb
Host smart-a205a9a4-5b46-43d9-8ee6-b8fcabe67709
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105130115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3105130115
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1250043638
Short name T444
Test name
Test status
Simulation time 166575251625 ps
CPU time 2441.54 seconds
Started Apr 18 02:56:47 PM PDT 24
Finished Apr 18 03:37:29 PM PDT 24
Peak memory 281932 kb
Host smart-1068c4fe-2134-48d5-a599-583df6730784
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250043638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1250043638
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3308036386
Short name T324
Test name
Test status
Simulation time 3489672615 ps
CPU time 158.54 seconds
Started Apr 18 02:56:43 PM PDT 24
Finished Apr 18 02:59:21 PM PDT 24
Peak memory 247272 kb
Host smart-a9664946-f3fe-424e-a78b-6c7195d60f54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308036386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3308036386
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.951372177
Short name T384
Test name
Test status
Simulation time 672964717 ps
CPU time 31 seconds
Started Apr 18 02:56:26 PM PDT 24
Finished Apr 18 02:56:57 PM PDT 24
Peak memory 255980 kb
Host smart-8fcb0a96-4bfc-43e0-ad11-9e0775415bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95137
2177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.951372177
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.538877675
Short name T698
Test name
Test status
Simulation time 73277641 ps
CPU time 5.75 seconds
Started Apr 18 02:56:27 PM PDT 24
Finished Apr 18 02:56:33 PM PDT 24
Peak memory 239384 kb
Host smart-8402fc57-da29-48e6-8279-907d9813d220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53887
7675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.538877675
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3398104105
Short name T482
Test name
Test status
Simulation time 72201266 ps
CPU time 8.49 seconds
Started Apr 18 02:56:41 PM PDT 24
Finished Apr 18 02:56:50 PM PDT 24
Peak memory 255660 kb
Host smart-9ede7522-7312-46ae-8419-28bb17106aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33981
04105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3398104105
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2419144933
Short name T298
Test name
Test status
Simulation time 3424832395 ps
CPU time 17.77 seconds
Started Apr 18 02:56:27 PM PDT 24
Finished Apr 18 02:56:45 PM PDT 24
Peak memory 249180 kb
Host smart-d7c00bfd-cdb0-4054-9b26-c6a02b3406c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24191
44933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2419144933
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2834095571
Short name T594
Test name
Test status
Simulation time 1371733677 ps
CPU time 114.92 seconds
Started Apr 18 02:56:46 PM PDT 24
Finished Apr 18 02:58:42 PM PDT 24
Peak memory 257232 kb
Host smart-4b7c6419-f4d4-433c-9f8c-9fbef4bef4de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834095571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2834095571
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.466343015
Short name T252
Test name
Test status
Simulation time 148923433301 ps
CPU time 2335.23 seconds
Started Apr 18 02:56:47 PM PDT 24
Finished Apr 18 03:35:43 PM PDT 24
Peak memory 290244 kb
Host smart-a560ec9c-3a50-4688-ad8f-08137659de25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466343015 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.466343015
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.964581317
Short name T72
Test name
Test status
Simulation time 153892405274 ps
CPU time 2600 seconds
Started Apr 18 02:56:55 PM PDT 24
Finished Apr 18 03:40:15 PM PDT 24
Peak memory 289556 kb
Host smart-e4ebc2f1-3ee6-41e2-9847-645a269f0bdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964581317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.964581317
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2168981442
Short name T655
Test name
Test status
Simulation time 6970542944 ps
CPU time 117.71 seconds
Started Apr 18 02:56:56 PM PDT 24
Finished Apr 18 02:58:55 PM PDT 24
Peak memory 256892 kb
Host smart-c5c19db0-b09a-4d66-af2f-71217b3a7c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21689
81442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2168981442
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3753366291
Short name T194
Test name
Test status
Simulation time 439677727 ps
CPU time 38 seconds
Started Apr 18 02:56:59 PM PDT 24
Finished Apr 18 02:57:37 PM PDT 24
Peak memory 256020 kb
Host smart-39222a93-5e5c-4dd0-b40b-750227c615f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37533
66291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3753366291
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1914795016
Short name T344
Test name
Test status
Simulation time 33876078434 ps
CPU time 1422.44 seconds
Started Apr 18 02:57:01 PM PDT 24
Finished Apr 18 03:20:44 PM PDT 24
Peak memory 287508 kb
Host smart-13471e16-4bcb-45db-9641-043330e12086
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914795016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1914795016
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.188834116
Short name T706
Test name
Test status
Simulation time 56398640869 ps
CPU time 1053.75 seconds
Started Apr 18 02:57:04 PM PDT 24
Finished Apr 18 03:14:38 PM PDT 24
Peak memory 281284 kb
Host smart-6b6c5246-1ff6-4aff-aa06-4e0799ca5024
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188834116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.188834116
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2397695417
Short name T191
Test name
Test status
Simulation time 12949128336 ps
CPU time 509.96 seconds
Started Apr 18 02:57:02 PM PDT 24
Finished Apr 18 03:05:32 PM PDT 24
Peak memory 248240 kb
Host smart-12f2d173-c8cb-4992-8604-e6d27a9d6059
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397695417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2397695417
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.4249989330
Short name T538
Test name
Test status
Simulation time 333837453 ps
CPU time 39.18 seconds
Started Apr 18 02:56:51 PM PDT 24
Finished Apr 18 02:57:30 PM PDT 24
Peak memory 256296 kb
Host smart-cb285245-6d80-4bdc-a16f-abd7f54293ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42499
89330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.4249989330
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1702681310
Short name T687
Test name
Test status
Simulation time 225372249 ps
CPU time 26.96 seconds
Started Apr 18 02:56:51 PM PDT 24
Finished Apr 18 02:57:18 PM PDT 24
Peak memory 255776 kb
Host smart-2b482ad8-b9b2-4c94-b8f6-93bdd21b7e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17026
81310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1702681310
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.43703148
Short name T644
Test name
Test status
Simulation time 654402497 ps
CPU time 41.08 seconds
Started Apr 18 02:56:56 PM PDT 24
Finished Apr 18 02:57:37 PM PDT 24
Peak memory 255532 kb
Host smart-0fc0ba87-3d1c-460a-b43a-39ccc59c703e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43703
148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.43703148
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2964086763
Short name T559
Test name
Test status
Simulation time 526494246 ps
CPU time 19.86 seconds
Started Apr 18 02:56:52 PM PDT 24
Finished Apr 18 02:57:12 PM PDT 24
Peak memory 256204 kb
Host smart-7c53a699-6b71-4802-b4d6-f33bb910b505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29640
86763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2964086763
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2770745767
Short name T295
Test name
Test status
Simulation time 302886479700 ps
CPU time 2867.88 seconds
Started Apr 18 02:57:08 PM PDT 24
Finished Apr 18 03:44:57 PM PDT 24
Peak memory 301100 kb
Host smart-fac0f13c-768d-40e4-afb9-b2b2849be55d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770745767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2770745767
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1405637645
Short name T439
Test name
Test status
Simulation time 70286294362 ps
CPU time 1078.48 seconds
Started Apr 18 02:57:14 PM PDT 24
Finished Apr 18 03:15:13 PM PDT 24
Peak memory 265564 kb
Host smart-48d0ecf9-9124-4da3-bf1b-677072cc9b22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405637645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1405637645
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.4268887201
Short name T466
Test name
Test status
Simulation time 436067612 ps
CPU time 10.25 seconds
Started Apr 18 02:57:08 PM PDT 24
Finished Apr 18 02:57:19 PM PDT 24
Peak memory 253964 kb
Host smart-4fddffd8-3373-4769-aa4e-8583af2d0b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42688
87201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.4268887201
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1520241237
Short name T661
Test name
Test status
Simulation time 377739646 ps
CPU time 14.28 seconds
Started Apr 18 02:57:08 PM PDT 24
Finished Apr 18 02:57:23 PM PDT 24
Peak memory 254196 kb
Host smart-d6d244e2-06cb-4463-881e-c7fc61a445c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15202
41237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1520241237
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1776761890
Short name T450
Test name
Test status
Simulation time 19079892574 ps
CPU time 1091.89 seconds
Started Apr 18 02:57:14 PM PDT 24
Finished Apr 18 03:15:26 PM PDT 24
Peak memory 265556 kb
Host smart-638d7134-7d96-4503-ac83-00f56e039720
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776761890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1776761890
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.472793945
Short name T422
Test name
Test status
Simulation time 33225440452 ps
CPU time 1676.84 seconds
Started Apr 18 02:57:12 PM PDT 24
Finished Apr 18 03:25:09 PM PDT 24
Peak memory 267540 kb
Host smart-e765d6d8-37f2-4989-986b-fd85692c4a21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472793945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.472793945
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3368296220
Short name T321
Test name
Test status
Simulation time 74173310023 ps
CPU time 479.8 seconds
Started Apr 18 02:57:11 PM PDT 24
Finished Apr 18 03:05:11 PM PDT 24
Peak memory 248328 kb
Host smart-a2ce0867-623c-4826-a21c-13625fe6aa0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368296220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3368296220
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.32573241
Short name T556
Test name
Test status
Simulation time 1052868741 ps
CPU time 22.66 seconds
Started Apr 18 02:57:08 PM PDT 24
Finished Apr 18 02:57:31 PM PDT 24
Peak memory 257224 kb
Host smart-c4ef1f34-587a-48e1-8abb-6023326e7ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32573
241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.32573241
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3576425907
Short name T498
Test name
Test status
Simulation time 4524274766 ps
CPU time 61.13 seconds
Started Apr 18 02:57:09 PM PDT 24
Finished Apr 18 02:58:10 PM PDT 24
Peak memory 255896 kb
Host smart-85c2366f-c2a8-4ea8-806a-84c6ecc51511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35764
25907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3576425907
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.382536310
Short name T268
Test name
Test status
Simulation time 3795477316 ps
CPU time 37.6 seconds
Started Apr 18 02:57:08 PM PDT 24
Finished Apr 18 02:57:45 PM PDT 24
Peak memory 255740 kb
Host smart-e7526836-199f-4ee4-9bf4-b050b4a05eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38253
6310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.382536310
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3310829
Short name T517
Test name
Test status
Simulation time 1076053249 ps
CPU time 29.19 seconds
Started Apr 18 02:57:10 PM PDT 24
Finished Apr 18 02:57:39 PM PDT 24
Peak memory 249036 kb
Host smart-1f269cf3-4288-49f8-88f0-38c903acab92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33108
29 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3310829
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.385048016
Short name T307
Test name
Test status
Simulation time 17044178914 ps
CPU time 219.61 seconds
Started Apr 18 02:57:17 PM PDT 24
Finished Apr 18 03:00:56 PM PDT 24
Peak memory 257324 kb
Host smart-02c033ea-d448-4e32-892a-59112b6adc84
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385048016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.385048016
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2975330862
Short name T683
Test name
Test status
Simulation time 45693863693 ps
CPU time 1409.74 seconds
Started Apr 18 02:57:47 PM PDT 24
Finished Apr 18 03:21:18 PM PDT 24
Peak memory 273672 kb
Host smart-4f8b5970-c24c-44c1-a4cb-856f3a95717d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975330862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2975330862
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.890141030
Short name T647
Test name
Test status
Simulation time 4131734965 ps
CPU time 224.48 seconds
Started Apr 18 02:57:39 PM PDT 24
Finished Apr 18 03:01:24 PM PDT 24
Peak memory 257272 kb
Host smart-8f570f2d-b6cc-4898-8f18-e72424a0d647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89014
1030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.890141030
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.279080977
Short name T97
Test name
Test status
Simulation time 862300944 ps
CPU time 24.57 seconds
Started Apr 18 02:57:36 PM PDT 24
Finished Apr 18 02:58:01 PM PDT 24
Peak memory 256096 kb
Host smart-b684351d-cb76-4906-b25c-7fbb511c6047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27908
0977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.279080977
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2733032696
Short name T526
Test name
Test status
Simulation time 29234494317 ps
CPU time 1520.24 seconds
Started Apr 18 02:57:45 PM PDT 24
Finished Apr 18 03:23:05 PM PDT 24
Peak memory 273740 kb
Host smart-86a9838f-d168-40d2-9e65-6dbdf29935f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733032696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2733032696
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3018893035
Short name T2
Test name
Test status
Simulation time 8813756504 ps
CPU time 873.04 seconds
Started Apr 18 02:57:46 PM PDT 24
Finished Apr 18 03:12:20 PM PDT 24
Peak memory 286124 kb
Host smart-b36c6ea4-a6c1-4bc0-90e4-c092051a48f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018893035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3018893035
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3639447091
Short name T596
Test name
Test status
Simulation time 10551000365 ps
CPU time 109.78 seconds
Started Apr 18 02:57:46 PM PDT 24
Finished Apr 18 02:59:36 PM PDT 24
Peak memory 248296 kb
Host smart-9909d532-2fc6-48b9-a8ab-2a791c4c1940
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639447091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3639447091
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.334252116
Short name T87
Test name
Test status
Simulation time 838706061 ps
CPU time 26.89 seconds
Started Apr 18 02:57:23 PM PDT 24
Finished Apr 18 02:57:50 PM PDT 24
Peak memory 248928 kb
Host smart-2348e2cd-09cd-45ba-83a2-ec1ffa44fd92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33425
2116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.334252116
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3874246017
Short name T529
Test name
Test status
Simulation time 2085701898 ps
CPU time 55.16 seconds
Started Apr 18 02:57:32 PM PDT 24
Finished Apr 18 02:58:27 PM PDT 24
Peak memory 248764 kb
Host smart-c4e6b7f9-6863-4a1a-a1ef-550f39a7b598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38742
46017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3874246017
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1494049832
Short name T282
Test name
Test status
Simulation time 63610171 ps
CPU time 4.74 seconds
Started Apr 18 02:57:47 PM PDT 24
Finished Apr 18 02:57:52 PM PDT 24
Peak memory 239272 kb
Host smart-8e34c580-d79a-48d4-9f7c-afd809ded58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14940
49832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1494049832
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3108391034
Short name T515
Test name
Test status
Simulation time 528437948 ps
CPU time 9.33 seconds
Started Apr 18 02:57:23 PM PDT 24
Finished Apr 18 02:57:32 PM PDT 24
Peak memory 249036 kb
Host smart-b26f8c03-fde4-4564-9460-860707ba5f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31083
91034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3108391034
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3627388109
Short name T616
Test name
Test status
Simulation time 26372157013 ps
CPU time 1461.59 seconds
Started Apr 18 02:57:51 PM PDT 24
Finished Apr 18 03:22:13 PM PDT 24
Peak memory 297968 kb
Host smart-90276b82-ff8c-40cb-8ac7-08462708154b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627388109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3627388109
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.677078319
Short name T533
Test name
Test status
Simulation time 81215269124 ps
CPU time 7202.13 seconds
Started Apr 18 02:57:53 PM PDT 24
Finished Apr 18 04:57:56 PM PDT 24
Peak memory 339068 kb
Host smart-1e4b2135-6f86-4e6d-ad1a-e79cbe42533d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677078319 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.677078319
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1449770024
Short name T681
Test name
Test status
Simulation time 30980249821 ps
CPU time 869.42 seconds
Started Apr 18 02:58:05 PM PDT 24
Finished Apr 18 03:12:35 PM PDT 24
Peak memory 269636 kb
Host smart-d5ad911f-aab8-4a16-8919-e61146b2ee1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449770024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1449770024
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2147387088
Short name T257
Test name
Test status
Simulation time 3321228952 ps
CPU time 100.79 seconds
Started Apr 18 02:58:06 PM PDT 24
Finished Apr 18 02:59:47 PM PDT 24
Peak memory 257340 kb
Host smart-fcbccf1b-682d-4cdb-bf82-22cbca984be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21473
87088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2147387088
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.653296297
Short name T42
Test name
Test status
Simulation time 3007462662 ps
CPU time 54.44 seconds
Started Apr 18 02:58:06 PM PDT 24
Finished Apr 18 02:59:01 PM PDT 24
Peak memory 255316 kb
Host smart-921eabed-c8e6-454e-b897-744668ee8c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65329
6297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.653296297
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1217753902
Short name T285
Test name
Test status
Simulation time 13274022269 ps
CPU time 1048.82 seconds
Started Apr 18 02:58:07 PM PDT 24
Finished Apr 18 03:15:37 PM PDT 24
Peak memory 272976 kb
Host smart-efcf69b5-8e3f-446c-9a60-b8f7cbe3f733
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217753902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1217753902
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.635652730
Short name T572
Test name
Test status
Simulation time 32418788537 ps
CPU time 1722.06 seconds
Started Apr 18 02:58:06 PM PDT 24
Finished Apr 18 03:26:48 PM PDT 24
Peak memory 273704 kb
Host smart-f12a43db-e592-4f47-a8b8-22b821736ce7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635652730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.635652730
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2869697641
Short name T294
Test name
Test status
Simulation time 1544778794 ps
CPU time 14.27 seconds
Started Apr 18 02:57:57 PM PDT 24
Finished Apr 18 02:58:11 PM PDT 24
Peak memory 249108 kb
Host smart-862ed3c8-f304-48f2-914b-3431a8be1366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28696
97641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2869697641
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.821032074
Short name T383
Test name
Test status
Simulation time 1168345462 ps
CPU time 20.29 seconds
Started Apr 18 02:57:57 PM PDT 24
Finished Apr 18 02:58:18 PM PDT 24
Peak memory 256428 kb
Host smart-909fc4a5-4468-49a3-99bc-bdc030d7fb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82103
2074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.821032074
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.337577981
Short name T114
Test name
Test status
Simulation time 513159763 ps
CPU time 15.2 seconds
Started Apr 18 02:58:08 PM PDT 24
Finished Apr 18 02:58:23 PM PDT 24
Peak memory 247428 kb
Host smart-809e96a8-7b25-48fe-9cc4-f2a95b45f9c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33757
7981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.337577981
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2967468910
Short name T682
Test name
Test status
Simulation time 950664948 ps
CPU time 61.42 seconds
Started Apr 18 02:57:53 PM PDT 24
Finished Apr 18 02:58:55 PM PDT 24
Peak memory 249020 kb
Host smart-3ba937cf-3e1d-4843-9817-3e8c723732e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29674
68910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2967468910
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.4153894244
Short name T273
Test name
Test status
Simulation time 1202877253 ps
CPU time 90.98 seconds
Started Apr 18 02:58:05 PM PDT 24
Finished Apr 18 02:59:36 PM PDT 24
Peak memory 257232 kb
Host smart-6aa1fe23-d63d-4e4b-8670-dc6e112c3bab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153894244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.4153894244
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.619040372
Short name T251
Test name
Test status
Simulation time 18206188321 ps
CPU time 1025.63 seconds
Started Apr 18 02:58:06 PM PDT 24
Finished Apr 18 03:15:12 PM PDT 24
Peak memory 281920 kb
Host smart-068664f1-bb83-4c39-93ea-3ceae28b3f0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619040372 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.619040372
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2257305638
Short name T648
Test name
Test status
Simulation time 149212592471 ps
CPU time 2448.05 seconds
Started Apr 18 02:58:16 PM PDT 24
Finished Apr 18 03:39:04 PM PDT 24
Peak memory 281944 kb
Host smart-42a56048-7549-4ae6-8afc-1fa11b1c346c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257305638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2257305638
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3851524604
Short name T48
Test name
Test status
Simulation time 6493936814 ps
CPU time 195.21 seconds
Started Apr 18 02:58:19 PM PDT 24
Finished Apr 18 03:01:35 PM PDT 24
Peak memory 257000 kb
Host smart-764bba53-2709-4fb2-83e7-bb9cb9a7e493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38515
24604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3851524604
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3988990079
Short name T638
Test name
Test status
Simulation time 297012355 ps
CPU time 28.83 seconds
Started Apr 18 02:58:13 PM PDT 24
Finished Apr 18 02:58:42 PM PDT 24
Peak memory 248796 kb
Host smart-8b4d26db-7458-4e17-88d2-3898da8d1254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39889
90079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3988990079
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.252097564
Short name T695
Test name
Test status
Simulation time 14483278541 ps
CPU time 1055.76 seconds
Started Apr 18 02:58:20 PM PDT 24
Finished Apr 18 03:15:56 PM PDT 24
Peak memory 281904 kb
Host smart-8ba998eb-d841-49d8-8893-6024dc12f704
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252097564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.252097564
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1636246513
Short name T703
Test name
Test status
Simulation time 11540178897 ps
CPU time 941.91 seconds
Started Apr 18 02:58:19 PM PDT 24
Finished Apr 18 03:14:02 PM PDT 24
Peak memory 281940 kb
Host smart-77911e81-3d63-4b37-8316-4c36bac3cce6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636246513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1636246513
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.4124162660
Short name T557
Test name
Test status
Simulation time 1493966238 ps
CPU time 67.78 seconds
Started Apr 18 02:58:18 PM PDT 24
Finished Apr 18 02:59:27 PM PDT 24
Peak memory 248192 kb
Host smart-6d8f8638-03cc-4748-bcc7-37c3cb1a9385
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124162660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4124162660
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1504581377
Short name T692
Test name
Test status
Simulation time 774215410 ps
CPU time 13.53 seconds
Started Apr 18 02:58:05 PM PDT 24
Finished Apr 18 02:58:19 PM PDT 24
Peak memory 253140 kb
Host smart-5baed94a-0021-4b97-8ec1-3ea34c6a53df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15045
81377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1504581377
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3540055429
Short name T49
Test name
Test status
Simulation time 705961842 ps
CPU time 16.28 seconds
Started Apr 18 02:58:09 PM PDT 24
Finished Apr 18 02:58:26 PM PDT 24
Peak memory 255764 kb
Host smart-b3edc1ef-9ec4-46b5-836c-53427bc6d3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35400
55429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3540055429
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3570927404
Short name T675
Test name
Test status
Simulation time 1326580594 ps
CPU time 10.62 seconds
Started Apr 18 02:58:15 PM PDT 24
Finished Apr 18 02:58:26 PM PDT 24
Peak memory 254084 kb
Host smart-4c357caf-ded2-4aa8-8835-78bc3ebd9a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35709
27404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3570927404
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3690418958
Short name T366
Test name
Test status
Simulation time 1552849175 ps
CPU time 14.17 seconds
Started Apr 18 02:58:06 PM PDT 24
Finished Apr 18 02:58:21 PM PDT 24
Peak memory 249052 kb
Host smart-7e0df266-2950-48e4-b028-dab54eb990cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36904
18958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3690418958
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1121251802
Short name T495
Test name
Test status
Simulation time 31605065441 ps
CPU time 1413.46 seconds
Started Apr 18 02:58:20 PM PDT 24
Finished Apr 18 03:21:54 PM PDT 24
Peak memory 289548 kb
Host smart-b8ad2d87-1225-4270-9a86-8ab24638dd70
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121251802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1121251802
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3059632198
Short name T636
Test name
Test status
Simulation time 10920196536 ps
CPU time 640.15 seconds
Started Apr 18 02:58:34 PM PDT 24
Finished Apr 18 03:09:15 PM PDT 24
Peak memory 265612 kb
Host smart-b57dc69a-78bb-48a2-9fd4-f2e49ec76607
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059632198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3059632198
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.305062656
Short name T646
Test name
Test status
Simulation time 2317253927 ps
CPU time 114.27 seconds
Started Apr 18 02:58:31 PM PDT 24
Finished Apr 18 03:00:25 PM PDT 24
Peak memory 257296 kb
Host smart-5acd8967-d87c-4e97-9662-d1966dec8243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30506
2656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.305062656
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.4163149955
Short name T464
Test name
Test status
Simulation time 310743163 ps
CPU time 24.97 seconds
Started Apr 18 02:58:29 PM PDT 24
Finished Apr 18 02:58:55 PM PDT 24
Peak memory 255676 kb
Host smart-ce2b28b8-723a-47d9-8a12-bd3239d82cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41631
49955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4163149955
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3305611140
Short name T349
Test name
Test status
Simulation time 52872981553 ps
CPU time 2863.51 seconds
Started Apr 18 02:58:44 PM PDT 24
Finished Apr 18 03:46:28 PM PDT 24
Peak memory 289160 kb
Host smart-66f4afa8-e414-4b76-b3e6-dcbe53db1212
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305611140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3305611140
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2063160042
Short name T586
Test name
Test status
Simulation time 38215264407 ps
CPU time 2164.07 seconds
Started Apr 18 02:58:44 PM PDT 24
Finished Apr 18 03:34:49 PM PDT 24
Peak memory 273724 kb
Host smart-7c1e1ade-fa91-48f4-b8b5-c818d70dd2cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063160042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2063160042
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1856238954
Short name T608
Test name
Test status
Simulation time 19828070134 ps
CPU time 220.29 seconds
Started Apr 18 02:58:36 PM PDT 24
Finished Apr 18 03:02:17 PM PDT 24
Peak memory 248416 kb
Host smart-61b62ce1-60bc-434d-a97c-f1b111ddf35e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856238954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1856238954
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2924482101
Short name T640
Test name
Test status
Simulation time 183773906 ps
CPU time 21.86 seconds
Started Apr 18 02:58:25 PM PDT 24
Finished Apr 18 02:58:47 PM PDT 24
Peak memory 257220 kb
Host smart-25435553-52bf-4fb5-9dda-d6b5faafb61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29244
82101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2924482101
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1348914515
Short name T109
Test name
Test status
Simulation time 817675485 ps
CPU time 19.55 seconds
Started Apr 18 02:58:24 PM PDT 24
Finished Apr 18 02:58:44 PM PDT 24
Peak memory 248896 kb
Host smart-3d74c702-aeb3-4a9c-ba72-677710c9a380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13489
14515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1348914515
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2394449557
Short name T433
Test name
Test status
Simulation time 335113069 ps
CPU time 14.92 seconds
Started Apr 18 02:58:25 PM PDT 24
Finished Apr 18 02:58:40 PM PDT 24
Peak memory 249056 kb
Host smart-3ddae4dd-a29e-4e71-8e84-30fe68179eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23944
49557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2394449557
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2515468876
Short name T421
Test name
Test status
Simulation time 270210069633 ps
CPU time 3496.21 seconds
Started Apr 18 02:58:44 PM PDT 24
Finished Apr 18 03:57:01 PM PDT 24
Peak memory 306376 kb
Host smart-34a7558b-35a1-4aca-ad91-710d4dd8668a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515468876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2515468876
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1608951207
Short name T190
Test name
Test status
Simulation time 6452165693 ps
CPU time 456.91 seconds
Started Apr 18 02:58:44 PM PDT 24
Finished Apr 18 03:06:21 PM PDT 24
Peak memory 265632 kb
Host smart-d76519c8-752b-4554-9b8b-10ce5504d687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608951207 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1608951207
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1305700250
Short name T227
Test name
Test status
Simulation time 19495761 ps
CPU time 2.84 seconds
Started Apr 18 02:47:34 PM PDT 24
Finished Apr 18 02:47:37 PM PDT 24
Peak memory 249292 kb
Host smart-dd484006-149f-4dac-9f97-209812634841
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1305700250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1305700250
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2111586715
Short name T476
Test name
Test status
Simulation time 26000503023 ps
CPU time 684.43 seconds
Started Apr 18 02:47:30 PM PDT 24
Finished Apr 18 02:58:54 PM PDT 24
Peak memory 267584 kb
Host smart-6706ebd6-dd9b-4dde-a321-0377dbf6a947
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111586715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2111586715
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.912468279
Short name T488
Test name
Test status
Simulation time 3214364516 ps
CPU time 33.27 seconds
Started Apr 18 02:47:30 PM PDT 24
Finished Apr 18 02:48:03 PM PDT 24
Peak memory 249172 kb
Host smart-983c00c1-a0d6-47ad-a46d-65f480dc3cbf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=912468279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.912468279
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3139520797
Short name T412
Test name
Test status
Simulation time 6176415677 ps
CPU time 129.95 seconds
Started Apr 18 02:47:31 PM PDT 24
Finished Apr 18 02:49:41 PM PDT 24
Peak memory 257208 kb
Host smart-82b5ddfc-9999-4db6-b85f-4a44842bfa04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31395
20797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3139520797
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.430866593
Short name T690
Test name
Test status
Simulation time 2168660970 ps
CPU time 31.66 seconds
Started Apr 18 02:47:30 PM PDT 24
Finished Apr 18 02:48:02 PM PDT 24
Peak memory 249156 kb
Host smart-4d452d6e-f076-4f81-8ece-aae9a4b0c213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43086
6593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.430866593
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.824647541
Short name T406
Test name
Test status
Simulation time 31125303024 ps
CPU time 1399.98 seconds
Started Apr 18 02:47:29 PM PDT 24
Finished Apr 18 03:10:49 PM PDT 24
Peak memory 287672 kb
Host smart-47abf309-31be-49ba-b188-7d39bfb1b6c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824647541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.824647541
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.766853828
Short name T192
Test name
Test status
Simulation time 183113233602 ps
CPU time 2543.34 seconds
Started Apr 18 02:47:29 PM PDT 24
Finished Apr 18 03:29:54 PM PDT 24
Peak memory 285260 kb
Host smart-40c0d4be-e2a2-4ca1-999f-7e122ea23f4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766853828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.766853828
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1023210717
Short name T242
Test name
Test status
Simulation time 9271859792 ps
CPU time 369 seconds
Started Apr 18 02:47:29 PM PDT 24
Finished Apr 18 02:53:39 PM PDT 24
Peak memory 248196 kb
Host smart-03f39834-ec87-424c-9140-d6ee0c03b138
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023210717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1023210717
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.4084592089
Short name T399
Test name
Test status
Simulation time 1417519114 ps
CPU time 10.73 seconds
Started Apr 18 02:47:25 PM PDT 24
Finished Apr 18 02:47:36 PM PDT 24
Peak memory 249256 kb
Host smart-541d1505-75cd-4d1c-b5c4-c928e69d91bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40845
92089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.4084592089
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2403900917
Short name T380
Test name
Test status
Simulation time 94230034 ps
CPU time 3.86 seconds
Started Apr 18 02:47:31 PM PDT 24
Finished Apr 18 02:47:35 PM PDT 24
Peak memory 249920 kb
Host smart-443cc622-1126-4447-8f59-0ac5aa22c464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24039
00917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2403900917
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1769871456
Short name T34
Test name
Test status
Simulation time 842667102 ps
CPU time 24.15 seconds
Started Apr 18 02:47:33 PM PDT 24
Finished Apr 18 02:47:58 PM PDT 24
Peak memory 265732 kb
Host smart-faddcb0d-7f78-4ba2-824e-5d2c177267cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1769871456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1769871456
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2656460484
Short name T534
Test name
Test status
Simulation time 498889752 ps
CPU time 28.08 seconds
Started Apr 18 02:47:23 PM PDT 24
Finished Apr 18 02:47:52 PM PDT 24
Peak memory 255924 kb
Host smart-77c04f76-9060-439b-b369-7cfa67439432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26564
60484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2656460484
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1976407393
Short name T478
Test name
Test status
Simulation time 477398291 ps
CPU time 32.17 seconds
Started Apr 18 02:47:20 PM PDT 24
Finished Apr 18 02:47:52 PM PDT 24
Peak memory 249060 kb
Host smart-1f5c33ff-512e-4e89-b2e7-c232c2a46f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19764
07393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1976407393
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1874436023
Short name T418
Test name
Test status
Simulation time 775977987 ps
CPU time 40.8 seconds
Started Apr 18 02:47:30 PM PDT 24
Finished Apr 18 02:48:11 PM PDT 24
Peak memory 248952 kb
Host smart-1a850c75-ba83-466e-9431-6d090bd2bff8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874436023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1874436023
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2713133319
Short name T279
Test name
Test status
Simulation time 33848786920 ps
CPU time 608.83 seconds
Started Apr 18 02:47:33 PM PDT 24
Finished Apr 18 02:57:42 PM PDT 24
Peak memory 271712 kb
Host smart-b524aca2-1873-41ad-b98c-f34d5dea0374
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713133319 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2713133319
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.4289264601
Short name T585
Test name
Test status
Simulation time 121813660524 ps
CPU time 1294.23 seconds
Started Apr 18 02:58:52 PM PDT 24
Finished Apr 18 03:20:27 PM PDT 24
Peak memory 267672 kb
Host smart-5526a468-fded-40c1-b64c-0f9874c9fe6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289264601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.4289264601
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2171542897
Short name T472
Test name
Test status
Simulation time 2896489618 ps
CPU time 162.09 seconds
Started Apr 18 02:58:54 PM PDT 24
Finished Apr 18 03:01:36 PM PDT 24
Peak memory 257176 kb
Host smart-0a976794-0e61-438d-a040-198991506c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21715
42897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2171542897
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.951887287
Short name T88
Test name
Test status
Simulation time 715239282 ps
CPU time 15.25 seconds
Started Apr 18 02:58:54 PM PDT 24
Finished Apr 18 02:59:10 PM PDT 24
Peak memory 255272 kb
Host smart-1c7474d9-6c23-4c83-a5c4-3cb77b2f6487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95188
7287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.951887287
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3188966714
Short name T542
Test name
Test status
Simulation time 72983773410 ps
CPU time 2064.23 seconds
Started Apr 18 02:59:00 PM PDT 24
Finished Apr 18 03:33:24 PM PDT 24
Peak memory 273112 kb
Host smart-2d62c314-4a69-4dba-84c1-7048b72f1dc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188966714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3188966714
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.389180033
Short name T368
Test name
Test status
Simulation time 18388527518 ps
CPU time 807.32 seconds
Started Apr 18 02:58:59 PM PDT 24
Finished Apr 18 03:12:27 PM PDT 24
Peak memory 273068 kb
Host smart-8cb6aaaa-9c84-4b18-8b44-173760e5e521
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389180033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.389180033
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3977052503
Short name T9
Test name
Test status
Simulation time 14021942249 ps
CPU time 282.89 seconds
Started Apr 18 02:58:59 PM PDT 24
Finished Apr 18 03:03:43 PM PDT 24
Peak memory 248004 kb
Host smart-23e819e8-1582-48b6-b098-dcd57288be22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977052503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3977052503
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3772800910
Short name T393
Test name
Test status
Simulation time 1224890484 ps
CPU time 43.64 seconds
Started Apr 18 02:58:49 PM PDT 24
Finished Apr 18 02:59:33 PM PDT 24
Peak memory 249024 kb
Host smart-457d72e7-a292-48a2-a9af-1dd422e44d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37728
00910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3772800910
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3539257958
Short name T684
Test name
Test status
Simulation time 2251374900 ps
CPU time 64.3 seconds
Started Apr 18 02:58:53 PM PDT 24
Finished Apr 18 02:59:57 PM PDT 24
Peak memory 249540 kb
Host smart-202b1cef-ecba-464c-a182-e1b5d6c85143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35392
57958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3539257958
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1939362449
Short name T39
Test name
Test status
Simulation time 1382704801 ps
CPU time 48.05 seconds
Started Apr 18 02:58:53 PM PDT 24
Finished Apr 18 02:59:42 PM PDT 24
Peak memory 256072 kb
Host smart-48157156-3c62-415c-9868-bf831b874124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19393
62449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1939362449
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.561324793
Short name T365
Test name
Test status
Simulation time 638851804 ps
CPU time 29.73 seconds
Started Apr 18 02:58:48 PM PDT 24
Finished Apr 18 02:59:18 PM PDT 24
Peak memory 249036 kb
Host smart-a23bbce7-0ee8-4eef-8e03-31079dd28dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56132
4793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.561324793
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2138992982
Short name T120
Test name
Test status
Simulation time 45510349933 ps
CPU time 2876.17 seconds
Started Apr 18 02:58:58 PM PDT 24
Finished Apr 18 03:46:55 PM PDT 24
Peak memory 298240 kb
Host smart-8f76112a-c92d-4a6e-b792-21ca32dd4069
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138992982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2138992982
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.742045065
Short name T63
Test name
Test status
Simulation time 150699200567 ps
CPU time 3336.88 seconds
Started Apr 18 02:58:59 PM PDT 24
Finished Apr 18 03:54:36 PM PDT 24
Peak memory 322392 kb
Host smart-75dff7ef-42e6-4c98-b6f9-a5568bdc7fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742045065 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.742045065
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3455974351
Short name T457
Test name
Test status
Simulation time 37568078573 ps
CPU time 2334.32 seconds
Started Apr 18 02:59:12 PM PDT 24
Finished Apr 18 03:38:06 PM PDT 24
Peak memory 289624 kb
Host smart-c60764a8-e4ee-4cb2-a730-a0e6b91aa242
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455974351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3455974351
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2350998941
Short name T416
Test name
Test status
Simulation time 572785727 ps
CPU time 35.99 seconds
Started Apr 18 02:59:09 PM PDT 24
Finished Apr 18 02:59:45 PM PDT 24
Peak memory 255168 kb
Host smart-5e9f2395-7455-413b-b7b9-cd96423ac88e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23509
98941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2350998941
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.4230502311
Short name T392
Test name
Test status
Simulation time 2027753501 ps
CPU time 31.98 seconds
Started Apr 18 02:59:03 PM PDT 24
Finished Apr 18 02:59:36 PM PDT 24
Peak memory 254944 kb
Host smart-4fb8a283-b59c-4f02-80d2-3de867bb1873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42305
02311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.4230502311
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2442105002
Short name T297
Test name
Test status
Simulation time 35891625447 ps
CPU time 2283.3 seconds
Started Apr 18 02:59:21 PM PDT 24
Finished Apr 18 03:37:25 PM PDT 24
Peak memory 281916 kb
Host smart-a36a2fbe-ab00-4326-9a7b-0b324981ec15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442105002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2442105002
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3167837252
Short name T409
Test name
Test status
Simulation time 56125324359 ps
CPU time 704.67 seconds
Started Apr 18 02:59:19 PM PDT 24
Finished Apr 18 03:11:04 PM PDT 24
Peak memory 266760 kb
Host smart-7bf93f72-7a3c-4e78-9bbc-dafb5599651b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167837252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3167837252
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3876709113
Short name T506
Test name
Test status
Simulation time 1017026935 ps
CPU time 18.2 seconds
Started Apr 18 02:59:03 PM PDT 24
Finished Apr 18 02:59:22 PM PDT 24
Peak memory 248936 kb
Host smart-770a6d1d-46f0-4c48-aaa7-f54b404fb601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38767
09113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3876709113
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1567891324
Short name T666
Test name
Test status
Simulation time 1155303792 ps
CPU time 31.15 seconds
Started Apr 18 02:59:01 PM PDT 24
Finished Apr 18 02:59:33 PM PDT 24
Peak memory 256164 kb
Host smart-8dbca1c5-7042-40c8-b902-22aed372a118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15678
91324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1567891324
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3647976805
Short name T485
Test name
Test status
Simulation time 366505237 ps
CPU time 6.87 seconds
Started Apr 18 02:59:00 PM PDT 24
Finished Apr 18 02:59:07 PM PDT 24
Peak memory 251192 kb
Host smart-20abffbd-7bad-452a-b0c2-b9a0cf0d74d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36479
76805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3647976805
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.90828272
Short name T206
Test name
Test status
Simulation time 639405044670 ps
CPU time 4239.73 seconds
Started Apr 18 02:59:23 PM PDT 24
Finished Apr 18 04:10:04 PM PDT 24
Peak memory 355232 kb
Host smart-717d0eba-ecac-48fe-92ae-9c6ec5cab4bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90828272 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.90828272
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.759427212
Short name T256
Test name
Test status
Simulation time 7266066191 ps
CPU time 206.57 seconds
Started Apr 18 02:59:33 PM PDT 24
Finished Apr 18 03:03:00 PM PDT 24
Peak memory 250340 kb
Host smart-fb5bbae0-f01e-4818-b344-6f966eb68737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75942
7212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.759427212
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2114328278
Short name T545
Test name
Test status
Simulation time 61291402 ps
CPU time 8.88 seconds
Started Apr 18 02:59:29 PM PDT 24
Finished Apr 18 02:59:38 PM PDT 24
Peak memory 254820 kb
Host smart-68787d3a-be02-46be-a814-376cd845152e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21143
28278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2114328278
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2421734905
Short name T352
Test name
Test status
Simulation time 40010674726 ps
CPU time 1047.53 seconds
Started Apr 18 02:59:42 PM PDT 24
Finished Apr 18 03:17:10 PM PDT 24
Peak memory 269652 kb
Host smart-67d560cc-18f6-44b9-a3b7-630954d90fe7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421734905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2421734905
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3128902182
Short name T407
Test name
Test status
Simulation time 26859065650 ps
CPU time 1692.1 seconds
Started Apr 18 02:59:57 PM PDT 24
Finished Apr 18 03:28:10 PM PDT 24
Peak memory 289056 kb
Host smart-d993faa7-7af9-4f49-b899-afd070d25815
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128902182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3128902182
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.777933556
Short name T331
Test name
Test status
Simulation time 8474879146 ps
CPU time 337.78 seconds
Started Apr 18 02:59:43 PM PDT 24
Finished Apr 18 03:05:21 PM PDT 24
Peak memory 248032 kb
Host smart-3280e4d3-2e0b-4d08-8567-930fd470d23f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777933556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.777933556
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.12236089
Short name T611
Test name
Test status
Simulation time 994329688 ps
CPU time 26.56 seconds
Started Apr 18 02:59:29 PM PDT 24
Finished Apr 18 02:59:56 PM PDT 24
Peak memory 255780 kb
Host smart-dc4c6592-03b3-4877-8f4e-e1e1cf515a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12236
089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.12236089
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1260111803
Short name T56
Test name
Test status
Simulation time 270907299 ps
CPU time 10.5 seconds
Started Apr 18 02:59:29 PM PDT 24
Finished Apr 18 02:59:40 PM PDT 24
Peak memory 249348 kb
Host smart-540efb1a-67fd-46d6-a300-d665117d2ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12601
11803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1260111803
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2608834431
Short name T261
Test name
Test status
Simulation time 654338873 ps
CPU time 22.93 seconds
Started Apr 18 02:59:38 PM PDT 24
Finished Apr 18 03:00:01 PM PDT 24
Peak memory 247972 kb
Host smart-b0205946-51d3-4e48-9527-bbfeadea4d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26088
34431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2608834431
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3888350684
Short name T544
Test name
Test status
Simulation time 2410609602 ps
CPU time 68.15 seconds
Started Apr 18 02:59:29 PM PDT 24
Finished Apr 18 03:00:38 PM PDT 24
Peak memory 249072 kb
Host smart-e4f79b67-09f6-4319-80a7-5e34f3c7b3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38883
50684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3888350684
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1790443217
Short name T401
Test name
Test status
Simulation time 12378466739 ps
CPU time 1241.99 seconds
Started Apr 18 02:59:48 PM PDT 24
Finished Apr 18 03:20:30 PM PDT 24
Peak memory 281792 kb
Host smart-626840ba-84d0-47d2-87b2-227007be4b7a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790443217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1790443217
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2898858447
Short name T607
Test name
Test status
Simulation time 37807717869 ps
CPU time 1389.65 seconds
Started Apr 18 03:00:03 PM PDT 24
Finished Apr 18 03:23:13 PM PDT 24
Peak memory 267592 kb
Host smart-b1143cb1-e3fd-4dde-95b7-954bd201de87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898858447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2898858447
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3961327895
Short name T430
Test name
Test status
Simulation time 11026056531 ps
CPU time 156.43 seconds
Started Apr 18 02:59:57 PM PDT 24
Finished Apr 18 03:02:34 PM PDT 24
Peak memory 257320 kb
Host smart-b6ba6ef7-9273-428a-8749-3515f8a86561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39613
27895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3961327895
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1152498926
Short name T705
Test name
Test status
Simulation time 127591009213 ps
CPU time 1511.13 seconds
Started Apr 18 03:00:06 PM PDT 24
Finished Apr 18 03:25:18 PM PDT 24
Peak memory 273332 kb
Host smart-5bf51995-ecc6-4c0d-bca3-789b41626e7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152498926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1152498926
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1053159680
Short name T627
Test name
Test status
Simulation time 20252881103 ps
CPU time 296.59 seconds
Started Apr 18 03:00:04 PM PDT 24
Finished Apr 18 03:05:01 PM PDT 24
Peak memory 247936 kb
Host smart-1f596428-7678-4272-934a-b7f3c46c0cd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053159680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1053159680
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3938753263
Short name T479
Test name
Test status
Simulation time 104074322 ps
CPU time 10.44 seconds
Started Apr 18 02:59:57 PM PDT 24
Finished Apr 18 03:00:08 PM PDT 24
Peak memory 255936 kb
Host smart-028f1df0-4820-4ef1-a2f1-3f455302bcf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39387
53263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3938753263
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.733523024
Short name T580
Test name
Test status
Simulation time 436520513 ps
CPU time 9.25 seconds
Started Apr 18 02:59:57 PM PDT 24
Finished Apr 18 03:00:07 PM PDT 24
Peak memory 247436 kb
Host smart-3f3879eb-3a4a-44cf-b0eb-981466a7ab4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73352
3024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.733523024
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.834515495
Short name T669
Test name
Test status
Simulation time 315794495 ps
CPU time 18.84 seconds
Started Apr 18 03:00:03 PM PDT 24
Finished Apr 18 03:00:23 PM PDT 24
Peak memory 255496 kb
Host smart-cdaec4f7-1401-4b3e-bba6-93fe3e2a209c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83451
5495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.834515495
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.495357096
Short name T588
Test name
Test status
Simulation time 1610088569 ps
CPU time 48.05 seconds
Started Apr 18 02:59:57 PM PDT 24
Finished Apr 18 03:00:45 PM PDT 24
Peak memory 256736 kb
Host smart-2effdee3-8362-4ee9-84be-ade0b8f188f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49535
7096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.495357096
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3573741641
Short name T563
Test name
Test status
Simulation time 57825474683 ps
CPU time 3381.46 seconds
Started Apr 18 03:00:12 PM PDT 24
Finished Apr 18 03:56:34 PM PDT 24
Peak memory 289980 kb
Host smart-a96fae38-bc7c-49d7-95ec-a0f4996785e6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573741641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3573741641
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.224911250
Short name T122
Test name
Test status
Simulation time 58809671419 ps
CPU time 4779.05 seconds
Started Apr 18 03:00:07 PM PDT 24
Finished Apr 18 04:19:47 PM PDT 24
Peak memory 298424 kb
Host smart-7c8e1743-d28c-4224-80cc-f4a80b11b979
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224911250 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.224911250
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.176149379
Short name T35
Test name
Test status
Simulation time 9812246812 ps
CPU time 910.5 seconds
Started Apr 18 03:00:14 PM PDT 24
Finished Apr 18 03:15:26 PM PDT 24
Peak memory 284660 kb
Host smart-7c5a2082-7341-4a6e-8a06-f9f755bc06be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176149379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.176149379
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2456732653
Short name T244
Test name
Test status
Simulation time 3397255697 ps
CPU time 228.38 seconds
Started Apr 18 03:00:14 PM PDT 24
Finished Apr 18 03:04:03 PM PDT 24
Peak memory 250168 kb
Host smart-ae16d654-05a3-49fe-bfac-b5b998d6463e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24567
32653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2456732653
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2449912419
Short name T69
Test name
Test status
Simulation time 1117129499 ps
CPU time 53.18 seconds
Started Apr 18 03:00:13 PM PDT 24
Finished Apr 18 03:01:07 PM PDT 24
Peak memory 249012 kb
Host smart-fbd2949b-6b0b-4a1f-b765-3ecfb38de951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24499
12419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2449912419
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.649027893
Short name T334
Test name
Test status
Simulation time 44222428138 ps
CPU time 1214.17 seconds
Started Apr 18 03:00:18 PM PDT 24
Finished Apr 18 03:20:33 PM PDT 24
Peak memory 273500 kb
Host smart-7c582bfa-8f71-455c-adfd-f35a2bb123e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649027893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.649027893
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1215612523
Short name T353
Test name
Test status
Simulation time 30191334515 ps
CPU time 1587.37 seconds
Started Apr 18 03:00:20 PM PDT 24
Finished Apr 18 03:26:48 PM PDT 24
Peak memory 273140 kb
Host smart-cf7f1c98-a1f3-474d-bfad-8b493029666d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215612523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1215612523
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2477223630
Short name T83
Test name
Test status
Simulation time 10662654927 ps
CPU time 419.48 seconds
Started Apr 18 03:00:19 PM PDT 24
Finished Apr 18 03:07:19 PM PDT 24
Peak memory 255408 kb
Host smart-b2ef3934-a6b0-435b-8a7f-fd14c5213826
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477223630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2477223630
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2662137448
Short name T21
Test name
Test status
Simulation time 748697324 ps
CPU time 15.32 seconds
Started Apr 18 03:00:13 PM PDT 24
Finished Apr 18 03:00:29 PM PDT 24
Peak memory 256248 kb
Host smart-300005ba-e2d3-4f4d-94cf-3a515ab4b0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26621
37448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2662137448
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2832488292
Short name T548
Test name
Test status
Simulation time 548368515 ps
CPU time 15.02 seconds
Started Apr 18 03:00:15 PM PDT 24
Finished Apr 18 03:00:30 PM PDT 24
Peak memory 255644 kb
Host smart-7f660b86-5d66-4d33-863a-34d653033f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28324
88292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2832488292
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1721984731
Short name T615
Test name
Test status
Simulation time 368448377 ps
CPU time 7.3 seconds
Started Apr 18 03:00:13 PM PDT 24
Finished Apr 18 03:00:21 PM PDT 24
Peak memory 251788 kb
Host smart-1d96fff8-d200-4121-9527-bfec152c2fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17219
84731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1721984731
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2443030270
Short name T539
Test name
Test status
Simulation time 66848468 ps
CPU time 3.21 seconds
Started Apr 18 03:00:07 PM PDT 24
Finished Apr 18 03:00:10 PM PDT 24
Peak memory 240796 kb
Host smart-1f71f675-b5ec-4c28-9fdc-b771bc196013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24430
30270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2443030270
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3006988433
Short name T50
Test name
Test status
Simulation time 40534704369 ps
CPU time 2307.81 seconds
Started Apr 18 03:00:26 PM PDT 24
Finished Apr 18 03:38:55 PM PDT 24
Peak memory 285120 kb
Host smart-c68592b9-ced4-4ce4-b6df-6ceb90366e7a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006988433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3006988433
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2537808335
Short name T543
Test name
Test status
Simulation time 37205514236 ps
CPU time 2275.32 seconds
Started Apr 18 03:00:33 PM PDT 24
Finished Apr 18 03:38:29 PM PDT 24
Peak memory 273252 kb
Host smart-1b613981-6f2a-423f-bf42-f6ddf86d521a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537808335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2537808335
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.285244357
Short name T610
Test name
Test status
Simulation time 3295664426 ps
CPU time 38.39 seconds
Started Apr 18 03:00:29 PM PDT 24
Finished Apr 18 03:01:08 PM PDT 24
Peak memory 256632 kb
Host smart-29d88238-40ed-4c13-978e-2512239582fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28524
4357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.285244357
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3174574684
Short name T345
Test name
Test status
Simulation time 477267503902 ps
CPU time 2268.59 seconds
Started Apr 18 03:00:48 PM PDT 24
Finished Apr 18 03:38:37 PM PDT 24
Peak memory 289136 kb
Host smart-2851aa1d-4669-4a92-8517-e33997dd746d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174574684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3174574684
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2816926059
Short name T668
Test name
Test status
Simulation time 69311365217 ps
CPU time 1207.6 seconds
Started Apr 18 03:00:49 PM PDT 24
Finished Apr 18 03:20:57 PM PDT 24
Peak memory 287952 kb
Host smart-5022f0cf-1c9b-4c2e-9996-c8513a201b8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816926059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2816926059
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2966843948
Short name T414
Test name
Test status
Simulation time 605985385 ps
CPU time 27.53 seconds
Started Apr 18 03:00:26 PM PDT 24
Finished Apr 18 03:00:54 PM PDT 24
Peak memory 249020 kb
Host smart-ca164004-1cd3-40e2-ada0-97ac2b5e88af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29668
43948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2966843948
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1011770578
Short name T84
Test name
Test status
Simulation time 82908081 ps
CPU time 6.86 seconds
Started Apr 18 03:00:28 PM PDT 24
Finished Apr 18 03:00:36 PM PDT 24
Peak memory 249848 kb
Host smart-3a6f67f6-54ff-485b-aefb-1c43786ae911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10117
70578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1011770578
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.903280856
Short name T62
Test name
Test status
Simulation time 815579046 ps
CPU time 10.03 seconds
Started Apr 18 03:00:37 PM PDT 24
Finished Apr 18 03:00:47 PM PDT 24
Peak memory 248996 kb
Host smart-aec1becc-b438-4acb-bad5-f3d2b6b2071f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90328
0856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.903280856
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.676047281
Short name T510
Test name
Test status
Simulation time 4646590797 ps
CPU time 301.91 seconds
Started Apr 18 03:00:49 PM PDT 24
Finished Apr 18 03:05:51 PM PDT 24
Peak memory 257280 kb
Host smart-25b6b0d9-3fc5-435a-9c86-0ab2ab635e53
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676047281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.676047281
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.684557362
Short name T305
Test name
Test status
Simulation time 8296890076 ps
CPU time 719.92 seconds
Started Apr 18 03:00:54 PM PDT 24
Finished Apr 18 03:12:54 PM PDT 24
Peak memory 269712 kb
Host smart-219ef628-2056-4543-8137-148a9beda97b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684557362 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.684557362
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2115641662
Short name T613
Test name
Test status
Simulation time 225826926185 ps
CPU time 3482.71 seconds
Started Apr 18 03:01:12 PM PDT 24
Finished Apr 18 03:59:16 PM PDT 24
Peak memory 289680 kb
Host smart-a5b0c6e8-4918-4f10-942a-eecd95a10146
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115641662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2115641662
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1783297836
Short name T634
Test name
Test status
Simulation time 318639508 ps
CPU time 19.75 seconds
Started Apr 18 03:01:12 PM PDT 24
Finished Apr 18 03:01:33 PM PDT 24
Peak memory 249056 kb
Host smart-5f5dcb4b-6d78-43d5-8e80-c95d0c91a30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17832
97836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1783297836
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3372419598
Short name T445
Test name
Test status
Simulation time 265205990 ps
CPU time 8.44 seconds
Started Apr 18 03:01:04 PM PDT 24
Finished Apr 18 03:01:13 PM PDT 24
Peak memory 247568 kb
Host smart-d46629e9-28b6-45a7-9684-132af4d289aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33724
19598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3372419598
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.538244646
Short name T338
Test name
Test status
Simulation time 24180922819 ps
CPU time 1408.45 seconds
Started Apr 18 03:01:19 PM PDT 24
Finished Apr 18 03:24:48 PM PDT 24
Peak memory 270248 kb
Host smart-a50a6e76-b9ff-41ba-91ea-1aa715fd7f0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538244646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.538244646
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2516559767
Short name T119
Test name
Test status
Simulation time 30911336409 ps
CPU time 1866.24 seconds
Started Apr 18 03:01:24 PM PDT 24
Finished Apr 18 03:32:30 PM PDT 24
Peak memory 283440 kb
Host smart-a6cdf94b-17ec-4284-ae2c-3d82c5271bc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516559767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2516559767
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1770865177
Short name T486
Test name
Test status
Simulation time 11250691172 ps
CPU time 205.02 seconds
Started Apr 18 03:01:16 PM PDT 24
Finished Apr 18 03:04:42 PM PDT 24
Peak memory 248272 kb
Host smart-538ce16b-d5e6-40b2-8184-622fc116238b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770865177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1770865177
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2719963259
Short name T624
Test name
Test status
Simulation time 747164695 ps
CPU time 24.5 seconds
Started Apr 18 03:01:04 PM PDT 24
Finished Apr 18 03:01:29 PM PDT 24
Peak memory 249052 kb
Host smart-0fc25218-19bc-4016-bae8-a803ddbc913a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27199
63259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2719963259
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.804011253
Short name T309
Test name
Test status
Simulation time 248530600 ps
CPU time 29.97 seconds
Started Apr 18 03:01:04 PM PDT 24
Finished Apr 18 03:01:34 PM PDT 24
Peak memory 247544 kb
Host smart-58b3dea9-6c6e-4fae-aa7b-37ad4c857cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80401
1253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.804011253
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3082670043
Short name T558
Test name
Test status
Simulation time 683056467 ps
CPU time 41.85 seconds
Started Apr 18 03:01:11 PM PDT 24
Finished Apr 18 03:01:53 PM PDT 24
Peak memory 254992 kb
Host smart-9b70819c-f217-4f1d-86cb-086285516f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30826
70043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3082670043
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3035240738
Short name T448
Test name
Test status
Simulation time 772676038 ps
CPU time 51.18 seconds
Started Apr 18 03:01:04 PM PDT 24
Finished Apr 18 03:01:56 PM PDT 24
Peak memory 249040 kb
Host smart-fecabec2-fe8d-47cb-a7fb-5f702b862bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30352
40738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3035240738
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1985567418
Short name T55
Test name
Test status
Simulation time 25908754310 ps
CPU time 1289.85 seconds
Started Apr 18 03:01:45 PM PDT 24
Finished Apr 18 03:23:15 PM PDT 24
Peak memory 290120 kb
Host smart-1326d0f3-2d62-45e9-a929-5bc107b421cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985567418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1985567418
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3871396321
Short name T574
Test name
Test status
Simulation time 2986177580 ps
CPU time 124.53 seconds
Started Apr 18 03:01:39 PM PDT 24
Finished Apr 18 03:03:44 PM PDT 24
Peak memory 257028 kb
Host smart-e1760267-1524-4695-a721-17a019ff12d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38713
96321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3871396321
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2951548296
Short name T535
Test name
Test status
Simulation time 474851665 ps
CPU time 24.28 seconds
Started Apr 18 03:01:39 PM PDT 24
Finished Apr 18 03:02:03 PM PDT 24
Peak memory 249048 kb
Host smart-0e3e8b80-f62c-457e-a9b0-0b8c1ff68ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29515
48296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2951548296
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.986302877
Short name T342
Test name
Test status
Simulation time 41538324118 ps
CPU time 2278.17 seconds
Started Apr 18 03:01:51 PM PDT 24
Finished Apr 18 03:39:50 PM PDT 24
Peak memory 271660 kb
Host smart-f15c29d2-a8f8-447b-92fd-df3309756ae1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986302877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.986302877
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2225672413
Short name T531
Test name
Test status
Simulation time 95547255123 ps
CPU time 3404.32 seconds
Started Apr 18 03:01:56 PM PDT 24
Finished Apr 18 03:58:41 PM PDT 24
Peak memory 281280 kb
Host smart-e2adc275-27bc-4162-b802-d4df55cf3791
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225672413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2225672413
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.4151461502
Short name T326
Test name
Test status
Simulation time 31647769441 ps
CPU time 341.72 seconds
Started Apr 18 03:01:51 PM PDT 24
Finished Apr 18 03:07:33 PM PDT 24
Peak memory 248200 kb
Host smart-e199dbc5-a91d-4147-b179-0b0c4b40c0df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151461502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.4151461502
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1927155470
Short name T370
Test name
Test status
Simulation time 1317898782 ps
CPU time 33.14 seconds
Started Apr 18 03:01:32 PM PDT 24
Finished Apr 18 03:02:05 PM PDT 24
Peak memory 248996 kb
Host smart-45851cc3-1b22-44a4-821e-ac1a64a17d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19271
55470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1927155470
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.637720097
Short name T504
Test name
Test status
Simulation time 214006917 ps
CPU time 22.63 seconds
Started Apr 18 03:01:39 PM PDT 24
Finished Apr 18 03:02:02 PM PDT 24
Peak memory 254872 kb
Host smart-30b58701-2e42-4514-bf3e-f56cc83c6f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63772
0097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.637720097
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1588642721
Short name T17
Test name
Test status
Simulation time 393551392 ps
CPU time 25.26 seconds
Started Apr 18 03:01:45 PM PDT 24
Finished Apr 18 03:02:11 PM PDT 24
Peak memory 247472 kb
Host smart-af371a5b-78df-4a1e-910d-dae4dfdee801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15886
42721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1588642721
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1084199702
Short name T451
Test name
Test status
Simulation time 997775468 ps
CPU time 14.82 seconds
Started Apr 18 03:01:35 PM PDT 24
Finished Apr 18 03:01:50 PM PDT 24
Peak memory 249232 kb
Host smart-79054302-eb24-4366-8072-fb5b3365dc2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10841
99702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1084199702
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.887179567
Short name T123
Test name
Test status
Simulation time 323456734935 ps
CPU time 1739.62 seconds
Started Apr 18 03:02:02 PM PDT 24
Finished Apr 18 03:31:02 PM PDT 24
Peak memory 289760 kb
Host smart-919127b2-603c-462f-a5f5-4694cecdee5c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887179567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.887179567
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.4087135429
Short name T110
Test name
Test status
Simulation time 256259827476 ps
CPU time 5903.59 seconds
Started Apr 18 03:02:03 PM PDT 24
Finished Apr 18 04:40:28 PM PDT 24
Peak memory 347400 kb
Host smart-495b40c1-f997-423c-a9fc-1943e3b4e7e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087135429 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.4087135429
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.20554275
Short name T387
Test name
Test status
Simulation time 68204781415 ps
CPU time 2033.55 seconds
Started Apr 18 03:02:16 PM PDT 24
Finished Apr 18 03:36:10 PM PDT 24
Peak memory 272340 kb
Host smart-788a30ec-14ee-42ae-ac65-3bcd3bf68e95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20554275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.20554275
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.419194412
Short name T694
Test name
Test status
Simulation time 618745583 ps
CPU time 58.12 seconds
Started Apr 18 03:02:10 PM PDT 24
Finished Apr 18 03:03:08 PM PDT 24
Peak memory 249060 kb
Host smart-09de64d1-2e60-4503-8043-c697fdd0d0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41919
4412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.419194412
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3284434994
Short name T431
Test name
Test status
Simulation time 1885158835 ps
CPU time 7.72 seconds
Started Apr 18 03:02:09 PM PDT 24
Finished Apr 18 03:02:17 PM PDT 24
Peak memory 249796 kb
Host smart-73f43a2b-2809-472c-a203-c9f85f8c67a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32844
34994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3284434994
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3630458897
Short name T312
Test name
Test status
Simulation time 14485874928 ps
CPU time 1121.23 seconds
Started Apr 18 03:02:17 PM PDT 24
Finished Apr 18 03:20:58 PM PDT 24
Peak memory 272072 kb
Host smart-a0aedb66-5668-4946-8eb7-48fe1d56ff0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630458897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3630458897
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3936605965
Short name T612
Test name
Test status
Simulation time 18680196397 ps
CPU time 1562.68 seconds
Started Apr 18 03:02:21 PM PDT 24
Finished Apr 18 03:28:24 PM PDT 24
Peak memory 289420 kb
Host smart-b2e94f44-8f9f-430e-86e8-f097e895198e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936605965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3936605965
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2019046485
Short name T91
Test name
Test status
Simulation time 6086230707 ps
CPU time 230 seconds
Started Apr 18 03:02:15 PM PDT 24
Finished Apr 18 03:06:05 PM PDT 24
Peak memory 248192 kb
Host smart-8fb285a8-2c4f-4d7d-a196-10d9e973c655
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019046485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2019046485
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1534518750
Short name T672
Test name
Test status
Simulation time 473884436 ps
CPU time 14.65 seconds
Started Apr 18 03:02:10 PM PDT 24
Finished Apr 18 03:02:25 PM PDT 24
Peak memory 249060 kb
Host smart-a090e272-597a-42c5-84cf-5c011bc53fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15345
18750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1534518750
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2955944443
Short name T549
Test name
Test status
Simulation time 2202101891 ps
CPU time 29.77 seconds
Started Apr 18 03:02:16 PM PDT 24
Finished Apr 18 03:02:47 PM PDT 24
Peak memory 257324 kb
Host smart-faa8f772-a0ce-4b6a-b1d8-d6ea59957723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29559
44443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2955944443
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3685492965
Short name T369
Test name
Test status
Simulation time 4774304811 ps
CPU time 30 seconds
Started Apr 18 03:02:09 PM PDT 24
Finished Apr 18 03:02:39 PM PDT 24
Peak memory 248116 kb
Host smart-dbd13008-5a66-41ff-9b77-8ad1189ba9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36854
92965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3685492965
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2187617250
Short name T704
Test name
Test status
Simulation time 505737378 ps
CPU time 14.48 seconds
Started Apr 18 03:02:03 PM PDT 24
Finished Apr 18 03:02:17 PM PDT 24
Peak memory 256560 kb
Host smart-d17758ac-a224-4eb6-be45-fd143d0ec656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21876
17250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2187617250
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.163264828
Short name T561
Test name
Test status
Simulation time 2508967622 ps
CPU time 134.21 seconds
Started Apr 18 03:02:28 PM PDT 24
Finished Apr 18 03:04:42 PM PDT 24
Peak memory 255844 kb
Host smart-cce7e4c5-7af3-40c9-82c7-6bbb8d752506
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163264828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.163264828
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.386486342
Short name T686
Test name
Test status
Simulation time 17701808761 ps
CPU time 813.29 seconds
Started Apr 18 03:02:40 PM PDT 24
Finished Apr 18 03:16:14 PM PDT 24
Peak memory 266592 kb
Host smart-8ff4488a-8154-44cd-a8be-08a777a6b85d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386486342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.386486342
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3457505001
Short name T649
Test name
Test status
Simulation time 569421335 ps
CPU time 10.2 seconds
Started Apr 18 03:02:39 PM PDT 24
Finished Apr 18 03:02:49 PM PDT 24
Peak memory 248868 kb
Host smart-b17e4457-ab6c-4fa3-8af8-a58a577dd2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34575
05001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3457505001
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2297914342
Short name T536
Test name
Test status
Simulation time 458757050 ps
CPU time 17.29 seconds
Started Apr 18 03:02:34 PM PDT 24
Finished Apr 18 03:02:52 PM PDT 24
Peak memory 248920 kb
Host smart-ad4b47a1-d1a2-44fb-9d09-0eaa9e7b0a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22979
14342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2297914342
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1364283149
Short name T337
Test name
Test status
Simulation time 321331604495 ps
CPU time 2291.44 seconds
Started Apr 18 03:02:42 PM PDT 24
Finished Apr 18 03:40:54 PM PDT 24
Peak memory 289104 kb
Host smart-5a47887c-2388-400b-8e4d-3a297c6438d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364283149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1364283149
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3676577713
Short name T578
Test name
Test status
Simulation time 18881606711 ps
CPU time 1153.99 seconds
Started Apr 18 03:02:39 PM PDT 24
Finished Apr 18 03:21:54 PM PDT 24
Peak memory 273480 kb
Host smart-163e3a37-675f-4065-a204-357d01d14f53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676577713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3676577713
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3175190887
Short name T605
Test name
Test status
Simulation time 11310921557 ps
CPU time 514.11 seconds
Started Apr 18 03:02:39 PM PDT 24
Finished Apr 18 03:11:13 PM PDT 24
Peak memory 248140 kb
Host smart-d3bca2c7-bef6-49f4-8f1a-191f09fdbb8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175190887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3175190887
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.969976503
Short name T592
Test name
Test status
Simulation time 401945434 ps
CPU time 46.36 seconds
Started Apr 18 03:02:35 PM PDT 24
Finished Apr 18 03:03:21 PM PDT 24
Peak memory 249032 kb
Host smart-d755de06-27cc-4389-956a-7f8e01708842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96997
6503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.969976503
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3164285628
Short name T639
Test name
Test status
Simulation time 817997295 ps
CPU time 29.07 seconds
Started Apr 18 03:02:34 PM PDT 24
Finished Apr 18 03:03:04 PM PDT 24
Peak memory 249444 kb
Host smart-43fe51b4-8d64-4770-ad3f-bbb84996767f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31642
85628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3164285628
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3050811142
Short name T272
Test name
Test status
Simulation time 158550731 ps
CPU time 20.37 seconds
Started Apr 18 03:02:39 PM PDT 24
Finished Apr 18 03:03:00 PM PDT 24
Peak memory 247584 kb
Host smart-4f239ec1-7a5d-4469-992a-77f7c856cc51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30508
11142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3050811142
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.4164530702
Short name T496
Test name
Test status
Simulation time 257346056 ps
CPU time 6.92 seconds
Started Apr 18 03:02:34 PM PDT 24
Finished Apr 18 03:02:41 PM PDT 24
Peak memory 249060 kb
Host smart-246e801c-65a2-4a19-aa59-1af6fd7398ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41645
30702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.4164530702
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1356997724
Short name T593
Test name
Test status
Simulation time 169398915 ps
CPU time 17.39 seconds
Started Apr 18 03:02:39 PM PDT 24
Finished Apr 18 03:02:57 PM PDT 24
Peak memory 255448 kb
Host smart-d4343049-f2e1-42e7-8e18-2e248b8a37d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356997724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1356997724
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.357625383
Short name T124
Test name
Test status
Simulation time 133577439729 ps
CPU time 2053.76 seconds
Started Apr 18 03:02:46 PM PDT 24
Finished Apr 18 03:37:01 PM PDT 24
Peak memory 290248 kb
Host smart-0e4bbd20-fa60-4ae7-8b94-6d2524c59b32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357625383 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.357625383
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2029319251
Short name T219
Test name
Test status
Simulation time 21926058 ps
CPU time 3.1 seconds
Started Apr 18 02:48:11 PM PDT 24
Finished Apr 18 02:48:15 PM PDT 24
Peak memory 249304 kb
Host smart-d4967da2-7b59-41c9-bfc1-a6c9442cefc5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2029319251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2029319251
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.4215755500
Short name T635
Test name
Test status
Simulation time 182960386014 ps
CPU time 2542.88 seconds
Started Apr 18 02:47:44 PM PDT 24
Finished Apr 18 03:30:08 PM PDT 24
Peak memory 283900 kb
Host smart-3f9d46dc-3034-49bc-85e9-dc1bae3b9cbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215755500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.4215755500
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1301688097
Short name T631
Test name
Test status
Simulation time 175528814 ps
CPU time 11.27 seconds
Started Apr 18 02:47:48 PM PDT 24
Finished Apr 18 02:48:00 PM PDT 24
Peak memory 252736 kb
Host smart-40b9abaa-efa5-4ee4-b8ac-842f8c922caa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1301688097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1301688097
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3009709970
Short name T523
Test name
Test status
Simulation time 1090427184 ps
CPU time 20.39 seconds
Started Apr 18 02:47:40 PM PDT 24
Finished Apr 18 02:48:00 PM PDT 24
Peak memory 256144 kb
Host smart-70a2f655-0f5b-4545-aede-0e7f6da843fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30097
09970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3009709970
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3124026106
Short name T528
Test name
Test status
Simulation time 638419073 ps
CPU time 21.68 seconds
Started Apr 18 02:47:38 PM PDT 24
Finished Apr 18 02:48:00 PM PDT 24
Peak memory 255656 kb
Host smart-e6ca6667-a671-41d6-b74d-8acdc65dcb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31240
26106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3124026106
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1792635
Short name T310
Test name
Test status
Simulation time 36391184994 ps
CPU time 2160.33 seconds
Started Apr 18 02:47:43 PM PDT 24
Finished Apr 18 03:23:44 PM PDT 24
Peak memory 289200 kb
Host smart-597beb7b-bd08-443d-a842-73996c2d49f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1792635
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1996063271
Short name T575
Test name
Test status
Simulation time 97903209468 ps
CPU time 1807.89 seconds
Started Apr 18 02:47:50 PM PDT 24
Finished Apr 18 03:17:58 PM PDT 24
Peak memory 282968 kb
Host smart-252c8024-664e-4e3f-89a2-5a37e0764f84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996063271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1996063271
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.4047844564
Short name T333
Test name
Test status
Simulation time 1634177766 ps
CPU time 68.01 seconds
Started Apr 18 02:47:44 PM PDT 24
Finished Apr 18 02:48:52 PM PDT 24
Peak memory 248200 kb
Host smart-4a559fc2-6ea1-405c-82e1-4654a97a997a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047844564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.4047844564
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1687673664
Short name T628
Test name
Test status
Simulation time 449374083 ps
CPU time 14.72 seconds
Started Apr 18 02:47:33 PM PDT 24
Finished Apr 18 02:47:48 PM PDT 24
Peak memory 249072 kb
Host smart-1e8be43f-bd75-43ef-be94-f2d41d14cbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16876
73664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1687673664
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.4177916056
Short name T453
Test name
Test status
Simulation time 980004207 ps
CPU time 23.56 seconds
Started Apr 18 02:47:33 PM PDT 24
Finished Apr 18 02:47:57 PM PDT 24
Peak memory 248964 kb
Host smart-35a75066-5a4e-4ddf-923d-0f685b87dc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41779
16056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.4177916056
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.829829643
Short name T626
Test name
Test status
Simulation time 453941640 ps
CPU time 23.83 seconds
Started Apr 18 02:47:38 PM PDT 24
Finished Apr 18 02:48:02 PM PDT 24
Peak memory 254552 kb
Host smart-1a63db7e-b264-4641-8bd8-e8eef888a961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82982
9643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.829829643
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1544846077
Short name T287
Test name
Test status
Simulation time 262177352 ps
CPU time 14.88 seconds
Started Apr 18 02:47:35 PM PDT 24
Finished Apr 18 02:47:50 PM PDT 24
Peak memory 249056 kb
Host smart-1e80e6b4-2e6f-42f9-823c-6a0c7b0eae27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15448
46077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1544846077
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1600883177
Short name T275
Test name
Test status
Simulation time 114656479217 ps
CPU time 1643.3 seconds
Started Apr 18 02:47:50 PM PDT 24
Finished Apr 18 03:15:14 PM PDT 24
Peak memory 281896 kb
Host smart-2c3f9ee1-22f8-4f2b-9cd4-23909bb69ca2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600883177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1600883177
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.857593531
Short name T221
Test name
Test status
Simulation time 46374842 ps
CPU time 3.95 seconds
Started Apr 18 02:48:09 PM PDT 24
Finished Apr 18 02:48:13 PM PDT 24
Peak memory 249252 kb
Host smart-a1bfb49a-8db5-4c88-8f33-aece16aa6c2e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=857593531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.857593531
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.718376079
Short name T699
Test name
Test status
Simulation time 50106686661 ps
CPU time 1782.36 seconds
Started Apr 18 02:47:59 PM PDT 24
Finished Apr 18 03:17:41 PM PDT 24
Peak memory 273000 kb
Host smart-6ca8b396-2428-4825-b4af-2d79420b3ff2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718376079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.718376079
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.947181284
Short name T375
Test name
Test status
Simulation time 159256490 ps
CPU time 8.32 seconds
Started Apr 18 02:48:03 PM PDT 24
Finished Apr 18 02:48:12 PM PDT 24
Peak memory 240848 kb
Host smart-69dd61d9-d68e-4e97-a0a1-47dcc150673e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=947181284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.947181284
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1093203430
Short name T417
Test name
Test status
Simulation time 473110492 ps
CPU time 45.16 seconds
Started Apr 18 02:47:57 PM PDT 24
Finished Apr 18 02:48:42 PM PDT 24
Peak memory 248620 kb
Host smart-11266b45-c1e5-4c48-b55b-8fb4ccc32073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10932
03430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1093203430
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.143426383
Short name T468
Test name
Test status
Simulation time 194635678 ps
CPU time 9.38 seconds
Started Apr 18 02:47:57 PM PDT 24
Finished Apr 18 02:48:06 PM PDT 24
Peak memory 253120 kb
Host smart-5de36ef9-cfc8-447e-b74c-dbf5c63ab61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14342
6383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.143426383
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1343631650
Short name T336
Test name
Test status
Simulation time 43968892055 ps
CPU time 1117.17 seconds
Started Apr 18 02:48:03 PM PDT 24
Finished Apr 18 03:06:41 PM PDT 24
Peak memory 284960 kb
Host smart-feab4a72-61c7-4593-b8cc-0b06ff2856e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343631650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1343631650
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1410614342
Short name T394
Test name
Test status
Simulation time 195505135644 ps
CPU time 1867.97 seconds
Started Apr 18 02:48:03 PM PDT 24
Finished Apr 18 03:19:12 PM PDT 24
Peak memory 273224 kb
Host smart-bac5b0dc-ca5b-4de0-80bd-35ec7a5c368e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410614342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1410614342
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1688400009
Short name T54
Test name
Test status
Simulation time 1620577861 ps
CPU time 26.04 seconds
Started Apr 18 02:47:56 PM PDT 24
Finished Apr 18 02:48:22 PM PDT 24
Peak memory 257236 kb
Host smart-c761b9bc-209d-43b7-9d4a-4ed9ba14917d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16884
00009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1688400009
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2330785622
Short name T442
Test name
Test status
Simulation time 5120614463 ps
CPU time 26.25 seconds
Started Apr 18 02:47:52 PM PDT 24
Finished Apr 18 02:48:19 PM PDT 24
Peak memory 247416 kb
Host smart-27664a3a-e370-4dd5-a9a5-d288f20a8d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23307
85622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2330785622
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3799494427
Short name T60
Test name
Test status
Simulation time 299635777 ps
CPU time 33.39 seconds
Started Apr 18 02:47:57 PM PDT 24
Finished Apr 18 02:48:31 PM PDT 24
Peak memory 247892 kb
Host smart-884dbba0-35d7-4cfc-8984-1ce75df6e79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37994
94427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3799494427
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3591013680
Short name T372
Test name
Test status
Simulation time 2565151785 ps
CPU time 34.35 seconds
Started Apr 18 02:47:54 PM PDT 24
Finished Apr 18 02:48:28 PM PDT 24
Peak memory 249196 kb
Host smart-4cce9f13-bec9-4cd3-a479-4fe9f621e4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35910
13680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3591013680
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3097970203
Short name T579
Test name
Test status
Simulation time 115604934810 ps
CPU time 1694.26 seconds
Started Apr 18 02:48:10 PM PDT 24
Finished Apr 18 03:16:24 PM PDT 24
Peak memory 273440 kb
Host smart-152480ce-4fc8-4458-8c82-4de7ea950bbd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097970203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3097970203
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.4158289289
Short name T216
Test name
Test status
Simulation time 14862770 ps
CPU time 2.22 seconds
Started Apr 18 02:48:19 PM PDT 24
Finished Apr 18 02:48:21 PM PDT 24
Peak memory 249288 kb
Host smart-7235ab95-b35a-4802-a622-5e93cef990b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4158289289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.4158289289
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2100140466
Short name T66
Test name
Test status
Simulation time 12782373225 ps
CPU time 1667.76 seconds
Started Apr 18 02:48:51 PM PDT 24
Finished Apr 18 03:16:40 PM PDT 24
Peak memory 289604 kb
Host smart-bdf341e9-4a11-4679-a6ad-5a9c6e7ac263
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100140466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2100140466
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2272641366
Short name T440
Test name
Test status
Simulation time 377776499 ps
CPU time 19 seconds
Started Apr 18 02:48:19 PM PDT 24
Finished Apr 18 02:48:38 PM PDT 24
Peak memory 240860 kb
Host smart-87ee7ffe-61fb-43a6-9879-fb0e28d1890a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2272641366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2272641366
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3050357595
Short name T245
Test name
Test status
Simulation time 14569977510 ps
CPU time 260.59 seconds
Started Apr 18 02:48:15 PM PDT 24
Finished Apr 18 02:52:36 PM PDT 24
Peak memory 257332 kb
Host smart-cdc9c6cc-78a9-40a4-bd93-be2068de5742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30503
57595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3050357595
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3882293822
Short name T679
Test name
Test status
Simulation time 245584036 ps
CPU time 26.86 seconds
Started Apr 18 02:48:14 PM PDT 24
Finished Apr 18 02:48:41 PM PDT 24
Peak memory 249064 kb
Host smart-2b61a823-10cc-4d93-abf7-5d3d262e5f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38822
93822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3882293822
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2630508497
Short name T463
Test name
Test status
Simulation time 47251669331 ps
CPU time 2721.55 seconds
Started Apr 18 02:48:20 PM PDT 24
Finished Apr 18 03:33:42 PM PDT 24
Peak memory 289988 kb
Host smart-80a04aa7-ee0b-49c1-9439-24e2b020eb79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630508497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2630508497
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1731081886
Short name T606
Test name
Test status
Simulation time 228847664251 ps
CPU time 3366.55 seconds
Started Apr 18 02:48:20 PM PDT 24
Finished Apr 18 03:44:27 PM PDT 24
Peak memory 281840 kb
Host smart-b625a90e-1344-467b-a532-97c8e317b6d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731081886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1731081886
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3430492065
Short name T27
Test name
Test status
Simulation time 23458152682 ps
CPU time 247.66 seconds
Started Apr 18 02:48:14 PM PDT 24
Finished Apr 18 02:52:22 PM PDT 24
Peak memory 248080 kb
Host smart-fcfdf6e8-1a56-4348-a3b4-d009de280433
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430492065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3430492065
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2121879142
Short name T427
Test name
Test status
Simulation time 239117299 ps
CPU time 20.94 seconds
Started Apr 18 02:48:08 PM PDT 24
Finished Apr 18 02:48:30 PM PDT 24
Peak memory 249036 kb
Host smart-44cbdfb2-8455-42c3-af45-fddff205a6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21218
79142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2121879142
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4180560651
Short name T289
Test name
Test status
Simulation time 12538244622 ps
CPU time 39.4 seconds
Started Apr 18 02:48:09 PM PDT 24
Finished Apr 18 02:48:49 PM PDT 24
Peak memory 249116 kb
Host smart-3f05d9e1-f265-4e16-ada4-959b219248dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41805
60651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4180560651
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1912397236
Short name T632
Test name
Test status
Simulation time 521417449 ps
CPU time 33.28 seconds
Started Apr 18 02:48:16 PM PDT 24
Finished Apr 18 02:48:49 PM PDT 24
Peak memory 247880 kb
Host smart-41cad9b4-41c6-4218-83ca-fa272bc943ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19123
97236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1912397236
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3719180817
Short name T530
Test name
Test status
Simulation time 2920178328 ps
CPU time 19.32 seconds
Started Apr 18 02:48:10 PM PDT 24
Finished Apr 18 02:48:30 PM PDT 24
Peak memory 248300 kb
Host smart-66f21357-aa03-49ab-8c35-d243ef512793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37191
80817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3719180817
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3978566188
Short name T443
Test name
Test status
Simulation time 6379975922 ps
CPU time 263.22 seconds
Started Apr 18 02:48:18 PM PDT 24
Finished Apr 18 02:52:42 PM PDT 24
Peak memory 255524 kb
Host smart-cb8c23dd-e0da-49ed-8e4e-2fd10fd8997c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978566188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3978566188
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.19104567
Short name T51
Test name
Test status
Simulation time 386041406850 ps
CPU time 8060.12 seconds
Started Apr 18 02:48:23 PM PDT 24
Finished Apr 18 05:02:44 PM PDT 24
Peak memory 322952 kb
Host smart-9278da95-a4d7-40c5-88dd-60aec85e4e14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19104567 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.19104567
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2175127078
Short name T209
Test name
Test status
Simulation time 150402401 ps
CPU time 3.18 seconds
Started Apr 18 02:48:35 PM PDT 24
Finished Apr 18 02:48:39 PM PDT 24
Peak memory 249324 kb
Host smart-a2abd9d6-9ea3-48d4-bf14-d3219b1e5133
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2175127078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2175127078
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1972352878
Short name T656
Test name
Test status
Simulation time 100466808874 ps
CPU time 3342.55 seconds
Started Apr 18 02:48:35 PM PDT 24
Finished Apr 18 03:44:18 PM PDT 24
Peak memory 289236 kb
Host smart-e82588b8-72cf-4ade-a7ec-00990df68844
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972352878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1972352878
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1194138705
Short name T673
Test name
Test status
Simulation time 1961337856 ps
CPU time 41.66 seconds
Started Apr 18 02:48:34 PM PDT 24
Finished Apr 18 02:49:16 PM PDT 24
Peak memory 240788 kb
Host smart-7f0518e4-9a1b-469f-820b-92fa05906f4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1194138705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1194138705
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1348360326
Short name T524
Test name
Test status
Simulation time 7338236920 ps
CPU time 142.53 seconds
Started Apr 18 02:48:29 PM PDT 24
Finished Apr 18 02:50:52 PM PDT 24
Peak memory 257048 kb
Host smart-520741bc-ee3d-42b3-8710-7686d433c058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13483
60326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1348360326
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.725481416
Short name T408
Test name
Test status
Simulation time 316274870 ps
CPU time 28.75 seconds
Started Apr 18 02:48:24 PM PDT 24
Finished Apr 18 02:48:53 PM PDT 24
Peak memory 255744 kb
Host smart-e2fc65be-eee6-494b-a21e-acce5e9cc6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72548
1416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.725481416
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.146678313
Short name T347
Test name
Test status
Simulation time 136335475808 ps
CPU time 1933.29 seconds
Started Apr 18 02:48:34 PM PDT 24
Finished Apr 18 03:20:48 PM PDT 24
Peak memory 270660 kb
Host smart-3b68cbe9-16d2-4697-9cbf-87d632d8a932
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146678313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.146678313
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1457871266
Short name T126
Test name
Test status
Simulation time 52011418683 ps
CPU time 1713.97 seconds
Started Apr 18 02:48:34 PM PDT 24
Finished Apr 18 03:17:09 PM PDT 24
Peak memory 284760 kb
Host smart-373e110b-86f6-4ca0-a2f6-33f8fefab172
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457871266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1457871266
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.4085418410
Short name T40
Test name
Test status
Simulation time 24456105691 ps
CPU time 301.63 seconds
Started Apr 18 02:48:35 PM PDT 24
Finished Apr 18 02:53:37 PM PDT 24
Peak memory 248104 kb
Host smart-0bd44e02-e487-4aef-8269-b49832d4dc88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085418410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.4085418410
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1610294853
Short name T420
Test name
Test status
Simulation time 400794573 ps
CPU time 33.62 seconds
Started Apr 18 02:48:24 PM PDT 24
Finished Apr 18 02:48:58 PM PDT 24
Peak memory 249288 kb
Host smart-544eebf8-4e22-4358-8f34-8830011cf86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16102
94853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1610294853
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.749080650
Short name T447
Test name
Test status
Simulation time 615521112 ps
CPU time 24.08 seconds
Started Apr 18 02:48:25 PM PDT 24
Finished Apr 18 02:48:49 PM PDT 24
Peak memory 247436 kb
Host smart-712aec2d-24a4-4710-9c79-3fd43dc73a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74908
0650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.749080650
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3953713720
Short name T262
Test name
Test status
Simulation time 902772944 ps
CPU time 50.43 seconds
Started Apr 18 02:48:34 PM PDT 24
Finished Apr 18 02:49:25 PM PDT 24
Peak memory 249060 kb
Host smart-d1e82c06-7b4c-4026-ad7b-66ebf4fac82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537
13720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3953713720
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3242418460
Short name T395
Test name
Test status
Simulation time 650535277 ps
CPU time 31.77 seconds
Started Apr 18 02:48:25 PM PDT 24
Finished Apr 18 02:48:57 PM PDT 24
Peak memory 249224 kb
Host smart-8ea076df-f2da-4a12-ae60-8339af299ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32424
18460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3242418460
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.4023549320
Short name T290
Test name
Test status
Simulation time 959866516 ps
CPU time 25.27 seconds
Started Apr 18 02:48:34 PM PDT 24
Finished Apr 18 02:48:59 PM PDT 24
Peak memory 248988 kb
Host smart-0e821e41-b57b-433e-b534-cf73e77a6430
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023549320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.4023549320
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.753643443
Short name T61
Test name
Test status
Simulation time 339467883632 ps
CPU time 1831.05 seconds
Started Apr 18 02:48:37 PM PDT 24
Finished Apr 18 03:19:09 PM PDT 24
Peak memory 290244 kb
Host smart-84ef7cab-00b1-4d3d-b650-92f8ca5fbb0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753643443 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.753643443
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1864478493
Short name T220
Test name
Test status
Simulation time 126906692 ps
CPU time 4.23 seconds
Started Apr 18 02:48:51 PM PDT 24
Finished Apr 18 02:48:55 PM PDT 24
Peak memory 249224 kb
Host smart-9b6c702a-db98-4d07-95aa-7da3de8f7653
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1864478493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1864478493
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.77402573
Short name T195
Test name
Test status
Simulation time 21665245576 ps
CPU time 1568.05 seconds
Started Apr 18 02:48:41 PM PDT 24
Finished Apr 18 03:14:49 PM PDT 24
Peak memory 273472 kb
Host smart-24278b41-8154-49fa-8a68-b3d532939208
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77402573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.77402573
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.4138705237
Short name T493
Test name
Test status
Simulation time 6384469976 ps
CPU time 26.83 seconds
Started Apr 18 02:48:43 PM PDT 24
Finished Apr 18 02:49:10 PM PDT 24
Peak memory 249188 kb
Host smart-3c41b91e-d431-4f3c-ab2a-a260249e88fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4138705237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.4138705237
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1422891546
Short name T429
Test name
Test status
Simulation time 4047480442 ps
CPU time 249.05 seconds
Started Apr 18 02:48:39 PM PDT 24
Finished Apr 18 02:52:49 PM PDT 24
Peak memory 251196 kb
Host smart-b397ac6b-57e7-402d-98b3-579fa0d52aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14228
91546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1422891546
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.997898957
Short name T424
Test name
Test status
Simulation time 1429383202 ps
CPU time 32.32 seconds
Started Apr 18 02:48:39 PM PDT 24
Finished Apr 18 02:49:12 PM PDT 24
Peak memory 249044 kb
Host smart-06495e27-553b-42b8-81fd-a89df386db2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99789
8957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.997898957
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3522282381
Short name T339
Test name
Test status
Simulation time 98890124766 ps
CPU time 1305.59 seconds
Started Apr 18 02:48:41 PM PDT 24
Finished Apr 18 03:10:27 PM PDT 24
Peak memory 265548 kb
Host smart-558e87a0-4709-487e-94cd-60a96d6925f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522282381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3522282381
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.424677006
Short name T508
Test name
Test status
Simulation time 29042398444 ps
CPU time 1935.05 seconds
Started Apr 18 02:48:43 PM PDT 24
Finished Apr 18 03:20:59 PM PDT 24
Peak memory 288732 kb
Host smart-0cd9fd76-2b2a-4e07-9da7-7d4b49e08d4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424677006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.424677006
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3633770151
Short name T582
Test name
Test status
Simulation time 78885224382 ps
CPU time 641.55 seconds
Started Apr 18 02:48:40 PM PDT 24
Finished Apr 18 02:59:22 PM PDT 24
Peak memory 255216 kb
Host smart-025c4e76-4af0-4530-8e1f-dd10b69d1633
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633770151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3633770151
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3253640880
Short name T234
Test name
Test status
Simulation time 460974209 ps
CPU time 19.63 seconds
Started Apr 18 02:48:33 PM PDT 24
Finished Apr 18 02:48:53 PM PDT 24
Peak memory 256300 kb
Host smart-2db21c7b-5f3f-4392-b83b-ab5b7bd886f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32536
40880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3253640880
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1975661541
Short name T598
Test name
Test status
Simulation time 746104777 ps
CPU time 32.76 seconds
Started Apr 18 02:48:40 PM PDT 24
Finished Apr 18 02:49:13 PM PDT 24
Peak memory 255980 kb
Host smart-e89d351c-e9b3-46e1-993d-e28aa387efa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19756
61541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1975661541
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2399230122
Short name T662
Test name
Test status
Simulation time 3382891394 ps
CPU time 53.43 seconds
Started Apr 18 02:48:41 PM PDT 24
Finished Apr 18 02:49:34 PM PDT 24
Peak memory 254524 kb
Host smart-848b7878-77f6-47c4-b724-650c5a428daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23992
30122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2399230122
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3348844939
Short name T70
Test name
Test status
Simulation time 1695563116 ps
CPU time 32.89 seconds
Started Apr 18 02:48:34 PM PDT 24
Finished Apr 18 02:49:08 PM PDT 24
Peak memory 248976 kb
Host smart-77541549-f6bc-4a77-bf41-db3098fc5c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33488
44939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3348844939
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3385579075
Short name T552
Test name
Test status
Simulation time 139014633 ps
CPU time 6.47 seconds
Started Apr 18 02:48:45 PM PDT 24
Finished Apr 18 02:48:52 PM PDT 24
Peak memory 249872 kb
Host smart-9de12082-b30a-4998-805f-c16c6d804419
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385579075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3385579075
Directory /workspace/9.alert_handler_stress_all/latest
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